1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/stat.h> 31 #include <sys/sunndi.h> 32 #include <sys/pci.h> 33 #include <sys/pci_impl.h> 34 #include <sys/pci_cfgspace.h> 35 #include <sys/memlist.h> 36 #include <sys/bootconf.h> 37 #include "mps_table.h" 38 #include <sys/pci_cfgspace.h> 39 #include <sys/pci_cfgspace_impl.h> 40 #include <sys/psw.h> 41 #include "../../../../common/pci/pci_strings.h" 42 43 #define pci_getb (*pci_getb_func) 44 #define pci_getw (*pci_getw_func) 45 #define pci_getl (*pci_getl_func) 46 #define pci_putb (*pci_putb_func) 47 #define pci_putw (*pci_putw_func) 48 #define pci_putl (*pci_putl_func) 49 #define dcmn_err if (pci_boot_debug) cmn_err 50 51 #define CONFIG_INFO 0 52 #define CONFIG_UPDATE 1 53 #define CONFIG_NEW 2 54 #define COMPAT_BUFSIZE 256 55 56 extern int pci_bios_nbus; 57 static uchar_t max_dev_pci = 32; /* PCI standard */ 58 int pci_boot_debug = 0; 59 extern struct memlist *find_bus_res(int, int); 60 61 /* 62 * Module prototypes 63 */ 64 static void enumerate_bus_devs(uchar_t bus, int config_op); 65 static void create_root_bus_dip(uchar_t bus); 66 static dev_info_t *new_func_pci(uchar_t, uchar_t, uchar_t, uchar_t, 67 ushort_t, int); 68 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 69 ushort_t, ushort_t, uchar_t, uint_t); 70 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 71 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t); 72 static void add_model_prop(dev_info_t *, uint_t); 73 static void add_bus_range_prop(int); 74 static int pci_slot_names_prop(int, char *, int); 75 static void add_bus_slot_names_prop(int); 76 static void add_ppb_ranges_prop(int); 77 static void add_bus_available_prop(int); 78 static void alloc_res_array(); 79 80 /* 81 * Enumerate all PCI devices 82 */ 83 void 84 pci_setup_tree() 85 { 86 uchar_t i, root_bus_addr = 0; 87 88 alloc_res_array(); 89 for (i = 0; i <= pci_bios_nbus; i++) { 90 pci_bus_res[i].par_bus = (uchar_t)-1; 91 pci_bus_res[i].root_addr = (uchar_t)-1; 92 pci_bus_res[i].sub_bus = i; 93 } 94 95 pci_bus_res[0].root_addr = root_bus_addr++; 96 create_root_bus_dip(0); 97 enumerate_bus_devs(0, CONFIG_INFO); 98 99 /* 100 * Now enumerate peer busses 101 * 102 * We loop till pci_bios_nbus. On most systems, there is 103 * one more bus at the high end, which implements the ISA 104 * compatibility bus. We don't care about that. 105 * 106 * Note: In the old (bootconf) enumeration, the peer bus 107 * address did not use the bus number, and there were 108 * too many peer busses created. The root_bus_addr is 109 * used to maintain the old peer bus address assignment. 110 * However, we stop enumerating phantom peers with no 111 * device below. 112 */ 113 for (i = 1; i <= pci_bios_nbus; i++) { 114 if (pci_bus_res[i].dip == NULL) { 115 pci_bus_res[i].root_addr = root_bus_addr++; 116 } 117 enumerate_bus_devs(i, CONFIG_INFO); 118 119 /* add slot-names property for named pci hot-plug slots */ 120 add_bus_slot_names_prop(i); 121 } 122 123 /* add bus-range property for root/peer bus nodes */ 124 for (i = 0; i <= pci_bios_nbus; i++) { 125 if (pci_bus_res[i].par_bus == (uchar_t)-1) 126 add_bus_range_prop(i); 127 } 128 } 129 130 void 131 pci_reprogram(void) 132 { 133 int i, pci_reconfig = 1; 134 char *onoff; 135 136 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 137 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 138 if (strcmp(onoff, "off") == 0) { 139 pci_reconfig = 0; 140 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 141 } 142 ddi_prop_free(onoff); 143 } 144 145 for (i = 0; i <= pci_bios_nbus; i++) { 146 /* configure devices not configured by bios */ 147 if (pci_reconfig) 148 enumerate_bus_devs(i, CONFIG_NEW); 149 /* All dev programmed, so we can create available prop */ 150 add_bus_available_prop(i); 151 } 152 } 153 154 /* 155 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 156 */ 157 static void 158 create_root_bus_dip(uchar_t bus) 159 { 160 int pci_regs[] = {0, 0, 0}; 161 dev_info_t *dip; 162 163 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 164 165 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 166 (pnode_t)DEVI_SID_NODEID, &dip); 167 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 168 "device_type", "pci"); 169 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 170 "#address-cells", 3); 171 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 172 "#size-cells", 2); 173 pci_regs[0] = pci_bus_res[bus].root_addr; 174 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 175 "reg", (int *)pci_regs, 3); 176 177 (void) ndi_devi_bind_driver(dip, 0); 178 pci_bus_res[bus].dip = dip; 179 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 180 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 181 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 182 183 if (bus != 0) 184 return; 185 186 /* 187 * Special treatment of bus 0: 188 * If no resource from MPSPEC/HRT, copy pcimem from boot 189 * and make io space the entire range. There is no difference 190 * between prefetchable memory or not. 191 */ 192 if (pci_bus_res[0].mem_space == NULL) 193 pci_bus_res[0].mem_space = 194 memlist_dup(bootops->boot_mem->pcimem); 195 if (pci_bus_res[0].io_ports == NULL) 196 memlist_insert(&pci_bus_res[0].io_ports, 0, 0x10000); 197 } 198 199 /* 200 * returns: 0 = not configured, 1 = configured, -1 = error 201 */ 202 static int 203 func_configured(uchar_t bus, uchar_t dev, uchar_t func) 204 { 205 uint16_t cmdreg; 206 uint32_t bar_low, bar_high, size_low; 207 uint8_t bar_base, bar_end; 208 int io_enabled, mem_enabled; 209 int configured; 210 211 212 /* 213 * Determine PCI config space type from header and 214 * adjust address and count of Base Address Registers 215 */ 216 switch (pci_getb(bus, dev, func, PCI_CONF_HEADER) & 217 PCI_HEADER_TYPE_M) { 218 case PCI_HEADER_ZERO: 219 bar_base = PCI_CONF_BASE0; 220 bar_end = bar_base + PCI_BASE_NUM * sizeof (uint32_t); 221 break; 222 case PCI_HEADER_PPB: 223 bar_base = PCI_CONF_BASE0; 224 bar_end = bar_base + PCI_BCNF_BASE_NUM * sizeof (uint32_t); 225 break; 226 case PCI_HEADER_CARDBUS: 227 bar_base = PCI_CBUS_SOCK_REG; 228 bar_end = bar_base + PCI_CBUS_BASE_NUM * sizeof (uint32_t); 229 break; 230 default: 231 /* invalid header value - return error */ 232 return (-1); 233 } 234 235 cmdreg = pci_getw(bus, dev, func, PCI_CONF_COMM); 236 io_enabled = cmdreg & PCI_COMM_IO; 237 mem_enabled = cmdreg & PCI_COMM_MAE; 238 /* 239 * If neither I/O or memory-access are enabled, this 240 * device is not configured 241 */ 242 if (!io_enabled && !mem_enabled) 243 return (0); 244 245 /* 246 * Start out believing the device is configured and scan 247 * the base address registers until we find a valid BAR 248 * that is unprogrammed. If all valid BARs are programmed, 249 * the device is assumed to be configured. 250 * 251 * Valid BARs have a non-zero size and are unprogrammed 252 * if they have a zero value. Note that the actual value 253 * of the BAR size doesn't matter and isn't calculated; 254 * if any bits in the probed size mask are non-zero, that 255 * indicates a non-zero size. 256 */ 257 configured = 1; 258 while (configured && bar_base < bar_end) { 259 /* disable device decoding while probing base register */ 260 pci_putw(bus, dev, func, PCI_CONF_COMM, 261 cmdreg & ~(PCI_COMM_IO | PCI_COMM_MAE)); 262 263 bar_high = 0; /* default to 32-bit */ 264 /* probe the BAR for size */ 265 bar_low = pci_getl(bus, dev, func, bar_base); 266 pci_putl(bus, dev, func, bar_base, 0xffffffff); 267 size_low = pci_getl(bus, dev, func, bar_base); 268 pci_putl(bus, dev, func, bar_base, bar_low); 269 bar_base += sizeof (uint32_t); 270 271 if (bar_low & PCI_BASE_SPACE_IO) { 272 bar_low &= PCI_BASE_IO_ADDR_M; 273 size_low &= PCI_BASE_IO_ADDR_M; 274 if (size_low != 0) 275 configured = io_enabled && (bar_low != 0); 276 } else { 277 if ((bar_low & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 278 /* 64-bit case */ 279 bar_high = pci_getl(bus, dev, func, bar_base); 280 bar_base += sizeof (uint32_t); 281 } 282 bar_low &= PCI_BASE_M_ADDR_M; 283 size_low &= PCI_BASE_M_ADDR_M; 284 /* 285 * Omit test of upper 32-bits of size; some 64-bit 286 * devices may not properly implement the top 32-bits 287 * of the size; if a card appears that requests 288 * 4GB or more, this will need to be revisited. 289 */ 290 if (size_low != 0) 291 configured = mem_enabled && 292 ((bar_low != 0) || (bar_high != 0)); 293 } 294 /* restore the enable bits for this device */ 295 pci_putw(bus, dev, func, PCI_CONF_COMM, cmdreg); 296 } 297 298 return (configured); 299 } 300 301 302 /* 303 * For any fixed configuration (often compatability) pci devices 304 * and those with their own expansion rom, create device nodes 305 * to hold the already configured device details. 306 */ 307 void 308 enumerate_bus_devs(uchar_t bus, int config_op) 309 { 310 uchar_t dev, func, nfunc, header; 311 ushort_t venid; 312 dev_info_t *dip; 313 struct pci_devfunc { 314 struct pci_devfunc *next; 315 dev_info_t *dip; 316 uchar_t bus; 317 uchar_t dev; 318 uchar_t func; 319 } *devlist = NULL, *entry; 320 321 if (config_op == CONFIG_NEW) { 322 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 323 } else 324 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 325 326 for (dev = 0; dev < max_dev_pci; dev++) { 327 nfunc = 1; 328 for (func = 0; func < nfunc; func++) { 329 int configured; 330 331 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 332 dev, func); 333 334 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 335 if ((venid == 0xffff) || (venid == 0)) { 336 /* no function at this address */ 337 continue; 338 } 339 340 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 341 if (header == 0xff) { 342 continue; /* illegal value */ 343 } 344 345 /* 346 * according to some mail from Microsoft posted 347 * to the pci-drivers alias, their only requirement 348 * for a multifunction device is for the 1st 349 * function to have to PCI_HEADER_MULTI bit set. 350 */ 351 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 352 nfunc = 8; 353 } 354 355 configured = func_configured(bus, dev, func); 356 357 /* 358 * If the device is not configured and we're in the 359 * first pass (CONFIG_INFO), skip the device and 360 * it will be programmed/enumerated on the second pass 361 * (CONFIG_NEW). Likewise, if a device is configured, 362 * skip it on the second pass 363 */ 364 if ((configured < 0) || 365 (!configured && config_op != CONFIG_NEW) || 366 (configured && config_op != CONFIG_INFO)) 367 continue; 368 369 dip = new_func_pci(bus, dev, func, header, venid, 370 config_op); 371 /* 372 * If dip isn't null, reprogram the device later. 373 * This only happens for CONFIG_INFO case. 374 */ 375 if (dip) { 376 entry = kmem_alloc(sizeof (*entry), KM_SLEEP); 377 entry->dip = dip; 378 entry->dev = dev; 379 entry->func = func; 380 entry->next = devlist; 381 devlist = entry; 382 } 383 } 384 } 385 386 if (config_op == CONFIG_NEW) { 387 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 388 while (devlist) { 389 entry = devlist; 390 devlist = entry->next; 391 cmn_err(CE_NOTE, 392 "!reprogram pci device [%d/%d/%d] (%s)", 393 bus, entry->dev, entry->func, 394 ddi_driver_name(entry->dip)); 395 (void) add_reg_props(entry->dip, bus, entry->dev, 396 entry->func, CONFIG_UPDATE, 0); 397 kmem_free(entry, sizeof (*entry)); 398 } 399 pci_bus_res[bus].privdata = NULL; 400 } else { 401 pci_bus_res[bus].privdata = devlist; 402 } 403 } 404 405 static int 406 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 407 ushort_t subvenid, ushort_t subdevid) 408 { 409 static int prop_exist = -1; 410 static char *pciide_str; 411 char compat[32]; 412 413 if (prop_exist == -1) { 414 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 415 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 416 &pciide_str) == DDI_SUCCESS); 417 } 418 419 if (!prop_exist) 420 return (0); 421 422 /* compare property value against various forms of compatible */ 423 if (subvenid) { 424 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 425 venid, devid, subvenid, subdevid, revid); 426 if (strcmp(pciide_str, compat) == 0) 427 return (1); 428 429 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 430 venid, devid, subvenid, subdevid); 431 if (strcmp(pciide_str, compat) == 0) 432 return (1); 433 434 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 435 subvenid, subdevid); 436 if (strcmp(pciide_str, compat) == 0) 437 return (1); 438 } 439 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 440 venid, devid, revid); 441 if (strcmp(pciide_str, compat) == 0) 442 return (1); 443 444 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 445 if (strcmp(pciide_str, compat) == 0) 446 return (1); 447 448 return (0); 449 } 450 451 static int 452 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 453 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 454 { 455 struct ide_table { /* table for PCI_MASS_OTHER */ 456 ushort_t venid; 457 ushort_t devid; 458 } *entry; 459 460 /* XXX SATA devices: need a way to add dynamically */ 461 static struct ide_table ide_other[] = { 462 {0x1095, 0x3112}, 463 {0x1095, 0x3114}, 464 {0x1095, 0x3512}, 465 {0, 0} 466 }; 467 468 if (basecl != PCI_CLASS_MASS) 469 return (0); 470 471 if (subcl == PCI_MASS_IDE) { 472 return (1); 473 } 474 475 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 476 return (0); 477 } 478 479 entry = &ide_other[0]; 480 while (entry->venid) { 481 if (entry->venid == venid && entry->devid == devid) 482 return (1); 483 entry++; 484 } 485 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 486 } 487 488 static int 489 is_display(uint_t classcode) 490 { 491 static uint_t disp_classes[] = { 492 0x000100, 493 0x030000, 494 0x030001 495 }; 496 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 497 498 for (i = 0; i < nclasses; i++) { 499 if (classcode == disp_classes[i]) 500 return (1); 501 } 502 return (0); 503 } 504 505 static dev_info_t * 506 new_func_pci(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 507 ushort_t vendorid, int config_op) 508 { 509 char nodename[32], unitaddr[5]; 510 dev_info_t *dip; 511 uchar_t basecl, subcl, intr, revid; 512 ushort_t subvenid, subdevid, status; 513 uint_t classcode, revclass; 514 int reprogram = 0, pciide; 515 int power[2] = {1, 1}; 516 517 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 518 519 switch (header & PCI_HEADER_TYPE_M) { 520 case PCI_HEADER_ZERO: 521 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 522 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 523 break; 524 case PCI_HEADER_CARDBUS: 525 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 526 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 527 break; 528 default: 529 subvenid = 0; 530 subdevid = 0; 531 break; 532 } 533 534 /* XXX should be use generic names? derive from class? */ 535 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 536 classcode = revclass >> 8; 537 revid = revclass & 0xff; 538 539 /* figure out if this is pci-ide */ 540 basecl = classcode >> 16; 541 subcl = (classcode >> 8) & 0xff; 542 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 543 subvenid, subdevid); 544 545 if (pciide) 546 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 547 else if (is_display(classcode)) 548 (void) snprintf(nodename, sizeof (nodename), "display"); 549 else if (subvenid != 0) 550 (void) snprintf(nodename, sizeof (nodename), 551 "pci%x,%x", subvenid, subdevid); 552 else 553 (void) snprintf(nodename, sizeof (nodename), 554 "pci%x,%x", vendorid, deviceid); 555 556 /* make sure parent bus dip has been created */ 557 if (pci_bus_res[bus].dip == NULL) { 558 create_root_bus_dip(bus); 559 } 560 561 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 562 DEVI_SID_NODEID, &dip); 563 564 /* add properties */ 565 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 566 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 567 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 568 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 569 "class-code", classcode); 570 if (func == 0) 571 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 572 else 573 (void) snprintf(unitaddr, sizeof (unitaddr), 574 "%x,%x", dev, func); 575 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 576 "unit-address", unitaddr); 577 578 /* add special stuff for header type */ 579 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 580 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 581 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 582 583 if (subvenid != 0) { 584 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 585 "subsystem-id", subdevid); 586 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 587 "subsystem-vendor-id", subvenid); 588 } 589 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 590 "min-grant", mingrant); 591 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 592 "max-latency", maxlatency); 593 } 594 595 /* interrupt, record if not 0 */ 596 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 597 if (intr != 0) 598 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 599 "interrupts", intr); 600 601 /* 602 * Add support for 133 mhz pci eventually 603 */ 604 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 605 606 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 607 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 608 if (status & PCI_STAT_FBBC) 609 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 610 "fast-back-to-back"); 611 if (status & PCI_STAT_66MHZ) 612 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 613 "66mhz-capable"); 614 if (status & PCI_STAT_UDF) 615 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 616 "udf-supported"); 617 618 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 619 "power-consumption", power, 2); 620 621 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) { 622 add_ppb_props(dip, bus, dev, func); 623 } 624 625 add_model_prop(dip, classcode); 626 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 627 revid, classcode); 628 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 629 (void) ndi_devi_bind_driver(dip, 0); 630 631 /* special handling for pci-ide */ 632 if (pciide) { 633 dev_info_t *cdip; 634 635 /* 636 * Create properties specified by P1275 Working Group 637 * Proposal #414 Version 1 638 */ 639 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 640 "device_type", "pci-ide"); 641 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 642 "#address-cells", 1); 643 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 644 "#size-cells", 0); 645 646 /* allocate two child nodes */ 647 ndi_devi_alloc_sleep(dip, "ide", 648 (pnode_t)DEVI_SID_NODEID, &cdip); 649 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 650 "reg", 0); 651 (void) ndi_devi_bind_driver(cdip, 0); 652 ndi_devi_alloc_sleep(dip, "ide", 653 (pnode_t)DEVI_SID_NODEID, &cdip); 654 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 655 "reg", 1); 656 (void) ndi_devi_bind_driver(cdip, 0); 657 658 reprogram = 0; /* don't reprogram pci-ide bridge */ 659 } 660 661 if (reprogram) 662 return (dip); 663 return (NULL); 664 } 665 666 /* 667 * Set the compatible property to a value compliant with 668 * rev 2.1 of the IEEE1275 PCI binding. 669 * 670 * pciVVVV,DDDD.SSSS.ssss.RR (0) 671 * pciVVVV,DDDD.SSSS.ssss (1) 672 * pciSSSS,ssss (2) 673 * pciVVVV,DDDD.RR (3) 674 * pciVVVV,DDDD (4) 675 * pciclass,CCSSPP (5) 676 * pciclass,CCSS (6) 677 * 678 * The Subsystem (SSSS) forms are not inserted if 679 * subsystem-vendor-id is 0. 680 * 681 * Set with setprop and \x00 between each 682 * to generate the encoded string array form. 683 */ 684 void 685 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 686 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode) 687 { 688 int i, size; 689 char *compat[7]; 690 char *buf, *curr; 691 692 #define COMPAT_BUFSIZE 256 693 i = 0; 694 size = COMPAT_BUFSIZE; 695 curr = buf = kmem_alloc(size, KM_SLEEP); 696 697 if (subvenid) { 698 compat[i++] = curr; /* form 0 */ 699 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 700 vendorid, deviceid, subvenid, subdevid, revid); 701 size -= strlen(curr) + 1; 702 curr += strlen(curr) + 1; 703 704 compat[i++] = curr; /* form 1 */ 705 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 706 vendorid, deviceid, subvenid, subdevid); 707 size -= strlen(curr) + 1; 708 curr += strlen(curr) + 1; 709 710 compat[i++] = curr; /* form 2 */ 711 (void) snprintf(curr, size, "pci%x,%x", 712 subvenid, subdevid); 713 size -= strlen(curr) + 1; 714 curr += strlen(curr) + 1; 715 } 716 compat[i++] = curr; /* form 3 */ 717 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 718 size -= strlen(curr) + 1; 719 curr += strlen(curr) + 1; 720 721 compat[i++] = curr; /* form 4 */ 722 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 723 size -= strlen(curr) + 1; 724 curr += strlen(curr) + 1; 725 726 compat[i++] = curr; /* form 5 */ 727 (void) snprintf(curr, size, "pciclass,%06x", classcode); 728 size -= strlen(curr) + 1; 729 curr += strlen(curr) + 1; 730 731 compat[i++] = curr; /* form 6 */ 732 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 733 734 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 735 "compatible", compat, i); 736 kmem_free(buf, COMPAT_BUFSIZE); 737 } 738 739 /* 740 * Adjust the reg properties for a dual channel PCI-IDE device. 741 * 742 * NOTE: don't do anything that changes the order of the hard-decodes 743 * and programmed BARs. The kernel driver depends on these values 744 * being in this order regardless of whether they're for a 'native' 745 * mode BAR or not. 746 */ 747 /* 748 * config info for pci-ide devices 749 */ 750 static struct { 751 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 752 uchar_t bar_offset; /* offset for alt status register */ 753 ushort_t addr; /* compatibility mode base address */ 754 ushort_t length; /* number of ports for this BAR */ 755 } pciide_bar[] = { 756 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 757 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 758 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 759 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 760 }; 761 762 static int 763 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 764 { 765 int hard_decode = 0; 766 767 /* 768 * Adjust the base and len for the BARs of the PCI-IDE 769 * device's primary and secondary controllers. The first 770 * two BARs are for the primary controller and the next 771 * two BARs are for the secondary controller. The fifth 772 * and sixth bars are never adjusted. 773 */ 774 if (index >= 0 && index <= 3) { 775 *lenp = pciide_bar[index].length; 776 777 if (progcl & pciide_bar[index].native_mask) { 778 *basep += pciide_bar[index].bar_offset; 779 } else { 780 *basep = pciide_bar[index].addr; 781 hard_decode = 1; 782 } 783 } 784 785 /* 786 * if either base or len is zero make certain both are zero 787 */ 788 if (*basep == 0 || *lenp == 0) { 789 *basep = 0; 790 *lenp = 0; 791 hard_decode = 0; 792 } 793 794 return (hard_decode); 795 } 796 797 798 /* 799 * Add the "reg" and "assigned-addresses" property 800 */ 801 static int 802 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 803 int config_op, int pciide) 804 { 805 uchar_t baseclass, subclass, progclass, header; 806 ushort_t bar_sz; 807 uint_t value = 0, len, devloc; 808 uint_t base, base_hi, type; 809 ushort_t offset, end; 810 int max_basereg, j, reprogram = 0; 811 uint_t phys_hi; 812 struct memlist **io_res, **mres, **mem_res, **pmem_res; 813 uint16_t cmd_reg; 814 815 pci_regspec_t regs[16] = {{0}}; 816 pci_regspec_t assigned[15] = {{0}}; 817 int nreg, nasgn, configured, enable = 0; 818 819 io_res = &pci_bus_res[bus].io_ports; 820 mem_res = &pci_bus_res[bus].mem_space; 821 if (bus == 0) /* for bus 0, there is only mem_space */ 822 pmem_res = mem_res; 823 else 824 pmem_res = &pci_bus_res[bus].pmem_space; 825 826 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 827 regs[0].pci_phys_hi = devloc; 828 nreg = 1; /* rest of regs[0] is all zero */ 829 nasgn = 0; 830 831 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 832 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 833 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 834 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 835 /* Fetch PCI command, disable I/O and memory */ 836 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 837 configured = cmd_reg & (PCI_COMM_IO | PCI_COMM_MAE); 838 pci_putw(bus, dev, func, PCI_CONF_COMM, 839 cmd_reg & ~(PCI_COMM_IO | PCI_COMM_MAE)); 840 ASSERT(configured || config_op == CONFIG_NEW); 841 842 switch (header) { 843 case PCI_HEADER_ZERO: 844 max_basereg = PCI_BASE_NUM; 845 break; 846 case PCI_HEADER_PPB: 847 max_basereg = PCI_BCNF_BASE_NUM; 848 break; 849 case PCI_HEADER_CARDBUS: 850 max_basereg = PCI_CBUS_BASE_NUM; 851 break; 852 default: 853 max_basereg = 0; 854 break; 855 } 856 857 /* 858 * Create the register property by saving the current 859 * value of the base register. Disable memory/io, then 860 * write 0xffffffff to the base register. Read the 861 * value back to determine the required size of the 862 * address space. Restore the base register 863 * contents. 864 */ 865 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 866 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 867 j++, offset += bar_sz) { 868 int hard_decode = 0; 869 870 /* determine the size of the address space */ 871 base = pci_getl(bus, dev, func, offset); 872 pci_putl(bus, dev, func, offset, 0xffffffff); 873 value = pci_getl(bus, dev, func, offset); 874 pci_putl(bus, dev, func, offset, base); 875 876 /* construct phys hi,med.lo, size hi, lo */ 877 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 878 /* i/o space */ 879 bar_sz = PCI_BAR_SZ_32; 880 value &= PCI_BASE_IO_ADDR_M; 881 len = ((value ^ (value-1)) + 1) >> 1; 882 883 /* XXX Adjust first 4 IDE registers */ 884 if (pciide) { 885 if (subclass != PCI_MASS_IDE) 886 progclass = (PCI_IDE_IF_NATIVE_PRI | 887 PCI_IDE_IF_NATIVE_SEC); 888 hard_decode = pciIdeAdjustBAR(progclass, j, 889 &base, &len); 890 } else if (value == 0) { 891 /* skip base regs with size of 0 */ 892 continue; 893 } 894 895 regs[nreg].pci_size_low = 896 assigned[nasgn].pci_size_low = len; 897 if (!hard_decode) { 898 regs[nreg].pci_phys_hi = 899 (PCI_ADDR_IO | devloc) + offset; 900 } else { 901 regs[nreg].pci_phys_hi = 902 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 903 offset; 904 regs[nreg].pci_phys_low = 905 base & PCI_BASE_IO_ADDR_M; 906 } 907 assigned[nasgn].pci_phys_hi = 908 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 909 type = base & (~PCI_BASE_IO_ADDR_M); 910 base &= PCI_BASE_IO_ADDR_M; 911 912 /* 913 * first pass - gather what's there 914 * update/second pass - adjust/allocate regions 915 * config - allocate regions 916 */ 917 if (config_op == CONFIG_INFO) { /* first pass */ 918 /* take out of the resource map of the bus */ 919 if (*io_res && base != 0) 920 (void) memlist_remove(io_res, 921 (uint64_t)base, (uint64_t)len); 922 else if (*io_res) 923 reprogram = 1; 924 } else if (*io_res && base == 0) { 925 base = (uint_t)memlist_find(io_res, 926 (uint64_t)len, (uint64_t)0x400); 927 if (base != 0) { 928 /* XXX need to worry about 64-bit? */ 929 pci_putl(bus, dev, func, offset, 930 base | type); 931 base = pci_getl(bus, dev, func, offset); 932 base &= PCI_BASE_IO_ADDR_M; 933 } 934 if (base == 0) { 935 cmn_err(CE_WARN, "failed to program" 936 " IO space 0x%x for [%d/%d/%d]", 937 len, bus, dev, func); 938 } else 939 enable |= PCI_COMM_IO; 940 } 941 assigned[nasgn].pci_phys_low = base; 942 nreg++, nasgn++; 943 944 } else { 945 /* memory space */ 946 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 947 bar_sz = PCI_BAR_SZ_64; 948 base_hi = pci_getl(bus, dev, func, offset + 4); 949 phys_hi = PCI_ADDR_MEM64; 950 } else { 951 bar_sz = PCI_BAR_SZ_32; 952 base_hi = 0; 953 phys_hi = PCI_ADDR_MEM32; 954 } 955 956 /* skip base regs with size of 0 */ 957 value &= PCI_BASE_M_ADDR_M; 958 959 if (value == 0) { 960 continue; 961 } 962 len = ((value ^ (value-1)) + 1) >> 1; 963 regs[nreg].pci_size_low = 964 assigned[nasgn].pci_size_low = len; 965 966 phys_hi |= (devloc | offset); 967 if (base & PCI_BASE_PREF_M) { 968 mres = pmem_res; 969 phys_hi |= PCI_PREFETCH_B; 970 } else { 971 mres = mem_res; 972 } 973 regs[nreg].pci_phys_hi = 974 assigned[nasgn].pci_phys_hi = phys_hi; 975 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 976 assigned[nasgn].pci_phys_mid = base_hi; 977 type = base & ~PCI_BASE_M_ADDR_M; 978 base &= PCI_BASE_M_ADDR_M; 979 980 if (config_op == CONFIG_INFO) { 981 /* take out of the resource map of the bus */ 982 if (*mres && base != 0) { 983 (void) memlist_remove(mres, 984 (uint64_t)base, (uint64_t)len); 985 } else if (*mres) 986 reprogram = 1; 987 } else if (*mres && base == 0) { 988 base = (uint_t)memlist_find(mres, 989 (uint64_t)len, (uint64_t)0x1000); 990 if (base != NULL) { 991 pci_putl(bus, dev, func, offset, 992 base | type); 993 base = pci_getl(bus, dev, func, offset); 994 base &= PCI_BASE_M_ADDR_M; 995 } 996 997 if (base == 0) { 998 cmn_err(CE_WARN, "failed to program " 999 "mem space 0x%x for [%d/%d/%d]", 1000 len, bus, dev, func); 1001 } else 1002 enable |= PCI_COMM_MAE; 1003 } 1004 assigned[nasgn].pci_phys_low = base; 1005 nreg++, nasgn++; 1006 } 1007 } 1008 switch (header) { 1009 case PCI_HEADER_ZERO: 1010 offset = PCI_CONF_ROM; 1011 break; 1012 case PCI_HEADER_PPB: 1013 offset = PCI_BCNF_ROM; 1014 break; 1015 default: /* including PCI_HEADER_CARDBUS */ 1016 goto done; 1017 } 1018 1019 /* 1020 * Add the expansion rom memory space 1021 * Determine the size of the ROM base reg; don't write reserved bits 1022 * ROM isn't in the PCI memory space. 1023 */ 1024 base = pci_getl(bus, dev, func, offset); 1025 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 1026 value = pci_getl(bus, dev, func, offset); 1027 pci_putl(bus, dev, func, offset, base); 1028 value &= PCI_BASE_ROM_ADDR_M; 1029 1030 if (value != 0) { 1031 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 1032 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 1033 PCI_ADDR_MEM32 | devloc) + offset; 1034 base &= PCI_BASE_ROM_ADDR_M; 1035 assigned[nasgn].pci_phys_low = base; 1036 len = ((value ^ (value-1)) + 1) >> 1; 1037 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 1038 nreg++, nasgn++; 1039 /* take it out of the memory resource */ 1040 if (*mem_res && base != 0) 1041 (void) memlist_remove(mem_res, 1042 (uint64_t)base, (uint64_t)len); 1043 } 1044 1045 /* 1046 * The following are ISA resources. There are not part 1047 * of the PCI local bus resources. So don't attempt to 1048 * do resource accounting against PCI. 1049 */ 1050 1051 /* add the three hard-decode, aliased address spaces for VGA */ 1052 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 1053 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 1054 1055 /* VGA hard decode 0x3b0-0x3bb */ 1056 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1057 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1058 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 1059 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 1060 nreg++, nasgn++; 1061 1062 /* VGA hard decode 0x3c0-0x3df */ 1063 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1064 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1065 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 1066 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 1067 nreg++, nasgn++; 1068 1069 /* Video memory */ 1070 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1071 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 1072 regs[nreg].pci_phys_low = 1073 assigned[nasgn].pci_phys_low = 0xa0000; 1074 regs[nreg].pci_size_low = 1075 assigned[nasgn].pci_size_low = 0x20000; 1076 nreg++, nasgn++; 1077 } 1078 1079 /* add the hard-decode, aliased address spaces for 8514 */ 1080 if ((baseclass == PCI_CLASS_DISPLAY) && 1081 (subclass == PCI_DISPLAY_VGA) && 1082 (progclass & PCI_DISPLAY_IF_8514)) { 1083 1084 /* hard decode 0x2e8 */ 1085 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1086 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1087 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 1088 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 1089 nreg++, nasgn++; 1090 1091 /* hard decode 0x2ea-0x2ef */ 1092 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 1093 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 1094 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 1095 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 1096 nreg++, nasgn++; 1097 } 1098 1099 done: 1100 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 1101 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1102 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1103 "assigned-addresses", 1104 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1105 if (config_op == CONFIG_NEW && enable) { 1106 cmn_err(CE_NOTE, 1107 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1108 cmd_reg |= (enable | PCI_COMM_ME); 1109 } 1110 /* restore device enables */ 1111 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1112 return (reprogram); 1113 } 1114 1115 static void 1116 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func) 1117 { 1118 int i; 1119 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1120 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1121 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1122 ASSERT(secbus <= subbus); 1123 1124 /* 1125 * Some BIOSes lie about max pci busses, we allow for 1126 * such mistakes here 1127 */ 1128 if (subbus > pci_bios_nbus) { 1129 pci_bios_nbus = subbus; 1130 alloc_res_array(); 1131 } 1132 1133 ASSERT(pci_bus_res[secbus].dip == NULL); 1134 pci_bus_res[secbus].dip = dip; 1135 pci_bus_res[secbus].par_bus = bus; 1136 1137 /* setup bus number hierarchy */ 1138 pci_bus_res[secbus].sub_bus = subbus; 1139 if (subbus > pci_bus_res[bus].sub_bus) 1140 pci_bus_res[bus].sub_bus = subbus; 1141 for (i = secbus + 1; i <= subbus; i++) 1142 pci_bus_res[i].par_bus = bus; 1143 1144 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1145 "device_type", "pci"); 1146 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1147 "#address-cells", 3); 1148 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1149 "#size-cells", 2); 1150 1151 /* 1152 * According to PPB spec, the base register should be programmed 1153 * with a value bigger than the limit register when there are 1154 * no resources available. This applies to io, memory, and 1155 * prefetchable memory. 1156 */ 1157 /* io range */ 1158 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1159 io_range[0] = ((val & 0xf0) << 8); 1160 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1161 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1162 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1163 memlist_insert(&pci_bus_res[secbus].io_ports, 1164 (uint64_t)io_range[0], 1165 (uint64_t)(io_range[1] - io_range[0] + 1)); 1166 if (pci_bus_res[bus].io_ports != NULL) { 1167 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1168 (uint64_t)io_range[0], 1169 (uint64_t)(io_range[1] - io_range[0] + 1)); 1170 } 1171 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1172 secbus, io_range[0], io_range[1]); 1173 /* if 32-bit supported, make sure upper bits are not set */ 1174 if ((val & 0xf) == 1 && 1175 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1176 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1177 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1178 } 1179 } 1180 1181 /* mem range */ 1182 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1183 mem_range[0] = ((val & 0xFFF0) << 16); 1184 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1185 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1186 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1187 memlist_insert(&pci_bus_res[secbus].mem_space, 1188 (uint64_t)mem_range[0], 1189 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1190 /* remove from parent resouce list */ 1191 if (pci_bus_res[bus].mem_space != NULL) { 1192 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1193 (uint64_t)mem_range[0], 1194 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1195 } 1196 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1197 secbus, mem_range[0], mem_range[1]); 1198 } 1199 1200 /* prefetchable memory range */ 1201 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1202 pmem_range[0] = ((val & 0xFFF0) << 16); 1203 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1204 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1205 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1206 memlist_insert(&pci_bus_res[secbus].pmem_space, 1207 (uint64_t)pmem_range[0], 1208 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1209 if (pci_bus_res[bus].pmem_space != NULL) { 1210 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1211 (uint64_t)pmem_range[0], 1212 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1213 } 1214 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1215 secbus, pmem_range[0], pmem_range[1]); 1216 /* if 64-bit supported, make sure upper bits are not set */ 1217 if ((val & 0xf) == 1 && 1218 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1219 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1220 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1221 } 1222 } 1223 1224 add_bus_range_prop(secbus); 1225 add_ppb_ranges_prop(secbus); 1226 } 1227 1228 extern const struct pci_class_strings_s class_pci[]; 1229 extern int class_pci_items; 1230 1231 static void 1232 add_model_prop(dev_info_t *dip, uint_t classcode) 1233 { 1234 const char *desc; 1235 int i; 1236 uchar_t baseclass = classcode >> 16; 1237 uchar_t subclass = (classcode >> 8) & 0xff; 1238 uchar_t progclass = classcode & 0xff; 1239 1240 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1241 desc = "IDE controller"; 1242 } else { 1243 for (desc = 0, i = 0; i < class_pci_items; i++) { 1244 if ((baseclass == class_pci[i].base_class) && 1245 (subclass == class_pci[i].sub_class) && 1246 (progclass == class_pci[i].prog_class)) { 1247 desc = class_pci[i].actual_desc; 1248 break; 1249 } 1250 } 1251 if (i == class_pci_items) 1252 desc = "Unknown class of pci/pnpbios device"; 1253 } 1254 1255 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1256 (char *)desc); 1257 } 1258 1259 static void 1260 add_bus_range_prop(int bus) 1261 { 1262 int bus_range[2]; 1263 1264 if (pci_bus_res[bus].dip == NULL) 1265 return; 1266 bus_range[0] = bus; 1267 bus_range[1] = pci_bus_res[bus].sub_bus; 1268 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1269 "bus-range", (int *)bus_range, 2); 1270 } 1271 1272 /* 1273 * pci irq routing information table 1274 */ 1275 static int pci_irq_nroutes; 1276 static pci_irq_route_t *pci_irq_routes; 1277 1278 /* 1279 * Issue the bios get irq routing information table interrupt 1280 * 1281 * Despite the name, the information in the table is only 1282 * used to derive slot names for some named pci hot-plug slots. 1283 * 1284 * Returns the number of irq routing table entries returned 1285 * by the bios, or 0 and optionally, the number of entries required. 1286 */ 1287 static int 1288 pci_bios_get_irq_routing(pci_irq_route_t *routes, int nroutes, int *nneededp) 1289 { 1290 struct bop_regs regs; 1291 uchar_t *hdrp; 1292 uchar_t *bufp; 1293 int i, n; 1294 int rval = 0; 1295 1296 if (nneededp) 1297 *nneededp = 0; 1298 1299 /* 1300 * Set up irq routing header with the size and address 1301 * of some useable low-memory data addresses. Initalize 1302 * data area to zero, avoiding memcpy/bzero. 1303 */ 1304 hdrp = (uchar_t *)BIOS_IRQ_ROUTING_HDR; 1305 bufp = (uchar_t *)BIOS_IRQ_ROUTING_DATA; 1306 1307 n = nroutes * sizeof (pci_irq_route_t); 1308 for (i = 0; i < n; i++) 1309 bufp[i] = 0; 1310 ((pci_irq_route_hdr_t *)hdrp)->pir_size = n; 1311 ((pci_irq_route_hdr_t *)hdrp)->pir_addr = (uint32_t)(uintptr_t)bufp; 1312 1313 bzero(®s, sizeof (regs)); 1314 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_GET_IRQ_ROUTING; 1315 1316 regs.ds = 0xf000; 1317 regs.es = FP_SEG((uint_t)(uintptr_t)hdrp); 1318 regs.edi.word.di = FP_OFF((uint_t)(uintptr_t)hdrp); 1319 1320 BOP_DOINT(bootops, 0x1a, ®s); 1321 1322 n = (int)(((pci_irq_route_hdr_t *)hdrp)->pir_size / 1323 sizeof (pci_irq_route_t)); 1324 1325 if ((regs.eflags & PS_C) != 0) { 1326 if (nneededp) 1327 *nneededp = n; 1328 } else { 1329 /* 1330 * Copy resulting irq routing data from low memory up to 1331 * the kernel address space, avoiding memcpy as usual. 1332 */ 1333 if (n <= nroutes) { 1334 for (i = 0; i < n * sizeof (pci_irq_route_t); i++) 1335 ((uchar_t *)routes)[i] = bufp[i]; 1336 rval = n; 1337 } 1338 } 1339 return (rval); 1340 } 1341 1342 static void 1343 pci_get_irq_routing_table(void) 1344 { 1345 pci_irq_route_t *routes; 1346 int n = N_PCI_IRQ_ROUTES; 1347 int nneeded = 0; 1348 int nroutes; 1349 1350 /* 1351 * Get irq routing table information. 1352 * Allocate a buffer for an initial default number of entries. 1353 * If the bios indicates it needs a larger buffer, try it again. 1354 * Drive on if it still won't cooperate and play nice after that. 1355 */ 1356 routes = kmem_zalloc(n * sizeof (pci_irq_route_t), KM_SLEEP); 1357 nroutes = pci_bios_get_irq_routing(routes, n, &nneeded); 1358 if (nroutes == 0 && nneeded > n) { 1359 kmem_free(routes, n * sizeof (pci_irq_route_t)); 1360 if (nneeded > N_PCI_IRQ_ROUTES_MAX) { 1361 cmn_err(CE_CONT, 1362 "pci: unable to get IRQ routing information, " 1363 "required buffer space of %d entries exceeds max\n", 1364 nneeded); 1365 return; 1366 } 1367 n = nneeded; 1368 routes = kmem_zalloc(n * sizeof (pci_irq_route_t), KM_SLEEP); 1369 nroutes = pci_bios_get_irq_routing(routes, n, NULL); 1370 if (nroutes == 0) { 1371 cmn_err(CE_CONT, 1372 "pci: unable to get IRQ routing information, " 1373 "required buffer space for %d entries\n", n); 1374 kmem_free(routes, n * sizeof (pci_irq_route_t)); 1375 } 1376 } 1377 1378 if (nroutes > 0) { 1379 pci_irq_routes = routes; 1380 pci_irq_nroutes = nroutes; 1381 } 1382 } 1383 /* 1384 * Use the results of the PCI BIOS call that returned the routing tables 1385 * to build the 1275 slot-names property for the indicated bus. 1386 * Results are returned in buf. Length is return value, -1 is returned on 1387 * overflow and zero is returned if no data exists to build a property. 1388 */ 1389 static int 1390 pci_slot_names_prop(int bus, char *buf, int len) 1391 { 1392 uchar_t dev; 1393 uchar_t slot[N_PCI_IRQ_ROUTES_MAX+1]; 1394 uint32_t mask; 1395 int i, nnames, plen; 1396 1397 ASSERT(pci_irq_nroutes <= N_PCI_IRQ_ROUTES_MAX); 1398 1399 if (pci_irq_nroutes == 0) 1400 return (0); 1401 nnames = 0; 1402 mask = 0; 1403 for (i = 0; i < pci_irq_nroutes; i++) 1404 slot[i] = 0xff; 1405 for (i = 0; i < pci_irq_nroutes; i++) { 1406 if (pci_irq_routes[i].pir_bus != bus) 1407 continue; 1408 if (pci_irq_routes[i].pir_slot != 0) { 1409 dev = (pci_irq_routes[i].pir_dev & 0xf8) >> 3; 1410 slot[dev] = pci_irq_routes[i].pir_slot; 1411 mask |= (1 << dev); 1412 nnames++; 1413 } 1414 } 1415 1416 if (nnames == 0) 1417 return (0); 1418 1419 if (len < (4 + nnames * 8)) 1420 return (-1); 1421 *(uint32_t *)buf = mask; 1422 plen = 4; 1423 for (i = 0; i < pci_irq_nroutes; i++) { 1424 if (slot[i] == 0xff) 1425 continue; 1426 (void) sprintf(buf + plen, "Slot %d", slot[i]); 1427 plen += strlen(buf+plen) + 1; 1428 *(buf + plen) = 0; 1429 } 1430 for (; plen % 4; plen++) 1431 *(buf + plen) = 0; 1432 return (plen); 1433 } 1434 1435 /* 1436 * Add slot-names property for any named pci hot-plug slots 1437 */ 1438 static void 1439 add_bus_slot_names_prop(int bus) 1440 { 1441 char slotprop[256]; 1442 int len; 1443 1444 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1445 if (len > 0) { 1446 if (pci_bus_res[bus].dip == NULL) 1447 create_root_bus_dip(bus); 1448 ASSERT(pci_bus_res[bus].dip); 1449 ASSERT((len % sizeof (int)) == 0); 1450 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1451 pci_bus_res[bus].dip, "slot-names", 1452 (int *)slotprop, len / sizeof (int)); 1453 } 1454 } 1455 1456 /* this should be in some header file, shared with pcicfg */ 1457 struct pcicfg_range { 1458 uint32_t child_hi; 1459 uint32_t child_mid; 1460 uint32_t child_lo; 1461 uint32_t parent_hi; 1462 uint32_t parent_mid; 1463 uint32_t parent_lo; 1464 uint32_t size_hi; 1465 uint32_t size_lo; 1466 }; 1467 1468 static int 1469 memlist_to_range(struct pcicfg_range *rp, struct memlist *entry, int type) 1470 { 1471 if (entry == NULL) 1472 return (0); 1473 1474 /* assume 32-bit addresses */ 1475 rp->child_hi = rp->parent_hi = type; 1476 rp->child_mid = rp->parent_mid = 0; 1477 rp->child_lo = rp->parent_lo = (uint32_t)entry->address; 1478 rp->size_hi = 0; 1479 rp->size_lo = (uint32_t)entry->size; 1480 return (1); 1481 } 1482 1483 static void 1484 add_ppb_ranges_prop(int bus) 1485 { 1486 int i = 0; 1487 struct pcicfg_range *rp; 1488 1489 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1490 1491 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1492 PCI_ADDR_IO | PCI_REG_REL_M); 1493 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1494 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1495 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1496 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1497 1498 if (i != 0) 1499 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1500 pci_bus_res[bus].dip, "ranges", (int *)rp, 1501 i * sizeof (struct pcicfg_range) / sizeof (int)); 1502 kmem_free(rp, 3 * sizeof (*rp)); 1503 } 1504 1505 static int 1506 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1507 { 1508 int i = 0; 1509 1510 while (list) { 1511 /* assume 32-bit addresses */ 1512 sp->pci_phys_hi = type; 1513 sp->pci_phys_mid = 0; 1514 sp->pci_phys_low = (uint32_t)list->address; 1515 sp->pci_size_hi = 0; 1516 sp->pci_size_low = (uint32_t)list->size; 1517 1518 list = list->next; 1519 sp++, i++; 1520 } 1521 return (i); 1522 } 1523 1524 static void 1525 add_bus_available_prop(int bus) 1526 { 1527 int i, count; 1528 struct pci_phys_spec *sp; 1529 1530 count = memlist_count(pci_bus_res[bus].io_ports) + 1531 memlist_count(pci_bus_res[bus].mem_space) + 1532 memlist_count(pci_bus_res[bus].pmem_space); 1533 1534 if (count == 0) /* nothing available */ 1535 return; 1536 1537 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1538 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1539 PCI_ADDR_IO | PCI_REG_REL_M); 1540 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1541 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1542 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1543 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1544 ASSERT(i == count); 1545 1546 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1547 "available", (int *)sp, 1548 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1549 kmem_free(sp, count * sizeof (*sp)); 1550 } 1551 1552 static void 1553 alloc_res_array(void) 1554 { 1555 static int array_max = 0; 1556 int old_max; 1557 void *old_res; 1558 1559 if (array_max > pci_bios_nbus + 1) 1560 return; /* array is big enough */ 1561 1562 old_max = array_max; 1563 old_res = pci_bus_res; 1564 1565 if (array_max == 0) 1566 array_max = 16; /* start with a reasonable number */ 1567 1568 while (array_max < pci_bios_nbus + 1) 1569 array_max <<= 1; 1570 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1571 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1572 1573 if (old_res) { /* copy content and free old array */ 1574 bcopy(old_res, pci_bus_res, 1575 old_max * sizeof (struct pci_bus_resource)); 1576 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1577 } 1578 } 1579