17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22c8589f13Ssethg * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate #include <sys/types.h> 297c478bd9Sstevel@tonic-gate #include <sys/stat.h> 307c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 337c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 347c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 357c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3670025d76Sjohnny #include <io/pci/mps_table.h> 37c88420b3Sdmick #include <sys/pci_cfgspace.h> 38c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 39c88420b3Sdmick #include <sys/psw.h> 4009f67678Sanish #include "../../../../common/pci/pci_strings.h" 41c8589f13Ssethg #include <sys/apic.h> 428a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 4325145214Smyers #include <sys/acpi/acpi.h> 4425145214Smyers #include <sys/acpica.h> 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 477c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 487c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 497c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 507c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 517c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 527c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 537c478bd9Sstevel@tonic-gate 547c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 557c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 567c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 57bd87be88Ssethg #define CONFIG_FIX 3 5870025d76Sjohnny #define COMPAT_BUFSIZE 512 597c478bd9Sstevel@tonic-gate 60bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 61bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 62bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 63bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 64bd87be88Ssethg 65bd87be88Ssethg struct pci_fixundo { 66bd87be88Ssethg uint8_t bus; 67bd87be88Ssethg uint8_t dev; 68bd87be88Ssethg uint8_t fn; 69bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 70bd87be88Ssethg struct pci_fixundo *next; 71bd87be88Ssethg }; 72bd87be88Ssethg 737c478bd9Sstevel@tonic-gate extern int pci_bios_nbus; 747c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 757c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 767c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 77bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate /* 807c478bd9Sstevel@tonic-gate * Module prototypes 817c478bd9Sstevel@tonic-gate */ 827c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 837c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 84bd87be88Ssethg static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 857c478bd9Sstevel@tonic-gate ushort_t, int); 867c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 8770025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 887c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 8970025d76Sjohnny static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 907c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 917c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 92b1f176e8Sjg static void add_bus_slot_names_prop(int); 937c478bd9Sstevel@tonic-gate static void add_ppb_ranges_prop(int); 947c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 95f55ce205Sszhou static void alloc_res_array(); 96c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 97c8589f13Ssethg ushort_t deviceid); 987c478bd9Sstevel@tonic-gate 9975bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 10075bcd456Sjg 101*ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 10225145214Smyers int pci_bus_always_renumber = 0; 10325145214Smyers 104fc396574Srw /* get the subordinate bus # for a root/peer bus */ 105fc396574Srw static int 106fc396574Srw pci_root_subbus(int bus, uchar_t *subbus) 107fc396574Srw { 108fc396574Srw ACPI_HANDLE hdl; 109fc396574Srw ACPI_BUFFER rb; 110fc396574Srw ACPI_RESOURCE *rp; 111fc396574Srw int rv; 112fc396574Srw 113fc396574Srw if (pci_bus_res[bus].dip == NULL) { 114fc396574Srw /* non-used bus # */ 115fc396574Srw return (AE_ERROR); 116fc396574Srw } 117fc396574Srw if (acpica_find_pciobj(pci_bus_res[bus].dip, &hdl) != AE_OK) { 118fc396574Srw cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 119fc396574Srw return (AE_ERROR); 120fc396574Srw } 121fc396574Srw 122fc396574Srw rb.Length = ACPI_ALLOCATE_BUFFER; 123fc396574Srw if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 124fc396574Srw cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 125fc396574Srw return (AE_ERROR); 126fc396574Srw } 127fc396574Srw 128fc396574Srw rv = AE_ERROR; 129fc396574Srw 130fc396574Srw for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 131fc396574Srw rp = ACPI_NEXT_RESOURCE(rp)) { 132fc396574Srw 133fc396574Srw switch (rp->Type) { 134fc396574Srw case ACPI_RESOURCE_TYPE_ADDRESS16: 135fc396574Srw if (rp->Data.Address.ResourceType 136fc396574Srw != ACPI_BUS_NUMBER_RANGE) 137fc396574Srw continue; 138fc396574Srw *subbus = (uchar_t)rp->Data.Address16.Maximum; 139fc396574Srw dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 140fc396574Srw break; 141fc396574Srw case ACPI_RESOURCE_TYPE_ADDRESS32: 142fc396574Srw if (rp->Data.Address.ResourceType 143fc396574Srw != ACPI_BUS_NUMBER_RANGE) 144fc396574Srw continue; 145fc396574Srw *subbus = (uchar_t)rp->Data.Address32.Maximum; 146fc396574Srw dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 147fc396574Srw break; 148fc396574Srw case ACPI_RESOURCE_TYPE_ADDRESS64: 149fc396574Srw if (rp->Data.Address.ResourceType 150fc396574Srw != ACPI_BUS_NUMBER_RANGE) 151fc396574Srw continue; 152fc396574Srw *subbus = (uchar_t)rp->Data.Address64.Maximum; 153fc396574Srw dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 154fc396574Srw break; 155fc396574Srw case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 156fc396574Srw if (rp->Data.Address.ResourceType 157fc396574Srw != ACPI_BUS_NUMBER_RANGE) 158fc396574Srw continue; 159fc396574Srw *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 160fc396574Srw dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 161fc396574Srw break; 162fc396574Srw default: 163fc396574Srw dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 164fc396574Srw continue; 165fc396574Srw } 166fc396574Srw 167fc396574Srw /* found the bus-range resource */ 168fc396574Srw dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 169fc396574Srw rv = AE_OK; 170fc396574Srw 171fc396574Srw /* This breaks out of the resource scanning loop */ 172fc396574Srw break; 173fc396574Srw } 174fc396574Srw 175fc396574Srw AcpiOsFree(rb.Pointer); 176fc396574Srw if (rv != AE_OK) 177fc396574Srw cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 178fc396574Srw 179fc396574Srw return (rv); 180fc396574Srw 181fc396574Srw } 182fc396574Srw 1837c478bd9Sstevel@tonic-gate /* 1847c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 1857c478bd9Sstevel@tonic-gate */ 1867c478bd9Sstevel@tonic-gate void 1877c478bd9Sstevel@tonic-gate pci_setup_tree() 1887c478bd9Sstevel@tonic-gate { 1897c478bd9Sstevel@tonic-gate uchar_t i, root_bus_addr = 0; 1907c478bd9Sstevel@tonic-gate 191f55ce205Sszhou alloc_res_array(); 1927c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 1937c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 1947c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 1957c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 1967c478bd9Sstevel@tonic-gate } 1977c478bd9Sstevel@tonic-gate 1987c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 1997c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 2007c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 2017c478bd9Sstevel@tonic-gate 2027c478bd9Sstevel@tonic-gate /* 2037c478bd9Sstevel@tonic-gate * Now enumerate peer busses 2047c478bd9Sstevel@tonic-gate * 2057c478bd9Sstevel@tonic-gate * We loop till pci_bios_nbus. On most systems, there is 2067c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 2077c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 2087c478bd9Sstevel@tonic-gate * 2097c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 2107c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 2117c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 2127c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 2137c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 2147c478bd9Sstevel@tonic-gate * device below. 2157c478bd9Sstevel@tonic-gate */ 2167c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_bios_nbus; i++) { 2177c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 2187c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 2197c478bd9Sstevel@tonic-gate } 2207c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 221b1f176e8Sjg 222b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 223b1f176e8Sjg add_bus_slot_names_prop(i); 2247c478bd9Sstevel@tonic-gate } 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate } 2277c478bd9Sstevel@tonic-gate 22825145214Smyers /* 22925145214Smyers * >0 = present, 0 = not present, <0 = error 23025145214Smyers */ 23125145214Smyers static int 23225145214Smyers pci_bbn_present(int bus) 23325145214Smyers { 23425145214Smyers ACPI_HANDLE hdl; 23525145214Smyers ACPI_BUFFER rb; 23625145214Smyers int rv; 23725145214Smyers 23825145214Smyers /* no dip means no _BBN */ 23925145214Smyers if (pci_bus_res[bus].dip == NULL) 24025145214Smyers return (0); 24125145214Smyers 24225145214Smyers rv = acpica_find_pciobj(pci_bus_res[bus].dip, &hdl); 24325145214Smyers if (rv != AE_OK) 24425145214Smyers return (-1); 24525145214Smyers 24625145214Smyers rb.Length = ACPI_ALLOCATE_BUFFER; 24725145214Smyers 24825145214Smyers rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 24925145214Smyers 25025145214Smyers if (rb.Length > 0) 25125145214Smyers AcpiOsFree(rb.Pointer); 25225145214Smyers 25325145214Smyers if (rv == AE_OK) 25425145214Smyers return (1); 25525145214Smyers else if (rv == AE_NOT_FOUND) 25625145214Smyers return (0); 25725145214Smyers else 25825145214Smyers return (-1); 25925145214Smyers } 26025145214Smyers 26125145214Smyers /* 26225145214Smyers * Return non-zero if any PCI bus in the system has an associated 26325145214Smyers * _BBN object, 0 otherwise. 26425145214Smyers */ 26525145214Smyers static int 26625145214Smyers pci_roots_have_bbn(void) 26725145214Smyers { 26825145214Smyers int i; 26925145214Smyers 27025145214Smyers /* 27125145214Smyers * Scan the PCI busses and look for at least 1 _BBN 27225145214Smyers */ 27325145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 27425145214Smyers /* skip non-root (peer) PCI busses */ 27525145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 27625145214Smyers continue; 27725145214Smyers 27825145214Smyers if (pci_bbn_present(i) > 0) 27925145214Smyers return (1); 28025145214Smyers } 28125145214Smyers return (0); 28225145214Smyers 28325145214Smyers } 28425145214Smyers 28525145214Smyers /* 28625145214Smyers * return non-zero if the machine is one on which we renumber 28725145214Smyers * the internal pci unit-addresses 28825145214Smyers */ 28925145214Smyers static int 29025145214Smyers pci_bus_renumber() 29125145214Smyers { 292*ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 29325145214Smyers 294*ee8c1d4aSdm if (pci_bus_always_renumber) 29525145214Smyers return (1); 296*ee8c1d4aSdm 297*ee8c1d4aSdm /* get the FADT */ 298*ee8c1d4aSdm if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 299*ee8c1d4aSdm (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 30025145214Smyers return (0); 30125145214Smyers 302*ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 303*ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 304*ee8c1d4aSdm return (0); 305*ee8c1d4aSdm else 306*ee8c1d4aSdm return (1); 30725145214Smyers } 30825145214Smyers 30925145214Smyers /* 31025145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 31125145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 31225145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 31325145214Smyers * _BBN object associated with each peer bus; use the presence 31425145214Smyers * of this object to remove gaps in the numbering of the peer 31525145214Smyers * PCI bus unit-addresses - only peer busses with an associated 31625145214Smyers * _BBN are counted. 31725145214Smyers */ 31825145214Smyers static void 31925145214Smyers pci_renumber_root_busses(void) 32025145214Smyers { 32125145214Smyers int pci_regs[] = {0, 0, 0}; 32225145214Smyers int i, root_addr = 0; 32325145214Smyers 324*ee8c1d4aSdm /* 325*ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 326*ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 327*ee8c1d4aSdm * issue of upgrade changing physical device paths 328*ee8c1d4aSdm */ 32925145214Smyers if (!pci_bus_renumber()) 33025145214Smyers return; 33125145214Smyers 33225145214Smyers /* 33325145214Smyers * If we find no _BBN objects at all, we either don't need 33425145214Smyers * to do anything or can't do anything anyway 33525145214Smyers */ 33625145214Smyers if (!pci_roots_have_bbn()) 33725145214Smyers return; 33825145214Smyers 33925145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 34025145214Smyers /* skip non-root (peer) PCI busses */ 34125145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 34225145214Smyers continue; 34325145214Smyers 34425145214Smyers if (pci_bbn_present(i) < 1) { 34525145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 34625145214Smyers continue; 34725145214Smyers } 34825145214Smyers 34925145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 35025145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 35125145214Smyers /* update reg property for node */ 35225145214Smyers pci_bus_res[i].root_addr = root_addr; 35325145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 35425145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 35525145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 35625145214Smyers } 35725145214Smyers root_addr++; 35825145214Smyers } 35925145214Smyers } 36025145214Smyers 361aaba6dfeSmyers static void 362aaba6dfeSmyers remove_resource_range(struct memlist **list, int *ranges, int range_count) 363aaba6dfeSmyers { 364aaba6dfeSmyers struct range { 365aaba6dfeSmyers uint32_t base; 366aaba6dfeSmyers uint32_t len; 367aaba6dfeSmyers }; 368aaba6dfeSmyers int index; 369aaba6dfeSmyers 370aaba6dfeSmyers for (index = 0; index < range_count; index++) { 371328364c0Smyers /* all done if list is or has become empty */ 372328364c0Smyers if (*list == NULL) 373328364c0Smyers break; 374aaba6dfeSmyers (void) memlist_remove(list, 375aaba6dfeSmyers (uint64_t)((struct range *)ranges)[index].base, 376aaba6dfeSmyers (uint64_t)((struct range *)ranges)[index].len); 377aaba6dfeSmyers } 378aaba6dfeSmyers } 379aaba6dfeSmyers 380aaba6dfeSmyers static void 381aaba6dfeSmyers remove_used_resources() 382aaba6dfeSmyers { 383aaba6dfeSmyers dev_info_t *used; 384aaba6dfeSmyers int *narray; 385aaba6dfeSmyers uint_t ncount; 386aaba6dfeSmyers int status; 387aaba6dfeSmyers int bus; 388aaba6dfeSmyers 389aaba6dfeSmyers used = ddi_find_devinfo("used-resources", -1, 0); 390328364c0Smyers if (used == NULL) 391aaba6dfeSmyers return; 392aaba6dfeSmyers 393aaba6dfeSmyers status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 394aaba6dfeSmyers DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 395aaba6dfeSmyers if (status == DDI_PROP_SUCCESS) { 396aaba6dfeSmyers for (bus = 0; bus <= pci_bios_nbus; bus++) 397328364c0Smyers remove_resource_range(&pci_bus_res[bus].io_ports, 398328364c0Smyers narray, ncount / 2); 399aaba6dfeSmyers ddi_prop_free(narray); 400aaba6dfeSmyers } 401aaba6dfeSmyers 402aaba6dfeSmyers status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 403aaba6dfeSmyers DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 404aaba6dfeSmyers if (status == DDI_PROP_SUCCESS) { 405aaba6dfeSmyers for (bus = 0; bus <= pci_bios_nbus; bus++) 406328364c0Smyers remove_resource_range(&pci_bus_res[bus].mem_space, 407aaba6dfeSmyers narray, ncount / 2); 408aaba6dfeSmyers ddi_prop_free(narray); 409aaba6dfeSmyers } 410aaba6dfeSmyers } 411aaba6dfeSmyers 4127c478bd9Sstevel@tonic-gate void 4137c478bd9Sstevel@tonic-gate pci_reprogram(void) 4147c478bd9Sstevel@tonic-gate { 4157c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 4167c478bd9Sstevel@tonic-gate char *onoff; 4177c478bd9Sstevel@tonic-gate 41825145214Smyers /* 41925145214Smyers * Excise phantom roots if possible 42025145214Smyers */ 42125145214Smyers pci_renumber_root_busses(); 42225145214Smyers 423fc396574Srw /* add bus-range property for root/peer bus nodes */ 424fc396574Srw for (i = 0; i <= pci_bios_nbus; i++) { 425fc396574Srw if (pci_bus_res[i].par_bus == (uchar_t)-1) { 426fc396574Srw uchar_t subbus; 427fc396574Srw if (pci_root_subbus(i, &subbus) == AE_OK) 428fc396574Srw pci_bus_res[i].sub_bus = subbus; 429fc396574Srw add_bus_range_prop(i); 430fc396574Srw } 431fc396574Srw } 432fc396574Srw 4337c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 4347c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 4357c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 4367c478bd9Sstevel@tonic-gate pci_reconfig = 0; 4377c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 4387c478bd9Sstevel@tonic-gate } 4397c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 4407c478bd9Sstevel@tonic-gate } 4417c478bd9Sstevel@tonic-gate 442aaba6dfeSmyers /* remove used-resources from PCI resource maps */ 443aaba6dfeSmyers remove_used_resources(); 444aaba6dfeSmyers 4457c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 4467c478bd9Sstevel@tonic-gate /* configure devices not configured by bios */ 4477c478bd9Sstevel@tonic-gate if (pci_reconfig) 4487c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 4497c478bd9Sstevel@tonic-gate /* All dev programmed, so we can create available prop */ 4507c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 4517c478bd9Sstevel@tonic-gate } 4527c478bd9Sstevel@tonic-gate } 4537c478bd9Sstevel@tonic-gate 4547c478bd9Sstevel@tonic-gate /* 4557c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 4567c478bd9Sstevel@tonic-gate */ 4577c478bd9Sstevel@tonic-gate static void 4587c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 4597c478bd9Sstevel@tonic-gate { 4607c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 4617c478bd9Sstevel@tonic-gate dev_info_t *dip; 4627c478bd9Sstevel@tonic-gate 4637c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 4647c478bd9Sstevel@tonic-gate 4657c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 466fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 4677c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 4687c478bd9Sstevel@tonic-gate "#address-cells", 3); 4697c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 4707c478bd9Sstevel@tonic-gate "#size-cells", 2); 4717c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 4727c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4737c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 4747c478bd9Sstevel@tonic-gate 47570025d76Sjohnny /* 47670025d76Sjohnny * If system has PCIe bus, then create different properties 47770025d76Sjohnny */ 47870025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 47970025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 48070025d76Sjohnny "device_type", "pci"); 48170025d76Sjohnny 4827c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 4837c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 4847c478bd9Sstevel@tonic-gate pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 4857c478bd9Sstevel@tonic-gate pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 4867c478bd9Sstevel@tonic-gate pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 4877c478bd9Sstevel@tonic-gate 4887c478bd9Sstevel@tonic-gate if (bus != 0) 4897c478bd9Sstevel@tonic-gate return; 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate /* 4927c478bd9Sstevel@tonic-gate * Special treatment of bus 0: 4937c478bd9Sstevel@tonic-gate * If no resource from MPSPEC/HRT, copy pcimem from boot 494aaba6dfeSmyers * and make I/O space the entire range starting at 0x100. There 495aaba6dfeSmyers * is no difference between prefetchable memory or not. 4967c478bd9Sstevel@tonic-gate */ 4977c478bd9Sstevel@tonic-gate if (pci_bus_res[0].mem_space == NULL) 4987c478bd9Sstevel@tonic-gate pci_bus_res[0].mem_space = 4997c478bd9Sstevel@tonic-gate memlist_dup(bootops->boot_mem->pcimem); 500aaba6dfeSmyers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 5017c478bd9Sstevel@tonic-gate if (pci_bus_res[0].io_ports == NULL) 502aaba6dfeSmyers memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xff00); 5037c478bd9Sstevel@tonic-gate } 5047c478bd9Sstevel@tonic-gate 5057c478bd9Sstevel@tonic-gate /* 5067c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 5077c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 5087c478bd9Sstevel@tonic-gate * to hold the already configured device details. 5097c478bd9Sstevel@tonic-gate */ 5107c478bd9Sstevel@tonic-gate void 5117c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 5127c478bd9Sstevel@tonic-gate { 5137c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 5147c478bd9Sstevel@tonic-gate ushort_t venid; 5157c478bd9Sstevel@tonic-gate dev_info_t *dip; 5167c478bd9Sstevel@tonic-gate struct pci_devfunc { 5177c478bd9Sstevel@tonic-gate struct pci_devfunc *next; 5187c478bd9Sstevel@tonic-gate dev_info_t *dip; 5197c478bd9Sstevel@tonic-gate uchar_t bus; 5207c478bd9Sstevel@tonic-gate uchar_t dev; 5217c478bd9Sstevel@tonic-gate uchar_t func; 5227c478bd9Sstevel@tonic-gate } *devlist = NULL, *entry; 5237c478bd9Sstevel@tonic-gate 5247c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 5257c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 526bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 527bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 5287c478bd9Sstevel@tonic-gate } else 5297c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 5307c478bd9Sstevel@tonic-gate 5317c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 5327c478bd9Sstevel@tonic-gate nfunc = 1; 5337c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 5347c478bd9Sstevel@tonic-gate 5357c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 5367c478bd9Sstevel@tonic-gate dev, func); 5377c478bd9Sstevel@tonic-gate 5387c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 539bd87be88Ssethg 5407c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 5417c478bd9Sstevel@tonic-gate /* no function at this address */ 5427c478bd9Sstevel@tonic-gate continue; 5437c478bd9Sstevel@tonic-gate } 5447c478bd9Sstevel@tonic-gate 5457c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 5467c478bd9Sstevel@tonic-gate if (header == 0xff) { 5477c478bd9Sstevel@tonic-gate continue; /* illegal value */ 5487c478bd9Sstevel@tonic-gate } 5497c478bd9Sstevel@tonic-gate 5507c478bd9Sstevel@tonic-gate /* 5517c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 5527c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 5537c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 5547c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 5557c478bd9Sstevel@tonic-gate */ 5567c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 5577c478bd9Sstevel@tonic-gate nfunc = 8; 5587c478bd9Sstevel@tonic-gate } 55946e9e839Smyers 560bd87be88Ssethg if (config_op == CONFIG_FIX) { 561bd87be88Ssethg /* 562bd87be88Ssethg * If we're processing PCI fixes, no dip 563bd87be88Ssethg * will be returned. 564bd87be88Ssethg */ 565bd87be88Ssethg (void) process_devfunc(bus, dev, func, header, 566bd87be88Ssethg venid, config_op); 567bd87be88Ssethg 568bd87be88Ssethg } else if (config_op == CONFIG_INFO) { 569ebf3afa8Sdmick /* 570ebf3afa8Sdmick * Create the node, unconditionally, on the 571ebf3afa8Sdmick * first pass only. It may still need 572ebf3afa8Sdmick * resource assignment, which will be 573ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 574ebf3afa8Sdmick */ 575bd87be88Ssethg dip = process_devfunc(bus, dev, func, header, 576ebf3afa8Sdmick venid, config_op); 577db063408Sdmick /* 578db063408Sdmick * If dip isn't null, put on a list to 579db063408Sdmick * save for reprogramming when config_op 580db063408Sdmick * is CONFIG_NEW. 581db063408Sdmick */ 582db063408Sdmick 583db063408Sdmick if (dip) { 584db063408Sdmick entry = kmem_alloc(sizeof (*entry), 585db063408Sdmick KM_SLEEP); 586db063408Sdmick entry->dip = dip; 587db063408Sdmick entry->dev = dev; 588db063408Sdmick entry->func = func; 589db063408Sdmick entry->next = devlist; 590db063408Sdmick devlist = entry; 591db063408Sdmick } 5927c478bd9Sstevel@tonic-gate } 5937c478bd9Sstevel@tonic-gate } 5947c478bd9Sstevel@tonic-gate } 5957c478bd9Sstevel@tonic-gate 5967c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 5977c478bd9Sstevel@tonic-gate devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 5987c478bd9Sstevel@tonic-gate while (devlist) { 5997c478bd9Sstevel@tonic-gate entry = devlist; 6007c478bd9Sstevel@tonic-gate devlist = entry->next; 6017c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, 6027c478bd9Sstevel@tonic-gate "!reprogram pci device [%d/%d/%d] (%s)", 6037c478bd9Sstevel@tonic-gate bus, entry->dev, entry->func, 6047c478bd9Sstevel@tonic-gate ddi_driver_name(entry->dip)); 6057c478bd9Sstevel@tonic-gate (void) add_reg_props(entry->dip, bus, entry->dev, 6067c478bd9Sstevel@tonic-gate entry->func, CONFIG_UPDATE, 0); 6077c478bd9Sstevel@tonic-gate kmem_free(entry, sizeof (*entry)); 6087c478bd9Sstevel@tonic-gate } 6097c478bd9Sstevel@tonic-gate pci_bus_res[bus].privdata = NULL; 610bd87be88Ssethg } else if (config_op != CONFIG_FIX) { 6117c478bd9Sstevel@tonic-gate pci_bus_res[bus].privdata = devlist; 6127c478bd9Sstevel@tonic-gate } 6137c478bd9Sstevel@tonic-gate } 6147c478bd9Sstevel@tonic-gate 6157c478bd9Sstevel@tonic-gate static int 6167c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 6177c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 6187c478bd9Sstevel@tonic-gate { 6197c478bd9Sstevel@tonic-gate static int prop_exist = -1; 6207c478bd9Sstevel@tonic-gate static char *pciide_str; 6217c478bd9Sstevel@tonic-gate char compat[32]; 6227c478bd9Sstevel@tonic-gate 6237c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 6247c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 6257c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 6267c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 6277c478bd9Sstevel@tonic-gate } 6287c478bd9Sstevel@tonic-gate 6297c478bd9Sstevel@tonic-gate if (!prop_exist) 6307c478bd9Sstevel@tonic-gate return (0); 6317c478bd9Sstevel@tonic-gate 6327c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 6337c478bd9Sstevel@tonic-gate if (subvenid) { 6347c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 6357c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 6367c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 6377c478bd9Sstevel@tonic-gate return (1); 6387c478bd9Sstevel@tonic-gate 6397c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 6407c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 6417c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 6427c478bd9Sstevel@tonic-gate return (1); 6437c478bd9Sstevel@tonic-gate 6447c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 6457c478bd9Sstevel@tonic-gate subvenid, subdevid); 6467c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 6477c478bd9Sstevel@tonic-gate return (1); 6487c478bd9Sstevel@tonic-gate } 6497c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 6507c478bd9Sstevel@tonic-gate venid, devid, revid); 6517c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 6527c478bd9Sstevel@tonic-gate return (1); 6537c478bd9Sstevel@tonic-gate 6547c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 6557c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 6567c478bd9Sstevel@tonic-gate return (1); 6577c478bd9Sstevel@tonic-gate 6587c478bd9Sstevel@tonic-gate return (0); 6597c478bd9Sstevel@tonic-gate } 6607c478bd9Sstevel@tonic-gate 6617c478bd9Sstevel@tonic-gate static int 6627c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 6637c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 6647c478bd9Sstevel@tonic-gate { 6657c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 6667c478bd9Sstevel@tonic-gate ushort_t venid; 6677c478bd9Sstevel@tonic-gate ushort_t devid; 6687c478bd9Sstevel@tonic-gate } *entry; 6697c478bd9Sstevel@tonic-gate 6707c478bd9Sstevel@tonic-gate /* XXX SATA devices: need a way to add dynamically */ 6717c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 6727c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 6737c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 6747c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 6757c478bd9Sstevel@tonic-gate {0, 0} 6767c478bd9Sstevel@tonic-gate }; 6777c478bd9Sstevel@tonic-gate 6787c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 6797c478bd9Sstevel@tonic-gate return (0); 6807c478bd9Sstevel@tonic-gate 6817c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 6827c478bd9Sstevel@tonic-gate return (1); 6837c478bd9Sstevel@tonic-gate } 6847c478bd9Sstevel@tonic-gate 6857c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 6867c478bd9Sstevel@tonic-gate return (0); 6877c478bd9Sstevel@tonic-gate } 6887c478bd9Sstevel@tonic-gate 6897c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 6907c478bd9Sstevel@tonic-gate while (entry->venid) { 6917c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 6927c478bd9Sstevel@tonic-gate return (1); 6937c478bd9Sstevel@tonic-gate entry++; 6947c478bd9Sstevel@tonic-gate } 6957c478bd9Sstevel@tonic-gate return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 6967c478bd9Sstevel@tonic-gate } 6977c478bd9Sstevel@tonic-gate 6987c478bd9Sstevel@tonic-gate static int 6997c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 7007c478bd9Sstevel@tonic-gate { 7017c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 7027c478bd9Sstevel@tonic-gate 0x000100, 7037c478bd9Sstevel@tonic-gate 0x030000, 7047c478bd9Sstevel@tonic-gate 0x030001 7057c478bd9Sstevel@tonic-gate }; 7067c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 7077c478bd9Sstevel@tonic-gate 7087c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 7097c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 7107c478bd9Sstevel@tonic-gate return (1); 7117c478bd9Sstevel@tonic-gate } 7127c478bd9Sstevel@tonic-gate return (0); 7137c478bd9Sstevel@tonic-gate } 7147c478bd9Sstevel@tonic-gate 715bd87be88Ssethg static void 716bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 717bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 718bd87be88Ssethg { 719bd87be88Ssethg struct pci_fixundo *newundo; 720bd87be88Ssethg 721bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 722bd87be88Ssethg 723bd87be88Ssethg /* 724bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 725bd87be88Ssethg * bit back on at a later time. 726bd87be88Ssethg */ 727bd87be88Ssethg newundo->bus = bus; 728bd87be88Ssethg newundo->dev = dev; 729bd87be88Ssethg newundo->fn = fn; 730bd87be88Ssethg newundo->undofn = undofn; 731bd87be88Ssethg newundo->next = undolist; 732bd87be88Ssethg 733bd87be88Ssethg /* add to the undo list in LIFO order */ 734bd87be88Ssethg undolist = newundo; 735bd87be88Ssethg } 736bd87be88Ssethg 737bd87be88Ssethg void 738bd87be88Ssethg add_pci_fixes(void) 739bd87be88Ssethg { 740bd87be88Ssethg int i; 741bd87be88Ssethg 742bd87be88Ssethg for (i = 0; i <= pci_bios_nbus; i++) { 743bd87be88Ssethg /* 744bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 745bd87be88Ssethg * This must be done before the main enumeration loop because 746bd87be88Ssethg * some fixes must be applied to devices normally encountered 747bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 748bd87be88Ssethg * applied before scanning device 6, applying fixes in the 749bd87be88Ssethg * normal enumeration loop would obviously be too late). 750bd87be88Ssethg */ 751bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 752bd87be88Ssethg } 753bd87be88Ssethg } 754bd87be88Ssethg 755bd87be88Ssethg void 756bd87be88Ssethg undo_pci_fixes(void) 757bd87be88Ssethg { 758bd87be88Ssethg struct pci_fixundo *nextundo; 759bd87be88Ssethg uint8_t bus, dev, fn; 760bd87be88Ssethg 761bd87be88Ssethg /* 762bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 763bd87be88Ssethg * fixes may require selective undo. 764bd87be88Ssethg */ 765bd87be88Ssethg while (undolist != NULL) { 766bd87be88Ssethg 767bd87be88Ssethg bus = undolist->bus; 768bd87be88Ssethg dev = undolist->dev; 769bd87be88Ssethg fn = undolist->fn; 770bd87be88Ssethg 771bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 772bd87be88Ssethg 773bd87be88Ssethg nextundo = undolist->next; 774bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 775bd87be88Ssethg undolist = nextundo; 776bd87be88Ssethg } 777bd87be88Ssethg } 778bd87be88Ssethg 779bd87be88Ssethg static void 780bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 781bd87be88Ssethg { 782bd87be88Ssethg uint8_t val8; 783bd87be88Ssethg 784bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 785bd87be88Ssethg /* 786bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 787bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 788bd87be88Ssethg */ 789bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 790bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 791bd87be88Ssethg } 792bd87be88Ssethg 793bd87be88Ssethg static void 794bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 795bd87be88Ssethg { 796bd87be88Ssethg uint8_t val8; 797bd87be88Ssethg 798bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 799bd87be88Ssethg 800bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 801bd87be88Ssethg return; 802bd87be88Ssethg 803bd87be88Ssethg /* 804bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 805bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 806bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 807bd87be88Ssethg */ 808bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 809bd87be88Ssethg 810bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 811bd87be88Ssethg 812bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 813bd87be88Ssethg } 814bd87be88Ssethg 8157c478bd9Sstevel@tonic-gate static dev_info_t * 816bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 8177c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 8187c478bd9Sstevel@tonic-gate { 8197c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 8207c478bd9Sstevel@tonic-gate dev_info_t *dip; 821c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 8227c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 82370025d76Sjohnny ushort_t slot_num; 8247c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 8257c478bd9Sstevel@tonic-gate int reprogram = 0, pciide; 8267c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 82770025d76Sjohnny int pciex = 0; 82870025d76Sjohnny ushort_t is_pci_bridge = 0; 8297c478bd9Sstevel@tonic-gate 8307c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 8317c478bd9Sstevel@tonic-gate 8327c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 8337c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 8347c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 8357c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 8367c478bd9Sstevel@tonic-gate break; 8377c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 8387c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 8397c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 8407c478bd9Sstevel@tonic-gate break; 8417c478bd9Sstevel@tonic-gate default: 8427c478bd9Sstevel@tonic-gate subvenid = 0; 8437c478bd9Sstevel@tonic-gate subdevid = 0; 8447c478bd9Sstevel@tonic-gate break; 8457c478bd9Sstevel@tonic-gate } 8467c478bd9Sstevel@tonic-gate 847bd87be88Ssethg if (config_op == CONFIG_FIX) { 848bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 849bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 850bd87be88Ssethg } 851bd87be88Ssethg return (NULL); 852bd87be88Ssethg } 853bd87be88Ssethg 8547c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 8557c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 8567c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 8577c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 8587c478bd9Sstevel@tonic-gate 8597c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 8607c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 8617c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 862c8589f13Ssethg progcl = classcode & 0xff; 8637c478bd9Sstevel@tonic-gate pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 8647c478bd9Sstevel@tonic-gate subvenid, subdevid); 8657c478bd9Sstevel@tonic-gate 8667c478bd9Sstevel@tonic-gate if (pciide) 8677c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 8687c478bd9Sstevel@tonic-gate else if (is_display(classcode)) 8697c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 8707c478bd9Sstevel@tonic-gate else if (subvenid != 0) 8717c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 8727c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 8737c478bd9Sstevel@tonic-gate else 8747c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 8757c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 8767c478bd9Sstevel@tonic-gate 8777c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 8787c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) { 8797c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 8807c478bd9Sstevel@tonic-gate } 8817c478bd9Sstevel@tonic-gate 8827c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 8837c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 8847c478bd9Sstevel@tonic-gate 88500d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 88600d0963fSdilpreet &is_pci_bridge) == B_TRUE) 88700d0963fSdilpreet pciex = 1; 88800d0963fSdilpreet 8897c478bd9Sstevel@tonic-gate /* add properties */ 8907c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 8917c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 8927c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 8937c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 8947c478bd9Sstevel@tonic-gate "class-code", classcode); 8957c478bd9Sstevel@tonic-gate if (func == 0) 8967c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 8977c478bd9Sstevel@tonic-gate else 8987c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 8997c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 9007c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 9017c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 9027c478bd9Sstevel@tonic-gate 903ebf3afa8Sdmick /* add device_type for display nodes */ 904ebf3afa8Sdmick if (is_display(classcode)) { 905ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 906ebf3afa8Sdmick "device_type", "display"); 907ebf3afa8Sdmick } 9087c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 9097c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 9107c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 9117c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 9127c478bd9Sstevel@tonic-gate 9137c478bd9Sstevel@tonic-gate if (subvenid != 0) { 9147c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9157c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 9167c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9177c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 9187c478bd9Sstevel@tonic-gate } 91970025d76Sjohnny if (!pciex) 92070025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 92170025d76Sjohnny "min-grant", mingrant); 92270025d76Sjohnny if (!pciex) 92370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 92470025d76Sjohnny "max-latency", maxlatency); 9257c478bd9Sstevel@tonic-gate } 9267c478bd9Sstevel@tonic-gate 9277c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 9287c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 9297c478bd9Sstevel@tonic-gate if (intr != 0) 9307c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9317c478bd9Sstevel@tonic-gate "interrupts", intr); 9327c478bd9Sstevel@tonic-gate 9337c478bd9Sstevel@tonic-gate /* 9347c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 9357c478bd9Sstevel@tonic-gate */ 9367c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 9377c478bd9Sstevel@tonic-gate 9387c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9397c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 94070025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 9417c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 9427c478bd9Sstevel@tonic-gate "fast-back-to-back"); 94370025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 9447c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 9457c478bd9Sstevel@tonic-gate "66mhz-capable"); 9467c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 9477c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 9487c478bd9Sstevel@tonic-gate "udf-supported"); 949e14a96cdSanish if (pciex && slot_num) 95070025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 95170025d76Sjohnny "physical-slot#", slot_num); 9527c478bd9Sstevel@tonic-gate 9537c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 9547c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 9557c478bd9Sstevel@tonic-gate 95670025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 95770025d76Sjohnny add_ppb_props(dip, bus, dev, func, pciex); 95870025d76Sjohnny 959c8589f13Ssethg if (config_op == CONFIG_INFO && 960c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 961c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 962c8589f13Ssethg } 963c8589f13Ssethg 96470025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 96570025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 96670025d76Sjohnny (func == 0)) 9678a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 96870025d76Sjohnny 96970025d76Sjohnny if (pciex && is_pci_bridge) 97070025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 97170025d76Sjohnny (char *)"PCIe-PCI bridge"); 97270025d76Sjohnny else 97370025d76Sjohnny add_model_prop(dip, classcode); 9747c478bd9Sstevel@tonic-gate 9757c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 97670025d76Sjohnny revid, classcode, pciex); 9777c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 9787c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 9797c478bd9Sstevel@tonic-gate 9807c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 9817c478bd9Sstevel@tonic-gate if (pciide) { 9827c478bd9Sstevel@tonic-gate dev_info_t *cdip; 9837c478bd9Sstevel@tonic-gate 9847c478bd9Sstevel@tonic-gate /* 9857c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 9867c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 9877c478bd9Sstevel@tonic-gate */ 9887c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 9897c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 9907c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9917c478bd9Sstevel@tonic-gate "#address-cells", 1); 9927c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 9937c478bd9Sstevel@tonic-gate "#size-cells", 0); 9947c478bd9Sstevel@tonic-gate 9957c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 9967c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 997fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 9987c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 9997c478bd9Sstevel@tonic-gate "reg", 0); 10007c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 10017c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1002fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 10037c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 10047c478bd9Sstevel@tonic-gate "reg", 1); 10057c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 10067c478bd9Sstevel@tonic-gate 10077c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 10087c478bd9Sstevel@tonic-gate } 10097c478bd9Sstevel@tonic-gate 101070025d76Sjohnny 10117c478bd9Sstevel@tonic-gate if (reprogram) 10127c478bd9Sstevel@tonic-gate return (dip); 10137c478bd9Sstevel@tonic-gate return (NULL); 10147c478bd9Sstevel@tonic-gate } 10157c478bd9Sstevel@tonic-gate 10167c478bd9Sstevel@tonic-gate /* 10177c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 10187c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 101970025d76Sjohnny * (Also used for PCI-Express devices). 10207c478bd9Sstevel@tonic-gate * 10217c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 10227c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 10237c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 10247c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 10257c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 10267c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 10277c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 10287c478bd9Sstevel@tonic-gate * 10297c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 10307c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 10317c478bd9Sstevel@tonic-gate * 103270025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 103370025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 103470025d76Sjohnny * 10357c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 10367c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 10377c478bd9Sstevel@tonic-gate */ 10387c478bd9Sstevel@tonic-gate void 10397c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 104070025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 104170025d76Sjohnny int pciex) 10427c478bd9Sstevel@tonic-gate { 104370025d76Sjohnny int i = 0; 104470025d76Sjohnny int size = COMPAT_BUFSIZE; 104570025d76Sjohnny char *compat[13]; 10467c478bd9Sstevel@tonic-gate char *buf, *curr; 10477c478bd9Sstevel@tonic-gate 10487c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 10497c478bd9Sstevel@tonic-gate 105070025d76Sjohnny if (pciex) { 105170025d76Sjohnny if (subvenid) { 105270025d76Sjohnny compat[i++] = curr; /* form 0 */ 105370025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 105470025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 105570025d76Sjohnny size -= strlen(curr) + 1; 105670025d76Sjohnny curr += strlen(curr) + 1; 105770025d76Sjohnny 105870025d76Sjohnny compat[i++] = curr; /* form 1 */ 105970025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 106070025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 106170025d76Sjohnny size -= strlen(curr) + 1; 106270025d76Sjohnny curr += strlen(curr) + 1; 106370025d76Sjohnny 106470025d76Sjohnny } 106570025d76Sjohnny compat[i++] = curr; /* form 3 */ 106670025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 106770025d76Sjohnny vendorid, deviceid, revid); 106870025d76Sjohnny size -= strlen(curr) + 1; 106970025d76Sjohnny curr += strlen(curr) + 1; 107070025d76Sjohnny 107170025d76Sjohnny compat[i++] = curr; /* form 4 */ 107270025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 107370025d76Sjohnny size -= strlen(curr) + 1; 107470025d76Sjohnny curr += strlen(curr) + 1; 107570025d76Sjohnny 107670025d76Sjohnny compat[i++] = curr; /* form 5 */ 107770025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 107870025d76Sjohnny size -= strlen(curr) + 1; 107970025d76Sjohnny curr += strlen(curr) + 1; 108070025d76Sjohnny 108170025d76Sjohnny compat[i++] = curr; /* form 6 */ 108270025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 108370025d76Sjohnny (classcode >> 8)); 108470025d76Sjohnny size -= strlen(curr) + 1; 108570025d76Sjohnny curr += strlen(curr) + 1; 108670025d76Sjohnny } 108770025d76Sjohnny 10887c478bd9Sstevel@tonic-gate if (subvenid) { 10897c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 10907c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 10917c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 10927c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 10937c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 10947c478bd9Sstevel@tonic-gate 10957c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 10967c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 10977c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 10987c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 10997c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 11007c478bd9Sstevel@tonic-gate 11017c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 2 */ 110270025d76Sjohnny (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 11037c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 11047c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 11057c478bd9Sstevel@tonic-gate } 11067c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 11077c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 11087c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 11097c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 11107c478bd9Sstevel@tonic-gate 11117c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 11127c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 11137c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 11147c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 11157c478bd9Sstevel@tonic-gate 11167c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 11177c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 11187c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 11197c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 11207c478bd9Sstevel@tonic-gate 11217c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 11227c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 112370025d76Sjohnny size -= strlen(curr) + 1; 112470025d76Sjohnny curr += strlen(curr) + 1; 11257c478bd9Sstevel@tonic-gate 11267c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 11277c478bd9Sstevel@tonic-gate "compatible", compat, i); 11287c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 11297c478bd9Sstevel@tonic-gate } 11307c478bd9Sstevel@tonic-gate 11317c478bd9Sstevel@tonic-gate /* 11327c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 11337c478bd9Sstevel@tonic-gate * 11347c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 11357c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 11367c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 11377c478bd9Sstevel@tonic-gate * mode BAR or not. 11387c478bd9Sstevel@tonic-gate */ 11397c478bd9Sstevel@tonic-gate /* 11407c478bd9Sstevel@tonic-gate * config info for pci-ide devices 11417c478bd9Sstevel@tonic-gate */ 11427c478bd9Sstevel@tonic-gate static struct { 11437c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 11447c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 11457c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 11467c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 11477c478bd9Sstevel@tonic-gate } pciide_bar[] = { 11487c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 11497c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 11507c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 11517c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 11527c478bd9Sstevel@tonic-gate }; 11537c478bd9Sstevel@tonic-gate 11547c478bd9Sstevel@tonic-gate static int 11557c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 11567c478bd9Sstevel@tonic-gate { 11577c478bd9Sstevel@tonic-gate int hard_decode = 0; 11587c478bd9Sstevel@tonic-gate 11597c478bd9Sstevel@tonic-gate /* 11607c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 11617c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 11627c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 11637c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 11647c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 11657c478bd9Sstevel@tonic-gate */ 11667c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 11677c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 11687c478bd9Sstevel@tonic-gate 11697c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 11707c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 11717c478bd9Sstevel@tonic-gate } else { 11727c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 11737c478bd9Sstevel@tonic-gate hard_decode = 1; 11747c478bd9Sstevel@tonic-gate } 11757c478bd9Sstevel@tonic-gate } 11767c478bd9Sstevel@tonic-gate 11777c478bd9Sstevel@tonic-gate /* 11787c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 11797c478bd9Sstevel@tonic-gate */ 11807c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 11817c478bd9Sstevel@tonic-gate *basep = 0; 11827c478bd9Sstevel@tonic-gate *lenp = 0; 11837c478bd9Sstevel@tonic-gate hard_decode = 0; 11847c478bd9Sstevel@tonic-gate } 11857c478bd9Sstevel@tonic-gate 11867c478bd9Sstevel@tonic-gate return (hard_decode); 11877c478bd9Sstevel@tonic-gate } 11887c478bd9Sstevel@tonic-gate 11897c478bd9Sstevel@tonic-gate 11907c478bd9Sstevel@tonic-gate /* 11917c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 11927c478bd9Sstevel@tonic-gate */ 11937c478bd9Sstevel@tonic-gate static int 11947c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 11957c478bd9Sstevel@tonic-gate int config_op, int pciide) 11967c478bd9Sstevel@tonic-gate { 11977c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 11987c478bd9Sstevel@tonic-gate ushort_t bar_sz; 11997c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 12007c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 12017c478bd9Sstevel@tonic-gate ushort_t offset, end; 12027c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 12037c478bd9Sstevel@tonic-gate uint_t phys_hi; 12047c478bd9Sstevel@tonic-gate struct memlist **io_res, **mres, **mem_res, **pmem_res; 120546e9e839Smyers uint16_t cmd_reg; 12067c478bd9Sstevel@tonic-gate 12077c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 12087c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 1209ebf3afa8Sdmick int nreg, nasgn, enable = 0; 12107c478bd9Sstevel@tonic-gate 12117c478bd9Sstevel@tonic-gate io_res = &pci_bus_res[bus].io_ports; 12127c478bd9Sstevel@tonic-gate mem_res = &pci_bus_res[bus].mem_space; 12137c478bd9Sstevel@tonic-gate if (bus == 0) /* for bus 0, there is only mem_space */ 12147c478bd9Sstevel@tonic-gate pmem_res = mem_res; 12157c478bd9Sstevel@tonic-gate else 12167c478bd9Sstevel@tonic-gate pmem_res = &pci_bus_res[bus].pmem_space; 12177c478bd9Sstevel@tonic-gate 12187c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 12197c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 12207c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 12217c478bd9Sstevel@tonic-gate nasgn = 0; 12227c478bd9Sstevel@tonic-gate 12237c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 12247c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 12257c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 12267c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 12277c478bd9Sstevel@tonic-gate 12287c478bd9Sstevel@tonic-gate switch (header) { 12297c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 12307c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 12317c478bd9Sstevel@tonic-gate break; 12327c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 12337c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 12347c478bd9Sstevel@tonic-gate break; 12357c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 12367c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 12377c478bd9Sstevel@tonic-gate break; 12387c478bd9Sstevel@tonic-gate default: 12397c478bd9Sstevel@tonic-gate max_basereg = 0; 12407c478bd9Sstevel@tonic-gate break; 12417c478bd9Sstevel@tonic-gate } 12427c478bd9Sstevel@tonic-gate 12437c478bd9Sstevel@tonic-gate /* 12447c478bd9Sstevel@tonic-gate * Create the register property by saving the current 12458d34f104Smyers * value of the base register. Write 0xffffffff to the 12468d34f104Smyers * base register. Read the value back to determine the 12478d34f104Smyers * required size of the address space. Restore the base 12488d34f104Smyers * register contents. 12498d34f104Smyers * 12508d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 12518d34f104Smyers * since no driver is yet attached to this device, and disabling 12528d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 12538d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 12548d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 12558d34f104Smyers * Spec V1.2). 12567c478bd9Sstevel@tonic-gate */ 12577c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 12587c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 12597c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 12607c478bd9Sstevel@tonic-gate int hard_decode = 0; 12617c478bd9Sstevel@tonic-gate 12627c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 12637c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 12647c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 12657c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 12667c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 12677c478bd9Sstevel@tonic-gate 12687c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 12697c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 12707c478bd9Sstevel@tonic-gate /* i/o space */ 12717c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 12727c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 12737c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 12747c478bd9Sstevel@tonic-gate 12757c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 12767c478bd9Sstevel@tonic-gate if (pciide) { 1277f088817aSyt if (subclass != PCI_MASS_IDE) 12787c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 12797c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 12807c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 12817c478bd9Sstevel@tonic-gate &base, &len); 12827c478bd9Sstevel@tonic-gate } else if (value == 0) { 12837c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 12847c478bd9Sstevel@tonic-gate continue; 12857c478bd9Sstevel@tonic-gate } 12867c478bd9Sstevel@tonic-gate 12877c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 12887c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 12897c478bd9Sstevel@tonic-gate if (!hard_decode) { 12907c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 12917c478bd9Sstevel@tonic-gate (PCI_ADDR_IO | devloc) + offset; 12927c478bd9Sstevel@tonic-gate } else { 12937c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 12947c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 12957c478bd9Sstevel@tonic-gate offset; 12967c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 12977c478bd9Sstevel@tonic-gate base & PCI_BASE_IO_ADDR_M; 12987c478bd9Sstevel@tonic-gate } 12997c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = 13007c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 13017c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 13027c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 13037c478bd9Sstevel@tonic-gate 13047c478bd9Sstevel@tonic-gate /* 13057c478bd9Sstevel@tonic-gate * first pass - gather what's there 13067c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 13077c478bd9Sstevel@tonic-gate * config - allocate regions 13087c478bd9Sstevel@tonic-gate */ 13097c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 13107c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 13117c478bd9Sstevel@tonic-gate if (*io_res && base != 0) 13127c478bd9Sstevel@tonic-gate (void) memlist_remove(io_res, 13137c478bd9Sstevel@tonic-gate (uint64_t)base, (uint64_t)len); 13147c478bd9Sstevel@tonic-gate else if (*io_res) 13157c478bd9Sstevel@tonic-gate reprogram = 1; 13167c478bd9Sstevel@tonic-gate } else if (*io_res && base == 0) { 13177c478bd9Sstevel@tonic-gate base = (uint_t)memlist_find(io_res, 1318ebf3afa8Sdmick (uint64_t)len, (uint64_t)0x4); 13197c478bd9Sstevel@tonic-gate if (base != 0) { 13207c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 13217c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 13227c478bd9Sstevel@tonic-gate base | type); 13237c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 13247c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 13257c478bd9Sstevel@tonic-gate } 13267c478bd9Sstevel@tonic-gate if (base == 0) { 13277c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 1328db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 1329db063408Sdmick " length 0x%x", 1330ebf3afa8Sdmick bus, dev, func, offset, len); 13317c478bd9Sstevel@tonic-gate } else 133246e9e839Smyers enable |= PCI_COMM_IO; 13337c478bd9Sstevel@tonic-gate } 13347c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 13357c478bd9Sstevel@tonic-gate nreg++, nasgn++; 13367c478bd9Sstevel@tonic-gate 13377c478bd9Sstevel@tonic-gate } else { 13387c478bd9Sstevel@tonic-gate /* memory space */ 13397c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 13407c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 13417c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 13427c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 13437c478bd9Sstevel@tonic-gate } else { 13447c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 13457c478bd9Sstevel@tonic-gate base_hi = 0; 13467c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 13477c478bd9Sstevel@tonic-gate } 13487c478bd9Sstevel@tonic-gate 13497c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 13507c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 13517c478bd9Sstevel@tonic-gate 13527c478bd9Sstevel@tonic-gate if (value == 0) { 13537c478bd9Sstevel@tonic-gate continue; 13547c478bd9Sstevel@tonic-gate } 13557c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 13567c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 13577c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 13587c478bd9Sstevel@tonic-gate 13597c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 13607c478bd9Sstevel@tonic-gate if (base & PCI_BASE_PREF_M) { 13617c478bd9Sstevel@tonic-gate mres = pmem_res; 13627c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 13637c478bd9Sstevel@tonic-gate } else { 13647c478bd9Sstevel@tonic-gate mres = mem_res; 13657c478bd9Sstevel@tonic-gate } 13667c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 13677c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 13687c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 13697c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 13707c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 13717c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 13727c478bd9Sstevel@tonic-gate 13737c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 13747c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 13757c478bd9Sstevel@tonic-gate if (*mres && base != 0) { 13767c478bd9Sstevel@tonic-gate (void) memlist_remove(mres, 13777c478bd9Sstevel@tonic-gate (uint64_t)base, (uint64_t)len); 13787c478bd9Sstevel@tonic-gate } else if (*mres) 13797c478bd9Sstevel@tonic-gate reprogram = 1; 13807c478bd9Sstevel@tonic-gate } else if (*mres && base == 0) { 13817c478bd9Sstevel@tonic-gate base = (uint_t)memlist_find(mres, 13827c478bd9Sstevel@tonic-gate (uint64_t)len, (uint64_t)0x1000); 13837c478bd9Sstevel@tonic-gate if (base != NULL) { 13847c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 13857c478bd9Sstevel@tonic-gate base | type); 13867c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 13877c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 13887c478bd9Sstevel@tonic-gate } 13897c478bd9Sstevel@tonic-gate 13907c478bd9Sstevel@tonic-gate if (base == 0) { 13917c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 1392ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 1393db063408Sdmick " length 0x%x", 1394ebf3afa8Sdmick bus, dev, func, offset, len); 13957c478bd9Sstevel@tonic-gate } else 139646e9e839Smyers enable |= PCI_COMM_MAE; 13977c478bd9Sstevel@tonic-gate } 13987c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 13997c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14007c478bd9Sstevel@tonic-gate } 14017c478bd9Sstevel@tonic-gate } 14027c478bd9Sstevel@tonic-gate switch (header) { 14037c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 14047c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 14057c478bd9Sstevel@tonic-gate break; 14067c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 14077c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 14087c478bd9Sstevel@tonic-gate break; 14097c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 14107c478bd9Sstevel@tonic-gate goto done; 14117c478bd9Sstevel@tonic-gate } 14127c478bd9Sstevel@tonic-gate 14137c478bd9Sstevel@tonic-gate /* 14147c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 14157c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 14167c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 14177c478bd9Sstevel@tonic-gate */ 14187c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 14197c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 14207c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 14217c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 142270025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 142370025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 142470025d76Sjohnny else 142570025d76Sjohnny value = 0; 14267c478bd9Sstevel@tonic-gate 14277c478bd9Sstevel@tonic-gate if (value != 0) { 14287c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 14297c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 14307c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 14317c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 14327c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 14337c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 14347c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 14357c478bd9Sstevel@tonic-gate nreg++, nasgn++; 143699ed6083Sszhou /* take it out of the memory resource */ 143799ed6083Sszhou if (*mem_res && base != 0) 143899ed6083Sszhou (void) memlist_remove(mem_res, 143999ed6083Sszhou (uint64_t)base, (uint64_t)len); 14407c478bd9Sstevel@tonic-gate } 14417c478bd9Sstevel@tonic-gate 14427c478bd9Sstevel@tonic-gate /* 14437c478bd9Sstevel@tonic-gate * The following are ISA resources. There are not part 14447c478bd9Sstevel@tonic-gate * of the PCI local bus resources. So don't attempt to 14457c478bd9Sstevel@tonic-gate * do resource accounting against PCI. 14467c478bd9Sstevel@tonic-gate */ 14477c478bd9Sstevel@tonic-gate 14487c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 14497c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 14507c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 14517c478bd9Sstevel@tonic-gate 14527c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 14537c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 14547c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 14557c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 14567c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 14577c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14587c478bd9Sstevel@tonic-gate 14597c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 14607c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 14617c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 14627c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 14637c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 14647c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14657c478bd9Sstevel@tonic-gate 14667c478bd9Sstevel@tonic-gate /* Video memory */ 14677c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 14687c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 14697c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 14707c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 14717c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 14727c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 14737c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14747c478bd9Sstevel@tonic-gate } 14757c478bd9Sstevel@tonic-gate 14767c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 14777c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 14787c478bd9Sstevel@tonic-gate (subclass == PCI_DISPLAY_VGA) && 14797c478bd9Sstevel@tonic-gate (progclass & PCI_DISPLAY_IF_8514)) { 14807c478bd9Sstevel@tonic-gate 14817c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 14827c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 14837c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 14847c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 14857c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 14867c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14877c478bd9Sstevel@tonic-gate 14887c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 14897c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 14907c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 14917c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 14927c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 14937c478bd9Sstevel@tonic-gate nreg++, nasgn++; 14947c478bd9Sstevel@tonic-gate } 14957c478bd9Sstevel@tonic-gate 14967c478bd9Sstevel@tonic-gate done: 14977c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 14987c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 14997c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 15007c478bd9Sstevel@tonic-gate "assigned-addresses", 15017c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 15027c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW && enable) { 15037c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, 15047c478bd9Sstevel@tonic-gate "!enable PCI device [%d/%d/%d]", bus, dev, func); 15058d34f104Smyers cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 150646e9e839Smyers cmd_reg |= (enable | PCI_COMM_ME); 15078d34f104Smyers pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 15087c478bd9Sstevel@tonic-gate } 15097c478bd9Sstevel@tonic-gate return (reprogram); 15107c478bd9Sstevel@tonic-gate } 15117c478bd9Sstevel@tonic-gate 15127c478bd9Sstevel@tonic-gate static void 151370025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 151470025d76Sjohnny int pciex) 15157c478bd9Sstevel@tonic-gate { 151670025d76Sjohnny char *dev_type; 15177c478bd9Sstevel@tonic-gate int i; 15187c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 15197c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 15207c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1521f55ce205Sszhou ASSERT(secbus <= subbus); 15227c478bd9Sstevel@tonic-gate 1523f55ce205Sszhou /* 1524f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 1525f55ce205Sszhou * such mistakes here 1526f55ce205Sszhou */ 1527f55ce205Sszhou if (subbus > pci_bios_nbus) { 1528f55ce205Sszhou pci_bios_nbus = subbus; 1529f55ce205Sszhou alloc_res_array(); 1530f55ce205Sszhou } 1531f55ce205Sszhou 1532f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 15337c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 15347c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 15357c478bd9Sstevel@tonic-gate 153670025d76Sjohnny dev_type = pciex ? "pciex" : "pci"; 153770025d76Sjohnny 15387c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 15397c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 154053273e82Ssethg /* 154153273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 154253273e82Ssethg * for peer busses because there is no other way of determining its 154353273e82Ssethg * subordinate bus number). 154453273e82Ssethg */ 15457c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 15467c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 154753273e82Ssethg /* 154853273e82Ssethg * Loop through subordinate busses, initializing their parent bus 154953273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 155053273e82Ssethg * fields may very well be further refined later, as child bridges 155153273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 155253273e82Ssethg * are not peer busses by changing their par_bus fields to anything 155353273e82Ssethg * other than -1.) 155453273e82Ssethg */ 15557c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 15567c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 15577c478bd9Sstevel@tonic-gate 15587c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 155970025d76Sjohnny "device_type", dev_type); 15607c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15617c478bd9Sstevel@tonic-gate "#address-cells", 3); 15627c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15637c478bd9Sstevel@tonic-gate "#size-cells", 2); 15647c478bd9Sstevel@tonic-gate 15657c478bd9Sstevel@tonic-gate /* 15667c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 15677c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 15687c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 15697c478bd9Sstevel@tonic-gate * prefetchable memory. 15707c478bd9Sstevel@tonic-gate */ 15717c478bd9Sstevel@tonic-gate /* io range */ 15727c478bd9Sstevel@tonic-gate val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 15737c478bd9Sstevel@tonic-gate io_range[0] = ((val & 0xf0) << 8); 15747c478bd9Sstevel@tonic-gate val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 15757c478bd9Sstevel@tonic-gate io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 15767c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 15777c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].io_ports, 15787c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 15797c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 15807c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].io_ports != NULL) { 15817c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].io_ports, 15827c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 15837c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 15847c478bd9Sstevel@tonic-gate } 15857c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 15867c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 15872269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 15882269adc8Sszhou if ((val & 0xf) == 1 && 15892269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 15902269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 15912269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 15922269adc8Sszhou } 15937c478bd9Sstevel@tonic-gate } 15947c478bd9Sstevel@tonic-gate 15957c478bd9Sstevel@tonic-gate /* mem range */ 15967c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 15977c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 15987c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 15997c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 16007c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 16017c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].mem_space, 16027c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 16037c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 16047c478bd9Sstevel@tonic-gate /* remove from parent resouce list */ 16057c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].mem_space != NULL) { 16067c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].mem_space, 16077c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 16087c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 16097c478bd9Sstevel@tonic-gate } 16107c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 16117c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 16127c478bd9Sstevel@tonic-gate } 16137c478bd9Sstevel@tonic-gate 16147c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 16157c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 16167c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 16177c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 16187c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 16197c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 16207c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].pmem_space, 16217c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 16227c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 16237c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].pmem_space != NULL) { 16247c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].pmem_space, 16257c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 16267c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 16277c478bd9Sstevel@tonic-gate } 16287c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 16297c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 16302269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 16312269adc8Sszhou if ((val & 0xf) == 1 && 16322269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 16332269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 16342269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 16352269adc8Sszhou } 16367c478bd9Sstevel@tonic-gate } 16377c478bd9Sstevel@tonic-gate 16387c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 16397c478bd9Sstevel@tonic-gate add_ppb_ranges_prop(secbus); 16407c478bd9Sstevel@tonic-gate } 16417c478bd9Sstevel@tonic-gate 164209f67678Sanish extern const struct pci_class_strings_s class_pci[]; 164309f67678Sanish extern int class_pci_items; 16447c478bd9Sstevel@tonic-gate 16457c478bd9Sstevel@tonic-gate static void 16467c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 16477c478bd9Sstevel@tonic-gate { 16487c478bd9Sstevel@tonic-gate const char *desc; 16497c478bd9Sstevel@tonic-gate int i; 16507c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 16517c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 16527c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 16537c478bd9Sstevel@tonic-gate 16547c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 16557c478bd9Sstevel@tonic-gate desc = "IDE controller"; 16567c478bd9Sstevel@tonic-gate } else { 16577c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 16587c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 16597c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 16607c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 166109f67678Sanish desc = class_pci[i].actual_desc; 16627c478bd9Sstevel@tonic-gate break; 16637c478bd9Sstevel@tonic-gate } 16647c478bd9Sstevel@tonic-gate } 166509f67678Sanish if (i == class_pci_items) 16667c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 16677c478bd9Sstevel@tonic-gate } 16687c478bd9Sstevel@tonic-gate 16697c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 16707c478bd9Sstevel@tonic-gate (char *)desc); 16717c478bd9Sstevel@tonic-gate } 16727c478bd9Sstevel@tonic-gate 16737c478bd9Sstevel@tonic-gate static void 16747c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 16757c478bd9Sstevel@tonic-gate { 16767c478bd9Sstevel@tonic-gate int bus_range[2]; 16777c478bd9Sstevel@tonic-gate 16787c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 16797c478bd9Sstevel@tonic-gate return; 16807c478bd9Sstevel@tonic-gate bus_range[0] = bus; 16817c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 16827c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 16837c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 16847c478bd9Sstevel@tonic-gate } 16857c478bd9Sstevel@tonic-gate 1686b1f176e8Sjg /* 1687b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 1688b1f176e8Sjg */ 1689b1f176e8Sjg static void 1690b1f176e8Sjg add_bus_slot_names_prop(int bus) 1691b1f176e8Sjg { 1692b1f176e8Sjg char slotprop[256]; 1693b1f176e8Sjg int len; 1694b1f176e8Sjg 1695b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1696b1f176e8Sjg if (len > 0) { 169753273e82Ssethg /* 169853273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 169953273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 170053273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 170153273e82Ssethg * subordinate to any PCI-PCI bridge). 170253273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 170353273e82Ssethg * will remove it later. 170453273e82Ssethg */ 170553273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 170653273e82Ssethg pci_bus_res[bus].dip == NULL) { 170753273e82Ssethg 1708b1f176e8Sjg create_root_bus_dip(bus); 170953273e82Ssethg } 171053273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 171153273e82Ssethg ASSERT((len % sizeof (int)) == 0); 171253273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 171353273e82Ssethg pci_bus_res[bus].dip, "slot-names", 171453273e82Ssethg (int *)slotprop, len / sizeof (int)); 171553273e82Ssethg } else { 171653273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 171753273e82Ssethg "IRQ routing table; Not adding slot-names " 171853273e82Ssethg "property for incorrect bus %d", bus); 171953273e82Ssethg } 1720b1f176e8Sjg } 1721b1f176e8Sjg } 1722b1f176e8Sjg 17237c478bd9Sstevel@tonic-gate static int 172400d0963fSdilpreet memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 17257c478bd9Sstevel@tonic-gate { 17267c478bd9Sstevel@tonic-gate if (entry == NULL) 17277c478bd9Sstevel@tonic-gate return (0); 17287c478bd9Sstevel@tonic-gate 17297c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 173000d0963fSdilpreet rp->child_high = rp->parent_high = type; 17317c478bd9Sstevel@tonic-gate rp->child_mid = rp->parent_mid = 0; 173200d0963fSdilpreet rp->child_low = rp->parent_low = (uint32_t)entry->address; 173300d0963fSdilpreet rp->size_high = 0; 173400d0963fSdilpreet rp->size_low = (uint32_t)entry->size; 17357c478bd9Sstevel@tonic-gate return (1); 17367c478bd9Sstevel@tonic-gate } 17377c478bd9Sstevel@tonic-gate 17387c478bd9Sstevel@tonic-gate static void 17397c478bd9Sstevel@tonic-gate add_ppb_ranges_prop(int bus) 17407c478bd9Sstevel@tonic-gate { 17417c478bd9Sstevel@tonic-gate int i = 0; 174200d0963fSdilpreet ppb_ranges_t *rp; 17437c478bd9Sstevel@tonic-gate 17447c478bd9Sstevel@tonic-gate rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 17457c478bd9Sstevel@tonic-gate 17467c478bd9Sstevel@tonic-gate i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 17477c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 17487c478bd9Sstevel@tonic-gate i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 17497c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 17507c478bd9Sstevel@tonic-gate i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 17517c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 17527c478bd9Sstevel@tonic-gate 17537c478bd9Sstevel@tonic-gate if (i != 0) 17547c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 17557c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip, "ranges", (int *)rp, 175600d0963fSdilpreet i * sizeof (ppb_ranges_t) / sizeof (int)); 17577c478bd9Sstevel@tonic-gate kmem_free(rp, 3 * sizeof (*rp)); 17587c478bd9Sstevel@tonic-gate } 17597c478bd9Sstevel@tonic-gate 17607c478bd9Sstevel@tonic-gate static int 17617c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 17627c478bd9Sstevel@tonic-gate { 17637c478bd9Sstevel@tonic-gate int i = 0; 17647c478bd9Sstevel@tonic-gate 17657c478bd9Sstevel@tonic-gate while (list) { 17667c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 17677c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 17687c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 17697c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 17707c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 17717c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 17727c478bd9Sstevel@tonic-gate 17737c478bd9Sstevel@tonic-gate list = list->next; 17747c478bd9Sstevel@tonic-gate sp++, i++; 17757c478bd9Sstevel@tonic-gate } 17767c478bd9Sstevel@tonic-gate return (i); 17777c478bd9Sstevel@tonic-gate } 17787c478bd9Sstevel@tonic-gate 17797c478bd9Sstevel@tonic-gate static void 17807c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 17817c478bd9Sstevel@tonic-gate { 17827c478bd9Sstevel@tonic-gate int i, count; 17837c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 17847c478bd9Sstevel@tonic-gate 17857c478bd9Sstevel@tonic-gate count = memlist_count(pci_bus_res[bus].io_ports) + 17867c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].mem_space) + 17877c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].pmem_space); 17887c478bd9Sstevel@tonic-gate 17897c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 17907c478bd9Sstevel@tonic-gate return; 17917c478bd9Sstevel@tonic-gate 17927c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 17937c478bd9Sstevel@tonic-gate i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 17947c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 17957c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 17967c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 17977c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 17987c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 17997c478bd9Sstevel@tonic-gate ASSERT(i == count); 18007c478bd9Sstevel@tonic-gate 18017c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 18027c478bd9Sstevel@tonic-gate "available", (int *)sp, 18037c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 18047c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 18057c478bd9Sstevel@tonic-gate } 1806f55ce205Sszhou 1807f55ce205Sszhou static void 1808f55ce205Sszhou alloc_res_array(void) 1809f55ce205Sszhou { 1810f55ce205Sszhou static int array_max = 0; 1811f55ce205Sszhou int old_max; 1812f55ce205Sszhou void *old_res; 1813f55ce205Sszhou 1814f55ce205Sszhou if (array_max > pci_bios_nbus + 1) 1815f55ce205Sszhou return; /* array is big enough */ 1816f55ce205Sszhou 1817f55ce205Sszhou old_max = array_max; 1818f55ce205Sszhou old_res = pci_bus_res; 1819f55ce205Sszhou 1820f55ce205Sszhou if (array_max == 0) 1821f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 1822f55ce205Sszhou 1823f55ce205Sszhou while (array_max < pci_bios_nbus + 1) 1824f55ce205Sszhou array_max <<= 1; 1825f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1826f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1827f55ce205Sszhou 1828f55ce205Sszhou if (old_res) { /* copy content and free old array */ 1829f55ce205Sszhou bcopy(old_res, pci_bus_res, 1830f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 1831f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1832f55ce205Sszhou } 1833f55ce205Sszhou } 1834c8589f13Ssethg 1835c8589f13Ssethg static void 1836c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 1837c8589f13Ssethg ushort_t deviceid) 1838c8589f13Ssethg { 1839c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 1840c8589f13Ssethg static int numioapics = 0; 1841c8589f13Ssethg dev_info_t *ioapic_node; 1842c8589f13Ssethg uint64_t physaddr; 1843c8589f13Ssethg uint32_t lobase, hibase = 0; 1844c8589f13Ssethg 1845c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 1846c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 1847c8589f13Ssethg 1848c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 1849c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 1850c8589f13Ssethg return; 1851c8589f13Ssethg 1852c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 1853c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 1854c8589f13Ssethg 1855c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 1856c8589f13Ssethg 1857c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 1858c8589f13Ssethg 1859c8589f13Ssethg /* 1860c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 1861c8589f13Ssethg */ 1862c8589f13Ssethg if (ioapicsnode == NULL) { 1863c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 1864c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 1865c8589f13Ssethg return; 1866c8589f13Ssethg } 1867c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 1868c8589f13Ssethg } 1869c8589f13Ssethg 1870c8589f13Ssethg /* 1871c8589f13Ssethg * Create a child node for this IOAPIC 1872c8589f13Ssethg */ 1873c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 1874c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 1875c8589f13Ssethg if (ioapic_node == NULL) { 1876c8589f13Ssethg return; 1877c8589f13Ssethg } 1878c8589f13Ssethg 1879c8589f13Ssethg /* Vendor and Device ID */ 1880c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1881c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 1882c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 1883c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 1884c8589f13Ssethg 1885c8589f13Ssethg /* device_type */ 1886c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 1887c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 1888c8589f13Ssethg 1889c8589f13Ssethg /* reg */ 1890c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 1891c8589f13Ssethg "reg", physaddr); 1892c8589f13Ssethg } 1893