1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/stat.h> 31 #include <sys/sunndi.h> 32 #include <sys/pci.h> 33 #include <sys/pci_impl.h> 34 #include <sys/pci_cfgspace.h> 35 #include <sys/memlist.h> 36 #include <sys/bootconf.h> 37 #include "mps_table.h" 38 #include <sys/pci_cfgspace.h> 39 #include <sys/pci_cfgspace_impl.h> 40 #include <sys/psw.h> 41 #include "../../../../common/pci/pci_strings.h" 42 43 #define pci_getb (*pci_getb_func) 44 #define pci_getw (*pci_getw_func) 45 #define pci_getl (*pci_getl_func) 46 #define pci_putb (*pci_putb_func) 47 #define pci_putw (*pci_putw_func) 48 #define pci_putl (*pci_putl_func) 49 #define dcmn_err if (pci_boot_debug) cmn_err 50 51 #define CONFIG_INFO 0 52 #define CONFIG_UPDATE 1 53 #define CONFIG_NEW 2 54 #define COMPAT_BUFSIZE 256 55 56 extern int pci_bios_nbus; 57 static uchar_t max_dev_pci = 32; /* PCI standard */ 58 int pci_boot_debug = 0; 59 extern struct memlist *find_bus_res(int, int); 60 61 /* 62 * Module prototypes 63 */ 64 static void enumerate_bus_devs(uchar_t bus, int config_op); 65 static void create_root_bus_dip(uchar_t bus); 66 static dev_info_t *new_func_pci(uchar_t, uchar_t, uchar_t, uchar_t, 67 ushort_t, int); 68 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 69 ushort_t, ushort_t, uchar_t, uint_t); 70 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 71 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t); 72 static void add_model_prop(dev_info_t *, uint_t); 73 static void add_bus_range_prop(int); 74 static int pci_slot_names_prop(int, char *, int); 75 static void add_bus_slot_names_prop(int); 76 static void add_ppb_ranges_prop(int); 77 static void add_bus_available_prop(int); 78 static void alloc_res_array(); 79 80 /* 81 * Enumerate all PCI devices 82 */ 83 void 84 pci_setup_tree() 85 { 86 uchar_t i, root_bus_addr = 0; 87 88 alloc_res_array(); 89 for (i = 0; i <= pci_bios_nbus; i++) { 90 pci_bus_res[i].par_bus = (uchar_t)-1; 91 pci_bus_res[i].root_addr = (uchar_t)-1; 92 pci_bus_res[i].sub_bus = i; 93 } 94 95 pci_bus_res[0].root_addr = root_bus_addr++; 96 create_root_bus_dip(0); 97 enumerate_bus_devs(0, CONFIG_INFO); 98 99 /* 100 * Now enumerate peer busses 101 * 102 * We loop till pci_bios_nbus. On most systems, there is 103 * one more bus at the high end, which implements the ISA 104 * compatibility bus. We don't care about that. 105 * 106 * Note: In the old (bootconf) enumeration, the peer bus 107 * address did not use the bus number, and there were 108 * too many peer busses created. The root_bus_addr is 109 * used to maintain the old peer bus address assignment. 110 * However, we stop enumerating phantom peers with no 111 * device below. 112 */ 113 for (i = 1; i <= pci_bios_nbus; i++) { 114 if (pci_bus_res[i].dip == NULL) { 115 pci_bus_res[i].root_addr = root_bus_addr++; 116 } 117 enumerate_bus_devs(i, CONFIG_INFO); 118 119 /* add slot-names property for named pci hot-plug slots */ 120 add_bus_slot_names_prop(i); 121 } 122 123 /* add bus-range property for root/peer bus nodes */ 124 for (i = 0; i <= pci_bios_nbus; i++) { 125 if (pci_bus_res[i].par_bus == (uchar_t)-1) 126 add_bus_range_prop(i); 127 } 128 } 129 130 void 131 pci_reprogram(void) 132 { 133 int i, pci_reconfig = 1; 134 char *onoff; 135 136 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 137 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 138 if (strcmp(onoff, "off") == 0) { 139 pci_reconfig = 0; 140 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 141 } 142 ddi_prop_free(onoff); 143 } 144 145 for (i = 0; i <= pci_bios_nbus; i++) { 146 /* configure devices not configured by bios */ 147 if (pci_reconfig) 148 enumerate_bus_devs(i, CONFIG_NEW); 149 /* All dev programmed, so we can create available prop */ 150 add_bus_available_prop(i); 151 } 152 } 153 154 /* 155 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 156 */ 157 static void 158 create_root_bus_dip(uchar_t bus) 159 { 160 int pci_regs[] = {0, 0, 0}; 161 dev_info_t *dip; 162 163 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 164 165 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 166 (pnode_t)DEVI_SID_NODEID, &dip); 167 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 168 "device_type", "pci"); 169 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 170 "#address-cells", 3); 171 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 172 "#size-cells", 2); 173 pci_regs[0] = pci_bus_res[bus].root_addr; 174 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 175 "reg", (int *)pci_regs, 3); 176 177 (void) ndi_devi_bind_driver(dip, 0); 178 pci_bus_res[bus].dip = dip; 179 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 180 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 181 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 182 183 if (bus != 0) 184 return; 185 186 /* 187 * Special treatment of bus 0: 188 * If no resource from MPSPEC/HRT, copy pcimem from boot 189 * and make io space the entire range. There is no difference 190 * between prefetchable memory or not. 191 */ 192 if (pci_bus_res[0].mem_space == NULL) 193 pci_bus_res[0].mem_space = 194 memlist_dup(bootops->boot_mem->pcimem); 195 if (pci_bus_res[0].io_ports == NULL) 196 memlist_insert(&pci_bus_res[0].io_ports, 0, 0x10000); 197 } 198 199 /* 200 * For any fixed configuration (often compatability) pci devices 201 * and those with their own expansion rom, create device nodes 202 * to hold the already configured device details. 203 */ 204 void 205 enumerate_bus_devs(uchar_t bus, int config_op) 206 { 207 uchar_t dev, func, nfunc, header; 208 ushort_t venid; 209 dev_info_t *dip; 210 struct pci_devfunc { 211 struct pci_devfunc *next; 212 dev_info_t *dip; 213 uchar_t bus; 214 uchar_t dev; 215 uchar_t func; 216 } *devlist = NULL, *entry; 217 218 if (config_op == CONFIG_NEW) { 219 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 220 } else 221 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 222 223 for (dev = 0; dev < max_dev_pci; dev++) { 224 nfunc = 1; 225 for (func = 0; func < nfunc; func++) { 226 227 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 228 dev, func); 229 230 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 231 if ((venid == 0xffff) || (venid == 0)) { 232 /* no function at this address */ 233 continue; 234 } 235 236 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 237 if (header == 0xff) { 238 continue; /* illegal value */ 239 } 240 241 /* 242 * according to some mail from Microsoft posted 243 * to the pci-drivers alias, their only requirement 244 * for a multifunction device is for the 1st 245 * function to have to PCI_HEADER_MULTI bit set. 246 */ 247 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 248 nfunc = 8; 249 } 250 251 if (config_op == CONFIG_INFO) { 252 /* 253 * Create the node, unconditionally, on the 254 * first pass only. It may still need 255 * resource assignment, which will be 256 * done on the second, CONFIG_NEW, pass. 257 */ 258 dip = new_func_pci(bus, dev, func, header, 259 venid, config_op); 260 /* 261 * If dip isn't null, put on a list to 262 * save for reprogramming when config_op 263 * is CONFIG_NEW. 264 */ 265 266 if (dip) { 267 entry = kmem_alloc(sizeof (*entry), 268 KM_SLEEP); 269 entry->dip = dip; 270 entry->dev = dev; 271 entry->func = func; 272 entry->next = devlist; 273 devlist = entry; 274 } 275 } 276 } 277 } 278 279 if (config_op == CONFIG_NEW) { 280 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 281 while (devlist) { 282 entry = devlist; 283 devlist = entry->next; 284 cmn_err(CE_NOTE, 285 "!reprogram pci device [%d/%d/%d] (%s)", 286 bus, entry->dev, entry->func, 287 ddi_driver_name(entry->dip)); 288 (void) add_reg_props(entry->dip, bus, entry->dev, 289 entry->func, CONFIG_UPDATE, 0); 290 kmem_free(entry, sizeof (*entry)); 291 } 292 pci_bus_res[bus].privdata = NULL; 293 } else { 294 pci_bus_res[bus].privdata = devlist; 295 } 296 } 297 298 static int 299 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 300 ushort_t subvenid, ushort_t subdevid) 301 { 302 static int prop_exist = -1; 303 static char *pciide_str; 304 char compat[32]; 305 306 if (prop_exist == -1) { 307 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 308 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 309 &pciide_str) == DDI_SUCCESS); 310 } 311 312 if (!prop_exist) 313 return (0); 314 315 /* compare property value against various forms of compatible */ 316 if (subvenid) { 317 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 318 venid, devid, subvenid, subdevid, revid); 319 if (strcmp(pciide_str, compat) == 0) 320 return (1); 321 322 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 323 venid, devid, subvenid, subdevid); 324 if (strcmp(pciide_str, compat) == 0) 325 return (1); 326 327 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 328 subvenid, subdevid); 329 if (strcmp(pciide_str, compat) == 0) 330 return (1); 331 } 332 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 333 venid, devid, revid); 334 if (strcmp(pciide_str, compat) == 0) 335 return (1); 336 337 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 338 if (strcmp(pciide_str, compat) == 0) 339 return (1); 340 341 return (0); 342 } 343 344 static int 345 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 346 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 347 { 348 struct ide_table { /* table for PCI_MASS_OTHER */ 349 ushort_t venid; 350 ushort_t devid; 351 } *entry; 352 353 /* XXX SATA devices: need a way to add dynamically */ 354 static struct ide_table ide_other[] = { 355 {0x1095, 0x3112}, 356 {0x1095, 0x3114}, 357 {0x1095, 0x3512}, 358 {0, 0} 359 }; 360 361 if (basecl != PCI_CLASS_MASS) 362 return (0); 363 364 if (subcl == PCI_MASS_IDE) { 365 return (1); 366 } 367 368 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 369 return (0); 370 } 371 372 entry = &ide_other[0]; 373 while (entry->venid) { 374 if (entry->venid == venid && entry->devid == devid) 375 return (1); 376 entry++; 377 } 378 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 379 } 380 381 static int 382 is_display(uint_t classcode) 383 { 384 static uint_t disp_classes[] = { 385 0x000100, 386 0x030000, 387 0x030001 388 }; 389 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 390 391 for (i = 0; i < nclasses; i++) { 392 if (classcode == disp_classes[i]) 393 return (1); 394 } 395 return (0); 396 } 397 398 static dev_info_t * 399 new_func_pci(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 400 ushort_t vendorid, int config_op) 401 { 402 char nodename[32], unitaddr[5]; 403 dev_info_t *dip; 404 uchar_t basecl, subcl, intr, revid; 405 ushort_t subvenid, subdevid, status; 406 uint_t classcode, revclass; 407 int reprogram = 0, pciide; 408 int power[2] = {1, 1}; 409 410 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 411 412 switch (header & PCI_HEADER_TYPE_M) { 413 case PCI_HEADER_ZERO: 414 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 415 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 416 break; 417 case PCI_HEADER_CARDBUS: 418 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 419 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 420 break; 421 default: 422 subvenid = 0; 423 subdevid = 0; 424 break; 425 } 426 427 /* XXX should be use generic names? derive from class? */ 428 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 429 classcode = revclass >> 8; 430 revid = revclass & 0xff; 431 432 /* figure out if this is pci-ide */ 433 basecl = classcode >> 16; 434 subcl = (classcode >> 8) & 0xff; 435 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 436 subvenid, subdevid); 437 438 if (pciide) 439 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 440 else if (is_display(classcode)) 441 (void) snprintf(nodename, sizeof (nodename), "display"); 442 else if (subvenid != 0) 443 (void) snprintf(nodename, sizeof (nodename), 444 "pci%x,%x", subvenid, subdevid); 445 else 446 (void) snprintf(nodename, sizeof (nodename), 447 "pci%x,%x", vendorid, deviceid); 448 449 /* make sure parent bus dip has been created */ 450 if (pci_bus_res[bus].dip == NULL) { 451 create_root_bus_dip(bus); 452 } 453 454 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 455 DEVI_SID_NODEID, &dip); 456 457 /* add properties */ 458 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 459 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 460 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 461 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 462 "class-code", classcode); 463 if (func == 0) 464 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 465 else 466 (void) snprintf(unitaddr, sizeof (unitaddr), 467 "%x,%x", dev, func); 468 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 469 "unit-address", unitaddr); 470 471 /* add device_type for display nodes */ 472 if (is_display(classcode)) { 473 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 474 "device_type", "display"); 475 } 476 /* add special stuff for header type */ 477 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 478 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 479 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 480 481 if (subvenid != 0) { 482 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 483 "subsystem-id", subdevid); 484 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 485 "subsystem-vendor-id", subvenid); 486 } 487 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 488 "min-grant", mingrant); 489 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 490 "max-latency", maxlatency); 491 } 492 493 /* interrupt, record if not 0 */ 494 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 495 if (intr != 0) 496 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 497 "interrupts", intr); 498 499 /* 500 * Add support for 133 mhz pci eventually 501 */ 502 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 503 504 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 505 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 506 if (status & PCI_STAT_FBBC) 507 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 508 "fast-back-to-back"); 509 if (status & PCI_STAT_66MHZ) 510 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 511 "66mhz-capable"); 512 if (status & PCI_STAT_UDF) 513 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 514 "udf-supported"); 515 516 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 517 "power-consumption", power, 2); 518 519 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) { 520 add_ppb_props(dip, bus, dev, func); 521 } 522 523 add_model_prop(dip, classcode); 524 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 525 revid, classcode); 526 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 527 (void) ndi_devi_bind_driver(dip, 0); 528 529 /* special handling for pci-ide */ 530 if (pciide) { 531 dev_info_t *cdip; 532 533 /* 534 * Create properties specified by P1275 Working Group 535 * Proposal #414 Version 1 536 */ 537 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 538 "device_type", "pci-ide"); 539 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 540 "#address-cells", 1); 541 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 542 "#size-cells", 0); 543 544 /* allocate two child nodes */ 545 ndi_devi_alloc_sleep(dip, "ide", 546 (pnode_t)DEVI_SID_NODEID, &cdip); 547 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 548 "reg", 0); 549 (void) ndi_devi_bind_driver(cdip, 0); 550 ndi_devi_alloc_sleep(dip, "ide", 551 (pnode_t)DEVI_SID_NODEID, &cdip); 552 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 553 "reg", 1); 554 (void) ndi_devi_bind_driver(cdip, 0); 555 556 reprogram = 0; /* don't reprogram pci-ide bridge */ 557 } 558 559 if (reprogram) 560 return (dip); 561 return (NULL); 562 } 563 564 /* 565 * Set the compatible property to a value compliant with 566 * rev 2.1 of the IEEE1275 PCI binding. 567 * 568 * pciVVVV,DDDD.SSSS.ssss.RR (0) 569 * pciVVVV,DDDD.SSSS.ssss (1) 570 * pciSSSS,ssss (2) 571 * pciVVVV,DDDD.RR (3) 572 * pciVVVV,DDDD (4) 573 * pciclass,CCSSPP (5) 574 * pciclass,CCSS (6) 575 * 576 * The Subsystem (SSSS) forms are not inserted if 577 * subsystem-vendor-id is 0. 578 * 579 * Set with setprop and \x00 between each 580 * to generate the encoded string array form. 581 */ 582 void 583 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 584 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode) 585 { 586 int i, size; 587 char *compat[7]; 588 char *buf, *curr; 589 590 #define COMPAT_BUFSIZE 256 591 i = 0; 592 size = COMPAT_BUFSIZE; 593 curr = buf = kmem_alloc(size, KM_SLEEP); 594 595 if (subvenid) { 596 compat[i++] = curr; /* form 0 */ 597 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 598 vendorid, deviceid, subvenid, subdevid, revid); 599 size -= strlen(curr) + 1; 600 curr += strlen(curr) + 1; 601 602 compat[i++] = curr; /* form 1 */ 603 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 604 vendorid, deviceid, subvenid, subdevid); 605 size -= strlen(curr) + 1; 606 curr += strlen(curr) + 1; 607 608 compat[i++] = curr; /* form 2 */ 609 (void) snprintf(curr, size, "pci%x,%x", 610 subvenid, subdevid); 611 size -= strlen(curr) + 1; 612 curr += strlen(curr) + 1; 613 } 614 compat[i++] = curr; /* form 3 */ 615 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 616 size -= strlen(curr) + 1; 617 curr += strlen(curr) + 1; 618 619 compat[i++] = curr; /* form 4 */ 620 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 621 size -= strlen(curr) + 1; 622 curr += strlen(curr) + 1; 623 624 compat[i++] = curr; /* form 5 */ 625 (void) snprintf(curr, size, "pciclass,%06x", classcode); 626 size -= strlen(curr) + 1; 627 curr += strlen(curr) + 1; 628 629 compat[i++] = curr; /* form 6 */ 630 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 631 632 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 633 "compatible", compat, i); 634 kmem_free(buf, COMPAT_BUFSIZE); 635 } 636 637 /* 638 * Adjust the reg properties for a dual channel PCI-IDE device. 639 * 640 * NOTE: don't do anything that changes the order of the hard-decodes 641 * and programmed BARs. The kernel driver depends on these values 642 * being in this order regardless of whether they're for a 'native' 643 * mode BAR or not. 644 */ 645 /* 646 * config info for pci-ide devices 647 */ 648 static struct { 649 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 650 uchar_t bar_offset; /* offset for alt status register */ 651 ushort_t addr; /* compatibility mode base address */ 652 ushort_t length; /* number of ports for this BAR */ 653 } pciide_bar[] = { 654 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 655 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 656 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 657 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 658 }; 659 660 static int 661 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 662 { 663 int hard_decode = 0; 664 665 /* 666 * Adjust the base and len for the BARs of the PCI-IDE 667 * device's primary and secondary controllers. The first 668 * two BARs are for the primary controller and the next 669 * two BARs are for the secondary controller. The fifth 670 * and sixth bars are never adjusted. 671 */ 672 if (index >= 0 && index <= 3) { 673 *lenp = pciide_bar[index].length; 674 675 if (progcl & pciide_bar[index].native_mask) { 676 *basep += pciide_bar[index].bar_offset; 677 } else { 678 *basep = pciide_bar[index].addr; 679 hard_decode = 1; 680 } 681 } 682 683 /* 684 * if either base or len is zero make certain both are zero 685 */ 686 if (*basep == 0 || *lenp == 0) { 687 *basep = 0; 688 *lenp = 0; 689 hard_decode = 0; 690 } 691 692 return (hard_decode); 693 } 694 695 696 /* 697 * Add the "reg" and "assigned-addresses" property 698 */ 699 static int 700 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 701 int config_op, int pciide) 702 { 703 uchar_t baseclass, subclass, progclass, header; 704 ushort_t bar_sz; 705 uint_t value = 0, len, devloc; 706 uint_t base, base_hi, type; 707 ushort_t offset, end; 708 int max_basereg, j, reprogram = 0; 709 uint_t phys_hi; 710 struct memlist **io_res, **mres, **mem_res, **pmem_res; 711 uint16_t cmd_reg; 712 713 pci_regspec_t regs[16] = {{0}}; 714 pci_regspec_t assigned[15] = {{0}}; 715 int nreg, nasgn, enable = 0; 716 717 io_res = &pci_bus_res[bus].io_ports; 718 mem_res = &pci_bus_res[bus].mem_space; 719 if (bus == 0) /* for bus 0, there is only mem_space */ 720 pmem_res = mem_res; 721 else 722 pmem_res = &pci_bus_res[bus].pmem_space; 723 724 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 725 regs[0].pci_phys_hi = devloc; 726 nreg = 1; /* rest of regs[0] is all zero */ 727 nasgn = 0; 728 729 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 730 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 731 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 732 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 733 /* Fetch PCI command, disable I/O and memory */ 734 cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 735 pci_putw(bus, dev, func, PCI_CONF_COMM, 736 cmd_reg & ~(PCI_COMM_IO | PCI_COMM_MAE)); 737 738 switch (header) { 739 case PCI_HEADER_ZERO: 740 max_basereg = PCI_BASE_NUM; 741 break; 742 case PCI_HEADER_PPB: 743 max_basereg = PCI_BCNF_BASE_NUM; 744 break; 745 case PCI_HEADER_CARDBUS: 746 max_basereg = PCI_CBUS_BASE_NUM; 747 break; 748 default: 749 max_basereg = 0; 750 break; 751 } 752 753 /* 754 * Create the register property by saving the current 755 * value of the base register. Disable memory/io, then 756 * write 0xffffffff to the base register. Read the 757 * value back to determine the required size of the 758 * address space. Restore the base register 759 * contents. 760 */ 761 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 762 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 763 j++, offset += bar_sz) { 764 int hard_decode = 0; 765 766 /* determine the size of the address space */ 767 base = pci_getl(bus, dev, func, offset); 768 pci_putl(bus, dev, func, offset, 0xffffffff); 769 value = pci_getl(bus, dev, func, offset); 770 pci_putl(bus, dev, func, offset, base); 771 772 /* construct phys hi,med.lo, size hi, lo */ 773 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 774 /* i/o space */ 775 bar_sz = PCI_BAR_SZ_32; 776 value &= PCI_BASE_IO_ADDR_M; 777 len = ((value ^ (value-1)) + 1) >> 1; 778 779 /* XXX Adjust first 4 IDE registers */ 780 if (pciide) { 781 if (subclass != PCI_MASS_IDE) 782 progclass = (PCI_IDE_IF_NATIVE_PRI | 783 PCI_IDE_IF_NATIVE_SEC); 784 hard_decode = pciIdeAdjustBAR(progclass, j, 785 &base, &len); 786 } else if (value == 0) { 787 /* skip base regs with size of 0 */ 788 continue; 789 } 790 791 regs[nreg].pci_size_low = 792 assigned[nasgn].pci_size_low = len; 793 if (!hard_decode) { 794 regs[nreg].pci_phys_hi = 795 (PCI_ADDR_IO | devloc) + offset; 796 } else { 797 regs[nreg].pci_phys_hi = 798 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 799 offset; 800 regs[nreg].pci_phys_low = 801 base & PCI_BASE_IO_ADDR_M; 802 } 803 assigned[nasgn].pci_phys_hi = 804 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 805 type = base & (~PCI_BASE_IO_ADDR_M); 806 base &= PCI_BASE_IO_ADDR_M; 807 808 /* 809 * first pass - gather what's there 810 * update/second pass - adjust/allocate regions 811 * config - allocate regions 812 */ 813 if (config_op == CONFIG_INFO) { /* first pass */ 814 /* take out of the resource map of the bus */ 815 if (*io_res && base != 0) 816 (void) memlist_remove(io_res, 817 (uint64_t)base, (uint64_t)len); 818 else if (*io_res) 819 reprogram = 1; 820 } else if (*io_res && base == 0) { 821 base = (uint_t)memlist_find(io_res, 822 (uint64_t)len, (uint64_t)0x4); 823 if (base != 0) { 824 /* XXX need to worry about 64-bit? */ 825 pci_putl(bus, dev, func, offset, 826 base | type); 827 base = pci_getl(bus, dev, func, offset); 828 base &= PCI_BASE_IO_ADDR_M; 829 } 830 if (base == 0) { 831 cmn_err(CE_WARN, "failed to program" 832 " IO space [%d/%d/%d] BAR@0x%x" 833 " length 0x%x", 834 bus, dev, func, offset, len); 835 } else 836 enable |= PCI_COMM_IO; 837 } 838 assigned[nasgn].pci_phys_low = base; 839 nreg++, nasgn++; 840 841 } else { 842 /* memory space */ 843 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 844 bar_sz = PCI_BAR_SZ_64; 845 base_hi = pci_getl(bus, dev, func, offset + 4); 846 phys_hi = PCI_ADDR_MEM64; 847 } else { 848 bar_sz = PCI_BAR_SZ_32; 849 base_hi = 0; 850 phys_hi = PCI_ADDR_MEM32; 851 } 852 853 /* skip base regs with size of 0 */ 854 value &= PCI_BASE_M_ADDR_M; 855 856 if (value == 0) { 857 continue; 858 } 859 len = ((value ^ (value-1)) + 1) >> 1; 860 regs[nreg].pci_size_low = 861 assigned[nasgn].pci_size_low = len; 862 863 phys_hi |= (devloc | offset); 864 if (base & PCI_BASE_PREF_M) { 865 mres = pmem_res; 866 phys_hi |= PCI_PREFETCH_B; 867 } else { 868 mres = mem_res; 869 } 870 regs[nreg].pci_phys_hi = 871 assigned[nasgn].pci_phys_hi = phys_hi; 872 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 873 assigned[nasgn].pci_phys_mid = base_hi; 874 type = base & ~PCI_BASE_M_ADDR_M; 875 base &= PCI_BASE_M_ADDR_M; 876 877 if (config_op == CONFIG_INFO) { 878 /* take out of the resource map of the bus */ 879 if (*mres && base != 0) { 880 (void) memlist_remove(mres, 881 (uint64_t)base, (uint64_t)len); 882 } else if (*mres) 883 reprogram = 1; 884 } else if (*mres && base == 0) { 885 base = (uint_t)memlist_find(mres, 886 (uint64_t)len, (uint64_t)0x1000); 887 if (base != NULL) { 888 pci_putl(bus, dev, func, offset, 889 base | type); 890 base = pci_getl(bus, dev, func, offset); 891 base &= PCI_BASE_M_ADDR_M; 892 } 893 894 if (base == 0) { 895 cmn_err(CE_WARN, "failed to program " 896 "mem space [%d/%d/%d] BAR@0x%x" 897 " length 0x%x", 898 bus, dev, func, offset, len); 899 } else 900 enable |= PCI_COMM_MAE; 901 } 902 assigned[nasgn].pci_phys_low = base; 903 nreg++, nasgn++; 904 } 905 } 906 switch (header) { 907 case PCI_HEADER_ZERO: 908 offset = PCI_CONF_ROM; 909 break; 910 case PCI_HEADER_PPB: 911 offset = PCI_BCNF_ROM; 912 break; 913 default: /* including PCI_HEADER_CARDBUS */ 914 goto done; 915 } 916 917 /* 918 * Add the expansion rom memory space 919 * Determine the size of the ROM base reg; don't write reserved bits 920 * ROM isn't in the PCI memory space. 921 */ 922 base = pci_getl(bus, dev, func, offset); 923 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 924 value = pci_getl(bus, dev, func, offset); 925 pci_putl(bus, dev, func, offset, base); 926 value &= PCI_BASE_ROM_ADDR_M; 927 928 if (value != 0) { 929 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 930 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 931 PCI_ADDR_MEM32 | devloc) + offset; 932 base &= PCI_BASE_ROM_ADDR_M; 933 assigned[nasgn].pci_phys_low = base; 934 len = ((value ^ (value-1)) + 1) >> 1; 935 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 936 nreg++, nasgn++; 937 /* take it out of the memory resource */ 938 if (*mem_res && base != 0) 939 (void) memlist_remove(mem_res, 940 (uint64_t)base, (uint64_t)len); 941 } 942 943 /* 944 * The following are ISA resources. There are not part 945 * of the PCI local bus resources. So don't attempt to 946 * do resource accounting against PCI. 947 */ 948 949 /* add the three hard-decode, aliased address spaces for VGA */ 950 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 951 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 952 953 /* VGA hard decode 0x3b0-0x3bb */ 954 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 955 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 956 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 957 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 958 nreg++, nasgn++; 959 960 /* VGA hard decode 0x3c0-0x3df */ 961 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 962 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 963 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 964 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 965 nreg++, nasgn++; 966 967 /* Video memory */ 968 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 969 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 970 regs[nreg].pci_phys_low = 971 assigned[nasgn].pci_phys_low = 0xa0000; 972 regs[nreg].pci_size_low = 973 assigned[nasgn].pci_size_low = 0x20000; 974 nreg++, nasgn++; 975 } 976 977 /* add the hard-decode, aliased address spaces for 8514 */ 978 if ((baseclass == PCI_CLASS_DISPLAY) && 979 (subclass == PCI_DISPLAY_VGA) && 980 (progclass & PCI_DISPLAY_IF_8514)) { 981 982 /* hard decode 0x2e8 */ 983 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 984 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 985 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 986 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 987 nreg++, nasgn++; 988 989 /* hard decode 0x2ea-0x2ef */ 990 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 991 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 992 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 993 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 994 nreg++, nasgn++; 995 } 996 997 done: 998 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 999 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 1000 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1001 "assigned-addresses", 1002 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 1003 if (config_op == CONFIG_NEW && enable) { 1004 cmn_err(CE_NOTE, 1005 "!enable PCI device [%d/%d/%d]", bus, dev, func); 1006 cmd_reg |= (enable | PCI_COMM_ME); 1007 } 1008 /* restore device enables */ 1009 pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 1010 return (reprogram); 1011 } 1012 1013 static void 1014 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func) 1015 { 1016 int i; 1017 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1018 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1019 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1020 ASSERT(secbus <= subbus); 1021 1022 /* 1023 * Some BIOSes lie about max pci busses, we allow for 1024 * such mistakes here 1025 */ 1026 if (subbus > pci_bios_nbus) { 1027 pci_bios_nbus = subbus; 1028 alloc_res_array(); 1029 } 1030 1031 ASSERT(pci_bus_res[secbus].dip == NULL); 1032 pci_bus_res[secbus].dip = dip; 1033 pci_bus_res[secbus].par_bus = bus; 1034 1035 /* setup bus number hierarchy */ 1036 pci_bus_res[secbus].sub_bus = subbus; 1037 if (subbus > pci_bus_res[bus].sub_bus) 1038 pci_bus_res[bus].sub_bus = subbus; 1039 for (i = secbus + 1; i <= subbus; i++) 1040 pci_bus_res[i].par_bus = bus; 1041 1042 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1043 "device_type", "pci"); 1044 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1045 "#address-cells", 3); 1046 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1047 "#size-cells", 2); 1048 1049 /* 1050 * According to PPB spec, the base register should be programmed 1051 * with a value bigger than the limit register when there are 1052 * no resources available. This applies to io, memory, and 1053 * prefetchable memory. 1054 */ 1055 /* io range */ 1056 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1057 io_range[0] = ((val & 0xf0) << 8); 1058 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1059 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1060 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1061 memlist_insert(&pci_bus_res[secbus].io_ports, 1062 (uint64_t)io_range[0], 1063 (uint64_t)(io_range[1] - io_range[0] + 1)); 1064 if (pci_bus_res[bus].io_ports != NULL) { 1065 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1066 (uint64_t)io_range[0], 1067 (uint64_t)(io_range[1] - io_range[0] + 1)); 1068 } 1069 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1070 secbus, io_range[0], io_range[1]); 1071 /* if 32-bit supported, make sure upper bits are not set */ 1072 if ((val & 0xf) == 1 && 1073 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1074 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1075 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1076 } 1077 } 1078 1079 /* mem range */ 1080 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1081 mem_range[0] = ((val & 0xFFF0) << 16); 1082 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1083 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1084 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1085 memlist_insert(&pci_bus_res[secbus].mem_space, 1086 (uint64_t)mem_range[0], 1087 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1088 /* remove from parent resouce list */ 1089 if (pci_bus_res[bus].mem_space != NULL) { 1090 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1091 (uint64_t)mem_range[0], 1092 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1093 } 1094 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1095 secbus, mem_range[0], mem_range[1]); 1096 } 1097 1098 /* prefetchable memory range */ 1099 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1100 pmem_range[0] = ((val & 0xFFF0) << 16); 1101 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1102 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1103 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1104 memlist_insert(&pci_bus_res[secbus].pmem_space, 1105 (uint64_t)pmem_range[0], 1106 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1107 if (pci_bus_res[bus].pmem_space != NULL) { 1108 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1109 (uint64_t)pmem_range[0], 1110 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1111 } 1112 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1113 secbus, pmem_range[0], pmem_range[1]); 1114 /* if 64-bit supported, make sure upper bits are not set */ 1115 if ((val & 0xf) == 1 && 1116 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1117 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1118 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1119 } 1120 } 1121 1122 add_bus_range_prop(secbus); 1123 add_ppb_ranges_prop(secbus); 1124 } 1125 1126 extern const struct pci_class_strings_s class_pci[]; 1127 extern int class_pci_items; 1128 1129 static void 1130 add_model_prop(dev_info_t *dip, uint_t classcode) 1131 { 1132 const char *desc; 1133 int i; 1134 uchar_t baseclass = classcode >> 16; 1135 uchar_t subclass = (classcode >> 8) & 0xff; 1136 uchar_t progclass = classcode & 0xff; 1137 1138 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1139 desc = "IDE controller"; 1140 } else { 1141 for (desc = 0, i = 0; i < class_pci_items; i++) { 1142 if ((baseclass == class_pci[i].base_class) && 1143 (subclass == class_pci[i].sub_class) && 1144 (progclass == class_pci[i].prog_class)) { 1145 desc = class_pci[i].actual_desc; 1146 break; 1147 } 1148 } 1149 if (i == class_pci_items) 1150 desc = "Unknown class of pci/pnpbios device"; 1151 } 1152 1153 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1154 (char *)desc); 1155 } 1156 1157 static void 1158 add_bus_range_prop(int bus) 1159 { 1160 int bus_range[2]; 1161 1162 if (pci_bus_res[bus].dip == NULL) 1163 return; 1164 bus_range[0] = bus; 1165 bus_range[1] = pci_bus_res[bus].sub_bus; 1166 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1167 "bus-range", (int *)bus_range, 2); 1168 } 1169 1170 /* 1171 * pci irq routing information table 1172 */ 1173 static int pci_irq_nroutes; 1174 static pci_irq_route_t *pci_irq_routes; 1175 1176 /* 1177 * Issue the bios get irq routing information table interrupt 1178 * 1179 * Despite the name, the information in the table is only 1180 * used to derive slot names for some named pci hot-plug slots. 1181 * 1182 * Returns the number of irq routing table entries returned 1183 * by the bios, or 0 and optionally, the number of entries required. 1184 */ 1185 static int 1186 pci_bios_get_irq_routing(pci_irq_route_t *routes, int nroutes, int *nneededp) 1187 { 1188 struct bop_regs regs; 1189 uchar_t *hdrp; 1190 uchar_t *bufp; 1191 int i, n; 1192 int rval = 0; 1193 1194 if (nneededp) 1195 *nneededp = 0; 1196 1197 /* 1198 * Set up irq routing header with the size and address 1199 * of some useable low-memory data addresses. Initalize 1200 * data area to zero, avoiding memcpy/bzero. 1201 */ 1202 hdrp = (uchar_t *)BIOS_IRQ_ROUTING_HDR; 1203 bufp = (uchar_t *)BIOS_IRQ_ROUTING_DATA; 1204 1205 n = nroutes * sizeof (pci_irq_route_t); 1206 for (i = 0; i < n; i++) 1207 bufp[i] = 0; 1208 ((pci_irq_route_hdr_t *)hdrp)->pir_size = n; 1209 ((pci_irq_route_hdr_t *)hdrp)->pir_addr = (uint32_t)(uintptr_t)bufp; 1210 1211 bzero(®s, sizeof (regs)); 1212 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_GET_IRQ_ROUTING; 1213 1214 regs.ds = 0xf000; 1215 regs.es = FP_SEG((uint_t)(uintptr_t)hdrp); 1216 regs.edi.word.di = FP_OFF((uint_t)(uintptr_t)hdrp); 1217 1218 BOP_DOINT(bootops, 0x1a, ®s); 1219 1220 n = (int)(((pci_irq_route_hdr_t *)hdrp)->pir_size / 1221 sizeof (pci_irq_route_t)); 1222 1223 if ((regs.eflags & PS_C) != 0) { 1224 if (nneededp) 1225 *nneededp = n; 1226 } else { 1227 /* 1228 * Copy resulting irq routing data from low memory up to 1229 * the kernel address space, avoiding memcpy as usual. 1230 */ 1231 if (n <= nroutes) { 1232 for (i = 0; i < n * sizeof (pci_irq_route_t); i++) 1233 ((uchar_t *)routes)[i] = bufp[i]; 1234 rval = n; 1235 } 1236 } 1237 return (rval); 1238 } 1239 1240 static void 1241 pci_get_irq_routing_table(void) 1242 { 1243 pci_irq_route_t *routes; 1244 int n = N_PCI_IRQ_ROUTES; 1245 int nneeded = 0; 1246 int nroutes; 1247 1248 /* 1249 * Get irq routing table information. 1250 * Allocate a buffer for an initial default number of entries. 1251 * If the bios indicates it needs a larger buffer, try it again. 1252 * Drive on if it still won't cooperate and play nice after that. 1253 */ 1254 routes = kmem_zalloc(n * sizeof (pci_irq_route_t), KM_SLEEP); 1255 nroutes = pci_bios_get_irq_routing(routes, n, &nneeded); 1256 if (nroutes == 0 && nneeded > n) { 1257 kmem_free(routes, n * sizeof (pci_irq_route_t)); 1258 if (nneeded > N_PCI_IRQ_ROUTES_MAX) { 1259 cmn_err(CE_CONT, 1260 "pci: unable to get IRQ routing information, " 1261 "required buffer space of %d entries exceeds max\n", 1262 nneeded); 1263 return; 1264 } 1265 n = nneeded; 1266 routes = kmem_zalloc(n * sizeof (pci_irq_route_t), KM_SLEEP); 1267 nroutes = pci_bios_get_irq_routing(routes, n, NULL); 1268 if (nroutes == 0) { 1269 cmn_err(CE_CONT, 1270 "pci: unable to get IRQ routing information, " 1271 "required buffer space for %d entries\n", n); 1272 kmem_free(routes, n * sizeof (pci_irq_route_t)); 1273 } 1274 } 1275 1276 if (nroutes > 0) { 1277 pci_irq_routes = routes; 1278 pci_irq_nroutes = nroutes; 1279 } 1280 } 1281 /* 1282 * Use the results of the PCI BIOS call that returned the routing tables 1283 * to build the 1275 slot-names property for the indicated bus. 1284 * Results are returned in buf. Length is return value, -1 is returned on 1285 * overflow and zero is returned if no data exists to build a property. 1286 */ 1287 static int 1288 pci_slot_names_prop(int bus, char *buf, int len) 1289 { 1290 uchar_t dev; 1291 uchar_t slot[N_PCI_IRQ_ROUTES_MAX+1]; 1292 uint32_t mask; 1293 int i, nnames, plen; 1294 1295 ASSERT(pci_irq_nroutes <= N_PCI_IRQ_ROUTES_MAX); 1296 1297 if (pci_irq_nroutes == 0) 1298 return (0); 1299 nnames = 0; 1300 mask = 0; 1301 for (i = 0; i < pci_irq_nroutes; i++) 1302 slot[i] = 0xff; 1303 for (i = 0; i < pci_irq_nroutes; i++) { 1304 if (pci_irq_routes[i].pir_bus != bus) 1305 continue; 1306 if (pci_irq_routes[i].pir_slot != 0) { 1307 dev = (pci_irq_routes[i].pir_dev & 0xf8) >> 3; 1308 slot[dev] = pci_irq_routes[i].pir_slot; 1309 mask |= (1 << dev); 1310 nnames++; 1311 } 1312 } 1313 1314 if (nnames == 0) 1315 return (0); 1316 1317 if (len < (4 + nnames * 8)) 1318 return (-1); 1319 *(uint32_t *)buf = mask; 1320 plen = 4; 1321 for (i = 0; i < pci_irq_nroutes; i++) { 1322 if (slot[i] == 0xff) 1323 continue; 1324 (void) sprintf(buf + plen, "Slot %d", slot[i]); 1325 plen += strlen(buf+plen) + 1; 1326 *(buf + plen) = 0; 1327 } 1328 for (; plen % 4; plen++) 1329 *(buf + plen) = 0; 1330 return (plen); 1331 } 1332 1333 /* 1334 * Add slot-names property for any named pci hot-plug slots 1335 */ 1336 static void 1337 add_bus_slot_names_prop(int bus) 1338 { 1339 char slotprop[256]; 1340 int len; 1341 1342 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1343 if (len > 0) { 1344 if (pci_bus_res[bus].dip == NULL) 1345 create_root_bus_dip(bus); 1346 ASSERT(pci_bus_res[bus].dip); 1347 ASSERT((len % sizeof (int)) == 0); 1348 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1349 pci_bus_res[bus].dip, "slot-names", 1350 (int *)slotprop, len / sizeof (int)); 1351 } 1352 } 1353 1354 /* this should be in some header file, shared with pcicfg */ 1355 struct pcicfg_range { 1356 uint32_t child_hi; 1357 uint32_t child_mid; 1358 uint32_t child_lo; 1359 uint32_t parent_hi; 1360 uint32_t parent_mid; 1361 uint32_t parent_lo; 1362 uint32_t size_hi; 1363 uint32_t size_lo; 1364 }; 1365 1366 static int 1367 memlist_to_range(struct pcicfg_range *rp, struct memlist *entry, int type) 1368 { 1369 if (entry == NULL) 1370 return (0); 1371 1372 /* assume 32-bit addresses */ 1373 rp->child_hi = rp->parent_hi = type; 1374 rp->child_mid = rp->parent_mid = 0; 1375 rp->child_lo = rp->parent_lo = (uint32_t)entry->address; 1376 rp->size_hi = 0; 1377 rp->size_lo = (uint32_t)entry->size; 1378 return (1); 1379 } 1380 1381 static void 1382 add_ppb_ranges_prop(int bus) 1383 { 1384 int i = 0; 1385 struct pcicfg_range *rp; 1386 1387 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1388 1389 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1390 PCI_ADDR_IO | PCI_REG_REL_M); 1391 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1392 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1393 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1394 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1395 1396 if (i != 0) 1397 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1398 pci_bus_res[bus].dip, "ranges", (int *)rp, 1399 i * sizeof (struct pcicfg_range) / sizeof (int)); 1400 kmem_free(rp, 3 * sizeof (*rp)); 1401 } 1402 1403 static int 1404 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1405 { 1406 int i = 0; 1407 1408 while (list) { 1409 /* assume 32-bit addresses */ 1410 sp->pci_phys_hi = type; 1411 sp->pci_phys_mid = 0; 1412 sp->pci_phys_low = (uint32_t)list->address; 1413 sp->pci_size_hi = 0; 1414 sp->pci_size_low = (uint32_t)list->size; 1415 1416 list = list->next; 1417 sp++, i++; 1418 } 1419 return (i); 1420 } 1421 1422 static void 1423 add_bus_available_prop(int bus) 1424 { 1425 int i, count; 1426 struct pci_phys_spec *sp; 1427 1428 count = memlist_count(pci_bus_res[bus].io_ports) + 1429 memlist_count(pci_bus_res[bus].mem_space) + 1430 memlist_count(pci_bus_res[bus].pmem_space); 1431 1432 if (count == 0) /* nothing available */ 1433 return; 1434 1435 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1436 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1437 PCI_ADDR_IO | PCI_REG_REL_M); 1438 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1439 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1440 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1441 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1442 ASSERT(i == count); 1443 1444 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1445 "available", (int *)sp, 1446 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1447 kmem_free(sp, count * sizeof (*sp)); 1448 } 1449 1450 static void 1451 alloc_res_array(void) 1452 { 1453 static int array_max = 0; 1454 int old_max; 1455 void *old_res; 1456 1457 if (array_max > pci_bios_nbus + 1) 1458 return; /* array is big enough */ 1459 1460 old_max = array_max; 1461 old_res = pci_bus_res; 1462 1463 if (array_max == 0) 1464 array_max = 16; /* start with a reasonable number */ 1465 1466 while (array_max < pci_bios_nbus + 1) 1467 array_max <<= 1; 1468 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1469 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1470 1471 if (old_res) { /* copy content and free old array */ 1472 bcopy(old_res, pci_bus_res, 1473 old_max * sizeof (struct pci_bus_resource)); 1474 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1475 } 1476 } 1477