17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22c8589f13Ssethg * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate #include <sys/types.h> 297c478bd9Sstevel@tonic-gate #include <sys/stat.h> 307c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 337c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 347c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 357c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3670025d76Sjohnny #include <io/pci/mps_table.h> 37c88420b3Sdmick #include <sys/pci_cfgspace.h> 38c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 39c88420b3Sdmick #include <sys/psw.h> 4009f67678Sanish #include "../../../../common/pci/pci_strings.h" 41c8589f13Ssethg #include <sys/apic.h> 428a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 435af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h> 4425145214Smyers #include <sys/acpi/acpi.h> 4525145214Smyers #include <sys/acpica.h> 467c478bd9Sstevel@tonic-gate 477c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 487c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 497c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 507c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 517c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 527c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 537c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 567c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 577c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 58bd87be88Ssethg #define CONFIG_FIX 3 5970025d76Sjohnny #define COMPAT_BUFSIZE 512 607c478bd9Sstevel@tonic-gate 61bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 62bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 63bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 64bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 65bd87be88Ssethg 66bd87be88Ssethg struct pci_fixundo { 67bd87be88Ssethg uint8_t bus; 68bd87be88Ssethg uint8_t dev; 69bd87be88Ssethg uint8_t fn; 70bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 71bd87be88Ssethg struct pci_fixundo *next; 72bd87be88Ssethg }; 73bd87be88Ssethg 747c478bd9Sstevel@tonic-gate extern int pci_bios_nbus; 757c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 767c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 777c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 78bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 797c478bd9Sstevel@tonic-gate 807c478bd9Sstevel@tonic-gate /* 817c478bd9Sstevel@tonic-gate * Module prototypes 827c478bd9Sstevel@tonic-gate */ 837c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 847c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 85bd87be88Ssethg static dev_info_t *process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 867c478bd9Sstevel@tonic-gate ushort_t, int); 877c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 8870025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 897c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 9070025d76Sjohnny static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int); 917c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 927c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 93b1f176e8Sjg static void add_bus_slot_names_prop(int); 947c478bd9Sstevel@tonic-gate static void add_ppb_ranges_prop(int); 957c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 965af4ae46Sjveta static ACPI_STATUS lookup_acpi_obj(ACPI_HANDLE, char *, ACPI_HANDLE *); 975af4ae46Sjveta static int check_ppb_hotplug(dev_info_t *); 989896aa55Sjveta static void fix_ppb_res(uchar_t); 99f55ce205Sszhou static void alloc_res_array(); 100c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 101c8589f13Ssethg ushort_t deviceid); 102*d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1037c478bd9Sstevel@tonic-gate 10475bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 1055af4ae46Sjveta extern ACPI_STATUS pciehpc_acpi_eval_osc(ACPI_HANDLE, uint32_t *); 10675bcd456Sjg 107ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 10825145214Smyers int pci_bus_always_renumber = 0; 10925145214Smyers 110fc396574Srw /* get the subordinate bus # for a root/peer bus */ 111fc396574Srw static int 112fc396574Srw pci_root_subbus(int bus, uchar_t *subbus) 113fc396574Srw { 114fc396574Srw ACPI_HANDLE hdl; 115fc396574Srw ACPI_BUFFER rb; 116fc396574Srw ACPI_RESOURCE *rp; 117fc396574Srw int rv; 118fc396574Srw 119fc396574Srw if (pci_bus_res[bus].dip == NULL) { 120fc396574Srw /* non-used bus # */ 121fc396574Srw return (AE_ERROR); 122fc396574Srw } 1235cff7825Smh if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) { 124fc396574Srw cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus); 125fc396574Srw return (AE_ERROR); 126fc396574Srw } 127fc396574Srw 128fc396574Srw rb.Length = ACPI_ALLOCATE_BUFFER; 129fc396574Srw if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) { 130fc396574Srw cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus); 131fc396574Srw return (AE_ERROR); 132fc396574Srw } 133fc396574Srw 134fc396574Srw rv = AE_ERROR; 135fc396574Srw 136fc396574Srw for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG; 137fc396574Srw rp = ACPI_NEXT_RESOURCE(rp)) { 138fc396574Srw 139fc396574Srw switch (rp->Type) { 1409896aa55Sjveta case ACPI_RESOURCE_TYPE_ADDRESS16: 1419896aa55Sjveta if (rp->Data.Address.ResourceType != 1429896aa55Sjveta ACPI_BUS_NUMBER_RANGE) 1439896aa55Sjveta continue; 1449896aa55Sjveta *subbus = (uchar_t)rp->Data.Address16.Maximum; 1459896aa55Sjveta dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus); 1469896aa55Sjveta break; 1479896aa55Sjveta case ACPI_RESOURCE_TYPE_ADDRESS32: 1489896aa55Sjveta if (rp->Data.Address.ResourceType != 1499896aa55Sjveta ACPI_BUS_NUMBER_RANGE) 1509896aa55Sjveta continue; 1519896aa55Sjveta *subbus = (uchar_t)rp->Data.Address32.Maximum; 1529896aa55Sjveta dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus); 1539896aa55Sjveta break; 1549896aa55Sjveta case ACPI_RESOURCE_TYPE_ADDRESS64: 1559896aa55Sjveta if (rp->Data.Address.ResourceType != 1569896aa55Sjveta ACPI_BUS_NUMBER_RANGE) 1579896aa55Sjveta continue; 1589896aa55Sjveta *subbus = (uchar_t)rp->Data.Address64.Maximum; 1599896aa55Sjveta dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus); 1609896aa55Sjveta break; 1619896aa55Sjveta case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64: 1629896aa55Sjveta if (rp->Data.Address.ResourceType != 1639896aa55Sjveta ACPI_BUS_NUMBER_RANGE) 1649896aa55Sjveta continue; 1659896aa55Sjveta *subbus = (uchar_t)rp->Data.ExtAddress64.Maximum; 1669896aa55Sjveta dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus); 1679896aa55Sjveta break; 1689896aa55Sjveta default: 1699896aa55Sjveta dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type); 1709896aa55Sjveta continue; 171fc396574Srw } 172fc396574Srw 173fc396574Srw /* found the bus-range resource */ 174fc396574Srw dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus); 175fc396574Srw rv = AE_OK; 176fc396574Srw 177fc396574Srw /* This breaks out of the resource scanning loop */ 178fc396574Srw break; 179fc396574Srw } 180fc396574Srw 181fc396574Srw AcpiOsFree(rb.Pointer); 182fc396574Srw if (rv != AE_OK) 183fc396574Srw cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus); 184fc396574Srw 185fc396574Srw return (rv); 186fc396574Srw 187fc396574Srw } 188fc396574Srw 1897c478bd9Sstevel@tonic-gate /* 1907c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 1917c478bd9Sstevel@tonic-gate */ 1927c478bd9Sstevel@tonic-gate void 1937c478bd9Sstevel@tonic-gate pci_setup_tree() 1947c478bd9Sstevel@tonic-gate { 1957c478bd9Sstevel@tonic-gate uchar_t i, root_bus_addr = 0; 1967c478bd9Sstevel@tonic-gate 197f55ce205Sszhou alloc_res_array(); 1987c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 1997c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 2007c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 2017c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 2027c478bd9Sstevel@tonic-gate } 2037c478bd9Sstevel@tonic-gate 2047c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 2057c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 2067c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 2077c478bd9Sstevel@tonic-gate 2087c478bd9Sstevel@tonic-gate /* 2097c478bd9Sstevel@tonic-gate * Now enumerate peer busses 2107c478bd9Sstevel@tonic-gate * 2117c478bd9Sstevel@tonic-gate * We loop till pci_bios_nbus. On most systems, there is 2127c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 2137c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 2147c478bd9Sstevel@tonic-gate * 2157c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 2167c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 2177c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 2187c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 2197c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 2207c478bd9Sstevel@tonic-gate * device below. 2217c478bd9Sstevel@tonic-gate */ 2227c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_bios_nbus; i++) { 2237c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 2247c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 2257c478bd9Sstevel@tonic-gate } 2267c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 227b1f176e8Sjg 228b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 229b1f176e8Sjg add_bus_slot_names_prop(i); 2307c478bd9Sstevel@tonic-gate } 2317c478bd9Sstevel@tonic-gate 2327c478bd9Sstevel@tonic-gate } 2337c478bd9Sstevel@tonic-gate 23425145214Smyers /* 23525145214Smyers * >0 = present, 0 = not present, <0 = error 23625145214Smyers */ 23725145214Smyers static int 23825145214Smyers pci_bbn_present(int bus) 23925145214Smyers { 24025145214Smyers ACPI_HANDLE hdl; 24125145214Smyers ACPI_BUFFER rb; 24225145214Smyers int rv; 24325145214Smyers 24425145214Smyers /* no dip means no _BBN */ 24525145214Smyers if (pci_bus_res[bus].dip == NULL) 24625145214Smyers return (0); 24725145214Smyers 2485cff7825Smh rv = acpica_get_handle(pci_bus_res[bus].dip, &hdl); 24925145214Smyers if (rv != AE_OK) 25025145214Smyers return (-1); 25125145214Smyers 25225145214Smyers rb.Length = ACPI_ALLOCATE_BUFFER; 25325145214Smyers 25425145214Smyers rv = AcpiEvaluateObject(hdl, "_BBN", NULL, &rb); 25525145214Smyers 25625145214Smyers if (rb.Length > 0) 25725145214Smyers AcpiOsFree(rb.Pointer); 25825145214Smyers 25925145214Smyers if (rv == AE_OK) 26025145214Smyers return (1); 26125145214Smyers else if (rv == AE_NOT_FOUND) 26225145214Smyers return (0); 26325145214Smyers else 26425145214Smyers return (-1); 26525145214Smyers } 26625145214Smyers 26725145214Smyers /* 26825145214Smyers * Return non-zero if any PCI bus in the system has an associated 26925145214Smyers * _BBN object, 0 otherwise. 27025145214Smyers */ 27125145214Smyers static int 27225145214Smyers pci_roots_have_bbn(void) 27325145214Smyers { 27425145214Smyers int i; 27525145214Smyers 27625145214Smyers /* 27725145214Smyers * Scan the PCI busses and look for at least 1 _BBN 27825145214Smyers */ 27925145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 28025145214Smyers /* skip non-root (peer) PCI busses */ 28125145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 28225145214Smyers continue; 28325145214Smyers 28425145214Smyers if (pci_bbn_present(i) > 0) 28525145214Smyers return (1); 28625145214Smyers } 28725145214Smyers return (0); 28825145214Smyers 28925145214Smyers } 29025145214Smyers 29125145214Smyers /* 29225145214Smyers * return non-zero if the machine is one on which we renumber 29325145214Smyers * the internal pci unit-addresses 29425145214Smyers */ 29525145214Smyers static int 29625145214Smyers pci_bus_renumber() 29725145214Smyers { 298ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 29925145214Smyers 300ee8c1d4aSdm if (pci_bus_always_renumber) 30125145214Smyers return (1); 302ee8c1d4aSdm 303ee8c1d4aSdm /* get the FADT */ 304ee8c1d4aSdm if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING, 305ee8c1d4aSdm (ACPI_TABLE_HEADER **)&fadt) != AE_OK) 30625145214Smyers return (0); 30725145214Smyers 308ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 309ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 310ee8c1d4aSdm return (0); 311ee8c1d4aSdm else 312ee8c1d4aSdm return (1); 31325145214Smyers } 31425145214Smyers 31525145214Smyers /* 31625145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 31725145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 31825145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 31925145214Smyers * _BBN object associated with each peer bus; use the presence 32025145214Smyers * of this object to remove gaps in the numbering of the peer 32125145214Smyers * PCI bus unit-addresses - only peer busses with an associated 32225145214Smyers * _BBN are counted. 32325145214Smyers */ 32425145214Smyers static void 32525145214Smyers pci_renumber_root_busses(void) 32625145214Smyers { 32725145214Smyers int pci_regs[] = {0, 0, 0}; 32825145214Smyers int i, root_addr = 0; 32925145214Smyers 330ee8c1d4aSdm /* 331ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 332ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 333ee8c1d4aSdm * issue of upgrade changing physical device paths 334ee8c1d4aSdm */ 33525145214Smyers if (!pci_bus_renumber()) 33625145214Smyers return; 33725145214Smyers 33825145214Smyers /* 33925145214Smyers * If we find no _BBN objects at all, we either don't need 34025145214Smyers * to do anything or can't do anything anyway 34125145214Smyers */ 34225145214Smyers if (!pci_roots_have_bbn()) 34325145214Smyers return; 34425145214Smyers 34525145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 34625145214Smyers /* skip non-root (peer) PCI busses */ 34725145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 34825145214Smyers continue; 34925145214Smyers 35025145214Smyers if (pci_bbn_present(i) < 1) { 35125145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 35225145214Smyers continue; 35325145214Smyers } 35425145214Smyers 35525145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 35625145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 35725145214Smyers /* update reg property for node */ 35825145214Smyers pci_bus_res[i].root_addr = root_addr; 35925145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 36025145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 36125145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 36225145214Smyers } 36325145214Smyers root_addr++; 36425145214Smyers } 36525145214Smyers } 36625145214Smyers 367aaba6dfeSmyers static void 368aaba6dfeSmyers remove_resource_range(struct memlist **list, int *ranges, int range_count) 369aaba6dfeSmyers { 370aaba6dfeSmyers struct range { 371aaba6dfeSmyers uint32_t base; 372aaba6dfeSmyers uint32_t len; 373aaba6dfeSmyers }; 374aaba6dfeSmyers int index; 375aaba6dfeSmyers 376aaba6dfeSmyers for (index = 0; index < range_count; index++) { 377328364c0Smyers /* all done if list is or has become empty */ 378328364c0Smyers if (*list == NULL) 379328364c0Smyers break; 380aaba6dfeSmyers (void) memlist_remove(list, 381aaba6dfeSmyers (uint64_t)((struct range *)ranges)[index].base, 382aaba6dfeSmyers (uint64_t)((struct range *)ranges)[index].len); 383aaba6dfeSmyers } 384aaba6dfeSmyers } 385aaba6dfeSmyers 386aaba6dfeSmyers static void 387aaba6dfeSmyers remove_used_resources() 388aaba6dfeSmyers { 389aaba6dfeSmyers dev_info_t *used; 390aaba6dfeSmyers int *narray; 391aaba6dfeSmyers uint_t ncount; 392aaba6dfeSmyers int status; 393aaba6dfeSmyers int bus; 394aaba6dfeSmyers 395aaba6dfeSmyers used = ddi_find_devinfo("used-resources", -1, 0); 396328364c0Smyers if (used == NULL) 397aaba6dfeSmyers return; 398aaba6dfeSmyers 399aaba6dfeSmyers status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 400aaba6dfeSmyers DDI_PROP_DONTPASS, "io-space", &narray, &ncount); 401aaba6dfeSmyers if (status == DDI_PROP_SUCCESS) { 402aaba6dfeSmyers for (bus = 0; bus <= pci_bios_nbus; bus++) 403328364c0Smyers remove_resource_range(&pci_bus_res[bus].io_ports, 404328364c0Smyers narray, ncount / 2); 405aaba6dfeSmyers ddi_prop_free(narray); 406aaba6dfeSmyers } 407aaba6dfeSmyers 408aaba6dfeSmyers status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used, 409aaba6dfeSmyers DDI_PROP_DONTPASS, "device-memory", &narray, &ncount); 410aaba6dfeSmyers if (status == DDI_PROP_SUCCESS) { 411aaba6dfeSmyers for (bus = 0; bus <= pci_bios_nbus; bus++) 412328364c0Smyers remove_resource_range(&pci_bus_res[bus].mem_space, 4139896aa55Sjveta narray, ncount / 2); 414aaba6dfeSmyers ddi_prop_free(narray); 415aaba6dfeSmyers } 416aaba6dfeSmyers } 417aaba6dfeSmyers 4185af4ae46Sjveta /* 4195af4ae46Sjveta * Walk up ACPI namespace starting from parobj looking for object with name 4205af4ae46Sjveta */ 4215af4ae46Sjveta static ACPI_STATUS 4225af4ae46Sjveta lookup_acpi_obj(ACPI_HANDLE parobj, char *name, ACPI_HANDLE *retobjp) 4235af4ae46Sjveta { 4245af4ae46Sjveta ACPI_HANDLE obj; 4255af4ae46Sjveta 4265af4ae46Sjveta do { 4275af4ae46Sjveta if (AcpiGetHandle(parobj, name, retobjp) == AE_OK) { 4285af4ae46Sjveta ASSERT(*retobjp != NULL); 4295af4ae46Sjveta return (AE_OK); 4305af4ae46Sjveta } 4315af4ae46Sjveta obj = parobj; 4325af4ae46Sjveta } while (AcpiGetParent(obj, &parobj) == AE_OK); 4335af4ae46Sjveta 4345af4ae46Sjveta *retobjp = NULL; 4355af4ae46Sjveta return (AE_NOT_FOUND); 4365af4ae46Sjveta } 4375af4ae46Sjveta 4385af4ae46Sjveta static int 4395af4ae46Sjveta check_ppb_hotplug(dev_info_t *dip) 4405af4ae46Sjveta { 4415af4ae46Sjveta ACPI_HANDLE pcibus_obj; 4425af4ae46Sjveta ACPI_HANDLE obj; 4435af4ae46Sjveta uint32_t hp_mode = ACPI_HP_MODE; 4445af4ae46Sjveta 4455af4ae46Sjveta if (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4465af4ae46Sjveta "pci-hotplug-type", INBAND_HPC_NONE) != INBAND_HPC_PCIE) 4475af4ae46Sjveta return (0); 4485af4ae46Sjveta 4495af4ae46Sjveta if (acpica_get_handle(dip, &pcibus_obj) != AE_OK) 4505af4ae46Sjveta return (0); 4515af4ae46Sjveta 4525af4ae46Sjveta if (lookup_acpi_obj(pcibus_obj, "_OSC", &obj) == AE_OK) { 4535af4ae46Sjveta if (pciehpc_acpi_eval_osc(obj, &hp_mode) != AE_OK) 4545af4ae46Sjveta hp_mode = ACPI_HP_MODE; 4555af4ae46Sjveta } 4565af4ae46Sjveta 4575af4ae46Sjveta if (hp_mode == NATIVE_HP_MODE) 4585af4ae46Sjveta return (1); 4595af4ae46Sjveta 4605af4ae46Sjveta /* 4615af4ae46Sjveta * if ACPI hotplug mode, a child obj for the slot is also required 4625af4ae46Sjveta */ 4635af4ae46Sjveta if (AcpiGetNextObject(ACPI_TYPE_DEVICE, pcibus_obj, NULL, &obj) != 4645af4ae46Sjveta AE_OK) 4655af4ae46Sjveta return (0); 4665af4ae46Sjveta 4675af4ae46Sjveta return (1); 4685af4ae46Sjveta } 4695af4ae46Sjveta 4709896aa55Sjveta /* 4719896aa55Sjveta * Assign i/o resources to unconfigured hotplug bridges after the first pass. 4729896aa55Sjveta * It must be after the first pass in order to use the ports left over after 4739896aa55Sjveta * accounting for i/o resources of bridges that have been configured by bios. 4749896aa55Sjveta * We are expecting unconfigured bridges to be empty bridges otherwise 4759896aa55Sjveta * this resource assignment needs to be done at an earlier stage. 4769896aa55Sjveta */ 4779896aa55Sjveta static void 4789896aa55Sjveta fix_ppb_res(uchar_t secbus) 4799896aa55Sjveta { 4809896aa55Sjveta uchar_t bus, dev, func; 4815af4ae46Sjveta uint_t base, limit; 4825af4ae46Sjveta uint_t io_size = 0x1000; /* io range must be mult of and 4k aligned */ 4835af4ae46Sjveta uint64_t addr; 4845af4ae46Sjveta int *regp = NULL; 4859896aa55Sjveta uint_t reglen; 4865af4ae46Sjveta int rv, cap_ptr, physhi; 4879896aa55Sjveta dev_info_t *dip; 4889896aa55Sjveta 4899896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 4905af4ae46Sjveta dip = pci_bus_res[secbus].dip; 4919896aa55Sjveta if (dip == NULL) 4929896aa55Sjveta return; 4939896aa55Sjveta 4945af4ae46Sjveta if (!check_ppb_hotplug(dip)) 4959896aa55Sjveta return; 4969896aa55Sjveta 4979896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4989896aa55Sjveta "reg", ®p, ®len); 4995af4ae46Sjveta ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0); 5005af4ae46Sjveta physhi = regp[0]; 5015af4ae46Sjveta ddi_prop_free(regp); 5029896aa55Sjveta 5035af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 5045af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 5055af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 5069896aa55Sjveta ASSERT(bus == pci_bus_res[secbus].par_bus); 5079896aa55Sjveta 5089896aa55Sjveta /* 5095af4ae46Sjveta * Check if the slot is enabled 5109896aa55Sjveta */ 5115af4ae46Sjveta cap_ptr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5125af4ae46Sjveta "pcie-capid-pointer", PCI_CAP_NEXT_PTR_NULL); 5135af4ae46Sjveta if (cap_ptr == PCI_CAP_NEXT_PTR_NULL) 5145af4ae46Sjveta return; 5159896aa55Sjveta 5165af4ae46Sjveta if (pci_getw(bus, dev, func, (uint16_t)cap_ptr + PCIE_LINKCTL) & 5175af4ae46Sjveta PCIE_LINKCTL_LINK_DISABLE) 5189896aa55Sjveta return; 5199896aa55Sjveta 5205af4ae46Sjveta /* 5215af4ae46Sjveta * base >= limit means that the bridge was not configured 5225af4ae46Sjveta * This may have been set by the bios or by add_ppb_props() upon 5235af4ae46Sjveta * detecting that I/O was disabled 5245af4ae46Sjveta */ 5255af4ae46Sjveta 5265af4ae46Sjveta /* 5275af4ae46Sjveta * I/O; check and attempt to allocate io_size amount from parent 5285af4ae46Sjveta */ 5295af4ae46Sjveta base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 5305af4ae46Sjveta limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 5315af4ae46Sjveta ASSERT(base != 0xff && limit != 0xff); 5325af4ae46Sjveta 5335af4ae46Sjveta base = (base & 0xf0) << 8; 5345af4ae46Sjveta limit = ((limit & 0xf0) << 8) | 0xfff; 5359896aa55Sjveta 5365af4ae46Sjveta addr = 0; 5375af4ae46Sjveta if ((base > limit || base == 0) && 5385af4ae46Sjveta pci_bus_res[bus].io_ports != NULL) { 5399896aa55Sjveta addr = memlist_find(&pci_bus_res[bus].io_ports, io_size, 5409896aa55Sjveta 0x1000); 5415af4ae46Sjveta ASSERT(addr <= 0xffff - io_size); 5425af4ae46Sjveta } 5435af4ae46Sjveta if (addr != 0) { 5445af4ae46Sjveta memlist_insert(&pci_bus_res[secbus].io_ports, addr, io_size); 5455af4ae46Sjveta base = addr; 5465af4ae46Sjveta limit = addr + io_size - 1; 5475af4ae46Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 5485af4ae46Sjveta (uint8_t)((base >> 8) & 0xf0)); 5495af4ae46Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 5505af4ae46Sjveta (uint8_t)((limit >> 8) & 0xf0)); 5519896aa55Sjveta } 5529896aa55Sjveta 5535af4ae46Sjveta /* 5545af4ae46Sjveta * Account for new resources 5555af4ae46Sjveta */ 5569896aa55Sjveta add_ppb_ranges_prop(secbus); 5579896aa55Sjveta } 5589896aa55Sjveta 5597c478bd9Sstevel@tonic-gate void 5607c478bd9Sstevel@tonic-gate pci_reprogram(void) 5617c478bd9Sstevel@tonic-gate { 5627c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 5637c478bd9Sstevel@tonic-gate char *onoff; 5647c478bd9Sstevel@tonic-gate 56525145214Smyers /* 56625145214Smyers * Excise phantom roots if possible 56725145214Smyers */ 56825145214Smyers pci_renumber_root_busses(); 56925145214Smyers 570fc396574Srw /* add bus-range property for root/peer bus nodes */ 571fc396574Srw for (i = 0; i <= pci_bios_nbus; i++) { 572fc396574Srw if (pci_bus_res[i].par_bus == (uchar_t)-1) { 573fc396574Srw uchar_t subbus; 574fc396574Srw if (pci_root_subbus(i, &subbus) == AE_OK) 5759896aa55Sjveta pci_bus_res[i].sub_bus = subbus; 576fc396574Srw add_bus_range_prop(i); 577fc396574Srw } 578fc396574Srw } 579fc396574Srw 5807c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 5817c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 5827c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 5837c478bd9Sstevel@tonic-gate pci_reconfig = 0; 5847c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 5857c478bd9Sstevel@tonic-gate } 5867c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 5877c478bd9Sstevel@tonic-gate } 5887c478bd9Sstevel@tonic-gate 589aaba6dfeSmyers /* remove used-resources from PCI resource maps */ 590aaba6dfeSmyers remove_used_resources(); 591aaba6dfeSmyers 5927c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 5937c478bd9Sstevel@tonic-gate /* configure devices not configured by bios */ 5949896aa55Sjveta if (pci_reconfig) { 5959896aa55Sjveta fix_ppb_res(i); 5967c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 5979896aa55Sjveta } 5987c478bd9Sstevel@tonic-gate /* All dev programmed, so we can create available prop */ 5997c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 6007c478bd9Sstevel@tonic-gate } 6017c478bd9Sstevel@tonic-gate } 6027c478bd9Sstevel@tonic-gate 6037c478bd9Sstevel@tonic-gate /* 6047c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 6057c478bd9Sstevel@tonic-gate */ 6067c478bd9Sstevel@tonic-gate static void 6077c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 6087c478bd9Sstevel@tonic-gate { 6097c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 6107c478bd9Sstevel@tonic-gate dev_info_t *dip; 6117c478bd9Sstevel@tonic-gate 6127c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 6137c478bd9Sstevel@tonic-gate 6147c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 615fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 6167c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 6177c478bd9Sstevel@tonic-gate "#address-cells", 3); 6187c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 6197c478bd9Sstevel@tonic-gate "#size-cells", 2); 6207c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 6217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 6227c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 6237c478bd9Sstevel@tonic-gate 62470025d76Sjohnny /* 62570025d76Sjohnny * If system has PCIe bus, then create different properties 62670025d76Sjohnny */ 62770025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 62870025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 62970025d76Sjohnny "device_type", "pci"); 63070025d76Sjohnny 6317c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 6327c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 6337c478bd9Sstevel@tonic-gate pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 6347c478bd9Sstevel@tonic-gate pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 6357c478bd9Sstevel@tonic-gate pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 6367c478bd9Sstevel@tonic-gate 6377c478bd9Sstevel@tonic-gate if (bus != 0) 6387c478bd9Sstevel@tonic-gate return; 6397c478bd9Sstevel@tonic-gate 6407c478bd9Sstevel@tonic-gate /* 6417c478bd9Sstevel@tonic-gate * Special treatment of bus 0: 6427c478bd9Sstevel@tonic-gate * If no resource from MPSPEC/HRT, copy pcimem from boot 643aaba6dfeSmyers * and make I/O space the entire range starting at 0x100. There 644aaba6dfeSmyers * is no difference between prefetchable memory or not. 6457c478bd9Sstevel@tonic-gate */ 6467c478bd9Sstevel@tonic-gate if (pci_bus_res[0].mem_space == NULL) 6477c478bd9Sstevel@tonic-gate pci_bus_res[0].mem_space = 6487c478bd9Sstevel@tonic-gate memlist_dup(bootops->boot_mem->pcimem); 649aaba6dfeSmyers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 6507c478bd9Sstevel@tonic-gate if (pci_bus_res[0].io_ports == NULL) 6515af4ae46Sjveta memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff); 6527c478bd9Sstevel@tonic-gate } 6537c478bd9Sstevel@tonic-gate 6547c478bd9Sstevel@tonic-gate /* 6557c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 6567c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 6577c478bd9Sstevel@tonic-gate * to hold the already configured device details. 6587c478bd9Sstevel@tonic-gate */ 6597c478bd9Sstevel@tonic-gate void 6607c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 6617c478bd9Sstevel@tonic-gate { 6627c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 6637c478bd9Sstevel@tonic-gate ushort_t venid; 6647c478bd9Sstevel@tonic-gate dev_info_t *dip; 6657c478bd9Sstevel@tonic-gate struct pci_devfunc { 6667c478bd9Sstevel@tonic-gate struct pci_devfunc *next; 6677c478bd9Sstevel@tonic-gate dev_info_t *dip; 6687c478bd9Sstevel@tonic-gate uchar_t bus; 6697c478bd9Sstevel@tonic-gate uchar_t dev; 6707c478bd9Sstevel@tonic-gate uchar_t func; 6717c478bd9Sstevel@tonic-gate } *devlist = NULL, *entry; 6727c478bd9Sstevel@tonic-gate 6737c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 6747c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 675bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 676bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 6777c478bd9Sstevel@tonic-gate } else 6787c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 6797c478bd9Sstevel@tonic-gate 6807c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 6817c478bd9Sstevel@tonic-gate nfunc = 1; 6827c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 6837c478bd9Sstevel@tonic-gate 6847c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 6857c478bd9Sstevel@tonic-gate dev, func); 6867c478bd9Sstevel@tonic-gate 6877c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 688bd87be88Ssethg 6897c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 6907c478bd9Sstevel@tonic-gate /* no function at this address */ 6917c478bd9Sstevel@tonic-gate continue; 6927c478bd9Sstevel@tonic-gate } 6937c478bd9Sstevel@tonic-gate 6947c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 6957c478bd9Sstevel@tonic-gate if (header == 0xff) { 6967c478bd9Sstevel@tonic-gate continue; /* illegal value */ 6977c478bd9Sstevel@tonic-gate } 6987c478bd9Sstevel@tonic-gate 6997c478bd9Sstevel@tonic-gate /* 7007c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 7017c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 7027c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 7037c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 7047c478bd9Sstevel@tonic-gate */ 7057c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 7067c478bd9Sstevel@tonic-gate nfunc = 8; 7077c478bd9Sstevel@tonic-gate } 70846e9e839Smyers 709bd87be88Ssethg if (config_op == CONFIG_FIX) { 710bd87be88Ssethg /* 711bd87be88Ssethg * If we're processing PCI fixes, no dip 712bd87be88Ssethg * will be returned. 713bd87be88Ssethg */ 714bd87be88Ssethg (void) process_devfunc(bus, dev, func, header, 715bd87be88Ssethg venid, config_op); 716bd87be88Ssethg 717bd87be88Ssethg } else if (config_op == CONFIG_INFO) { 718ebf3afa8Sdmick /* 719ebf3afa8Sdmick * Create the node, unconditionally, on the 720ebf3afa8Sdmick * first pass only. It may still need 721ebf3afa8Sdmick * resource assignment, which will be 722ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 723ebf3afa8Sdmick */ 724bd87be88Ssethg dip = process_devfunc(bus, dev, func, header, 725ebf3afa8Sdmick venid, config_op); 726db063408Sdmick /* 727db063408Sdmick * If dip isn't null, put on a list to 728db063408Sdmick * save for reprogramming when config_op 729db063408Sdmick * is CONFIG_NEW. 730db063408Sdmick */ 731db063408Sdmick 732db063408Sdmick if (dip) { 733db063408Sdmick entry = kmem_alloc(sizeof (*entry), 734db063408Sdmick KM_SLEEP); 735db063408Sdmick entry->dip = dip; 736db063408Sdmick entry->dev = dev; 737db063408Sdmick entry->func = func; 738db063408Sdmick entry->next = devlist; 739db063408Sdmick devlist = entry; 740db063408Sdmick } 7417c478bd9Sstevel@tonic-gate } 7427c478bd9Sstevel@tonic-gate } 7437c478bd9Sstevel@tonic-gate } 7447c478bd9Sstevel@tonic-gate 7457c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 7467c478bd9Sstevel@tonic-gate devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 7477c478bd9Sstevel@tonic-gate while (devlist) { 7487c478bd9Sstevel@tonic-gate entry = devlist; 7497c478bd9Sstevel@tonic-gate devlist = entry->next; 7507c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, 7517c478bd9Sstevel@tonic-gate "!reprogram pci device [%d/%d/%d] (%s)", 7527c478bd9Sstevel@tonic-gate bus, entry->dev, entry->func, 7537c478bd9Sstevel@tonic-gate ddi_driver_name(entry->dip)); 7547c478bd9Sstevel@tonic-gate (void) add_reg_props(entry->dip, bus, entry->dev, 7557c478bd9Sstevel@tonic-gate entry->func, CONFIG_UPDATE, 0); 7567c478bd9Sstevel@tonic-gate kmem_free(entry, sizeof (*entry)); 7577c478bd9Sstevel@tonic-gate } 7587c478bd9Sstevel@tonic-gate pci_bus_res[bus].privdata = NULL; 759bd87be88Ssethg } else if (config_op != CONFIG_FIX) { 7607c478bd9Sstevel@tonic-gate pci_bus_res[bus].privdata = devlist; 7617c478bd9Sstevel@tonic-gate } 7627c478bd9Sstevel@tonic-gate } 7637c478bd9Sstevel@tonic-gate 7647c478bd9Sstevel@tonic-gate static int 7657c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 7667c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 7677c478bd9Sstevel@tonic-gate { 7687c478bd9Sstevel@tonic-gate static int prop_exist = -1; 7697c478bd9Sstevel@tonic-gate static char *pciide_str; 7707c478bd9Sstevel@tonic-gate char compat[32]; 7717c478bd9Sstevel@tonic-gate 7727c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 7737c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 7747c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 7757c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 7767c478bd9Sstevel@tonic-gate } 7777c478bd9Sstevel@tonic-gate 7787c478bd9Sstevel@tonic-gate if (!prop_exist) 7797c478bd9Sstevel@tonic-gate return (0); 7807c478bd9Sstevel@tonic-gate 7817c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 7827c478bd9Sstevel@tonic-gate if (subvenid) { 7837c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 7847c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 7857c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 7867c478bd9Sstevel@tonic-gate return (1); 7877c478bd9Sstevel@tonic-gate 7887c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 7897c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 7907c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 7917c478bd9Sstevel@tonic-gate return (1); 7927c478bd9Sstevel@tonic-gate 7937c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 7947c478bd9Sstevel@tonic-gate subvenid, subdevid); 7957c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 7967c478bd9Sstevel@tonic-gate return (1); 7977c478bd9Sstevel@tonic-gate } 7987c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 7997c478bd9Sstevel@tonic-gate venid, devid, revid); 8007c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 8017c478bd9Sstevel@tonic-gate return (1); 8027c478bd9Sstevel@tonic-gate 8037c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 8047c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 8057c478bd9Sstevel@tonic-gate return (1); 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate return (0); 8087c478bd9Sstevel@tonic-gate } 8097c478bd9Sstevel@tonic-gate 8107c478bd9Sstevel@tonic-gate static int 8117c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 8127c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 8137c478bd9Sstevel@tonic-gate { 8147c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 8157c478bd9Sstevel@tonic-gate ushort_t venid; 8167c478bd9Sstevel@tonic-gate ushort_t devid; 8177c478bd9Sstevel@tonic-gate } *entry; 8187c478bd9Sstevel@tonic-gate 8197c478bd9Sstevel@tonic-gate /* XXX SATA devices: need a way to add dynamically */ 8207c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 8217c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 8227c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 8237c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 8247c478bd9Sstevel@tonic-gate {0, 0} 8257c478bd9Sstevel@tonic-gate }; 8267c478bd9Sstevel@tonic-gate 8277c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 8287c478bd9Sstevel@tonic-gate return (0); 8297c478bd9Sstevel@tonic-gate 8307c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 8317c478bd9Sstevel@tonic-gate return (1); 8327c478bd9Sstevel@tonic-gate } 8337c478bd9Sstevel@tonic-gate 8347c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 8357c478bd9Sstevel@tonic-gate return (0); 8367c478bd9Sstevel@tonic-gate } 8377c478bd9Sstevel@tonic-gate 8387c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 8397c478bd9Sstevel@tonic-gate while (entry->venid) { 8407c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 8417c478bd9Sstevel@tonic-gate return (1); 8427c478bd9Sstevel@tonic-gate entry++; 8437c478bd9Sstevel@tonic-gate } 8447c478bd9Sstevel@tonic-gate return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 8457c478bd9Sstevel@tonic-gate } 8467c478bd9Sstevel@tonic-gate 8477c478bd9Sstevel@tonic-gate static int 8487c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 8497c478bd9Sstevel@tonic-gate { 8507c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 8517c478bd9Sstevel@tonic-gate 0x000100, 8527c478bd9Sstevel@tonic-gate 0x030000, 8537c478bd9Sstevel@tonic-gate 0x030001 8547c478bd9Sstevel@tonic-gate }; 8557c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 8567c478bd9Sstevel@tonic-gate 8577c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 8587c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 8597c478bd9Sstevel@tonic-gate return (1); 8607c478bd9Sstevel@tonic-gate } 8617c478bd9Sstevel@tonic-gate return (0); 8627c478bd9Sstevel@tonic-gate } 8637c478bd9Sstevel@tonic-gate 864bd87be88Ssethg static void 865bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 866bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 867bd87be88Ssethg { 868bd87be88Ssethg struct pci_fixundo *newundo; 869bd87be88Ssethg 870bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 871bd87be88Ssethg 872bd87be88Ssethg /* 873bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 874bd87be88Ssethg * bit back on at a later time. 875bd87be88Ssethg */ 876bd87be88Ssethg newundo->bus = bus; 877bd87be88Ssethg newundo->dev = dev; 878bd87be88Ssethg newundo->fn = fn; 879bd87be88Ssethg newundo->undofn = undofn; 880bd87be88Ssethg newundo->next = undolist; 881bd87be88Ssethg 882bd87be88Ssethg /* add to the undo list in LIFO order */ 883bd87be88Ssethg undolist = newundo; 884bd87be88Ssethg } 885bd87be88Ssethg 886bd87be88Ssethg void 887bd87be88Ssethg add_pci_fixes(void) 888bd87be88Ssethg { 889bd87be88Ssethg int i; 890bd87be88Ssethg 891bd87be88Ssethg for (i = 0; i <= pci_bios_nbus; i++) { 892bd87be88Ssethg /* 893bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 894bd87be88Ssethg * This must be done before the main enumeration loop because 895bd87be88Ssethg * some fixes must be applied to devices normally encountered 896bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 897bd87be88Ssethg * applied before scanning device 6, applying fixes in the 898bd87be88Ssethg * normal enumeration loop would obviously be too late). 899bd87be88Ssethg */ 900bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 901bd87be88Ssethg } 902bd87be88Ssethg } 903bd87be88Ssethg 904bd87be88Ssethg void 905bd87be88Ssethg undo_pci_fixes(void) 906bd87be88Ssethg { 907bd87be88Ssethg struct pci_fixundo *nextundo; 908bd87be88Ssethg uint8_t bus, dev, fn; 909bd87be88Ssethg 910bd87be88Ssethg /* 911bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 912bd87be88Ssethg * fixes may require selective undo. 913bd87be88Ssethg */ 914bd87be88Ssethg while (undolist != NULL) { 915bd87be88Ssethg 916bd87be88Ssethg bus = undolist->bus; 917bd87be88Ssethg dev = undolist->dev; 918bd87be88Ssethg fn = undolist->fn; 919bd87be88Ssethg 920bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 921bd87be88Ssethg 922bd87be88Ssethg nextundo = undolist->next; 923bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 924bd87be88Ssethg undolist = nextundo; 925bd87be88Ssethg } 926bd87be88Ssethg } 927bd87be88Ssethg 928bd87be88Ssethg static void 929bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 930bd87be88Ssethg { 931bd87be88Ssethg uint8_t val8; 932bd87be88Ssethg 933bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 934bd87be88Ssethg /* 935bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 936bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 937bd87be88Ssethg */ 938bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 939bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 940bd87be88Ssethg } 941bd87be88Ssethg 942bd87be88Ssethg static void 943bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 944bd87be88Ssethg { 945bd87be88Ssethg uint8_t val8; 946bd87be88Ssethg 947bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 948bd87be88Ssethg 949bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 950bd87be88Ssethg return; 951bd87be88Ssethg 952bd87be88Ssethg /* 953bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 954bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 955bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 956bd87be88Ssethg */ 957bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 958bd87be88Ssethg 959bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 960bd87be88Ssethg 961bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 962bd87be88Ssethg } 963bd87be88Ssethg 9647c478bd9Sstevel@tonic-gate static dev_info_t * 965bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 9667c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 9677c478bd9Sstevel@tonic-gate { 9687c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 9697c478bd9Sstevel@tonic-gate dev_info_t *dip; 970c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 9717c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 97270025d76Sjohnny ushort_t slot_num; 9737c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 9748d483882Smlf int reprogram = 0, pciide = 0; 9757c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 97670025d76Sjohnny int pciex = 0; 97770025d76Sjohnny ushort_t is_pci_bridge = 0; 9787c478bd9Sstevel@tonic-gate 9797c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 9807c478bd9Sstevel@tonic-gate 9817c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 9827c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 9837c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 9847c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 9857c478bd9Sstevel@tonic-gate break; 9867c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 9877c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 9887c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 9897c478bd9Sstevel@tonic-gate break; 9907c478bd9Sstevel@tonic-gate default: 9917c478bd9Sstevel@tonic-gate subvenid = 0; 9927c478bd9Sstevel@tonic-gate subdevid = 0; 9937c478bd9Sstevel@tonic-gate break; 9947c478bd9Sstevel@tonic-gate } 9957c478bd9Sstevel@tonic-gate 996bd87be88Ssethg if (config_op == CONFIG_FIX) { 997bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 998bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 999bd87be88Ssethg } 1000bd87be88Ssethg return (NULL); 1001bd87be88Ssethg } 1002bd87be88Ssethg 10037c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 10047c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 10057c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 10067c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 10077c478bd9Sstevel@tonic-gate 10087c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 10097c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 10107c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1011c8589f13Ssethg progcl = classcode & 0xff; 10127c478bd9Sstevel@tonic-gate 10138d483882Smlf 10148d483882Smlf if (is_display(classcode)) 10157c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 10167c478bd9Sstevel@tonic-gate else if (subvenid != 0) 10177c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 10187c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 10197c478bd9Sstevel@tonic-gate else 10207c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 10217c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 10227c478bd9Sstevel@tonic-gate 10237c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 10247c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) { 10257c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 10267c478bd9Sstevel@tonic-gate } 10277c478bd9Sstevel@tonic-gate 10287c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 10297c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 10307c478bd9Sstevel@tonic-gate 103100d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 103200d0963fSdilpreet &is_pci_bridge) == B_TRUE) 103300d0963fSdilpreet pciex = 1; 103400d0963fSdilpreet 10357c478bd9Sstevel@tonic-gate /* add properties */ 10367c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 10377c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 10387c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 10397c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10407c478bd9Sstevel@tonic-gate "class-code", classcode); 10417c478bd9Sstevel@tonic-gate if (func == 0) 10427c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 10437c478bd9Sstevel@tonic-gate else 10447c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 10457c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 10467c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 10477c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 10487c478bd9Sstevel@tonic-gate 1049ebf3afa8Sdmick /* add device_type for display nodes */ 1050ebf3afa8Sdmick if (is_display(classcode)) { 1051ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1052ebf3afa8Sdmick "device_type", "display"); 1053ebf3afa8Sdmick } 10547c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 10557c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 10567c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 10577c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 10587c478bd9Sstevel@tonic-gate 10597c478bd9Sstevel@tonic-gate if (subvenid != 0) { 10607c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10617c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 10627c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10637c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 10647c478bd9Sstevel@tonic-gate } 106570025d76Sjohnny if (!pciex) 106670025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 106770025d76Sjohnny "min-grant", mingrant); 106870025d76Sjohnny if (!pciex) 106970025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 107070025d76Sjohnny "max-latency", maxlatency); 10717c478bd9Sstevel@tonic-gate } 10727c478bd9Sstevel@tonic-gate 10737c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 10747c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 10757c478bd9Sstevel@tonic-gate if (intr != 0) 10767c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10777c478bd9Sstevel@tonic-gate "interrupts", intr); 10787c478bd9Sstevel@tonic-gate 10797c478bd9Sstevel@tonic-gate /* 10807c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 10817c478bd9Sstevel@tonic-gate */ 10827c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 10837c478bd9Sstevel@tonic-gate 10847c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 10857c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 108670025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 10877c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 10887c478bd9Sstevel@tonic-gate "fast-back-to-back"); 108970025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 10907c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 10917c478bd9Sstevel@tonic-gate "66mhz-capable"); 10927c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 10937c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 10947c478bd9Sstevel@tonic-gate "udf-supported"); 1095*d57b3b3dSprasad if (pciex && slot_num) { 109670025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 109770025d76Sjohnny "physical-slot#", slot_num); 1098*d57b3b3dSprasad if (!is_pci_bridge) 1099*d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 1100*d57b3b3dSprasad } 11017c478bd9Sstevel@tonic-gate 11027c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 11037c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 11047c478bd9Sstevel@tonic-gate 110570025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 110670025d76Sjohnny add_ppb_props(dip, bus, dev, func, pciex); 110770025d76Sjohnny 1108c8589f13Ssethg if (config_op == CONFIG_INFO && 1109c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1110c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 1111c8589f13Ssethg } 1112c8589f13Ssethg 111370025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 111470025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 111570025d76Sjohnny (func == 0)) 11168a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 111770025d76Sjohnny 111870025d76Sjohnny if (pciex && is_pci_bridge) 111970025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 112070025d76Sjohnny (char *)"PCIe-PCI bridge"); 112170025d76Sjohnny else 112270025d76Sjohnny add_model_prop(dip, classcode); 11237c478bd9Sstevel@tonic-gate 11247c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 112570025d76Sjohnny revid, classcode, pciex); 11268d483882Smlf 11278d483882Smlf /* 11288d483882Smlf * See if this device is a controller that advertises 11298d483882Smlf * itself to be a standard ATA task file controller, or one that 11308d483882Smlf * has been hard coded. 11318d483882Smlf * 11328d483882Smlf * If it is, check if any other higher precedence driver listed in 11338d483882Smlf * driver_aliases will claim the node by calling 11348d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 11358d483882Smlf * create a pci-ide node or any other special handling. 11368d483882Smlf * 11378d483882Smlf * If another driver does not bind, set the node name to pci-ide 11388d483882Smlf * and then let the special pci-ide handling for registers and 11398d483882Smlf * child pci-ide nodes proceed below. 11408d483882Smlf */ 11418d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 11428d483882Smlf subvenid, subdevid) == 1) { 11438d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 11448d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 11458d483882Smlf pciide = 1; 11468d483882Smlf } 11478d483882Smlf } 11488d483882Smlf 11497c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 11507c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 11517c478bd9Sstevel@tonic-gate 11527c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 11537c478bd9Sstevel@tonic-gate if (pciide) { 11547c478bd9Sstevel@tonic-gate dev_info_t *cdip; 11557c478bd9Sstevel@tonic-gate 11567c478bd9Sstevel@tonic-gate /* 11577c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 11587c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 11597c478bd9Sstevel@tonic-gate */ 11607c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 11617c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 11627c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 11637c478bd9Sstevel@tonic-gate "#address-cells", 1); 11647c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 11657c478bd9Sstevel@tonic-gate "#size-cells", 0); 11667c478bd9Sstevel@tonic-gate 11677c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 11687c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1169fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 11707c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 11717c478bd9Sstevel@tonic-gate "reg", 0); 11727c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 11737c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1174fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 11757c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 11767c478bd9Sstevel@tonic-gate "reg", 1); 11777c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 11787c478bd9Sstevel@tonic-gate 11797c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 11807c478bd9Sstevel@tonic-gate } 11817c478bd9Sstevel@tonic-gate 118270025d76Sjohnny 11837c478bd9Sstevel@tonic-gate if (reprogram) 11847c478bd9Sstevel@tonic-gate return (dip); 11857c478bd9Sstevel@tonic-gate return (NULL); 11867c478bd9Sstevel@tonic-gate } 11877c478bd9Sstevel@tonic-gate 11887c478bd9Sstevel@tonic-gate /* 11897c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 11907c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 119170025d76Sjohnny * (Also used for PCI-Express devices). 11927c478bd9Sstevel@tonic-gate * 11937c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 11947c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 11957c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 11967c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 11977c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 11987c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 11997c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 12007c478bd9Sstevel@tonic-gate * 12017c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 12027c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 12037c478bd9Sstevel@tonic-gate * 120470025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 120570025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 120670025d76Sjohnny * 12077c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 12087c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 12097c478bd9Sstevel@tonic-gate */ 12107c478bd9Sstevel@tonic-gate void 12117c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 121270025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 121370025d76Sjohnny int pciex) 12147c478bd9Sstevel@tonic-gate { 121570025d76Sjohnny int i = 0; 121670025d76Sjohnny int size = COMPAT_BUFSIZE; 121770025d76Sjohnny char *compat[13]; 12187c478bd9Sstevel@tonic-gate char *buf, *curr; 12197c478bd9Sstevel@tonic-gate 12207c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 12217c478bd9Sstevel@tonic-gate 122270025d76Sjohnny if (pciex) { 122370025d76Sjohnny if (subvenid) { 122470025d76Sjohnny compat[i++] = curr; /* form 0 */ 122570025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 122670025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 122770025d76Sjohnny size -= strlen(curr) + 1; 122870025d76Sjohnny curr += strlen(curr) + 1; 122970025d76Sjohnny 123070025d76Sjohnny compat[i++] = curr; /* form 1 */ 123170025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 123270025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 123370025d76Sjohnny size -= strlen(curr) + 1; 123470025d76Sjohnny curr += strlen(curr) + 1; 123570025d76Sjohnny 123670025d76Sjohnny } 123770025d76Sjohnny compat[i++] = curr; /* form 3 */ 123870025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 123970025d76Sjohnny vendorid, deviceid, revid); 124070025d76Sjohnny size -= strlen(curr) + 1; 124170025d76Sjohnny curr += strlen(curr) + 1; 124270025d76Sjohnny 124370025d76Sjohnny compat[i++] = curr; /* form 4 */ 124470025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 124570025d76Sjohnny size -= strlen(curr) + 1; 124670025d76Sjohnny curr += strlen(curr) + 1; 124770025d76Sjohnny 124870025d76Sjohnny compat[i++] = curr; /* form 5 */ 124970025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 125070025d76Sjohnny size -= strlen(curr) + 1; 125170025d76Sjohnny curr += strlen(curr) + 1; 125270025d76Sjohnny 125370025d76Sjohnny compat[i++] = curr; /* form 6 */ 125470025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 125570025d76Sjohnny (classcode >> 8)); 125670025d76Sjohnny size -= strlen(curr) + 1; 125770025d76Sjohnny curr += strlen(curr) + 1; 125870025d76Sjohnny } 125970025d76Sjohnny 12607c478bd9Sstevel@tonic-gate if (subvenid) { 12617c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 12627c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 12637c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 12647c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12657c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12667c478bd9Sstevel@tonic-gate 12677c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 12687c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 12697c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 12707c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12717c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12727c478bd9Sstevel@tonic-gate 12737c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 2 */ 127470025d76Sjohnny (void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid); 12757c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12767c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12777c478bd9Sstevel@tonic-gate } 12787c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 12797c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 12807c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12817c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12827c478bd9Sstevel@tonic-gate 12837c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 12847c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 12857c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12867c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12877c478bd9Sstevel@tonic-gate 12887c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 12897c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 12907c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 12917c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 12927c478bd9Sstevel@tonic-gate 12937c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 12947c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 129570025d76Sjohnny size -= strlen(curr) + 1; 129670025d76Sjohnny curr += strlen(curr) + 1; 12977c478bd9Sstevel@tonic-gate 12987c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 12997c478bd9Sstevel@tonic-gate "compatible", compat, i); 13007c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 13017c478bd9Sstevel@tonic-gate } 13027c478bd9Sstevel@tonic-gate 13037c478bd9Sstevel@tonic-gate /* 13047c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 13057c478bd9Sstevel@tonic-gate * 13067c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 13077c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 13087c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 13097c478bd9Sstevel@tonic-gate * mode BAR or not. 13107c478bd9Sstevel@tonic-gate */ 13117c478bd9Sstevel@tonic-gate /* 13127c478bd9Sstevel@tonic-gate * config info for pci-ide devices 13137c478bd9Sstevel@tonic-gate */ 13147c478bd9Sstevel@tonic-gate static struct { 13157c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 13167c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 13177c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 13187c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 13197c478bd9Sstevel@tonic-gate } pciide_bar[] = { 13207c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 13217c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 13227c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 13237c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 13247c478bd9Sstevel@tonic-gate }; 13257c478bd9Sstevel@tonic-gate 13267c478bd9Sstevel@tonic-gate static int 13277c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 13287c478bd9Sstevel@tonic-gate { 13297c478bd9Sstevel@tonic-gate int hard_decode = 0; 13307c478bd9Sstevel@tonic-gate 13317c478bd9Sstevel@tonic-gate /* 13327c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 13337c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 13347c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 13357c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 13367c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 13377c478bd9Sstevel@tonic-gate */ 13387c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 13397c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 13407c478bd9Sstevel@tonic-gate 13417c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 13427c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 13437c478bd9Sstevel@tonic-gate } else { 13447c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 13457c478bd9Sstevel@tonic-gate hard_decode = 1; 13467c478bd9Sstevel@tonic-gate } 13477c478bd9Sstevel@tonic-gate } 13487c478bd9Sstevel@tonic-gate 13497c478bd9Sstevel@tonic-gate /* 13507c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 13517c478bd9Sstevel@tonic-gate */ 13527c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 13537c478bd9Sstevel@tonic-gate *basep = 0; 13547c478bd9Sstevel@tonic-gate *lenp = 0; 13557c478bd9Sstevel@tonic-gate hard_decode = 0; 13567c478bd9Sstevel@tonic-gate } 13577c478bd9Sstevel@tonic-gate 13587c478bd9Sstevel@tonic-gate return (hard_decode); 13597c478bd9Sstevel@tonic-gate } 13607c478bd9Sstevel@tonic-gate 13617c478bd9Sstevel@tonic-gate 13627c478bd9Sstevel@tonic-gate /* 13637c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 13647c478bd9Sstevel@tonic-gate */ 13657c478bd9Sstevel@tonic-gate static int 13667c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 13677c478bd9Sstevel@tonic-gate int config_op, int pciide) 13687c478bd9Sstevel@tonic-gate { 13697c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 13707c478bd9Sstevel@tonic-gate ushort_t bar_sz; 13717c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 13727c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 13737c478bd9Sstevel@tonic-gate ushort_t offset, end; 13747c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 13757c478bd9Sstevel@tonic-gate uint_t phys_hi; 13767c478bd9Sstevel@tonic-gate struct memlist **io_res, **mres, **mem_res, **pmem_res; 137746e9e839Smyers uint16_t cmd_reg; 13787c478bd9Sstevel@tonic-gate 13797c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 13807c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 1381ebf3afa8Sdmick int nreg, nasgn, enable = 0; 13827c478bd9Sstevel@tonic-gate 13837c478bd9Sstevel@tonic-gate io_res = &pci_bus_res[bus].io_ports; 13847c478bd9Sstevel@tonic-gate mem_res = &pci_bus_res[bus].mem_space; 13857c478bd9Sstevel@tonic-gate if (bus == 0) /* for bus 0, there is only mem_space */ 13867c478bd9Sstevel@tonic-gate pmem_res = mem_res; 13877c478bd9Sstevel@tonic-gate else 13887c478bd9Sstevel@tonic-gate pmem_res = &pci_bus_res[bus].pmem_space; 13897c478bd9Sstevel@tonic-gate 13907c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 13917c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 13927c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 13937c478bd9Sstevel@tonic-gate nasgn = 0; 13947c478bd9Sstevel@tonic-gate 13957c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 13967c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 13977c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 13987c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 13997c478bd9Sstevel@tonic-gate 14007c478bd9Sstevel@tonic-gate switch (header) { 14017c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 14027c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 14037c478bd9Sstevel@tonic-gate break; 14047c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 14057c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 14067c478bd9Sstevel@tonic-gate break; 14077c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 14087c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 14097c478bd9Sstevel@tonic-gate break; 14107c478bd9Sstevel@tonic-gate default: 14117c478bd9Sstevel@tonic-gate max_basereg = 0; 14127c478bd9Sstevel@tonic-gate break; 14137c478bd9Sstevel@tonic-gate } 14147c478bd9Sstevel@tonic-gate 14157c478bd9Sstevel@tonic-gate /* 14167c478bd9Sstevel@tonic-gate * Create the register property by saving the current 14178d34f104Smyers * value of the base register. Write 0xffffffff to the 14188d34f104Smyers * base register. Read the value back to determine the 14198d34f104Smyers * required size of the address space. Restore the base 14208d34f104Smyers * register contents. 14218d34f104Smyers * 14228d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 14238d34f104Smyers * since no driver is yet attached to this device, and disabling 14248d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 14258d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 14268d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 14278d34f104Smyers * Spec V1.2). 14287c478bd9Sstevel@tonic-gate */ 14297c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 14307c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 14317c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 14327c478bd9Sstevel@tonic-gate int hard_decode = 0; 14337c478bd9Sstevel@tonic-gate 14347c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 14357c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 14367c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 14377c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 14387c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 14397c478bd9Sstevel@tonic-gate 14407c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 14417c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 14427c478bd9Sstevel@tonic-gate /* i/o space */ 14437c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 14447c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 14457c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 14467c478bd9Sstevel@tonic-gate 14477c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 14487c478bd9Sstevel@tonic-gate if (pciide) { 1449f088817aSyt if (subclass != PCI_MASS_IDE) 14507c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 14517c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 14527c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 14537c478bd9Sstevel@tonic-gate &base, &len); 14547c478bd9Sstevel@tonic-gate } else if (value == 0) { 14557c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 14567c478bd9Sstevel@tonic-gate continue; 14577c478bd9Sstevel@tonic-gate } 14587c478bd9Sstevel@tonic-gate 14597c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 14607c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 14617c478bd9Sstevel@tonic-gate if (!hard_decode) { 14627c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 14637c478bd9Sstevel@tonic-gate (PCI_ADDR_IO | devloc) + offset; 14647c478bd9Sstevel@tonic-gate } else { 14657c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 14667c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 14677c478bd9Sstevel@tonic-gate offset; 14687c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 14697c478bd9Sstevel@tonic-gate base & PCI_BASE_IO_ADDR_M; 14707c478bd9Sstevel@tonic-gate } 14717c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = 14727c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 14737c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 14747c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 14757c478bd9Sstevel@tonic-gate 14767c478bd9Sstevel@tonic-gate /* 14777c478bd9Sstevel@tonic-gate * first pass - gather what's there 14787c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 14797c478bd9Sstevel@tonic-gate * config - allocate regions 14807c478bd9Sstevel@tonic-gate */ 14817c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 14827c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 14837c478bd9Sstevel@tonic-gate if (*io_res && base != 0) 14847c478bd9Sstevel@tonic-gate (void) memlist_remove(io_res, 14857c478bd9Sstevel@tonic-gate (uint64_t)base, (uint64_t)len); 14867c478bd9Sstevel@tonic-gate else if (*io_res) 14877c478bd9Sstevel@tonic-gate reprogram = 1; 14887c478bd9Sstevel@tonic-gate } else if (*io_res && base == 0) { 14897c478bd9Sstevel@tonic-gate base = (uint_t)memlist_find(io_res, 1490ebf3afa8Sdmick (uint64_t)len, (uint64_t)0x4); 14917c478bd9Sstevel@tonic-gate if (base != 0) { 14927c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 14937c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 14947c478bd9Sstevel@tonic-gate base | type); 14957c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 14967c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 14977c478bd9Sstevel@tonic-gate } 14987c478bd9Sstevel@tonic-gate if (base == 0) { 14997c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 1500db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 1501db063408Sdmick " length 0x%x", 1502ebf3afa8Sdmick bus, dev, func, offset, len); 15037c478bd9Sstevel@tonic-gate } else 150446e9e839Smyers enable |= PCI_COMM_IO; 15057c478bd9Sstevel@tonic-gate } 15067c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 15077c478bd9Sstevel@tonic-gate nreg++, nasgn++; 15087c478bd9Sstevel@tonic-gate 15097c478bd9Sstevel@tonic-gate } else { 15107c478bd9Sstevel@tonic-gate /* memory space */ 15117c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 15127c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 15137c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 15147c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 15157c478bd9Sstevel@tonic-gate } else { 15167c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 15177c478bd9Sstevel@tonic-gate base_hi = 0; 15187c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 15197c478bd9Sstevel@tonic-gate } 15207c478bd9Sstevel@tonic-gate 15217c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 15227c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 15237c478bd9Sstevel@tonic-gate 15247c478bd9Sstevel@tonic-gate if (value == 0) { 15257c478bd9Sstevel@tonic-gate continue; 15267c478bd9Sstevel@tonic-gate } 15277c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 15287c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 15297c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 15307c478bd9Sstevel@tonic-gate 15317c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 15327c478bd9Sstevel@tonic-gate if (base & PCI_BASE_PREF_M) { 15337c478bd9Sstevel@tonic-gate mres = pmem_res; 15347c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 15357c478bd9Sstevel@tonic-gate } else { 15367c478bd9Sstevel@tonic-gate mres = mem_res; 15377c478bd9Sstevel@tonic-gate } 15387c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 15397c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 15407c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 15417c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 15427c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 15437c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 15447c478bd9Sstevel@tonic-gate 15457c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 15467c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 15477c478bd9Sstevel@tonic-gate if (*mres && base != 0) { 15487c478bd9Sstevel@tonic-gate (void) memlist_remove(mres, 15497c478bd9Sstevel@tonic-gate (uint64_t)base, (uint64_t)len); 15507c478bd9Sstevel@tonic-gate } else if (*mres) 15517c478bd9Sstevel@tonic-gate reprogram = 1; 15527c478bd9Sstevel@tonic-gate } else if (*mres && base == 0) { 15537c478bd9Sstevel@tonic-gate base = (uint_t)memlist_find(mres, 15547c478bd9Sstevel@tonic-gate (uint64_t)len, (uint64_t)0x1000); 15557c478bd9Sstevel@tonic-gate if (base != NULL) { 15567c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 15577c478bd9Sstevel@tonic-gate base | type); 15587c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 15597c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 15607c478bd9Sstevel@tonic-gate } 15617c478bd9Sstevel@tonic-gate 15627c478bd9Sstevel@tonic-gate if (base == 0) { 15637c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 1564ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 1565db063408Sdmick " length 0x%x", 1566ebf3afa8Sdmick bus, dev, func, offset, len); 15677c478bd9Sstevel@tonic-gate } else 156846e9e839Smyers enable |= PCI_COMM_MAE; 15697c478bd9Sstevel@tonic-gate } 15707c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 15717c478bd9Sstevel@tonic-gate nreg++, nasgn++; 15727c478bd9Sstevel@tonic-gate } 15737c478bd9Sstevel@tonic-gate } 15747c478bd9Sstevel@tonic-gate switch (header) { 15757c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 15767c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 15777c478bd9Sstevel@tonic-gate break; 15787c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 15797c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 15807c478bd9Sstevel@tonic-gate break; 15817c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 15827c478bd9Sstevel@tonic-gate goto done; 15837c478bd9Sstevel@tonic-gate } 15847c478bd9Sstevel@tonic-gate 15857c478bd9Sstevel@tonic-gate /* 15867c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 15877c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 15887c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 15897c478bd9Sstevel@tonic-gate */ 15907c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 15917c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 15927c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 15937c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 159470025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 159570025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 159670025d76Sjohnny else 159770025d76Sjohnny value = 0; 15987c478bd9Sstevel@tonic-gate 15997c478bd9Sstevel@tonic-gate if (value != 0) { 16007c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 16017c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 16027c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 16037c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 16047c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 16057c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 16067c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 16077c478bd9Sstevel@tonic-gate nreg++, nasgn++; 160899ed6083Sszhou /* take it out of the memory resource */ 160999ed6083Sszhou if (*mem_res && base != 0) 161099ed6083Sszhou (void) memlist_remove(mem_res, 161199ed6083Sszhou (uint64_t)base, (uint64_t)len); 16127c478bd9Sstevel@tonic-gate } 16137c478bd9Sstevel@tonic-gate 16147c478bd9Sstevel@tonic-gate /* 16157c478bd9Sstevel@tonic-gate * The following are ISA resources. There are not part 16167c478bd9Sstevel@tonic-gate * of the PCI local bus resources. So don't attempt to 16177c478bd9Sstevel@tonic-gate * do resource accounting against PCI. 16187c478bd9Sstevel@tonic-gate */ 16197c478bd9Sstevel@tonic-gate 16207c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 16217c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 16227c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 16237c478bd9Sstevel@tonic-gate 16247c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 16257c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 16267c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 16277c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 16287c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 16297c478bd9Sstevel@tonic-gate nreg++, nasgn++; 16307c478bd9Sstevel@tonic-gate 16317c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 16327c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 16337c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 16347c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 16357c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 16367c478bd9Sstevel@tonic-gate nreg++, nasgn++; 16377c478bd9Sstevel@tonic-gate 16387c478bd9Sstevel@tonic-gate /* Video memory */ 16397c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 16407c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 16417c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 16427c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 16437c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 16447c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 16457c478bd9Sstevel@tonic-gate nreg++, nasgn++; 16467c478bd9Sstevel@tonic-gate } 16477c478bd9Sstevel@tonic-gate 16487c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 16497c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 16509896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 16519896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 16527c478bd9Sstevel@tonic-gate 16537c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 16547c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 16557c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 16567c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 16577c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 16587c478bd9Sstevel@tonic-gate nreg++, nasgn++; 16597c478bd9Sstevel@tonic-gate 16607c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 16617c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 16627c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 16637c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 16647c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 16657c478bd9Sstevel@tonic-gate nreg++, nasgn++; 16667c478bd9Sstevel@tonic-gate } 16677c478bd9Sstevel@tonic-gate 16687c478bd9Sstevel@tonic-gate done: 16697c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 16707c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 16717c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 16727c478bd9Sstevel@tonic-gate "assigned-addresses", 16737c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 16747c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW && enable) { 16757c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, 16767c478bd9Sstevel@tonic-gate "!enable PCI device [%d/%d/%d]", bus, dev, func); 16778d34f104Smyers cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 167846e9e839Smyers cmd_reg |= (enable | PCI_COMM_ME); 16798d34f104Smyers pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 16807c478bd9Sstevel@tonic-gate } 16817c478bd9Sstevel@tonic-gate return (reprogram); 16827c478bd9Sstevel@tonic-gate } 16837c478bd9Sstevel@tonic-gate 16847c478bd9Sstevel@tonic-gate static void 168570025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 168670025d76Sjohnny int pciex) 16877c478bd9Sstevel@tonic-gate { 168870025d76Sjohnny char *dev_type; 16897c478bd9Sstevel@tonic-gate int i; 16907c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 16917c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 16927c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1693f55ce205Sszhou ASSERT(secbus <= subbus); 16947c478bd9Sstevel@tonic-gate 1695f55ce205Sszhou /* 1696f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 1697f55ce205Sszhou * such mistakes here 1698f55ce205Sszhou */ 1699f55ce205Sszhou if (subbus > pci_bios_nbus) { 1700f55ce205Sszhou pci_bios_nbus = subbus; 1701f55ce205Sszhou alloc_res_array(); 1702f55ce205Sszhou } 1703f55ce205Sszhou 1704f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 17057c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 17067c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 17077c478bd9Sstevel@tonic-gate 170870025d76Sjohnny dev_type = pciex ? "pciex" : "pci"; 170970025d76Sjohnny 17107c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 17117c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 171253273e82Ssethg /* 171353273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 171453273e82Ssethg * for peer busses because there is no other way of determining its 171553273e82Ssethg * subordinate bus number). 171653273e82Ssethg */ 17177c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 17187c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 171953273e82Ssethg /* 172053273e82Ssethg * Loop through subordinate busses, initializing their parent bus 172153273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 172253273e82Ssethg * fields may very well be further refined later, as child bridges 172353273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 172453273e82Ssethg * are not peer busses by changing their par_bus fields to anything 172553273e82Ssethg * other than -1.) 172653273e82Ssethg */ 17277c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 17287c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 17297c478bd9Sstevel@tonic-gate 17307c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 173170025d76Sjohnny "device_type", dev_type); 17327c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 17337c478bd9Sstevel@tonic-gate "#address-cells", 3); 17347c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 17357c478bd9Sstevel@tonic-gate "#size-cells", 2); 17367c478bd9Sstevel@tonic-gate 17377c478bd9Sstevel@tonic-gate /* 17387c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 17397c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 17407c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 17417c478bd9Sstevel@tonic-gate * prefetchable memory. 17427c478bd9Sstevel@tonic-gate */ 17439896aa55Sjveta 17449896aa55Sjveta /* 17459896aa55Sjveta * io range 17469896aa55Sjveta * We determine i/o windows that are left unconfigured by bios 17479896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 17489896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 17499896aa55Sjveta * later passes by setting the base > limit 17509896aa55Sjveta */ 17519896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 17529896aa55Sjveta if (val & PCI_COMM_IO) { 17539896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 17549896aa55Sjveta io_range[0] = ((val & 0xf0) << 8); 17559896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 17569896aa55Sjveta io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 17579896aa55Sjveta } else { 17589896aa55Sjveta io_range[0] = 0x9fff; 17599896aa55Sjveta io_range[1] = 0x1000; 17609896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 17619896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 17629896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 17639896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 17649896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 17659896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 17669896aa55Sjveta } 17679896aa55Sjveta 17687c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 17697c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].io_ports, 17707c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 17717c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 17727c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].io_ports != NULL) { 17737c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].io_ports, 17747c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 17757c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 17767c478bd9Sstevel@tonic-gate } 17777c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 17787c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 17792269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 17802269adc8Sszhou if ((val & 0xf) == 1 && 17812269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 17822269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 17832269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 17842269adc8Sszhou } 17857c478bd9Sstevel@tonic-gate } 17867c478bd9Sstevel@tonic-gate 17877c478bd9Sstevel@tonic-gate /* mem range */ 17887c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 17897c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 17907c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 17917c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 17927c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 17937c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].mem_space, 17947c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 17957c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 17967c478bd9Sstevel@tonic-gate /* remove from parent resouce list */ 17977c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].mem_space != NULL) { 17987c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].mem_space, 17997c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 18007c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 18017c478bd9Sstevel@tonic-gate } 18027c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 18037c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 18047c478bd9Sstevel@tonic-gate } 18057c478bd9Sstevel@tonic-gate 18067c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 18077c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 18087c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 18097c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 18107c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 18117c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 18127c478bd9Sstevel@tonic-gate memlist_insert(&pci_bus_res[secbus].pmem_space, 18137c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 18147c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 18157c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].pmem_space != NULL) { 18167c478bd9Sstevel@tonic-gate (void) memlist_remove(&pci_bus_res[bus].pmem_space, 18177c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 18187c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 18197c478bd9Sstevel@tonic-gate } 18207c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 18217c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 18222269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 18232269adc8Sszhou if ((val & 0xf) == 1 && 18242269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 18252269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 18262269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 18272269adc8Sszhou } 18287c478bd9Sstevel@tonic-gate } 18297c478bd9Sstevel@tonic-gate 18307c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 18317c478bd9Sstevel@tonic-gate add_ppb_ranges_prop(secbus); 18327c478bd9Sstevel@tonic-gate } 18337c478bd9Sstevel@tonic-gate 183409f67678Sanish extern const struct pci_class_strings_s class_pci[]; 183509f67678Sanish extern int class_pci_items; 18367c478bd9Sstevel@tonic-gate 18377c478bd9Sstevel@tonic-gate static void 18387c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 18397c478bd9Sstevel@tonic-gate { 18407c478bd9Sstevel@tonic-gate const char *desc; 18417c478bd9Sstevel@tonic-gate int i; 18427c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 18437c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 18447c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 18457c478bd9Sstevel@tonic-gate 18467c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 18477c478bd9Sstevel@tonic-gate desc = "IDE controller"; 18487c478bd9Sstevel@tonic-gate } else { 18497c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 18507c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 18517c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 18527c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 185309f67678Sanish desc = class_pci[i].actual_desc; 18547c478bd9Sstevel@tonic-gate break; 18557c478bd9Sstevel@tonic-gate } 18567c478bd9Sstevel@tonic-gate } 185709f67678Sanish if (i == class_pci_items) 18587c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 18597c478bd9Sstevel@tonic-gate } 18607c478bd9Sstevel@tonic-gate 18617c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 18627c478bd9Sstevel@tonic-gate (char *)desc); 18637c478bd9Sstevel@tonic-gate } 18647c478bd9Sstevel@tonic-gate 18657c478bd9Sstevel@tonic-gate static void 18667c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 18677c478bd9Sstevel@tonic-gate { 18687c478bd9Sstevel@tonic-gate int bus_range[2]; 18697c478bd9Sstevel@tonic-gate 18707c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 18717c478bd9Sstevel@tonic-gate return; 18727c478bd9Sstevel@tonic-gate bus_range[0] = bus; 18737c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 18747c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 18757c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 18767c478bd9Sstevel@tonic-gate } 18777c478bd9Sstevel@tonic-gate 1878b1f176e8Sjg /* 1879b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 1880b1f176e8Sjg */ 1881b1f176e8Sjg static void 1882b1f176e8Sjg add_bus_slot_names_prop(int bus) 1883b1f176e8Sjg { 1884b1f176e8Sjg char slotprop[256]; 1885b1f176e8Sjg int len; 1886b1f176e8Sjg 1887*d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 1888*d57b3b3dSprasad /* simply return if the property is already defined */ 1889*d57b3b3dSprasad if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 1890*d57b3b3dSprasad DDI_PROP_DONTPASS, "slot-names")) 1891*d57b3b3dSprasad return; 1892*d57b3b3dSprasad } 1893*d57b3b3dSprasad 1894b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1895b1f176e8Sjg if (len > 0) { 189653273e82Ssethg /* 189753273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 189853273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 189953273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 190053273e82Ssethg * subordinate to any PCI-PCI bridge). 190153273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 190253273e82Ssethg * will remove it later. 190353273e82Ssethg */ 190453273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 190553273e82Ssethg pci_bus_res[bus].dip == NULL) { 190653273e82Ssethg 1907b1f176e8Sjg create_root_bus_dip(bus); 190853273e82Ssethg } 190953273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 191053273e82Ssethg ASSERT((len % sizeof (int)) == 0); 191153273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 191253273e82Ssethg pci_bus_res[bus].dip, "slot-names", 191353273e82Ssethg (int *)slotprop, len / sizeof (int)); 191453273e82Ssethg } else { 191553273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 191653273e82Ssethg "IRQ routing table; Not adding slot-names " 191753273e82Ssethg "property for incorrect bus %d", bus); 191853273e82Ssethg } 1919b1f176e8Sjg } 1920b1f176e8Sjg } 1921b1f176e8Sjg 19227c478bd9Sstevel@tonic-gate static int 192300d0963fSdilpreet memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type) 19247c478bd9Sstevel@tonic-gate { 19257c478bd9Sstevel@tonic-gate if (entry == NULL) 19267c478bd9Sstevel@tonic-gate return (0); 19277c478bd9Sstevel@tonic-gate 19287c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 192900d0963fSdilpreet rp->child_high = rp->parent_high = type; 19307c478bd9Sstevel@tonic-gate rp->child_mid = rp->parent_mid = 0; 193100d0963fSdilpreet rp->child_low = rp->parent_low = (uint32_t)entry->address; 193200d0963fSdilpreet rp->size_high = 0; 193300d0963fSdilpreet rp->size_low = (uint32_t)entry->size; 19347c478bd9Sstevel@tonic-gate return (1); 19357c478bd9Sstevel@tonic-gate } 19367c478bd9Sstevel@tonic-gate 19377c478bd9Sstevel@tonic-gate static void 19387c478bd9Sstevel@tonic-gate add_ppb_ranges_prop(int bus) 19397c478bd9Sstevel@tonic-gate { 19407c478bd9Sstevel@tonic-gate int i = 0; 194100d0963fSdilpreet ppb_ranges_t *rp; 19427c478bd9Sstevel@tonic-gate 19437c478bd9Sstevel@tonic-gate rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 19447c478bd9Sstevel@tonic-gate 19457c478bd9Sstevel@tonic-gate i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 19467c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 19477c478bd9Sstevel@tonic-gate i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 19487c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 19497c478bd9Sstevel@tonic-gate i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 19507c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 19517c478bd9Sstevel@tonic-gate 19527c478bd9Sstevel@tonic-gate if (i != 0) 19537c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 19547c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip, "ranges", (int *)rp, 195500d0963fSdilpreet i * sizeof (ppb_ranges_t) / sizeof (int)); 19567c478bd9Sstevel@tonic-gate kmem_free(rp, 3 * sizeof (*rp)); 19577c478bd9Sstevel@tonic-gate } 19587c478bd9Sstevel@tonic-gate 19597c478bd9Sstevel@tonic-gate static int 19607c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 19617c478bd9Sstevel@tonic-gate { 19627c478bd9Sstevel@tonic-gate int i = 0; 19637c478bd9Sstevel@tonic-gate 19647c478bd9Sstevel@tonic-gate while (list) { 19657c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 19667c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 19677c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 19687c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 19697c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 19707c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 19717c478bd9Sstevel@tonic-gate 19727c478bd9Sstevel@tonic-gate list = list->next; 19737c478bd9Sstevel@tonic-gate sp++, i++; 19747c478bd9Sstevel@tonic-gate } 19757c478bd9Sstevel@tonic-gate return (i); 19767c478bd9Sstevel@tonic-gate } 19777c478bd9Sstevel@tonic-gate 19787c478bd9Sstevel@tonic-gate static void 19797c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 19807c478bd9Sstevel@tonic-gate { 19817c478bd9Sstevel@tonic-gate int i, count; 19827c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 19837c478bd9Sstevel@tonic-gate 19847c478bd9Sstevel@tonic-gate count = memlist_count(pci_bus_res[bus].io_ports) + 19857c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].mem_space) + 19867c478bd9Sstevel@tonic-gate memlist_count(pci_bus_res[bus].pmem_space); 19877c478bd9Sstevel@tonic-gate 19887c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 19897c478bd9Sstevel@tonic-gate return; 19907c478bd9Sstevel@tonic-gate 19917c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 19927c478bd9Sstevel@tonic-gate i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 19937c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 19947c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 19957c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 19967c478bd9Sstevel@tonic-gate i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 19977c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 19987c478bd9Sstevel@tonic-gate ASSERT(i == count); 19997c478bd9Sstevel@tonic-gate 20007c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 20017c478bd9Sstevel@tonic-gate "available", (int *)sp, 20027c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 20037c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 20047c478bd9Sstevel@tonic-gate } 2005f55ce205Sszhou 2006f55ce205Sszhou static void 2007f55ce205Sszhou alloc_res_array(void) 2008f55ce205Sszhou { 2009f55ce205Sszhou static int array_max = 0; 2010f55ce205Sszhou int old_max; 2011f55ce205Sszhou void *old_res; 2012f55ce205Sszhou 2013f55ce205Sszhou if (array_max > pci_bios_nbus + 1) 2014f55ce205Sszhou return; /* array is big enough */ 2015f55ce205Sszhou 2016f55ce205Sszhou old_max = array_max; 2017f55ce205Sszhou old_res = pci_bus_res; 2018f55ce205Sszhou 2019f55ce205Sszhou if (array_max == 0) 2020f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 2021f55ce205Sszhou 2022f55ce205Sszhou while (array_max < pci_bios_nbus + 1) 2023f55ce205Sszhou array_max <<= 1; 2024f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2025f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2026f55ce205Sszhou 2027f55ce205Sszhou if (old_res) { /* copy content and free old array */ 2028f55ce205Sszhou bcopy(old_res, pci_bus_res, 2029f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 2030f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2031f55ce205Sszhou } 2032f55ce205Sszhou } 2033c8589f13Ssethg 2034c8589f13Ssethg static void 2035c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2036c8589f13Ssethg ushort_t deviceid) 2037c8589f13Ssethg { 2038c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 2039c8589f13Ssethg static int numioapics = 0; 2040c8589f13Ssethg dev_info_t *ioapic_node; 2041c8589f13Ssethg uint64_t physaddr; 2042c8589f13Ssethg uint32_t lobase, hibase = 0; 2043c8589f13Ssethg 2044c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2045c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2046c8589f13Ssethg 2047c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2048c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2049c8589f13Ssethg return; 2050c8589f13Ssethg 2051c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2052c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2053c8589f13Ssethg 2054c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 2055c8589f13Ssethg 2056c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 2057c8589f13Ssethg 2058c8589f13Ssethg /* 2059c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 2060c8589f13Ssethg */ 2061c8589f13Ssethg if (ioapicsnode == NULL) { 2062c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2063c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2064c8589f13Ssethg return; 2065c8589f13Ssethg } 2066c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 2067c8589f13Ssethg } 2068c8589f13Ssethg 2069c8589f13Ssethg /* 2070c8589f13Ssethg * Create a child node for this IOAPIC 2071c8589f13Ssethg */ 2072c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2073c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 2074c8589f13Ssethg if (ioapic_node == NULL) { 2075c8589f13Ssethg return; 2076c8589f13Ssethg } 2077c8589f13Ssethg 2078c8589f13Ssethg /* Vendor and Device ID */ 2079c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2080c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 2081c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2082c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 2083c8589f13Ssethg 2084c8589f13Ssethg /* device_type */ 2085c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2086c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 2087c8589f13Ssethg 2088c8589f13Ssethg /* reg */ 2089c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2090c8589f13Ssethg "reg", physaddr); 2091c8589f13Ssethg } 2092*d57b3b3dSprasad 2093*d57b3b3dSprasad /* 2094*d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 2095*d57b3b3dSprasad * information obtained from Slot Capabilities register. 2096*d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 2097*d57b3b3dSprasad * information in the PCI IRQ table. 2098*d57b3b3dSprasad */ 2099*d57b3b3dSprasad static void 2100*d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2101*d57b3b3dSprasad { 2102*d57b3b3dSprasad char slotprop[256]; 2103*d57b3b3dSprasad int len; 2104*d57b3b3dSprasad 2105*d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 2106*d57b3b3dSprasad 2107*d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 2108*d57b3b3dSprasad *(uint32_t *)slotprop = 1; 2109*d57b3b3dSprasad len = 4; 2110*d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2111*d57b3b3dSprasad slot_num); 2112*d57b3b3dSprasad len += strlen(slotprop + len) + 1; 2113*d57b3b3dSprasad len += len % 4; 2114*d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2115*d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 2116*d57b3b3dSprasad } 2117