17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 220db3240dSStephen Hanson * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23*bfa93d39SRobert Mustacchi * Copyright 2019 Joyent, Inc. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/stat.h> 28ffa17327SGuoli Shu #include <sys/sysmacros.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 307c478bd9Sstevel@tonic-gate #include <sys/pci.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 32c0da6274SZhi-Jun Robin Fu #include <sys/pcie_impl.h> 337c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 347c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3570025d76Sjohnny #include <io/pci/mps_table.h> 36c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc.h> 37c88420b3Sdmick #include <sys/pci_cfgspace.h> 38c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 39c88420b3Sdmick #include <sys/psw.h> 4009f67678Sanish #include "../../../../common/pci/pci_strings.h" 41c8589f13Ssethg #include <sys/apic.h> 428a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 4326947304SEvan Yan #include <sys/hotplug/pci/pciehpc_acpi.h> 4425145214Smyers #include <sys/acpi/acpi.h> 4525145214Smyers #include <sys/acpica.h> 4694f1124eSVikram Hegde #include <sys/iommulib.h> 4700dfdf4aSDana Myers #include <sys/devcache.h> 48c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc_x86.h> 497c478bd9Sstevel@tonic-gate 507c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 517c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 527c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 537c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 547c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 557c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 567c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 577c478bd9Sstevel@tonic-gate 587c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 597c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 607c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 61bd87be88Ssethg #define CONFIG_FIX 3 6270025d76Sjohnny #define COMPAT_BUFSIZE 512 637c478bd9Sstevel@tonic-gate 6405f867c3Sgs #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 6505f867c3Sgs #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 66ffa17327SGuoli Shu /* round down to nearest power of two */ 67ffa17327SGuoli Shu #define P2LE(align) \ 68ffa17327SGuoli Shu { \ 69ffa17327SGuoli Shu int i = 0; \ 70ffa17327SGuoli Shu while (align >>= 1) \ 71ffa17327SGuoli Shu i ++; \ 72ffa17327SGuoli Shu align = 1 << i; \ 73ffa17327SGuoli Shu } \ 7405f867c3Sgs 752f283da5SDan Mick /* for is_vga and list_is_vga_only */ 762f283da5SDan Mick 772f283da5SDan Mick enum io_mem { 782f283da5SDan Mick IO, 792f283da5SDan Mick MEM 802f283da5SDan Mick }; 812f283da5SDan Mick 82bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 83bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 84bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 85bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 86bd87be88Ssethg 87bd87be88Ssethg struct pci_fixundo { 88bd87be88Ssethg uint8_t bus; 89bd87be88Ssethg uint8_t dev; 90bd87be88Ssethg uint8_t fn; 91bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 92bd87be88Ssethg struct pci_fixundo *next; 93bd87be88Ssethg }; 94bd87be88Ssethg 9505f867c3Sgs struct pci_devfunc { 9605f867c3Sgs struct pci_devfunc *next; 9705f867c3Sgs dev_info_t *dip; 9805f867c3Sgs uchar_t dev; 9905f867c3Sgs uchar_t func; 10005f867c3Sgs boolean_t reprogram; /* this device needs to be reprogrammed */ 10105f867c3Sgs }; 10205f867c3Sgs 1037ff178cdSJimmy Vetayases extern int apic_nvidia_io_max; 10478323854SJudy Chen extern int pseudo_isa; 10547310cedSDana Myers extern int pci_bios_maxbus; 1067c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 1077c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 1087c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 109bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 11005f867c3Sgs static int num_root_bus = 0; /* count of root buses */ 1118fc7923fSDana Myers extern volatile int acpi_resource_discovery; 112c0da6274SZhi-Jun Robin Fu extern uint64_t mcfg_mem_base; 113c0da6274SZhi-Jun Robin Fu extern void pci_cfgacc_add_workaround(uint16_t, uchar_t, uchar_t); 114c0da6274SZhi-Jun Robin Fu extern dev_info_t *pcie_get_rc_dip(dev_info_t *); 1157c478bd9Sstevel@tonic-gate 1167c478bd9Sstevel@tonic-gate /* 1177c478bd9Sstevel@tonic-gate * Module prototypes 1187c478bd9Sstevel@tonic-gate */ 1197c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 1207c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 12105f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 1227c478bd9Sstevel@tonic-gate ushort_t, int); 1237c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 12470025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 1257c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 12649fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 12749fbdd30SErwin T Tsaur ushort_t); 1287c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 1297c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 130b1f176e8Sjg static void add_bus_slot_names_prop(int); 1318fc7923fSDana Myers static void add_ranges_prop(int, int); 1327c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 13349fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 13405f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t); 135f55ce205Sszhou static void alloc_res_array(); 136c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 137c8589f13Ssethg ushort_t deviceid); 138d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1398fc7923fSDana Myers static void populate_bus_res(uchar_t bus); 1408fc7923fSDana Myers static void memlist_remove_list(struct memlist **list, 1418fc7923fSDana Myers struct memlist *remove_list); 142c0da6274SZhi-Jun Robin Fu static void ck804_fix_aer_ptr(dev_info_t *, pcie_req_id_t); 1437c478bd9Sstevel@tonic-gate 14400dfdf4aSDana Myers static void pci_scan_bbn(void); 14500dfdf4aSDana Myers static int pci_unitaddr_cache_valid(void); 14600dfdf4aSDana Myers static int pci_bus_unitaddr(int); 14700dfdf4aSDana Myers static void pci_unitaddr_cache_create(void); 14800dfdf4aSDana Myers 14900dfdf4aSDana Myers static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 15000dfdf4aSDana Myers static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 15100dfdf4aSDana Myers static void pci_cache_free_list(nvf_handle_t); 15200dfdf4aSDana Myers 15375bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 15475bcd456Sjg 155ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 15625145214Smyers int pci_bus_always_renumber = 0; 15725145214Smyers 1581d6b7b34SJudy Chen /* 1591d6b7b34SJudy Chen * used to register ISA resource usage which must not be made 1601d6b7b34SJudy Chen * "available" from other PCI node' resource maps 1611d6b7b34SJudy Chen */ 1621d6b7b34SJudy Chen static struct { 1632f283da5SDan Mick struct memlist *io_used; 1642f283da5SDan Mick struct memlist *mem_used; 1651d6b7b34SJudy Chen } isa_res; 1661d6b7b34SJudy Chen 16700dfdf4aSDana Myers /* 16800dfdf4aSDana Myers * PCI unit-address cache management 16900dfdf4aSDana Myers */ 17000dfdf4aSDana Myers static nvf_ops_t pci_unitaddr_cache_ops = { 17100dfdf4aSDana Myers "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 17200dfdf4aSDana Myers pci_cache_unpack_nvlist, /* read in nvlist form */ 17300dfdf4aSDana Myers pci_cache_pack_nvlist, /* convert to nvlist form */ 17400dfdf4aSDana Myers pci_cache_free_list, /* free data list */ 17500dfdf4aSDana Myers NULL /* write complete callback */ 17600dfdf4aSDana Myers }; 17700dfdf4aSDana Myers 17800dfdf4aSDana Myers typedef struct { 17900dfdf4aSDana Myers list_node_t pua_nodes; 18000dfdf4aSDana Myers int pua_index; 18100dfdf4aSDana Myers int pua_addr; 18200dfdf4aSDana Myers } pua_node_t; 18300dfdf4aSDana Myers 18400dfdf4aSDana Myers nvf_handle_t puafd_handle; 18500dfdf4aSDana Myers int pua_cache_valid = 0; 18600dfdf4aSDana Myers 18700dfdf4aSDana Myers 18800dfdf4aSDana Myers /*ARGSUSED*/ 18900dfdf4aSDana Myers static ACPI_STATUS 19000dfdf4aSDana Myers pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) 19100dfdf4aSDana Myers { 19200dfdf4aSDana Myers ACPI_BUFFER rb; 19300dfdf4aSDana Myers ACPI_OBJECT ro; 19400dfdf4aSDana Myers ACPI_DEVICE_INFO *adi; 195fbe8965dSDana Myers int busnum; 19600dfdf4aSDana Myers 19700dfdf4aSDana Myers /* 19800dfdf4aSDana Myers * Use AcpiGetObjectInfo() to find the device _HID 19900dfdf4aSDana Myers * If not a PCI root-bus, ignore this device and continue 20000dfdf4aSDana Myers * the walk 20100dfdf4aSDana Myers */ 20257190917SDana Myers if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &adi))) 20300dfdf4aSDana Myers return (AE_OK); 20400dfdf4aSDana Myers 20500dfdf4aSDana Myers if (!(adi->Valid & ACPI_VALID_HID)) { 20600dfdf4aSDana Myers AcpiOsFree(adi); 20700dfdf4aSDana Myers return (AE_OK); 20800dfdf4aSDana Myers } 20900dfdf4aSDana Myers 21057190917SDana Myers if (strncmp(adi->HardwareId.String, PCI_ROOT_HID_STRING, 21100dfdf4aSDana Myers sizeof (PCI_ROOT_HID_STRING)) && 21257190917SDana Myers strncmp(adi->HardwareId.String, PCI_EXPRESS_ROOT_HID_STRING, 21300dfdf4aSDana Myers sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { 21400dfdf4aSDana Myers AcpiOsFree(adi); 21500dfdf4aSDana Myers return (AE_OK); 21600dfdf4aSDana Myers } 21700dfdf4aSDana Myers 21800dfdf4aSDana Myers AcpiOsFree(adi); 21900dfdf4aSDana Myers 22000dfdf4aSDana Myers /* 22100dfdf4aSDana Myers * XXX: ancient Big Bear broken _BBN will result in two 22200dfdf4aSDana Myers * bus 0 _BBNs being found, so we need to handle duplicate 22300dfdf4aSDana Myers * bus 0 gracefully. However, broken _BBN does not 22400dfdf4aSDana Myers * hide a childless root-bridge so no need to work-around it 22500dfdf4aSDana Myers * here 22600dfdf4aSDana Myers */ 22700dfdf4aSDana Myers rb.Pointer = &ro; 22800dfdf4aSDana Myers rb.Length = sizeof (ro); 22900dfdf4aSDana Myers if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", 23000dfdf4aSDana Myers NULL, &rb, ACPI_TYPE_INTEGER))) { 231fbe8965dSDana Myers busnum = ro.Integer.Value; 232fbe8965dSDana Myers 233fbe8965dSDana Myers /* 234fbe8965dSDana Myers * Ignore invalid _BBN return values here (rather 235fbe8965dSDana Myers * than panic) and emit a warning; something else 236fbe8965dSDana Myers * may suffer failure as a result of the broken BIOS. 237fbe8965dSDana Myers */ 238fbe8965dSDana Myers if ((busnum < 0) || (busnum > pci_bios_maxbus)) { 2391c21d439SDana Myers dcmn_err(CE_NOTE, 240fbe8965dSDana Myers "pci_process_acpi_device: invalid _BBN 0x%x\n", 241fbe8965dSDana Myers busnum); 242fbe8965dSDana Myers return (AE_CTRL_DEPTH); 243fbe8965dSDana Myers } 244fbe8965dSDana Myers 245fbe8965dSDana Myers /* PCI with valid _BBN */ 246fbe8965dSDana Myers if (pci_bus_res[busnum].par_bus == (uchar_t)-1 && 247fbe8965dSDana Myers pci_bus_res[busnum].dip == NULL) 248fbe8965dSDana Myers create_root_bus_dip((uchar_t)busnum); 24900dfdf4aSDana Myers return (AE_CTRL_DEPTH); 25000dfdf4aSDana Myers } 25100dfdf4aSDana Myers 25200dfdf4aSDana Myers /* PCI and no _BBN, continue walk */ 25300dfdf4aSDana Myers return (AE_OK); 25400dfdf4aSDana Myers } 25500dfdf4aSDana Myers 25600dfdf4aSDana Myers /* 25700dfdf4aSDana Myers * Scan the ACPI namespace for all top-level instances of _BBN 25800dfdf4aSDana Myers * in order to discover childless root-bridges (which enumeration 25900dfdf4aSDana Myers * may not find; root-bridges are inferred by the existence of 26000dfdf4aSDana Myers * children). This scan should find all root-bridges that have 26100dfdf4aSDana Myers * been enumerated, and any childless root-bridges not enumerated. 26200dfdf4aSDana Myers * Root-bridge for bus 0 may not have a _BBN object. 26300dfdf4aSDana Myers */ 26400dfdf4aSDana Myers static void 26500dfdf4aSDana Myers pci_scan_bbn() 26600dfdf4aSDana Myers { 26700dfdf4aSDana Myers void *rv; 26800dfdf4aSDana Myers 26900dfdf4aSDana Myers (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); 27000dfdf4aSDana Myers } 27100dfdf4aSDana Myers 27200dfdf4aSDana Myers static void 27300dfdf4aSDana Myers pci_unitaddr_cache_init(void) 27400dfdf4aSDana Myers { 27500dfdf4aSDana Myers 27600dfdf4aSDana Myers puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 27700dfdf4aSDana Myers ASSERT(puafd_handle); 27800dfdf4aSDana Myers 27900dfdf4aSDana Myers list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 28000dfdf4aSDana Myers offsetof(pua_node_t, pua_nodes)); 28100dfdf4aSDana Myers 28200dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 28300dfdf4aSDana Myers (void) nvf_read_file(puafd_handle); 28400dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 28500dfdf4aSDana Myers } 28600dfdf4aSDana Myers 28700dfdf4aSDana Myers /* 28800dfdf4aSDana Myers * Format of /etc/devices/pci_unitaddr_persistent: 28900dfdf4aSDana Myers * 29000dfdf4aSDana Myers * The persistent record of unit-address assignments contains 29100dfdf4aSDana Myers * a list of name/value pairs, where name is a string representation 29200dfdf4aSDana Myers * of the "index value" of the PCI root-bus and the value is 29300dfdf4aSDana Myers * the assigned unit-address. 29400dfdf4aSDana Myers * 29500dfdf4aSDana Myers * The "index value" is simply the zero-based index of the PCI 29600dfdf4aSDana Myers * root-buses ordered by physical bus number; first PCI bus is 0, 29700dfdf4aSDana Myers * second is 1, and so on. 29800dfdf4aSDana Myers */ 29900dfdf4aSDana Myers 300e07545cfSDana Myers /*ARGSUSED*/ 30100dfdf4aSDana Myers static int 30200dfdf4aSDana Myers pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 30300dfdf4aSDana Myers { 30400dfdf4aSDana Myers long index; 30500dfdf4aSDana Myers int32_t value; 30600dfdf4aSDana Myers nvpair_t *np; 30700dfdf4aSDana Myers pua_node_t *node; 30800dfdf4aSDana Myers 30900dfdf4aSDana Myers np = NULL; 31000dfdf4aSDana Myers while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 31100dfdf4aSDana Myers /* name of nvpair is index value */ 31200dfdf4aSDana Myers if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 31300dfdf4aSDana Myers continue; 31400dfdf4aSDana Myers 31500dfdf4aSDana Myers if (nvpair_value_int32(np, &value) != 0) 31600dfdf4aSDana Myers continue; 31700dfdf4aSDana Myers 31800dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 31900dfdf4aSDana Myers node->pua_index = index; 32000dfdf4aSDana Myers node->pua_addr = value; 32100dfdf4aSDana Myers list_insert_tail(nvf_list(hdl), node); 32200dfdf4aSDana Myers } 32300dfdf4aSDana Myers 32400dfdf4aSDana Myers pua_cache_valid = 1; 32500dfdf4aSDana Myers return (DDI_SUCCESS); 32600dfdf4aSDana Myers } 32700dfdf4aSDana Myers 32800dfdf4aSDana Myers static int 32900dfdf4aSDana Myers pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 33000dfdf4aSDana Myers { 33100dfdf4aSDana Myers int rval; 33200dfdf4aSDana Myers nvlist_t *nvl, *sub_nvl; 33300dfdf4aSDana Myers list_t *listp; 33400dfdf4aSDana Myers pua_node_t *pua; 33500dfdf4aSDana Myers char buf[13]; 33600dfdf4aSDana Myers 33700dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 33800dfdf4aSDana Myers 33900dfdf4aSDana Myers rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 34000dfdf4aSDana Myers if (rval != DDI_SUCCESS) { 34100dfdf4aSDana Myers nvf_error("%s: nvlist alloc error %d\n", 34200dfdf4aSDana Myers nvf_cache_name(hdl), rval); 34300dfdf4aSDana Myers return (DDI_FAILURE); 34400dfdf4aSDana Myers } 34500dfdf4aSDana Myers 34600dfdf4aSDana Myers sub_nvl = NULL; 34700dfdf4aSDana Myers rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 34800dfdf4aSDana Myers if (rval != DDI_SUCCESS) 34900dfdf4aSDana Myers goto error; 35000dfdf4aSDana Myers 35100dfdf4aSDana Myers listp = nvf_list(hdl); 35200dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 35300dfdf4aSDana Myers pua = list_next(listp, pua)) { 354e07545cfSDana Myers (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 35500dfdf4aSDana Myers rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 35600dfdf4aSDana Myers if (rval != DDI_SUCCESS) 35700dfdf4aSDana Myers goto error; 35800dfdf4aSDana Myers } 35900dfdf4aSDana Myers 36000dfdf4aSDana Myers rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 36100dfdf4aSDana Myers if (rval != DDI_SUCCESS) 36200dfdf4aSDana Myers goto error; 36300dfdf4aSDana Myers nvlist_free(sub_nvl); 36400dfdf4aSDana Myers 36500dfdf4aSDana Myers *ret_nvl = nvl; 36600dfdf4aSDana Myers return (DDI_SUCCESS); 36700dfdf4aSDana Myers 36800dfdf4aSDana Myers error: 369aab83bb8SJosef 'Jeff' Sipek nvlist_free(sub_nvl); 37000dfdf4aSDana Myers ASSERT(nvl); 37100dfdf4aSDana Myers nvlist_free(nvl); 37200dfdf4aSDana Myers *ret_nvl = NULL; 37300dfdf4aSDana Myers return (DDI_FAILURE); 37400dfdf4aSDana Myers } 37500dfdf4aSDana Myers 37600dfdf4aSDana Myers static void 37700dfdf4aSDana Myers pci_cache_free_list(nvf_handle_t hdl) 37800dfdf4aSDana Myers { 37900dfdf4aSDana Myers list_t *listp; 38000dfdf4aSDana Myers pua_node_t *pua; 38100dfdf4aSDana Myers 38200dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 38300dfdf4aSDana Myers 38400dfdf4aSDana Myers listp = nvf_list(hdl); 38500dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 38600dfdf4aSDana Myers pua = list_next(listp, pua)) { 38700dfdf4aSDana Myers list_remove(listp, pua); 38800dfdf4aSDana Myers kmem_free(pua, sizeof (pua_node_t)); 38900dfdf4aSDana Myers } 39000dfdf4aSDana Myers } 39100dfdf4aSDana Myers 39200dfdf4aSDana Myers 39300dfdf4aSDana Myers static int 39400dfdf4aSDana Myers pci_unitaddr_cache_valid(void) 39500dfdf4aSDana Myers { 39600dfdf4aSDana Myers 39700dfdf4aSDana Myers /* read only, no need for rw lock */ 39800dfdf4aSDana Myers return (pua_cache_valid); 39900dfdf4aSDana Myers } 40000dfdf4aSDana Myers 40100dfdf4aSDana Myers 40200dfdf4aSDana Myers static int 40300dfdf4aSDana Myers pci_bus_unitaddr(int index) 40400dfdf4aSDana Myers { 40500dfdf4aSDana Myers pua_node_t *pua; 40600dfdf4aSDana Myers list_t *listp; 40700dfdf4aSDana Myers int addr; 40800dfdf4aSDana Myers 40900dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_READER); 41000dfdf4aSDana Myers 41100dfdf4aSDana Myers addr = -1; /* default return if no match */ 41200dfdf4aSDana Myers listp = nvf_list(puafd_handle); 41300dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 41400dfdf4aSDana Myers pua = list_next(listp, pua)) { 41500dfdf4aSDana Myers if (pua->pua_index == index) { 41600dfdf4aSDana Myers addr = pua->pua_addr; 41700dfdf4aSDana Myers break; 41800dfdf4aSDana Myers } 41900dfdf4aSDana Myers } 42000dfdf4aSDana Myers 42100dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 42200dfdf4aSDana Myers return (addr); 42300dfdf4aSDana Myers } 42400dfdf4aSDana Myers 42500dfdf4aSDana Myers static void 42600dfdf4aSDana Myers pci_unitaddr_cache_create(void) 42700dfdf4aSDana Myers { 42800dfdf4aSDana Myers int i, index; 42900dfdf4aSDana Myers pua_node_t *node; 43000dfdf4aSDana Myers list_t *listp; 43100dfdf4aSDana Myers 43200dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 43300dfdf4aSDana Myers 43400dfdf4aSDana Myers index = 0; 43500dfdf4aSDana Myers listp = nvf_list(puafd_handle); 43647310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 43700dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 43800dfdf4aSDana Myers if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 43900dfdf4aSDana Myers (pci_bus_res[i].dip == NULL)) 44000dfdf4aSDana Myers continue; 44100dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 44200dfdf4aSDana Myers node->pua_index = index++; 44300dfdf4aSDana Myers node->pua_addr = pci_bus_res[i].root_addr; 44400dfdf4aSDana Myers list_insert_tail(listp, node); 44500dfdf4aSDana Myers } 44600dfdf4aSDana Myers 44700dfdf4aSDana Myers (void) nvf_mark_dirty(puafd_handle); 44800dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 44900dfdf4aSDana Myers nvf_wake_daemon(); 45000dfdf4aSDana Myers } 45100dfdf4aSDana Myers 45200dfdf4aSDana Myers 4537c478bd9Sstevel@tonic-gate /* 4547c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 4557c478bd9Sstevel@tonic-gate */ 4567c478bd9Sstevel@tonic-gate void 45700dfdf4aSDana Myers pci_setup_tree(void) 4587c478bd9Sstevel@tonic-gate { 45905043691Sjames north - Sun Microsystems - Austin United States uint_t i, root_bus_addr = 0; 4607c478bd9Sstevel@tonic-gate 461f55ce205Sszhou alloc_res_array(); 46247310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 4637c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 4647c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 4657c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 4667c478bd9Sstevel@tonic-gate } 4677c478bd9Sstevel@tonic-gate 4687c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 4697c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 4707c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 4717c478bd9Sstevel@tonic-gate 4727c478bd9Sstevel@tonic-gate /* 4737c478bd9Sstevel@tonic-gate * Now enumerate peer busses 4747c478bd9Sstevel@tonic-gate * 47547310cedSDana Myers * We loop till pci_bios_maxbus. On most systems, there is 4767c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 4777c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 4787c478bd9Sstevel@tonic-gate * 4797c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 4807c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 4817c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 4827c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 4837c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 4847c478bd9Sstevel@tonic-gate * device below. 4857c478bd9Sstevel@tonic-gate */ 48647310cedSDana Myers for (i = 1; i <= pci_bios_maxbus; i++) { 4877c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 4887c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 4897c478bd9Sstevel@tonic-gate } 4907c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 491b1f176e8Sjg 492b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 493b1f176e8Sjg add_bus_slot_names_prop(i); 4947c478bd9Sstevel@tonic-gate } 4957c478bd9Sstevel@tonic-gate } 4967c478bd9Sstevel@tonic-gate 49725145214Smyers /* 49825145214Smyers * >0 = present, 0 = not present, <0 = error 49925145214Smyers */ 50025145214Smyers static int 50125145214Smyers pci_bbn_present(int bus) 50225145214Smyers { 50325145214Smyers ACPI_HANDLE hdl; 50425145214Smyers int rv; 50525145214Smyers 50625145214Smyers /* no dip means no _BBN */ 50725145214Smyers if (pci_bus_res[bus].dip == NULL) 50825145214Smyers return (0); 50925145214Smyers 510db2bae30SDana Myers rv = -1; /* default return value in case of error below */ 511db2bae30SDana Myers if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 512db2bae30SDana Myers switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 513db2bae30SDana Myers case AE_OK: 514db2bae30SDana Myers rv = 1; 515db2bae30SDana Myers break; 516db2bae30SDana Myers case AE_NOT_FOUND: 517db2bae30SDana Myers rv = 0; 518db2bae30SDana Myers break; 519db2bae30SDana Myers default: 520db2bae30SDana Myers break; 521db2bae30SDana Myers } 522db2bae30SDana Myers } 52325145214Smyers 524db2bae30SDana Myers return (rv); 52525145214Smyers } 52625145214Smyers 52725145214Smyers /* 52825145214Smyers * Return non-zero if any PCI bus in the system has an associated 52925145214Smyers * _BBN object, 0 otherwise. 53025145214Smyers */ 53125145214Smyers static int 53225145214Smyers pci_roots_have_bbn(void) 53325145214Smyers { 53425145214Smyers int i; 53525145214Smyers 53625145214Smyers /* 53725145214Smyers * Scan the PCI busses and look for at least 1 _BBN 53825145214Smyers */ 53947310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 54025145214Smyers /* skip non-root (peer) PCI busses */ 54125145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 54225145214Smyers continue; 54325145214Smyers 54425145214Smyers if (pci_bbn_present(i) > 0) 54525145214Smyers return (1); 54625145214Smyers } 54725145214Smyers return (0); 54825145214Smyers 54925145214Smyers } 55025145214Smyers 55125145214Smyers /* 55225145214Smyers * return non-zero if the machine is one on which we renumber 55325145214Smyers * the internal pci unit-addresses 55425145214Smyers */ 55525145214Smyers static int 55625145214Smyers pci_bus_renumber() 55725145214Smyers { 558ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 55925145214Smyers 560ee8c1d4aSdm if (pci_bus_always_renumber) 56125145214Smyers return (1); 562ee8c1d4aSdm 563ee8c1d4aSdm /* get the FADT */ 564db2bae30SDana Myers if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 565db2bae30SDana Myers AE_OK) 56625145214Smyers return (0); 56725145214Smyers 568ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 569ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 570ee8c1d4aSdm return (0); 571ee8c1d4aSdm else 572ee8c1d4aSdm return (1); 57325145214Smyers } 57425145214Smyers 57525145214Smyers /* 57625145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 57725145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 57825145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 57925145214Smyers * _BBN object associated with each peer bus; use the presence 58025145214Smyers * of this object to remove gaps in the numbering of the peer 58125145214Smyers * PCI bus unit-addresses - only peer busses with an associated 58225145214Smyers * _BBN are counted. 58325145214Smyers */ 58425145214Smyers static void 58525145214Smyers pci_renumber_root_busses(void) 58625145214Smyers { 58725145214Smyers int pci_regs[] = {0, 0, 0}; 58825145214Smyers int i, root_addr = 0; 58925145214Smyers 590ee8c1d4aSdm /* 591ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 592ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 593ee8c1d4aSdm * issue of upgrade changing physical device paths 594ee8c1d4aSdm */ 59525145214Smyers if (!pci_bus_renumber()) 59625145214Smyers return; 59725145214Smyers 59825145214Smyers /* 59925145214Smyers * If we find no _BBN objects at all, we either don't need 60025145214Smyers * to do anything or can't do anything anyway 60125145214Smyers */ 60225145214Smyers if (!pci_roots_have_bbn()) 60325145214Smyers return; 60425145214Smyers 60547310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 60625145214Smyers /* skip non-root (peer) PCI busses */ 60725145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 60825145214Smyers continue; 60925145214Smyers 61025145214Smyers if (pci_bbn_present(i) < 1) { 61125145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 61225145214Smyers continue; 61325145214Smyers } 61425145214Smyers 61525145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 61625145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 61725145214Smyers /* update reg property for node */ 61825145214Smyers pci_bus_res[i].root_addr = root_addr; 61925145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 62025145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 62125145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 62225145214Smyers } 62325145214Smyers root_addr++; 62425145214Smyers } 62525145214Smyers } 62625145214Smyers 62778323854SJudy Chen void 6281d6b7b34SJudy Chen pci_register_isa_resources(int type, uint32_t base, uint32_t size) 629aaba6dfeSmyers { 6301d6b7b34SJudy Chen (void) memlist_insert( 6312f283da5SDan Mick (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 6321d6b7b34SJudy Chen base, size); 633aaba6dfeSmyers } 634aaba6dfeSmyers 6355af4ae46Sjveta /* 63605f867c3Sgs * Remove the resources which are already used by devices under a subtractive 63705f867c3Sgs * bridge from the bus's resources lists, because they're not available, and 63805f867c3Sgs * shouldn't be allocated to other buses. This is necessary because tracking 63905f867c3Sgs * resources for subtractive bridges is not complete. (Subtractive bridges only 64005f867c3Sgs * track some of their claimed resources, not "the rest of the address space" as 64105f867c3Sgs * they should, so that allocation to peer non-subtractive PPBs is easier. We 64205f867c3Sgs * need a fully-capable global resource allocator). 6435af4ae46Sjveta */ 64405f867c3Sgs static void 64505f867c3Sgs remove_subtractive_res() 6465af4ae46Sjveta { 64705f867c3Sgs int i, j; 64805f867c3Sgs struct memlist *list; 6495af4ae46Sjveta 65047310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 65105f867c3Sgs if (pci_bus_res[i].subtractive) { 65205f867c3Sgs /* remove used io ports */ 6532f283da5SDan Mick list = pci_bus_res[i].io_used; 65405f867c3Sgs while (list) { 65547310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) 6568fc7923fSDana Myers (void) memlist_remove( 6572f283da5SDan Mick &pci_bus_res[j].io_avail, 65856f33205SJonathan Adams list->ml_address, list->ml_size); 65956f33205SJonathan Adams list = list->ml_next; 66005f867c3Sgs } 66105f867c3Sgs /* remove used mem resource */ 6622f283da5SDan Mick list = pci_bus_res[i].mem_used; 66305f867c3Sgs while (list) { 66447310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) { 6658fc7923fSDana Myers (void) memlist_remove( 6662f283da5SDan Mick &pci_bus_res[j].mem_avail, 66756f33205SJonathan Adams list->ml_address, list->ml_size); 6688fc7923fSDana Myers (void) memlist_remove( 6692f283da5SDan Mick &pci_bus_res[j].pmem_avail, 67056f33205SJonathan Adams list->ml_address, list->ml_size); 67105f867c3Sgs } 67256f33205SJonathan Adams list = list->ml_next; 67305f867c3Sgs } 67405f867c3Sgs /* remove used prefetchable mem resource */ 6752f283da5SDan Mick list = pci_bus_res[i].pmem_used; 67605f867c3Sgs while (list) { 67747310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) { 6788fc7923fSDana Myers (void) memlist_remove( 6792f283da5SDan Mick &pci_bus_res[j].pmem_avail, 68056f33205SJonathan Adams list->ml_address, list->ml_size); 6818fc7923fSDana Myers (void) memlist_remove( 6822f283da5SDan Mick &pci_bus_res[j].mem_avail, 68356f33205SJonathan Adams list->ml_address, list->ml_size); 68405f867c3Sgs } 68556f33205SJonathan Adams list = list->ml_next; 68605f867c3Sgs } 6875af4ae46Sjveta } 68805f867c3Sgs } 68905f867c3Sgs } 69005f867c3Sgs 6918fc7923fSDana Myers /* 6922f283da5SDan Mick * Set up (or complete the setup of) the bus_avail resource list 6938fc7923fSDana Myers */ 69405f867c3Sgs static void 69505f867c3Sgs setup_bus_res(int bus) 69605f867c3Sgs { 69705f867c3Sgs uchar_t par_bus; 69805f867c3Sgs 69905f867c3Sgs if (pci_bus_res[bus].dip == NULL) /* unused bus */ 70005f867c3Sgs return; 70105f867c3Sgs 7028fc7923fSDana Myers /* 7032f283da5SDan Mick * Set up bus_avail if not already filled in by populate_bus_res() 7048fc7923fSDana Myers */ 7052f283da5SDan Mick if (pci_bus_res[bus].bus_avail == NULL) { 7068fc7923fSDana Myers ASSERT(pci_bus_res[bus].sub_bus >= bus); 7072f283da5SDan Mick memlist_insert(&pci_bus_res[bus].bus_avail, bus, 7088fc7923fSDana Myers pci_bus_res[bus].sub_bus - bus + 1); 70905f867c3Sgs } 7105af4ae46Sjveta 7112f283da5SDan Mick ASSERT(pci_bus_res[bus].bus_avail != NULL); 7128fc7923fSDana Myers 71305f867c3Sgs /* 71405f867c3Sgs * Remove resources from parent bus node if this is not a 71505f867c3Sgs * root bus. 71605f867c3Sgs */ 71705f867c3Sgs par_bus = pci_bus_res[bus].par_bus; 71805f867c3Sgs if (par_bus != (uchar_t)-1) { 7192f283da5SDan Mick ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 7202f283da5SDan Mick memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 7212f283da5SDan Mick pci_bus_res[bus].bus_avail); 72205f867c3Sgs } 7238fc7923fSDana Myers 7242f283da5SDan Mick /* remove self from bus_avail */; 7252f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 7265af4ae46Sjveta } 7275af4ae46Sjveta 72805f867c3Sgs static uint64_t 72905f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 7305af4ae46Sjveta { 73105f867c3Sgs uint64_t addr = 0; 73205f867c3Sgs uchar_t res_bus; 7335af4ae46Sjveta 73405f867c3Sgs /* 7358fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7368fc7923fSDana Myers * ACPI resource discovery was not successfully done. 73705f867c3Sgs */ 73805f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7398fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7405af4ae46Sjveta return (0); 7415af4ae46Sjveta 74205f867c3Sgs res_bus = parbus; 74305f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7442f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) 74505f867c3Sgs break; 74605f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 74705f867c3Sgs if (res_bus == (uchar_t)-1) 74805f867c3Sgs break; /* root bus already */ 74905f867c3Sgs } 7505af4ae46Sjveta 7512f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 7522f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].io_avail, 75305f867c3Sgs size, align); 75405f867c3Sgs if (addr) { 7552f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].io_used, 75605f867c3Sgs addr, size); 7578fc7923fSDana Myers 75805f867c3Sgs /* free the old resource */ 7592f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_avail); 7602f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_used); 7618fc7923fSDana Myers 76205f867c3Sgs /* add the new resource */ 7632f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 76405f867c3Sgs } 7655af4ae46Sjveta } 7665af4ae46Sjveta 76705f867c3Sgs return (addr); 76805f867c3Sgs } 76905f867c3Sgs 77005f867c3Sgs static uint64_t 77105f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 77205f867c3Sgs { 77305f867c3Sgs uint64_t addr = 0; 77405f867c3Sgs uchar_t res_bus; 7755af4ae46Sjveta 7765af4ae46Sjveta /* 7778fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7788fc7923fSDana Myers * ACPI resource discovery was not successfully done. 7795af4ae46Sjveta */ 78005f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7818fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7825af4ae46Sjveta return (0); 7835af4ae46Sjveta 78405f867c3Sgs res_bus = parbus; 78505f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7862f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) 78705f867c3Sgs break; 78805f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 78905f867c3Sgs if (res_bus == (uchar_t)-1) 79005f867c3Sgs break; /* root bus already */ 79105f867c3Sgs } 79205f867c3Sgs 7932f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) { 7942f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 79505f867c3Sgs size, align); 79605f867c3Sgs if (addr) { 7972f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].mem_used, 79805f867c3Sgs addr, size); 7992f283da5SDan Mick (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 8008fc7923fSDana Myers addr, size); 8018fc7923fSDana Myers 80205f867c3Sgs /* free the old resource */ 8032f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_avail); 8042f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_used); 8058fc7923fSDana Myers 80605f867c3Sgs /* add the new resource */ 8072f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 80805f867c3Sgs } 80905f867c3Sgs } 81005f867c3Sgs 81105f867c3Sgs return (addr); 8125af4ae46Sjveta } 8135af4ae46Sjveta 81449fbdd30SErwin T Tsaur /* 81549fbdd30SErwin T Tsaur * given a cap_id, return its cap_id location in config space 81649fbdd30SErwin T Tsaur */ 81749fbdd30SErwin T Tsaur static int 81849fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 81949fbdd30SErwin T Tsaur { 82049fbdd30SErwin T Tsaur uint8_t curcap, cap_id_loc; 82149fbdd30SErwin T Tsaur uint16_t status; 82249fbdd30SErwin T Tsaur int location = -1; 82349fbdd30SErwin T Tsaur 82449fbdd30SErwin T Tsaur /* 82549fbdd30SErwin T Tsaur * Need to check the Status register for ECP support first. 82649fbdd30SErwin T Tsaur * Also please note that for type 1 devices, the 82749fbdd30SErwin T Tsaur * offset could change. Should support type 1 next. 82849fbdd30SErwin T Tsaur */ 82949fbdd30SErwin T Tsaur status = pci_getw(bus, dev, func, PCI_CONF_STAT); 83049fbdd30SErwin T Tsaur if (!(status & PCI_STAT_CAP)) { 83149fbdd30SErwin T Tsaur return (-1); 83249fbdd30SErwin T Tsaur } 83349fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 83449fbdd30SErwin T Tsaur 83549fbdd30SErwin T Tsaur /* Walk the list of capabilities */ 83649fbdd30SErwin T Tsaur while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 83749fbdd30SErwin T Tsaur curcap = pci_getb(bus, dev, func, cap_id_loc); 83849fbdd30SErwin T Tsaur 83949fbdd30SErwin T Tsaur if (curcap == cap_id) { 84049fbdd30SErwin T Tsaur location = cap_id_loc; 84149fbdd30SErwin T Tsaur break; 84249fbdd30SErwin T Tsaur } 84349fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 84449fbdd30SErwin T Tsaur } 84549fbdd30SErwin T Tsaur return (location); 84649fbdd30SErwin T Tsaur } 84749fbdd30SErwin T Tsaur 8482f283da5SDan Mick /* 8492f283da5SDan Mick * Does this resource element live in the legacy VGA range? 8502f283da5SDan Mick */ 8512f283da5SDan Mick 8522f283da5SDan Mick int 8532f283da5SDan Mick is_vga(struct memlist *elem, enum io_mem io) 8542f283da5SDan Mick { 8552f283da5SDan Mick 8562f283da5SDan Mick if (io == IO) { 85756f33205SJonathan Adams if ((elem->ml_address == 0x3b0 && elem->ml_size == 0xc) || 85856f33205SJonathan Adams (elem->ml_address == 0x3c0 && elem->ml_size == 0x20)) 8592f283da5SDan Mick return (1); 8602f283da5SDan Mick } else { 86156f33205SJonathan Adams if (elem->ml_address == 0xa0000 && elem->ml_size == 0x20000) 8622f283da5SDan Mick return (1); 8632f283da5SDan Mick } 8642f283da5SDan Mick return (0); 8652f283da5SDan Mick } 8662f283da5SDan Mick 8672f283da5SDan Mick /* 8682f283da5SDan Mick * Does this entire resource list consist only of legacy VGA resources? 8692f283da5SDan Mick */ 8702f283da5SDan Mick 8712f283da5SDan Mick int 8722f283da5SDan Mick list_is_vga_only(struct memlist *l, enum io_mem io) 8732f283da5SDan Mick { 8742f283da5SDan Mick do { 8752f283da5SDan Mick if (!is_vga(l, io)) 8762f283da5SDan Mick return (0); 87756f33205SJonathan Adams } while ((l = l->ml_next) != NULL); 8782f283da5SDan Mick return (1); 8792f283da5SDan Mick } 8802f283da5SDan Mick 8819896aa55Sjveta /* 88205f867c3Sgs * Assign valid resources to unconfigured pci(e) bridges. We are trying 88305f867c3Sgs * to reprogram the bridge when its 88458b49504SHans Rosenfeld * i) SECBUS == SUBBUS || 88558b49504SHans Rosenfeld * ii) IOBASE > IOLIM || 88658b49504SHans Rosenfeld * iii) MEMBASE > MEMLIM 88705f867c3Sgs * This must be done after one full pass through the PCI tree to collect 88805f867c3Sgs * all BIOS-configured resources, so that we know what resources are 88905f867c3Sgs * free and available to assign to the unconfigured PPBs. 8909896aa55Sjveta */ 8919896aa55Sjveta static void 89205f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 8939896aa55Sjveta { 8949896aa55Sjveta uchar_t bus, dev, func; 89505f867c3Sgs uchar_t parbus, subbus; 896b5cf5bc2SHans Rosenfeld uint_t io_base, io_limit, mem_base; 897b5cf5bc2SHans Rosenfeld uint_t io_size, io_align; 898b5cf5bc2SHans Rosenfeld uint64_t mem_size, mem_align, mem_limit; 89905f867c3Sgs uint64_t addr = 0; 9005af4ae46Sjveta int *regp = NULL; 9019896aa55Sjveta uint_t reglen; 9025af4ae46Sjveta int rv, cap_ptr, physhi; 9039896aa55Sjveta dev_info_t *dip; 90405f867c3Sgs uint16_t cmd_reg; 90542e542bcSDan Mick struct memlist *list, *scratch_list; 90605f867c3Sgs 90705f867c3Sgs /* skip root (peer) PCI busses */ 90805f867c3Sgs if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 90905f867c3Sgs return; 91005f867c3Sgs 91105f867c3Sgs /* skip subtractive PPB when prog_sub is not TRUE */ 91205f867c3Sgs if (pci_bus_res[secbus].subtractive && !prog_sub) 91305f867c3Sgs return; 9149896aa55Sjveta 9159896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 9165af4ae46Sjveta dip = pci_bus_res[secbus].dip; 9179896aa55Sjveta if (dip == NULL) 9189896aa55Sjveta return; 9199896aa55Sjveta 9209896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 9219896aa55Sjveta "reg", ®p, ®len); 9222f283da5SDan Mick if (rv != DDI_PROP_SUCCESS || reglen == 0) 9232f283da5SDan Mick return; 9245af4ae46Sjveta physhi = regp[0]; 9255af4ae46Sjveta ddi_prop_free(regp); 9269896aa55Sjveta 9275af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 9285af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 9295af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 9309896aa55Sjveta 9319896aa55Sjveta /* 93205f867c3Sgs * If pcie bridge, check to see if link is enabled 9339896aa55Sjveta */ 93449fbdd30SErwin T Tsaur cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 93549fbdd30SErwin T Tsaur if (cap_ptr != -1) { 93605f867c3Sgs cmd_reg = pci_getw(bus, dev, func, 93705f867c3Sgs (uint16_t)cap_ptr + PCIE_LINKCTL); 93805f867c3Sgs if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 93905f867c3Sgs dcmn_err(CE_NOTE, 94005f867c3Sgs "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 94105f867c3Sgs bus, dev, func); 94205f867c3Sgs return; 94305f867c3Sgs } 94405f867c3Sgs } 9459896aa55Sjveta 94605f867c3Sgs subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 94705f867c3Sgs parbus = pci_bus_res[secbus].par_bus; 94805f867c3Sgs ASSERT(parbus == bus); 949707a5600Sgs cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 9509896aa55Sjveta 9515af4ae46Sjveta /* 95205f867c3Sgs * If we have a Cardbus bridge, but no bus space 9535af4ae46Sjveta */ 95405f867c3Sgs if (pci_bus_res[secbus].num_cbb != 0 && 9552f283da5SDan Mick pci_bus_res[secbus].bus_avail == NULL) { 95605f867c3Sgs uchar_t range; 9575af4ae46Sjveta 95805f867c3Sgs /* normally there are 2 buses under a cardbus bridge */ 95905f867c3Sgs range = pci_bus_res[secbus].num_cbb * 2; 96005f867c3Sgs 96105f867c3Sgs /* 96205f867c3Sgs * Try to find and allocate a bus-range starting at subbus+1 96305f867c3Sgs * from the parent of the PPB. 96405f867c3Sgs */ 96505f867c3Sgs for (; range != 0; range--) { 96605f867c3Sgs if (memlist_find_with_startaddr( 9672f283da5SDan Mick &pci_bus_res[parbus].bus_avail, 96832b17656SToomas Soome subbus + 1, range, 1) != 0) 96905f867c3Sgs break; /* find bus range resource at parent */ 97005f867c3Sgs } 97105f867c3Sgs if (range != 0) { 9722f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].bus_avail, 97305f867c3Sgs subbus + 1, range); 97405f867c3Sgs subbus = subbus + range; 97505f867c3Sgs pci_bus_res[secbus].sub_bus = subbus; 97605f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 97705f867c3Sgs add_bus_range_prop(secbus); 97805f867c3Sgs 97905f867c3Sgs cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 98005f867c3Sgs "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 98105f867c3Sgs secbus, subbus); 98205f867c3Sgs } 98305f867c3Sgs } 98405f867c3Sgs 98505f867c3Sgs /* 986ffa17327SGuoli Shu * Calculate required IO size and alignment 987ffa17327SGuoli Shu * If bus io_size is zero, we are going to assign 512 bytes per bus, 988ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 989ffa17327SGuoli Shu * bus io_size. The size needs to be 4K aligned. 990ffa17327SGuoli Shu * 991ffa17327SGuoli Shu * We calculate alignment as the largest power of two less than the 992ffa17327SGuoli Shu * the sum of all children's IO size requirements, because this will 993ffa17327SGuoli Shu * align to the size of the largest child request within that size 994ffa17327SGuoli Shu * (which is always a power of two). 99505f867c3Sgs */ 99605f867c3Sgs io_size = (subbus - secbus + 1) * 0x200; 997ffa17327SGuoli Shu if (io_size < pci_bus_res[secbus].io_size) 998ffa17327SGuoli Shu io_size = pci_bus_res[secbus].io_size; 999ffa17327SGuoli Shu io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 1000ffa17327SGuoli Shu io_align = io_size; 1001ffa17327SGuoli Shu P2LE(io_align); 1002ffa17327SGuoli Shu 10035af4ae46Sjveta /* 1004ffa17327SGuoli Shu * Calculate required MEM size and alignment 1005ffa17327SGuoli Shu * If bus mem_size is zero, we are going to assign 1M bytes per bus, 1006ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 1007ffa17327SGuoli Shu * bus mem_size. The size needs to be 1M aligned. 1008ffa17327SGuoli Shu * 1009ffa17327SGuoli Shu * For the alignment, refer to the I/O comment above. 10105af4ae46Sjveta */ 101105f867c3Sgs mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 1012ffa17327SGuoli Shu if (mem_size < pci_bus_res[secbus].mem_size) { 1013ffa17327SGuoli Shu mem_size = pci_bus_res[secbus].mem_size; 1014ffa17327SGuoli Shu mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 1015ffa17327SGuoli Shu } 1016ffa17327SGuoli Shu mem_align = mem_size; 1017ffa17327SGuoli Shu P2LE(mem_align); 101805f867c3Sgs 101905f867c3Sgs /* Subtractive bridge */ 102005f867c3Sgs if (pci_bus_res[secbus].subtractive && prog_sub) { 102105f867c3Sgs /* 102205f867c3Sgs * We program an arbitrary amount of I/O and memory resource 102305f867c3Sgs * for the subtractive bridge so that child dynamic-resource- 102405f867c3Sgs * allocating devices (such as Cardbus bridges) have a chance 102505f867c3Sgs * of success. Until we have full-tree resource rebalancing, 102605f867c3Sgs * dynamic resource allocation (thru busra) only looks at the 102705f867c3Sgs * parent bridge, so all PPBs must have some allocatable 102805f867c3Sgs * resource. For non-subtractive bridges, the resources come 102905f867c3Sgs * from the base/limit register "windows", but subtractive 103005f867c3Sgs * bridges often don't program those (since they don't need to). 103105f867c3Sgs * If we put all the remaining resources on the subtractive 103205f867c3Sgs * bridge, then peer non-subtractive bridges can't allocate 103305f867c3Sgs * more space (even though this is probably most correct). 103405f867c3Sgs * If we put the resources only on the parent, then allocations 103505f867c3Sgs * from children of subtractive bridges will fail without 103605f867c3Sgs * special-case code for bypassing the subtractive bridge. 103705f867c3Sgs * This solution is the middle-ground temporary solution until 103805f867c3Sgs * we have fully-capable resource allocation. 103905f867c3Sgs */ 104005f867c3Sgs 104105f867c3Sgs /* 104205f867c3Sgs * Add an arbitrary I/O resource to the subtractive PPB 104305f867c3Sgs */ 10442f283da5SDan Mick if (pci_bus_res[secbus].io_avail == NULL) { 104505f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1046ffa17327SGuoli Shu io_align); 104705f867c3Sgs if (addr) { 10488fc7923fSDana Myers add_ranges_prop(secbus, 1); 104905f867c3Sgs pci_bus_res[secbus].io_reprogram = 105005f867c3Sgs pci_bus_res[parbus].io_reprogram; 105105f867c3Sgs 105205f867c3Sgs cmn_err(CE_NOTE, "!add io-range on subtractive" 1053b5cf5bc2SHans Rosenfeld " ppb[%x/%x/%x]: " 1054b5cf5bc2SHans Rosenfeld "0x%"PRIx64" ~ 0x%"PRIx64"\n", 1055b5cf5bc2SHans Rosenfeld bus, dev, func, addr, addr + io_size - 1); 105605f867c3Sgs } 105705f867c3Sgs } 105805f867c3Sgs /* 105905f867c3Sgs * Add an arbitrary memory resource to the subtractive PPB 106005f867c3Sgs */ 10612f283da5SDan Mick if (pci_bus_res[secbus].mem_avail == NULL) { 106205f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1063ffa17327SGuoli Shu mem_align); 106405f867c3Sgs if (addr) { 10658fc7923fSDana Myers add_ranges_prop(secbus, 1); 106605f867c3Sgs pci_bus_res[secbus].mem_reprogram = 106705f867c3Sgs pci_bus_res[parbus].mem_reprogram; 106805f867c3Sgs 106905f867c3Sgs cmn_err(CE_NOTE, "!add mem-range on " 1070b5cf5bc2SHans Rosenfeld "subtractive ppb[%x/%x/%x]: " 1071b5cf5bc2SHans Rosenfeld "0x%"PRIx64" ~ 0x%"PRIx64"\n", 1072b5cf5bc2SHans Rosenfeld bus, dev, func, 1073b5cf5bc2SHans Rosenfeld addr, addr + mem_size - 1); 107405f867c3Sgs } 107505f867c3Sgs } 107605f867c3Sgs 107705f867c3Sgs goto cmd_enable; 10785af4ae46Sjveta } 107905f867c3Sgs 108005f867c3Sgs /* 1081707a5600Sgs * Check to see if we need to reprogram I/O space, either because the 1082707a5600Sgs * parent bus needed reprogramming and so do we, or because I/O space is 1083707a5600Sgs * disabled in base/limit or command register. 108405f867c3Sgs */ 108505f867c3Sgs io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 108605f867c3Sgs io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 10871f0c5e61SRobert Mustacchi io_base = (io_base & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT; 10881f0c5e61SRobert Mustacchi io_limit = ((io_limit & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 0xfff; 10891f0c5e61SRobert Mustacchi if ((io_base & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 10901f0c5e61SRobert Mustacchi uint16_t io_base_hi, io_limit_hi; 10911f0c5e61SRobert Mustacchi io_base_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI); 10921f0c5e61SRobert Mustacchi io_limit_hi = pci_getw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI); 10931f0c5e61SRobert Mustacchi 10941f0c5e61SRobert Mustacchi io_base |= (uint_t)io_base_hi << 16; 10951f0c5e61SRobert Mustacchi io_limit |= (uint_t)io_limit_hi << 16; 10961f0c5e61SRobert Mustacchi } 109705f867c3Sgs 10982f283da5SDan Mick /* Form list of all resources passed (avail + used) */ 109942e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 110042e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 11012f283da5SDan Mick 11022f283da5SDan Mick if ((pci_bus_res[parbus].io_reprogram || 11032f283da5SDan Mick (io_base > io_limit) || 11042f283da5SDan Mick (!(cmd_reg & PCI_COMM_IO))) && 110542e542bcSDan Mick !list_is_vga_only(scratch_list, IO)) { 11062f283da5SDan Mick if (pci_bus_res[secbus].io_used) { 11072f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].io_used, 11082f283da5SDan Mick &pci_bus_res[secbus].io_avail); 110905f867c3Sgs } 11102f283da5SDan Mick if (pci_bus_res[secbus].io_avail && 111105f867c3Sgs (!pci_bus_res[parbus].io_reprogram) && 111205f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 111305f867c3Sgs /* rechoose old io ports info */ 11142f283da5SDan Mick list = pci_bus_res[secbus].io_avail; 11152f283da5SDan Mick io_base = 0; 11162f283da5SDan Mick do { 11172f283da5SDan Mick if (is_vga(list, IO)) 11182f283da5SDan Mick continue; 11192f283da5SDan Mick if (!io_base) { 112056f33205SJonathan Adams io_base = (uint_t)list->ml_address; 112156f33205SJonathan Adams io_limit = (uint_t)list->ml_address + 112256f33205SJonathan Adams list->ml_size - 1; 11232f283da5SDan Mick io_base = 11242f283da5SDan Mick P2ALIGN(io_base, PPB_IO_ALIGNMENT); 11252f283da5SDan Mick } else { 112656f33205SJonathan Adams if (list->ml_address + list->ml_size > 11272f283da5SDan Mick io_limit) { 11282f283da5SDan Mick io_limit = (uint_t) 112956f33205SJonathan Adams (list->ml_address + 113056f33205SJonathan Adams list->ml_size - 1); 11312f283da5SDan Mick } 11322f283da5SDan Mick } 113356f33205SJonathan Adams } while ((list = list->ml_next) != NULL); 113405f867c3Sgs /* 4K aligned */ 11352f283da5SDan Mick io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 11362f283da5SDan Mick io_size = io_limit - io_base + 1; 113705f867c3Sgs ASSERT(io_base <= io_limit); 11382f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].io_avail); 11392f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 114005f867c3Sgs io_base, io_size); 11412f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].io_used, 114205f867c3Sgs io_base, io_size); 11432f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].io_avail, 11448fc7923fSDana Myers io_base, io_size); 114505f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 114605f867c3Sgs } else { 114705f867c3Sgs /* get new io ports from parent bus */ 114805f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1149ffa17327SGuoli Shu io_align); 115005f867c3Sgs if (addr) { 115105f867c3Sgs io_base = addr; 115205f867c3Sgs io_limit = addr + io_size - 1; 115305f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 115405f867c3Sgs } 115505f867c3Sgs } 115605f867c3Sgs if (pci_bus_res[secbus].io_reprogram) { 115705f867c3Sgs /* reprogram PPB regs */ 115805f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 115905f867c3Sgs (uchar_t)((io_base>>8) & 0xf0)); 116005f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 116105f867c3Sgs (uchar_t)((io_limit>>8) & 0xf0)); 116205f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 116305f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 11648fc7923fSDana Myers add_ranges_prop(secbus, 1); 116505f867c3Sgs 116605f867c3Sgs cmn_err(CE_NOTE, "!reprogram io-range on" 116705f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 116805f867c3Sgs bus, dev, func, io_base, io_limit); 116905f867c3Sgs } 11709896aa55Sjveta } 117142e542bcSDan Mick memlist_free_all(&scratch_list); 11729896aa55Sjveta 11735af4ae46Sjveta /* 1174707a5600Sgs * Check memory space as we did I/O space. 11755af4ae46Sjveta */ 117605f867c3Sgs mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 117705f867c3Sgs mem_base = (mem_base & 0xfff0) << 16; 117805f867c3Sgs mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1179707a5600Sgs mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 1180707a5600Sgs 118142e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 118242e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 11832f283da5SDan Mick 11842f283da5SDan Mick if ((pci_bus_res[parbus].mem_reprogram || 11852f283da5SDan Mick (mem_base > mem_limit) || 11862f283da5SDan Mick (!(cmd_reg & PCI_COMM_MAE))) && 118742e542bcSDan Mick !list_is_vga_only(scratch_list, MEM)) { 11882f283da5SDan Mick if (pci_bus_res[secbus].mem_used) { 11892f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].mem_used, 11902f283da5SDan Mick &pci_bus_res[secbus].mem_avail); 119105f867c3Sgs } 11922f283da5SDan Mick if (pci_bus_res[secbus].mem_avail && 119305f867c3Sgs (!pci_bus_res[parbus].mem_reprogram) && 119405f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 119505f867c3Sgs /* rechoose old mem resource */ 11962f283da5SDan Mick list = pci_bus_res[secbus].mem_avail; 11972f283da5SDan Mick mem_base = 0; 11982f283da5SDan Mick do { 11992f283da5SDan Mick if (is_vga(list, MEM)) 12002f283da5SDan Mick continue; 12012f283da5SDan Mick if (mem_base == 0) { 1202b5cf5bc2SHans Rosenfeld mem_base = list->ml_address; 12032f283da5SDan Mick mem_base = P2ALIGN(mem_base, 12042f283da5SDan Mick PPB_MEM_ALIGNMENT); 1205b5cf5bc2SHans Rosenfeld mem_limit = (list->ml_address + 120656f33205SJonathan Adams list->ml_size - 1); 12072f283da5SDan Mick } else { 120856f33205SJonathan Adams if ((list->ml_address + list->ml_size) > 12092f283da5SDan Mick mem_limit) { 1210b5cf5bc2SHans Rosenfeld mem_limit = 121156f33205SJonathan Adams (list->ml_address + 121256f33205SJonathan Adams list->ml_size - 1); 12132f283da5SDan Mick } 12142f283da5SDan Mick } 121556f33205SJonathan Adams } while ((list = list->ml_next) != NULL); 12162f283da5SDan Mick mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 12172f283da5SDan Mick mem_size = mem_limit + 1 - mem_base; 121805f867c3Sgs ASSERT(mem_base <= mem_limit); 12192f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].mem_avail); 12202f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 122105f867c3Sgs mem_base, mem_size); 12222f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].mem_used, 122305f867c3Sgs mem_base, mem_size); 12242f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 12258fc7923fSDana Myers mem_base, mem_size); 122605f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 122705f867c3Sgs } else { 122805f867c3Sgs /* get new mem resource from parent bus */ 122905f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1230ffa17327SGuoli Shu mem_align); 123105f867c3Sgs if (addr) { 123205f867c3Sgs mem_base = addr; 123305f867c3Sgs mem_limit = addr + mem_size - 1; 123405f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 123505f867c3Sgs } 123605f867c3Sgs } 123705f867c3Sgs 123805f867c3Sgs if (pci_bus_res[secbus].mem_reprogram) { 123902c2c4edSGuoli Shu /* reprogram PPB MEM regs */ 124005f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 124105f867c3Sgs (uint16_t)((mem_base>>16) & 0xfff0)); 124205f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 124305f867c3Sgs (uint16_t)((mem_limit>>16) & 0xfff0)); 124402c2c4edSGuoli Shu /* 124502c2c4edSGuoli Shu * Disable PMEM window by setting base > limit. 124602c2c4edSGuoli Shu * We currently don't reprogram the PMEM like we've 124702c2c4edSGuoli Shu * done for I/O and MEM. (Devices that support prefetch 124802c2c4edSGuoli Shu * can use non-prefetch MEM.) Anyway, if the MEM access 124902c2c4edSGuoli Shu * bit is initially disabled by BIOS, we disable the 125002c2c4edSGuoli Shu * PMEM window manually by setting PMEM base > PMEM 125102c2c4edSGuoli Shu * limit here, in case there are incorrect values in 125202c2c4edSGuoli Shu * them from BIOS, so that we won't get in trouble once 125302c2c4edSGuoli Shu * the MEM access bit is enabled at the end of this 125402c2c4edSGuoli Shu * function. 125502c2c4edSGuoli Shu */ 125602c2c4edSGuoli Shu if (!(cmd_reg & PCI_COMM_MAE)) { 125702c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 125802c2c4edSGuoli Shu 0xfff0); 125902c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 126002c2c4edSGuoli Shu 0x0); 126102c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 126202c2c4edSGuoli Shu 0xffffffff); 126302c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 126402c2c4edSGuoli Shu 0x0); 126502c2c4edSGuoli Shu } 126602c2c4edSGuoli Shu 12678fc7923fSDana Myers add_ranges_prop(secbus, 1); 126805f867c3Sgs 126905f867c3Sgs cmn_err(CE_NOTE, "!reprogram mem-range on" 1270b5cf5bc2SHans Rosenfeld " ppb[%x/%x/%x]: 0x%x ~ 0x%"PRIx64"\n", 127105f867c3Sgs bus, dev, func, mem_base, mem_limit); 127205f867c3Sgs } 127305f867c3Sgs } 127442e542bcSDan Mick memlist_free_all(&scratch_list); 127505f867c3Sgs 127605f867c3Sgs cmd_enable: 12772f283da5SDan Mick if (pci_bus_res[secbus].io_avail) 127805f867c3Sgs cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 12792f283da5SDan Mick if (pci_bus_res[secbus].mem_avail) 128005f867c3Sgs cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 128105f867c3Sgs pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 12829896aa55Sjveta } 12839896aa55Sjveta 12847c478bd9Sstevel@tonic-gate void 12857c478bd9Sstevel@tonic-gate pci_reprogram(void) 12867c478bd9Sstevel@tonic-gate { 12877c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 12887c478bd9Sstevel@tonic-gate char *onoff; 12898fc7923fSDana Myers int bus; 12907c478bd9Sstevel@tonic-gate 129125145214Smyers /* 129200dfdf4aSDana Myers * Scan ACPI namespace for _BBN objects, make sure that 129300dfdf4aSDana Myers * childless root-bridges appear in devinfo tree 129425145214Smyers */ 129500dfdf4aSDana Myers pci_scan_bbn(); 129600dfdf4aSDana Myers pci_unitaddr_cache_init(); 129700dfdf4aSDana Myers 129800dfdf4aSDana Myers /* 129900dfdf4aSDana Myers * Fix-up unit-address assignments if cache is available 130000dfdf4aSDana Myers */ 130100dfdf4aSDana Myers if (pci_unitaddr_cache_valid()) { 130200dfdf4aSDana Myers int pci_regs[] = {0, 0, 0}; 130300dfdf4aSDana Myers int new_addr; 130400dfdf4aSDana Myers int index = 0; 130500dfdf4aSDana Myers 130647310cedSDana Myers for (bus = 0; bus <= pci_bios_maxbus; bus++) { 130700dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 130800dfdf4aSDana Myers if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 130900dfdf4aSDana Myers (pci_bus_res[bus].dip == NULL)) 131000dfdf4aSDana Myers continue; 131100dfdf4aSDana Myers 131200dfdf4aSDana Myers new_addr = pci_bus_unitaddr(index); 131300dfdf4aSDana Myers if (pci_bus_res[bus].root_addr != new_addr) { 131400dfdf4aSDana Myers /* update reg property for node */ 131500dfdf4aSDana Myers pci_regs[0] = pci_bus_res[bus].root_addr = 131600dfdf4aSDana Myers new_addr; 131700dfdf4aSDana Myers (void) ndi_prop_update_int_array( 131800dfdf4aSDana Myers DDI_DEV_T_NONE, pci_bus_res[bus].dip, 131900dfdf4aSDana Myers "reg", (int *)pci_regs, 3); 132000dfdf4aSDana Myers } 132100dfdf4aSDana Myers index++; 132200dfdf4aSDana Myers } 132300dfdf4aSDana Myers } else { 132400dfdf4aSDana Myers /* perform legacy processing */ 132500dfdf4aSDana Myers pci_renumber_root_busses(); 132600dfdf4aSDana Myers pci_unitaddr_cache_create(); 132700dfdf4aSDana Myers } 132825145214Smyers 13298fc7923fSDana Myers /* 13308fc7923fSDana Myers * Do root-bus resource discovery 13318fc7923fSDana Myers */ 133247310cedSDana Myers for (bus = 0; bus <= pci_bios_maxbus; bus++) { 13338fc7923fSDana Myers /* skip non-root (peer) PCI busses */ 13348fc7923fSDana Myers if (pci_bus_res[bus].par_bus != (uchar_t)-1) 13358fc7923fSDana Myers continue; 13368fc7923fSDana Myers 13378fc7923fSDana Myers /* 13388fc7923fSDana Myers * 1. find resources associated with this root bus 13398fc7923fSDana Myers */ 13408fc7923fSDana Myers populate_bus_res(bus); 13418fc7923fSDana Myers 13428fc7923fSDana Myers 13438fc7923fSDana Myers /* 13441d6b7b34SJudy Chen * 2. Remove used PCI and ISA resources from bus resource map 13458fc7923fSDana Myers */ 13468fc7923fSDana Myers 13472f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13482f283da5SDan Mick pci_bus_res[bus].io_used); 13492f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13502f283da5SDan Mick pci_bus_res[bus].mem_used); 13512f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13522f283da5SDan Mick pci_bus_res[bus].pmem_used); 13532f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13542f283da5SDan Mick pci_bus_res[bus].pmem_used); 13552f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13562f283da5SDan Mick pci_bus_res[bus].mem_used); 13571d6b7b34SJudy Chen 13582f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13592f283da5SDan Mick isa_res.io_used); 13602f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13612f283da5SDan Mick isa_res.mem_used); 13624b8b26d4SGuoli Shu 13634b8b26d4SGuoli Shu /* 13644b8b26d4SGuoli Shu * 3. Exclude <1M address range here in case below reserved 13654b8b26d4SGuoli Shu * ranges for BIOS data area, ROM area etc are wrongly reported 13664b8b26d4SGuoli Shu * in ACPI resource producer entries for PCI root bus. 136758b49504SHans Rosenfeld * 00000000 - 000003FF RAM 136858b49504SHans Rosenfeld * 00000400 - 000004FF BIOS data area 136958b49504SHans Rosenfeld * 00000500 - 0009FFFF RAM 137058b49504SHans Rosenfeld * 000A0000 - 000BFFFF VGA RAM 137158b49504SHans Rosenfeld * 000C0000 - 000FFFFF ROM area 13724b8b26d4SGuoli Shu */ 13734f2f7396SGuoli Shu (void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000); 13744f2f7396SGuoli Shu (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 13754f2f7396SGuoli Shu 0, 0x100000); 13768fc7923fSDana Myers } 13778fc7923fSDana Myers 13782f283da5SDan Mick memlist_free_all(&isa_res.io_used); 13792f283da5SDan Mick memlist_free_all(&isa_res.mem_used); 13808fc7923fSDana Myers 1381fc396574Srw /* add bus-range property for root/peer bus nodes */ 138247310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 13838fc7923fSDana Myers /* create bus-range property on root/peer buses */ 13848fc7923fSDana Myers if (pci_bus_res[i].par_bus == (uchar_t)-1) 1385fc396574Srw add_bus_range_prop(i); 13868fc7923fSDana Myers 138705f867c3Sgs /* setup bus range resource on each bus */ 138805f867c3Sgs setup_bus_res(i); 1389fc396574Srw } 1390fc396574Srw 13917c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 13927c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 13937c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 13947c478bd9Sstevel@tonic-gate pci_reconfig = 0; 13957c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 13967c478bd9Sstevel@tonic-gate } 13977c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 13987c478bd9Sstevel@tonic-gate } 13997c478bd9Sstevel@tonic-gate 140005f867c3Sgs remove_subtractive_res(); 140105f867c3Sgs 140205f867c3Sgs /* reprogram the non-subtractive PPB */ 140305f867c3Sgs if (pci_reconfig) 140447310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) 140505f867c3Sgs fix_ppb_res(i, B_FALSE); 1406aaba6dfeSmyers 140747310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 140805f867c3Sgs /* configure devices not configured by BIOS */ 14099896aa55Sjveta if (pci_reconfig) { 141005f867c3Sgs /* 141105f867c3Sgs * Reprogram the subtractive PPB. At this time, all its 141205f867c3Sgs * siblings should have got their resources already. 141305f867c3Sgs */ 141405f867c3Sgs if (pci_bus_res[i].subtractive) 141505f867c3Sgs fix_ppb_res(i, B_TRUE); 14167c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 14179896aa55Sjveta } 14188fc7923fSDana Myers } 14198fc7923fSDana Myers 14208fc7923fSDana Myers /* All dev programmed, so we can create available prop */ 142147310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) 14227c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 14238fc7923fSDana Myers } 14248fc7923fSDana Myers 14258fc7923fSDana Myers /* 14268fc7923fSDana Myers * populate bus resources 14278fc7923fSDana Myers */ 14288fc7923fSDana Myers static void 14298fc7923fSDana Myers populate_bus_res(uchar_t bus) 14308fc7923fSDana Myers { 14318fc7923fSDana Myers 14328fc7923fSDana Myers /* scan BIOS structures */ 14332f283da5SDan Mick pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 14342f283da5SDan Mick pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 14352f283da5SDan Mick pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 14362f283da5SDan Mick pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 14378fc7923fSDana Myers 14386b57bdc9SDana Myers /* 14396b57bdc9SDana Myers * attempt to initialize sub_bus from the largest range-end 14402f283da5SDan Mick * in the bus_avail list 14416b57bdc9SDana Myers */ 14422f283da5SDan Mick if (pci_bus_res[bus].bus_avail != NULL) { 14436b57bdc9SDana Myers struct memlist *entry; 14446b57bdc9SDana Myers int current; 14456b57bdc9SDana Myers 14462f283da5SDan Mick entry = pci_bus_res[bus].bus_avail; 14476b57bdc9SDana Myers while (entry != NULL) { 144856f33205SJonathan Adams current = entry->ml_address + entry->ml_size - 1; 14496b57bdc9SDana Myers if (current > pci_bus_res[bus].sub_bus) 14506b57bdc9SDana Myers pci_bus_res[bus].sub_bus = current; 145156f33205SJonathan Adams entry = entry->ml_next; 14526b57bdc9SDana Myers } 14536b57bdc9SDana Myers } 14546b57bdc9SDana Myers 14558fc7923fSDana Myers if (bus == 0) { 14568fc7923fSDana Myers /* 14578fc7923fSDana Myers * Special treatment of bus 0: 14588fc7923fSDana Myers * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 14598fc7923fSDana Myers * pcimem from boot and make I/O space the entire range 14606b57bdc9SDana Myers * starting at 0x100. 14618fc7923fSDana Myers */ 14622f283da5SDan Mick if (pci_bus_res[0].mem_avail == NULL) 14632f283da5SDan Mick pci_bus_res[0].mem_avail = 14648fc7923fSDana Myers memlist_dup(bootops->boot_mem->pcimem); 14658fc7923fSDana Myers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 14662f283da5SDan Mick if (pci_bus_res[0].io_avail == NULL) 14672f283da5SDan Mick memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 14687c478bd9Sstevel@tonic-gate } 14698fc7923fSDana Myers 14708fc7923fSDana Myers /* 14718fc7923fSDana Myers * Create 'ranges' property here before any resources are 14728fc7923fSDana Myers * removed from the resource lists 14738fc7923fSDana Myers */ 14748fc7923fSDana Myers add_ranges_prop(bus, 0); 14757c478bd9Sstevel@tonic-gate } 14767c478bd9Sstevel@tonic-gate 14778fc7923fSDana Myers 14787c478bd9Sstevel@tonic-gate /* 14797c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 14807c478bd9Sstevel@tonic-gate */ 14817c478bd9Sstevel@tonic-gate static void 14827c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 14837c478bd9Sstevel@tonic-gate { 14847c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 14857c478bd9Sstevel@tonic-gate dev_info_t *dip; 14867c478bd9Sstevel@tonic-gate 14877c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 14887c478bd9Sstevel@tonic-gate 148905f867c3Sgs num_root_bus++; 14907c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1491fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 14927c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14937c478bd9Sstevel@tonic-gate "#address-cells", 3); 14947c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14957c478bd9Sstevel@tonic-gate "#size-cells", 2); 14967c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 14977c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 14987c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 14997c478bd9Sstevel@tonic-gate 150070025d76Sjohnny /* 150170025d76Sjohnny * If system has PCIe bus, then create different properties 150270025d76Sjohnny */ 150370025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 150470025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 150570025d76Sjohnny "device_type", "pci"); 150670025d76Sjohnny 15077c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 15087c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 15097c478bd9Sstevel@tonic-gate } 15107c478bd9Sstevel@tonic-gate 15117c478bd9Sstevel@tonic-gate /* 15127c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 15137c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 15147c478bd9Sstevel@tonic-gate * to hold the already configured device details. 15157c478bd9Sstevel@tonic-gate */ 15167c478bd9Sstevel@tonic-gate void 15177c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 15187c478bd9Sstevel@tonic-gate { 15197c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 15207c478bd9Sstevel@tonic-gate ushort_t venid; 152105f867c3Sgs struct pci_devfunc *devlist = NULL, *entry; 15227c478bd9Sstevel@tonic-gate 15237c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 15247c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1525bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 1526bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 15277c478bd9Sstevel@tonic-gate } else 15287c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 15297c478bd9Sstevel@tonic-gate 15308fc7923fSDana Myers if (config_op == CONFIG_NEW) { 15318fc7923fSDana Myers devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 15328fc7923fSDana Myers while (devlist) { 15338fc7923fSDana Myers entry = devlist; 15348fc7923fSDana Myers devlist = entry->next; 15358fc7923fSDana Myers if (entry->reprogram || 15368fc7923fSDana Myers pci_bus_res[bus].io_reprogram || 15378fc7923fSDana Myers pci_bus_res[bus].mem_reprogram) { 15388fc7923fSDana Myers /* reprogram device(s) */ 15398fc7923fSDana Myers (void) add_reg_props(entry->dip, bus, 15408fc7923fSDana Myers entry->dev, entry->func, CONFIG_NEW, 0); 15418fc7923fSDana Myers } 15428fc7923fSDana Myers kmem_free(entry, sizeof (*entry)); 15438fc7923fSDana Myers } 15448fc7923fSDana Myers pci_bus_res[bus].privdata = NULL; 15458fc7923fSDana Myers return; 15468fc7923fSDana Myers } 15478fc7923fSDana Myers 15487c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 15497c478bd9Sstevel@tonic-gate nfunc = 1; 15507c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 15517c478bd9Sstevel@tonic-gate 15527c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 15537c478bd9Sstevel@tonic-gate dev, func); 15547c478bd9Sstevel@tonic-gate 15557c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1556bd87be88Ssethg 15577c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 15587c478bd9Sstevel@tonic-gate /* no function at this address */ 15597c478bd9Sstevel@tonic-gate continue; 15607c478bd9Sstevel@tonic-gate } 15617c478bd9Sstevel@tonic-gate 15627c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 15637c478bd9Sstevel@tonic-gate if (header == 0xff) { 15647c478bd9Sstevel@tonic-gate continue; /* illegal value */ 15657c478bd9Sstevel@tonic-gate } 15667c478bd9Sstevel@tonic-gate 15677c478bd9Sstevel@tonic-gate /* 15687c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 15697c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 15707c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 15717c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 15727c478bd9Sstevel@tonic-gate */ 15737c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 15747c478bd9Sstevel@tonic-gate nfunc = 8; 15757c478bd9Sstevel@tonic-gate } 157646e9e839Smyers 157705f867c3Sgs if (config_op == CONFIG_FIX || 157805f867c3Sgs config_op == CONFIG_INFO) { 1579ebf3afa8Sdmick /* 1580ebf3afa8Sdmick * Create the node, unconditionally, on the 1581ebf3afa8Sdmick * first pass only. It may still need 1582ebf3afa8Sdmick * resource assignment, which will be 1583ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 1584ebf3afa8Sdmick */ 158505f867c3Sgs process_devfunc(bus, dev, func, header, 1586ebf3afa8Sdmick venid, config_op); 1587db063408Sdmick 15887c478bd9Sstevel@tonic-gate } 15897c478bd9Sstevel@tonic-gate } 15907c478bd9Sstevel@tonic-gate } 15917c478bd9Sstevel@tonic-gate 15928fc7923fSDana Myers /* percolate bus used resources up through parents to root */ 15938fc7923fSDana Myers if (config_op == CONFIG_INFO) { 15948fc7923fSDana Myers int par_bus; 15958fc7923fSDana Myers 15968fc7923fSDana Myers par_bus = pci_bus_res[bus].par_bus; 15978fc7923fSDana Myers while (par_bus != (uchar_t)-1) { 1598ffa17327SGuoli Shu pci_bus_res[par_bus].io_size += 1599ffa17327SGuoli Shu pci_bus_res[bus].io_size; 1600ffa17327SGuoli Shu pci_bus_res[par_bus].mem_size += 1601ffa17327SGuoli Shu pci_bus_res[bus].mem_size; 16028fc7923fSDana Myers 16032f283da5SDan Mick if (pci_bus_res[bus].io_used) 16042f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, 16052f283da5SDan Mick &pci_bus_res[par_bus].io_used); 16068fc7923fSDana Myers 16072f283da5SDan Mick if (pci_bus_res[bus].mem_used) 16082f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, 16092f283da5SDan Mick &pci_bus_res[par_bus].mem_used); 16108fc7923fSDana Myers 16112f283da5SDan Mick if (pci_bus_res[bus].pmem_used) 16122f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, 16132f283da5SDan Mick &pci_bus_res[par_bus].pmem_used); 16148fc7923fSDana Myers 16152f283da5SDan Mick bus = par_bus; 16168fc7923fSDana Myers par_bus = pci_bus_res[par_bus].par_bus; 16177c478bd9Sstevel@tonic-gate } 16187c478bd9Sstevel@tonic-gate } 16197c478bd9Sstevel@tonic-gate } 16207c478bd9Sstevel@tonic-gate 16217c478bd9Sstevel@tonic-gate static int 16227c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 16237c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 16247c478bd9Sstevel@tonic-gate { 16257c478bd9Sstevel@tonic-gate static int prop_exist = -1; 16267c478bd9Sstevel@tonic-gate static char *pciide_str; 16277c478bd9Sstevel@tonic-gate char compat[32]; 16287c478bd9Sstevel@tonic-gate 16297c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 16307c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 16317c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 16327c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 16337c478bd9Sstevel@tonic-gate } 16347c478bd9Sstevel@tonic-gate 16357c478bd9Sstevel@tonic-gate if (!prop_exist) 16367c478bd9Sstevel@tonic-gate return (0); 16377c478bd9Sstevel@tonic-gate 16387c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 16397c478bd9Sstevel@tonic-gate if (subvenid) { 16407c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 16417c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 16427c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16437c478bd9Sstevel@tonic-gate return (1); 16447c478bd9Sstevel@tonic-gate 16457c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 16467c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 16477c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16487c478bd9Sstevel@tonic-gate return (1); 16497c478bd9Sstevel@tonic-gate 16507c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 16517c478bd9Sstevel@tonic-gate subvenid, subdevid); 16527c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16537c478bd9Sstevel@tonic-gate return (1); 16547c478bd9Sstevel@tonic-gate } 16557c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 16567c478bd9Sstevel@tonic-gate venid, devid, revid); 16577c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16587c478bd9Sstevel@tonic-gate return (1); 16597c478bd9Sstevel@tonic-gate 16607c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 16617c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16627c478bd9Sstevel@tonic-gate return (1); 16637c478bd9Sstevel@tonic-gate 16647c478bd9Sstevel@tonic-gate return (0); 16657c478bd9Sstevel@tonic-gate } 16667c478bd9Sstevel@tonic-gate 16677c478bd9Sstevel@tonic-gate static int 16687c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 16697c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 16707c478bd9Sstevel@tonic-gate { 16717c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 16727c478bd9Sstevel@tonic-gate ushort_t venid; 16737c478bd9Sstevel@tonic-gate ushort_t devid; 16747c478bd9Sstevel@tonic-gate } *entry; 16757c478bd9Sstevel@tonic-gate 1676334edc48Sml /* XXX SATA and other devices: need a way to add dynamically */ 16777c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 16787c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 16797c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 16807c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 1681d01a0451Stt {0x1095, 0x680}, /* Sil0680 */ 1682334edc48Sml {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 16837c478bd9Sstevel@tonic-gate {0, 0} 16847c478bd9Sstevel@tonic-gate }; 16857c478bd9Sstevel@tonic-gate 16867c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 16877c478bd9Sstevel@tonic-gate return (0); 16887c478bd9Sstevel@tonic-gate 16897c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 16907c478bd9Sstevel@tonic-gate return (1); 16917c478bd9Sstevel@tonic-gate } 16927c478bd9Sstevel@tonic-gate 1693d01a0451Stt if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1694d01a0451Stt return (1); 1695d01a0451Stt 16967c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 16977c478bd9Sstevel@tonic-gate return (0); 16987c478bd9Sstevel@tonic-gate } 16997c478bd9Sstevel@tonic-gate 17007c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 17017c478bd9Sstevel@tonic-gate while (entry->venid) { 17027c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 17037c478bd9Sstevel@tonic-gate return (1); 17047c478bd9Sstevel@tonic-gate entry++; 17057c478bd9Sstevel@tonic-gate } 1706d01a0451Stt return (0); 17077c478bd9Sstevel@tonic-gate } 17087c478bd9Sstevel@tonic-gate 17097c478bd9Sstevel@tonic-gate static int 17107c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 17117c478bd9Sstevel@tonic-gate { 17127c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 17137c478bd9Sstevel@tonic-gate 0x000100, 17147c478bd9Sstevel@tonic-gate 0x030000, 17157c478bd9Sstevel@tonic-gate 0x030001 17167c478bd9Sstevel@tonic-gate }; 17177c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 17187c478bd9Sstevel@tonic-gate 17197c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 17207c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 17217c478bd9Sstevel@tonic-gate return (1); 17227c478bd9Sstevel@tonic-gate } 17237c478bd9Sstevel@tonic-gate return (0); 17247c478bd9Sstevel@tonic-gate } 17257c478bd9Sstevel@tonic-gate 1726bd87be88Ssethg static void 1727bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1728bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 1729bd87be88Ssethg { 1730bd87be88Ssethg struct pci_fixundo *newundo; 1731bd87be88Ssethg 1732bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1733bd87be88Ssethg 1734bd87be88Ssethg /* 1735bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 1736bd87be88Ssethg * bit back on at a later time. 1737bd87be88Ssethg */ 1738bd87be88Ssethg newundo->bus = bus; 1739bd87be88Ssethg newundo->dev = dev; 1740bd87be88Ssethg newundo->fn = fn; 1741bd87be88Ssethg newundo->undofn = undofn; 1742bd87be88Ssethg newundo->next = undolist; 1743bd87be88Ssethg 1744bd87be88Ssethg /* add to the undo list in LIFO order */ 1745bd87be88Ssethg undolist = newundo; 1746bd87be88Ssethg } 1747bd87be88Ssethg 1748bd87be88Ssethg void 1749bd87be88Ssethg add_pci_fixes(void) 1750bd87be88Ssethg { 1751bd87be88Ssethg int i; 1752bd87be88Ssethg 175347310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 1754bd87be88Ssethg /* 1755bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 1756bd87be88Ssethg * This must be done before the main enumeration loop because 1757bd87be88Ssethg * some fixes must be applied to devices normally encountered 1758bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 1759bd87be88Ssethg * applied before scanning device 6, applying fixes in the 1760bd87be88Ssethg * normal enumeration loop would obviously be too late). 1761bd87be88Ssethg */ 1762bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 1763bd87be88Ssethg } 1764bd87be88Ssethg } 1765bd87be88Ssethg 1766bd87be88Ssethg void 1767bd87be88Ssethg undo_pci_fixes(void) 1768bd87be88Ssethg { 1769bd87be88Ssethg struct pci_fixundo *nextundo; 1770bd87be88Ssethg uint8_t bus, dev, fn; 1771bd87be88Ssethg 1772bd87be88Ssethg /* 1773bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 1774bd87be88Ssethg * fixes may require selective undo. 1775bd87be88Ssethg */ 1776bd87be88Ssethg while (undolist != NULL) { 1777bd87be88Ssethg 1778bd87be88Ssethg bus = undolist->bus; 1779bd87be88Ssethg dev = undolist->dev; 1780bd87be88Ssethg fn = undolist->fn; 1781bd87be88Ssethg 1782bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 1783bd87be88Ssethg 1784bd87be88Ssethg nextundo = undolist->next; 1785bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 1786bd87be88Ssethg undolist = nextundo; 1787bd87be88Ssethg } 1788bd87be88Ssethg } 1789bd87be88Ssethg 1790bd87be88Ssethg static void 1791bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1792bd87be88Ssethg { 1793bd87be88Ssethg uint8_t val8; 1794bd87be88Ssethg 1795bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1796bd87be88Ssethg /* 1797bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 1798bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 1799bd87be88Ssethg */ 1800bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 1801bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1802bd87be88Ssethg } 1803bd87be88Ssethg 1804bd87be88Ssethg static void 1805bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1806bd87be88Ssethg { 1807bd87be88Ssethg uint8_t val8; 1808bd87be88Ssethg 1809bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1810bd87be88Ssethg 1811bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 1812bd87be88Ssethg return; 1813bd87be88Ssethg 1814bd87be88Ssethg /* 1815bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 1816bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 1817bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 1818bd87be88Ssethg */ 1819bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 1820bd87be88Ssethg 1821bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1822bd87be88Ssethg 1823bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1824bd87be88Ssethg } 1825bd87be88Ssethg 1826c8711d4dSgs static void 1827c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1828c8711d4dSgs { 1829c8711d4dSgs uint16_t status; 1830c8711d4dSgs uint8_t header; 1831c8711d4dSgs uint8_t cap_ptr; 1832c8711d4dSgs uint8_t cap_id; 1833c8711d4dSgs uint16_t pmcsr; 1834c8711d4dSgs 1835c8711d4dSgs status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1836c8711d4dSgs if (!(status & PCI_STAT_CAP)) 1837c8711d4dSgs return; /* No capabilities list */ 1838c8711d4dSgs 1839c8711d4dSgs header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1840c8711d4dSgs if (header == PCI_HEADER_CARDBUS) 1841fb66942fSCasper H.S. Dik cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1842c8711d4dSgs else 1843c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1844c8711d4dSgs /* 1845c8711d4dSgs * Walk the capabilities list searching for a PM entry. 1846c8711d4dSgs */ 1847c8711d4dSgs while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1848c8711d4dSgs cap_ptr &= PCI_CAP_PTR_MASK; 1849c8711d4dSgs cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1850c8711d4dSgs if (cap_id == PCI_CAP_ID_PM) { 1851c8711d4dSgs pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1852c8711d4dSgs pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1853c8711d4dSgs pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1854c8711d4dSgs pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1855c8711d4dSgs break; 1856c8711d4dSgs } 1857c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1858c8711d4dSgs } 1859c8711d4dSgs 1860c8711d4dSgs } 1861c8711d4dSgs 186278323854SJudy Chen #define is_isa(bc, sc) \ 186378323854SJudy Chen (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 186478323854SJudy Chen 186505f867c3Sgs static void 1866bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 18677c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 18687c478bd9Sstevel@tonic-gate { 18697c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 18707c478bd9Sstevel@tonic-gate dev_info_t *dip; 1871c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 18727c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 187370025d76Sjohnny ushort_t slot_num; 18747c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 18758d483882Smlf int reprogram = 0, pciide = 0; 18767c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 187770025d76Sjohnny int pciex = 0; 187870025d76Sjohnny ushort_t is_pci_bridge = 0; 187905f867c3Sgs struct pci_devfunc *devlist = NULL, *entry = NULL; 18800db3240dSStephen Hanson boolean_t slot_valid; 188194f1124eSVikram Hegde gfx_entry_t *gfxp; 1882c0da6274SZhi-Jun Robin Fu pcie_req_id_t bdf; 18837c478bd9Sstevel@tonic-gate 18847c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 18857c478bd9Sstevel@tonic-gate 18867c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 18877c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 18887c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 18897c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 18907c478bd9Sstevel@tonic-gate break; 18917c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 18927c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 18937c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 189405f867c3Sgs /* Record the # of cardbus bridges found on the bus */ 189505f867c3Sgs if (config_op == CONFIG_INFO) 189605f867c3Sgs pci_bus_res[bus].num_cbb++; 18977c478bd9Sstevel@tonic-gate break; 18987c478bd9Sstevel@tonic-gate default: 18997c478bd9Sstevel@tonic-gate subvenid = 0; 19007c478bd9Sstevel@tonic-gate subdevid = 0; 19017c478bd9Sstevel@tonic-gate break; 19027c478bd9Sstevel@tonic-gate } 19037c478bd9Sstevel@tonic-gate 1904bd87be88Ssethg if (config_op == CONFIG_FIX) { 1905bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1906bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 1907bd87be88Ssethg } 190805f867c3Sgs return; 1909bd87be88Ssethg } 1910bd87be88Ssethg 19117c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 19127c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 19137c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 19147c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 19157c478bd9Sstevel@tonic-gate 19167c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 19177c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 19187c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1919c8589f13Ssethg progcl = classcode & 0xff; 19207c478bd9Sstevel@tonic-gate 19218d483882Smlf 19228d483882Smlf if (is_display(classcode)) 19237c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 192478323854SJudy Chen else if (!pseudo_isa && is_isa(basecl, subcl)) 192578323854SJudy Chen (void) snprintf(nodename, sizeof (nodename), "isa"); 19267c478bd9Sstevel@tonic-gate else if (subvenid != 0) 19277c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 19287c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 19297c478bd9Sstevel@tonic-gate else 19307c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 19317c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 19327c478bd9Sstevel@tonic-gate 19337c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 19348fc7923fSDana Myers if (pci_bus_res[bus].dip == NULL) 19357c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 19367c478bd9Sstevel@tonic-gate 19377c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 19387c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 19397c478bd9Sstevel@tonic-gate 19400db3240dSStephen Hanson if (check_if_device_is_pciex(dip, bus, dev, func, &slot_valid, 19410db3240dSStephen Hanson &slot_num, &is_pci_bridge) == B_TRUE) 194200d0963fSdilpreet pciex = 1; 194300d0963fSdilpreet 1944c0da6274SZhi-Jun Robin Fu bdf = PCI_GETBDF(bus, dev, func); 1945c0da6274SZhi-Jun Robin Fu /* 1946c0da6274SZhi-Jun Robin Fu * Record BAD AMD bridges which don't support MMIO config access. 1947c0da6274SZhi-Jun Robin Fu */ 1948c0da6274SZhi-Jun Robin Fu if (IS_BAD_AMD_NTBRIDGE(vendorid, deviceid) || 1949c0da6274SZhi-Jun Robin Fu IS_AMD_8132_CHIP(vendorid, deviceid)) { 1950c0da6274SZhi-Jun Robin Fu uchar_t secbus = 0; 1951c0da6274SZhi-Jun Robin Fu uchar_t subbus = 0; 1952c0da6274SZhi-Jun Robin Fu 1953c0da6274SZhi-Jun Robin Fu if ((basecl == PCI_CLASS_BRIDGE) && 1954c0da6274SZhi-Jun Robin Fu (subcl == PCI_BRIDGE_PCI)) { 1955c0da6274SZhi-Jun Robin Fu secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1956c0da6274SZhi-Jun Robin Fu subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1957c0da6274SZhi-Jun Robin Fu } 1958c0da6274SZhi-Jun Robin Fu pci_cfgacc_add_workaround(bdf, secbus, subbus); 1959c0da6274SZhi-Jun Robin Fu } 1960c0da6274SZhi-Jun Robin Fu 196151ac2e32SZhi-Jun Robin Fu /* 196299abc823SJoshua M. Clulow * Only populate bus_t if this device is sitting under a PCIE root 196399abc823SJoshua M. Clulow * complex. Some particular machines have both a PCIE root complex and 196499abc823SJoshua M. Clulow * a PCI hostbridge, in which case only devices under the PCIE root 196599abc823SJoshua M. Clulow * complex will have their bus_t populated. 196651ac2e32SZhi-Jun Robin Fu */ 196799abc823SJoshua M. Clulow if (pcie_get_rc_dip(dip) != NULL) { 1968c0da6274SZhi-Jun Robin Fu ck804_fix_aer_ptr(dip, bdf); 1969c0da6274SZhi-Jun Robin Fu (void) pcie_init_bus(dip, bdf, PCIE_BUS_INITIAL); 1970c0da6274SZhi-Jun Robin Fu } 1971c0da6274SZhi-Jun Robin Fu 19727c478bd9Sstevel@tonic-gate /* add properties */ 19737c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 19747c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 19757c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 19767c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19777c478bd9Sstevel@tonic-gate "class-code", classcode); 19787c478bd9Sstevel@tonic-gate if (func == 0) 19797c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 19807c478bd9Sstevel@tonic-gate else 19817c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 19827c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 19837c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 19847c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 19857c478bd9Sstevel@tonic-gate 1986ebf3afa8Sdmick /* add device_type for display nodes */ 1987ebf3afa8Sdmick if (is_display(classcode)) { 1988ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1989ebf3afa8Sdmick "device_type", "display"); 1990ebf3afa8Sdmick } 19917c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 19927c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 19937c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 19947c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 19957c478bd9Sstevel@tonic-gate 19967c478bd9Sstevel@tonic-gate if (subvenid != 0) { 19977c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19987c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 19997c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20007c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 20017c478bd9Sstevel@tonic-gate } 200270025d76Sjohnny if (!pciex) 200370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 200470025d76Sjohnny "min-grant", mingrant); 200570025d76Sjohnny if (!pciex) 200670025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 200770025d76Sjohnny "max-latency", maxlatency); 20087c478bd9Sstevel@tonic-gate } 20097c478bd9Sstevel@tonic-gate 20107c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 20117c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 20127c478bd9Sstevel@tonic-gate if (intr != 0) 20137c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20147c478bd9Sstevel@tonic-gate "interrupts", intr); 20157c478bd9Sstevel@tonic-gate 20167c478bd9Sstevel@tonic-gate /* 20177c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 20187c478bd9Sstevel@tonic-gate */ 20197c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 20207c478bd9Sstevel@tonic-gate 20217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20227c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 202370025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 20247c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 20257c478bd9Sstevel@tonic-gate "fast-back-to-back"); 202670025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 20277c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 20287c478bd9Sstevel@tonic-gate "66mhz-capable"); 20297c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 20307c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 20317c478bd9Sstevel@tonic-gate "udf-supported"); 20320db3240dSStephen Hanson if (pciex && slot_valid) { 203370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 203470025d76Sjohnny "physical-slot#", slot_num); 2035d57b3b3dSprasad if (!is_pci_bridge) 2036d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 2037d57b3b3dSprasad } 20387c478bd9Sstevel@tonic-gate 20397c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 20407c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 20417c478bd9Sstevel@tonic-gate 2042c8711d4dSgs /* Set the device PM state to D0 */ 2043c8711d4dSgs set_devpm_d0(bus, dev, func); 2044c8711d4dSgs 204570025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 204649fbdd30SErwin T Tsaur add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 204705f867c3Sgs else { 204805f867c3Sgs /* 204905f867c3Sgs * Record the non-PPB devices on the bus for possible 205005f867c3Sgs * reprogramming at 2nd bus enumeration. 205105f867c3Sgs * Note: PPB reprogramming is done in fix_ppb_res() 205205f867c3Sgs */ 205305f867c3Sgs devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 205405f867c3Sgs entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 205505f867c3Sgs entry->dip = dip; 205605f867c3Sgs entry->dev = dev; 205705f867c3Sgs entry->func = func; 205805f867c3Sgs entry->next = devlist; 205905f867c3Sgs pci_bus_res[bus].privdata = entry; 206005f867c3Sgs } 206170025d76Sjohnny 20627ff178cdSJimmy Vetayases if (IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 2063c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 2064c8589f13Ssethg } 2065c8589f13Ssethg 20667ff178cdSJimmy Vetayases /* check for NVIDIA CK8-04/MCP55 based LPC bridge */ 206770025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 20687ff178cdSJimmy Vetayases (func == 0)) { 20698a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 20707ff178cdSJimmy Vetayases /* each LPC bridge has an integrated IOAPIC */ 20717ff178cdSJimmy Vetayases apic_nvidia_io_max++; 20727ff178cdSJimmy Vetayases } 207370025d76Sjohnny 207470025d76Sjohnny if (pciex && is_pci_bridge) 207570025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 207670025d76Sjohnny (char *)"PCIe-PCI bridge"); 207770025d76Sjohnny else 207870025d76Sjohnny add_model_prop(dip, classcode); 20797c478bd9Sstevel@tonic-gate 20807c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 208170025d76Sjohnny revid, classcode, pciex); 20828d483882Smlf 20838d483882Smlf /* 20848d483882Smlf * See if this device is a controller that advertises 20858d483882Smlf * itself to be a standard ATA task file controller, or one that 20868d483882Smlf * has been hard coded. 20878d483882Smlf * 20888d483882Smlf * If it is, check if any other higher precedence driver listed in 20898d483882Smlf * driver_aliases will claim the node by calling 20908d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 20918d483882Smlf * create a pci-ide node or any other special handling. 20928d483882Smlf * 20938d483882Smlf * If another driver does not bind, set the node name to pci-ide 20948d483882Smlf * and then let the special pci-ide handling for registers and 20958d483882Smlf * child pci-ide nodes proceed below. 20968d483882Smlf */ 20978d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 20988d483882Smlf subvenid, subdevid) == 1) { 20998d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 21008d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 21018d483882Smlf pciide = 1; 21028d483882Smlf } 21038d483882Smlf } 21048d483882Smlf 21053a634bfcSVikram Hegde DEVI_SET_PCI(dip); 21067c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 21077c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 21087c478bd9Sstevel@tonic-gate 21097c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 21107c478bd9Sstevel@tonic-gate if (pciide) { 21117c478bd9Sstevel@tonic-gate dev_info_t *cdip; 21127c478bd9Sstevel@tonic-gate 21137c478bd9Sstevel@tonic-gate /* 21147c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 21157c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 21167c478bd9Sstevel@tonic-gate */ 21177c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 21187c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 21197c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 21207c478bd9Sstevel@tonic-gate "#address-cells", 1); 21217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 21227c478bd9Sstevel@tonic-gate "#size-cells", 0); 21237c478bd9Sstevel@tonic-gate 21247c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 21257c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2126fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 21277c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 21287c478bd9Sstevel@tonic-gate "reg", 0); 21297c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 21307c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2131fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 21327c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 21337c478bd9Sstevel@tonic-gate "reg", 1); 21347c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 21357c478bd9Sstevel@tonic-gate 21367c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 21377c478bd9Sstevel@tonic-gate } 21387c478bd9Sstevel@tonic-gate 21397e301000SVikram Hegde if (is_display(classcode)) { 214094f1124eSVikram Hegde gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 214194f1124eSVikram Hegde gfxp->g_dip = dip; 214294f1124eSVikram Hegde gfxp->g_prev = NULL; 214394f1124eSVikram Hegde gfxp->g_next = gfx_devinfo_list; 214494f1124eSVikram Hegde gfx_devinfo_list = gfxp; 214594f1124eSVikram Hegde if (gfxp->g_next) 214694f1124eSVikram Hegde gfxp->g_next->g_prev = gfxp; 214794f1124eSVikram Hegde } 214894f1124eSVikram Hegde 214978323854SJudy Chen /* special handling for isa */ 215078323854SJudy Chen if (!pseudo_isa && is_isa(basecl, subcl)) { 215178323854SJudy Chen /* add device_type */ 215278323854SJudy Chen (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 215378323854SJudy Chen "device_type", "isa"); 215478323854SJudy Chen } 215578323854SJudy Chen 215605f867c3Sgs if (reprogram && (entry != NULL)) 215705f867c3Sgs entry->reprogram = B_TRUE; 21587e301000SVikram Hegde 21597c478bd9Sstevel@tonic-gate } 21607c478bd9Sstevel@tonic-gate 2161c2de8625SScott Carter, SD IOSW /* 2162c2de8625SScott Carter, SD IOSW * Some vendors do not use unique subsystem IDs in their products, which 2163c2de8625SScott Carter, SD IOSW * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2164c2de8625SScott Carter, SD IOSW * Allow for these compatible forms to be excluded on a per-device basis. 2165c2de8625SScott Carter, SD IOSW */ 2166c2de8625SScott Carter, SD IOSW /*ARGSUSED*/ 2167c2de8625SScott Carter, SD IOSW static boolean_t 2168c2de8625SScott Carter, SD IOSW subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2169c2de8625SScott Carter, SD IOSW ushort_t subdevid, uchar_t revid, uint_t classcode) 2170c2de8625SScott Carter, SD IOSW { 2171c2de8625SScott Carter, SD IOSW /* Nvidia display adapters */ 2172c2de8625SScott Carter, SD IOSW if ((venid == 0x10de) && (is_display(classcode))) 2173c2de8625SScott Carter, SD IOSW return (B_TRUE); 2174c2de8625SScott Carter, SD IOSW 2175*bfa93d39SRobert Mustacchi /* 2176*bfa93d39SRobert Mustacchi * 8086,166 is the Ivy Bridge built-in graphics controller on some 2177*bfa93d39SRobert Mustacchi * models. Unfortunately 8086,2044 is the Skylake Server processor 2178*bfa93d39SRobert Mustacchi * memory channel device. The Ivy Bridge device uses the Skylake 2179*bfa93d39SRobert Mustacchi * ID as its sub-device ID. The GPU is not a memory controller DIMM 2180*bfa93d39SRobert Mustacchi * channel. 2181*bfa93d39SRobert Mustacchi */ 2182*bfa93d39SRobert Mustacchi if (venid == 0x8086 && devid == 0x166 && subvenid == 0x8086 && 2183*bfa93d39SRobert Mustacchi subdevid == 0x2044) { 2184*bfa93d39SRobert Mustacchi return (B_TRUE); 2185*bfa93d39SRobert Mustacchi } 2186*bfa93d39SRobert Mustacchi 2187c2de8625SScott Carter, SD IOSW return (B_FALSE); 2188c2de8625SScott Carter, SD IOSW } 2189c2de8625SScott Carter, SD IOSW 21907c478bd9Sstevel@tonic-gate /* 2191*bfa93d39SRobert Mustacchi * Set the compatible property to a value compliant with rev 2.1 of the IEEE1275 2192*bfa93d39SRobert Mustacchi * PCI binding. This is also used for PCI express devices and we have our own 2193*bfa93d39SRobert Mustacchi * minor additions. 21947c478bd9Sstevel@tonic-gate * 21957c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 21967c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 2197*bfa93d39SRobert Mustacchi * pciSSSS,ssss,s (2+) 21987c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 21997c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 2200*bfa93d39SRobert Mustacchi * pciVVVV,DDDD,p (4+) 22017c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 22027c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 22037c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 22047c478bd9Sstevel@tonic-gate * 2205*bfa93d39SRobert Mustacchi * The Subsystem (SSSS) forms are not inserted if subsystem-vendor-id is 0 or if 2206*bfa93d39SRobert Mustacchi * it is a case where we know that the IDs overlap. 2207*bfa93d39SRobert Mustacchi * 2208*bfa93d39SRobert Mustacchi * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above and 2209*bfa93d39SRobert Mustacchi * property 2 is not created as per "1275 bindings for PCI Express 2210*bfa93d39SRobert Mustacchi * Interconnect". 22117c478bd9Sstevel@tonic-gate * 2212*bfa93d39SRobert Mustacchi * Unlike on SPARC, we generate both the "pciex" and "pci" versions of the 2213*bfa93d39SRobert Mustacchi * above. The problem with property 2 is that it has an ambiguity with 2214*bfa93d39SRobert Mustacchi * property 4. To make sure that drivers can specify either form of 2 or 4 2215*bfa93d39SRobert Mustacchi * without ambiguity we add a suffix. The 'p' suffix represents the primary ID, 2216*bfa93d39SRobert Mustacchi * meaning that it is guaranteed to be form 4. The 's' suffix means that it is 2217*bfa93d39SRobert Mustacchi * sub-vendor and sub-device form, meaning it is guaranteed to be form 2. 221870025d76Sjohnny * 2219*bfa93d39SRobert Mustacchi * Set with setprop and \x00 between each to generate the encoded string array 2220*bfa93d39SRobert Mustacchi * form. 22217c478bd9Sstevel@tonic-gate */ 22227c478bd9Sstevel@tonic-gate void 22237c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 222470025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 222570025d76Sjohnny int pciex) 22267c478bd9Sstevel@tonic-gate { 222770025d76Sjohnny int i = 0; 222870025d76Sjohnny int size = COMPAT_BUFSIZE; 2229*bfa93d39SRobert Mustacchi char *compat[15]; 22307c478bd9Sstevel@tonic-gate char *buf, *curr; 22317c478bd9Sstevel@tonic-gate 22327c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 22337c478bd9Sstevel@tonic-gate 223470025d76Sjohnny if (pciex) { 223570025d76Sjohnny if (subvenid) { 223670025d76Sjohnny compat[i++] = curr; /* form 0 */ 223770025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 223870025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 223970025d76Sjohnny size -= strlen(curr) + 1; 224070025d76Sjohnny curr += strlen(curr) + 1; 224170025d76Sjohnny 224270025d76Sjohnny compat[i++] = curr; /* form 1 */ 224370025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 224470025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 224570025d76Sjohnny size -= strlen(curr) + 1; 224670025d76Sjohnny curr += strlen(curr) + 1; 224770025d76Sjohnny 224870025d76Sjohnny } 224970025d76Sjohnny compat[i++] = curr; /* form 3 */ 225070025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 225170025d76Sjohnny vendorid, deviceid, revid); 225270025d76Sjohnny size -= strlen(curr) + 1; 225370025d76Sjohnny curr += strlen(curr) + 1; 225470025d76Sjohnny 225570025d76Sjohnny compat[i++] = curr; /* form 4 */ 225670025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 225770025d76Sjohnny size -= strlen(curr) + 1; 225870025d76Sjohnny curr += strlen(curr) + 1; 225970025d76Sjohnny 226070025d76Sjohnny compat[i++] = curr; /* form 5 */ 226170025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 226270025d76Sjohnny size -= strlen(curr) + 1; 226370025d76Sjohnny curr += strlen(curr) + 1; 226470025d76Sjohnny 226570025d76Sjohnny compat[i++] = curr; /* form 6 */ 226670025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 226770025d76Sjohnny (classcode >> 8)); 226870025d76Sjohnny size -= strlen(curr) + 1; 226970025d76Sjohnny curr += strlen(curr) + 1; 227070025d76Sjohnny } 227170025d76Sjohnny 22727c478bd9Sstevel@tonic-gate if (subvenid) { 22737c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 22747c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 22757c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 22767c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22777c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22787c478bd9Sstevel@tonic-gate 22797c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 22807c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 22817c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 22827c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22837c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22847c478bd9Sstevel@tonic-gate 2285c2de8625SScott Carter, SD IOSW if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2286c2de8625SScott Carter, SD IOSW subdevid, revid, classcode) == B_FALSE) { 2287*bfa93d39SRobert Mustacchi compat[i++] = curr; /* form 2+ */ 2288*bfa93d39SRobert Mustacchi (void) snprintf(curr, size, "pci%x,%x,s", subvenid, 2289*bfa93d39SRobert Mustacchi subdevid); 2290*bfa93d39SRobert Mustacchi size -= strlen(curr) + 1; 2291*bfa93d39SRobert Mustacchi curr += strlen(curr) + 1; 2292*bfa93d39SRobert Mustacchi 2293c2de8625SScott Carter, SD IOSW compat[i++] = curr; /* form 2 */ 2294c2de8625SScott Carter, SD IOSW (void) snprintf(curr, size, "pci%x,%x", subvenid, 2295c2de8625SScott Carter, SD IOSW subdevid); 2296c2de8625SScott Carter, SD IOSW size -= strlen(curr) + 1; 2297c2de8625SScott Carter, SD IOSW curr += strlen(curr) + 1; 2298c2de8625SScott Carter, SD IOSW } 22997c478bd9Sstevel@tonic-gate } 23007c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 23017c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 23027c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 23037c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 23047c478bd9Sstevel@tonic-gate 2305*bfa93d39SRobert Mustacchi compat[i++] = curr; /* form 4+ */ 2306*bfa93d39SRobert Mustacchi (void) snprintf(curr, size, "pci%x,%x,p", vendorid, deviceid); 2307*bfa93d39SRobert Mustacchi size -= strlen(curr) + 1; 2308*bfa93d39SRobert Mustacchi curr += strlen(curr) + 1; 2309*bfa93d39SRobert Mustacchi 23107c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 23117c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 23127c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 23137c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 23147c478bd9Sstevel@tonic-gate 23157c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 23167c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 23177c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 23187c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 23197c478bd9Sstevel@tonic-gate 23207c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 23217c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 232270025d76Sjohnny size -= strlen(curr) + 1; 232370025d76Sjohnny curr += strlen(curr) + 1; 23247c478bd9Sstevel@tonic-gate 23257c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 23267c478bd9Sstevel@tonic-gate "compatible", compat, i); 23277c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 23287c478bd9Sstevel@tonic-gate } 23297c478bd9Sstevel@tonic-gate 23307c478bd9Sstevel@tonic-gate /* 23317c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 23327c478bd9Sstevel@tonic-gate * 23337c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 23347c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 23357c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 23367c478bd9Sstevel@tonic-gate * mode BAR or not. 23377c478bd9Sstevel@tonic-gate */ 23387c478bd9Sstevel@tonic-gate /* 23397c478bd9Sstevel@tonic-gate * config info for pci-ide devices 23407c478bd9Sstevel@tonic-gate */ 23417c478bd9Sstevel@tonic-gate static struct { 23427c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 23437c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 23447c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 23457c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 23467c478bd9Sstevel@tonic-gate } pciide_bar[] = { 23477c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 23487c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 23497c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 23507c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 23517c478bd9Sstevel@tonic-gate }; 23527c478bd9Sstevel@tonic-gate 23537c478bd9Sstevel@tonic-gate static int 23547c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 23557c478bd9Sstevel@tonic-gate { 23567c478bd9Sstevel@tonic-gate int hard_decode = 0; 23577c478bd9Sstevel@tonic-gate 23587c478bd9Sstevel@tonic-gate /* 23597c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 23607c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 23617c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 23627c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 23637c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 23647c478bd9Sstevel@tonic-gate */ 23657c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 23667c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 23677c478bd9Sstevel@tonic-gate 23687c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 23697c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 23707c478bd9Sstevel@tonic-gate } else { 23717c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 23727c478bd9Sstevel@tonic-gate hard_decode = 1; 23737c478bd9Sstevel@tonic-gate } 23747c478bd9Sstevel@tonic-gate } 23757c478bd9Sstevel@tonic-gate 23767c478bd9Sstevel@tonic-gate /* 23777c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 23787c478bd9Sstevel@tonic-gate */ 23797c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 23807c478bd9Sstevel@tonic-gate *basep = 0; 23817c478bd9Sstevel@tonic-gate *lenp = 0; 23827c478bd9Sstevel@tonic-gate hard_decode = 0; 23837c478bd9Sstevel@tonic-gate } 23847c478bd9Sstevel@tonic-gate 23857c478bd9Sstevel@tonic-gate return (hard_decode); 23867c478bd9Sstevel@tonic-gate } 23877c478bd9Sstevel@tonic-gate 23887c478bd9Sstevel@tonic-gate 23897c478bd9Sstevel@tonic-gate /* 23907c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 23917c478bd9Sstevel@tonic-gate */ 23927c478bd9Sstevel@tonic-gate static int 23937c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 23947c478bd9Sstevel@tonic-gate int config_op, int pciide) 23957c478bd9Sstevel@tonic-gate { 23967c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 23977c478bd9Sstevel@tonic-gate ushort_t bar_sz; 2398b5cf5bc2SHans Rosenfeld uint64_t value = 0; 2399b5cf5bc2SHans Rosenfeld uint_t devloc; 24007c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 24017c478bd9Sstevel@tonic-gate ushort_t offset, end; 24027c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 24037c478bd9Sstevel@tonic-gate uint_t phys_hi; 24042f283da5SDan Mick struct memlist **io_avail, **io_used; 24052f283da5SDan Mick struct memlist **mem_avail, **mem_used; 24062f283da5SDan Mick struct memlist **pmem_avail, **pmem_used; 240705f867c3Sgs uchar_t res_bus; 24087c478bd9Sstevel@tonic-gate 24097c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 24107c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 2411c8711d4dSgs int nreg, nasgn; 24127c478bd9Sstevel@tonic-gate 24132f283da5SDan Mick io_avail = &pci_bus_res[bus].io_avail; 24142f283da5SDan Mick io_used = &pci_bus_res[bus].io_used; 24152f283da5SDan Mick mem_avail = &pci_bus_res[bus].mem_avail; 24162f283da5SDan Mick mem_used = &pci_bus_res[bus].mem_used; 24172f283da5SDan Mick pmem_avail = &pci_bus_res[bus].pmem_avail; 24182f283da5SDan Mick pmem_used = &pci_bus_res[bus].pmem_used; 24197c478bd9Sstevel@tonic-gate 24207c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 24217c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 24227c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 24237c478bd9Sstevel@tonic-gate nasgn = 0; 24247c478bd9Sstevel@tonic-gate 24257c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 24267c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 24277c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 24287c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 24297c478bd9Sstevel@tonic-gate 24307c478bd9Sstevel@tonic-gate switch (header) { 24317c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 24327c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 24337c478bd9Sstevel@tonic-gate break; 24347c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 24357c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 24367c478bd9Sstevel@tonic-gate break; 24377c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 24387c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 2439ffa17327SGuoli Shu reprogram = 1; 24407c478bd9Sstevel@tonic-gate break; 24417c478bd9Sstevel@tonic-gate default: 24427c478bd9Sstevel@tonic-gate max_basereg = 0; 24437c478bd9Sstevel@tonic-gate break; 24447c478bd9Sstevel@tonic-gate } 24457c478bd9Sstevel@tonic-gate 24467c478bd9Sstevel@tonic-gate /* 24477c478bd9Sstevel@tonic-gate * Create the register property by saving the current 24488d34f104Smyers * value of the base register. Write 0xffffffff to the 24498d34f104Smyers * base register. Read the value back to determine the 24508d34f104Smyers * required size of the address space. Restore the base 24518d34f104Smyers * register contents. 24528d34f104Smyers * 2453ab290850SDana Myers * Do not disable I/O and memory access for bridges; this 2454ab290850SDana Myers * has the side-effect of making the bridge transparent to 2455ab290850SDana Myers * secondary-bus activity (see sections 4.1-4.3 of the 2456ab290850SDana Myers * PCI-PCI Bridge Spec V1.2). For non-bridges, disable 2457ab290850SDana Myers * I/O and memory access to avoid difficulty with USB 2458ab290850SDana Myers * emulation (see OHCI spec1.0a appendix B 2459ab290850SDana Myers * "Host Controller Mapping") 24607c478bd9Sstevel@tonic-gate */ 24617c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 24627c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 24637c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 2464ab290850SDana Myers uint_t command; 2465ab290850SDana Myers 24667c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 24677c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 2468ab290850SDana Myers if (baseclass != PCI_CLASS_BRIDGE) { 2469ab290850SDana Myers command = (uint_t)pci_getw(bus, dev, func, 2470ab290850SDana Myers PCI_CONF_COMM); 2471ab290850SDana Myers pci_putw(bus, dev, func, PCI_CONF_COMM, 2472ab290850SDana Myers command & ~(PCI_COMM_MAE | PCI_COMM_IO)); 2473ab290850SDana Myers } 24747c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 24757c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 24767c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 2477ab290850SDana Myers if (baseclass != PCI_CLASS_BRIDGE) 2478ab290850SDana Myers pci_putw(bus, dev, func, PCI_CONF_COMM, command); 24797c478bd9Sstevel@tonic-gate 24807c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 24817c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 24823e98767bSMax zhen int hard_decode = 0; 2483b5cf5bc2SHans Rosenfeld uint_t len; 24843e98767bSMax zhen 24857c478bd9Sstevel@tonic-gate /* i/o space */ 24867c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 24877c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 24887c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 24897c478bd9Sstevel@tonic-gate 24907c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 24917c478bd9Sstevel@tonic-gate if (pciide) { 2492f088817aSyt if (subclass != PCI_MASS_IDE) 24937c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 24947c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 24957c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 24967c478bd9Sstevel@tonic-gate &base, &len); 24977c478bd9Sstevel@tonic-gate } else if (value == 0) { 24987c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 24997c478bd9Sstevel@tonic-gate continue; 25007c478bd9Sstevel@tonic-gate } 25017c478bd9Sstevel@tonic-gate 25023e98767bSMax zhen regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 25033e98767bSMax zhen (hard_decode ? PCI_RELOCAT_B : offset); 25043e98767bSMax zhen regs[nreg].pci_phys_low = hard_decode ? 25053e98767bSMax zhen base & PCI_BASE_IO_ADDR_M : 0; 25063e98767bSMax zhen assigned[nasgn].pci_phys_hi = 25073e98767bSMax zhen PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 25087c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 25097c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 25107c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 25117c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 251205f867c3Sgs /* 251305f867c3Sgs * A device under a subtractive PPB can allocate 251405f867c3Sgs * resources from its parent bus if there is no resource 251505f867c3Sgs * available on its own bus. 251605f867c3Sgs */ 25172f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 251805f867c3Sgs res_bus = bus; 251905f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 252005f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 252105f867c3Sgs if (res_bus == (uchar_t)-1) 252205f867c3Sgs break; /* root bus already */ 25232f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 25242f283da5SDan Mick io_avail = &pci_bus_res 25252f283da5SDan Mick [res_bus].io_avail; 252605f867c3Sgs break; 252705f867c3Sgs } 252805f867c3Sgs } 252905f867c3Sgs } 25307c478bd9Sstevel@tonic-gate 25317c478bd9Sstevel@tonic-gate /* 25327c478bd9Sstevel@tonic-gate * first pass - gather what's there 25337c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 25347c478bd9Sstevel@tonic-gate * config - allocate regions 25357c478bd9Sstevel@tonic-gate */ 25367c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 25377c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 253805f867c3Sgs if (base != 0) { 25392f283da5SDan Mick (void) memlist_remove(io_avail, base, 25408fc7923fSDana Myers len); 25412f283da5SDan Mick memlist_insert(io_used, base, len); 2542ffa17327SGuoli Shu } else { 25437c478bd9Sstevel@tonic-gate reprogram = 1; 2544ffa17327SGuoli Shu } 2545ffa17327SGuoli Shu pci_bus_res[bus].io_size += len; 25462f283da5SDan Mick } else if ((*io_avail && base == 0) || 254705f867c3Sgs pci_bus_res[bus].io_reprogram) { 25482f283da5SDan Mick base = (uint_t)memlist_find(io_avail, len, len); 25497c478bd9Sstevel@tonic-gate if (base != 0) { 25502f283da5SDan Mick memlist_insert(io_used, base, len); 25517c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 25527c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 25537c478bd9Sstevel@tonic-gate base | type); 25547c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 25557c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 25567c478bd9Sstevel@tonic-gate } 25577c478bd9Sstevel@tonic-gate if (base == 0) { 25587c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 2559db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 2560db063408Sdmick " length 0x%x", 2561ebf3afa8Sdmick bus, dev, func, offset, len); 2562c8711d4dSgs } 25637c478bd9Sstevel@tonic-gate } 25647c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 25657c478bd9Sstevel@tonic-gate nreg++, nasgn++; 25667c478bd9Sstevel@tonic-gate 25677c478bd9Sstevel@tonic-gate } else { 2568b5cf5bc2SHans Rosenfeld uint64_t len; 25697c478bd9Sstevel@tonic-gate /* memory space */ 25707c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 25717c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 25727c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 2573b5cf5bc2SHans Rosenfeld pci_putl(bus, dev, func, offset + 4, 2574b5cf5bc2SHans Rosenfeld 0xffffffff); 2575b5cf5bc2SHans Rosenfeld value |= (uint64_t)pci_getl(bus, dev, func, 2576b5cf5bc2SHans Rosenfeld offset + 4) << 32; 2577b5cf5bc2SHans Rosenfeld pci_putl(bus, dev, func, offset + 4, base_hi); 25787c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 2579b5cf5bc2SHans Rosenfeld value &= PCI_BASE_M_ADDR64_M; 25807c478bd9Sstevel@tonic-gate } else { 25817c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 25827c478bd9Sstevel@tonic-gate base_hi = 0; 25837c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 2584b5cf5bc2SHans Rosenfeld value &= PCI_BASE_M_ADDR_M; 25857c478bd9Sstevel@tonic-gate } 25867c478bd9Sstevel@tonic-gate 25877c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 25888fc7923fSDana Myers if (value == 0) 25897c478bd9Sstevel@tonic-gate continue; 25908fc7923fSDana Myers 25917c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 25927c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 2593b5cf5bc2SHans Rosenfeld assigned[nasgn].pci_size_low = len & 0xffffffff; 2594b5cf5bc2SHans Rosenfeld regs[nreg].pci_size_hi = 2595b5cf5bc2SHans Rosenfeld assigned[nasgn].pci_size_hi = len >> 32; 25967c478bd9Sstevel@tonic-gate 25977c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 25988fc7923fSDana Myers if (base & PCI_BASE_PREF_M) 25997c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 26008fc7923fSDana Myers 260105f867c3Sgs /* 260205f867c3Sgs * A device under a subtractive PPB can allocate 260305f867c3Sgs * resources from its parent bus if there is no resource 260405f867c3Sgs * available on its own bus. 260505f867c3Sgs */ 26062f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 260705f867c3Sgs res_bus = bus; 260805f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 260905f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 261005f867c3Sgs if (res_bus == (uchar_t)-1) 261105f867c3Sgs break; /* root bus already */ 26122f283da5SDan Mick mem_avail = 26132f283da5SDan Mick &pci_bus_res[res_bus].mem_avail; 26142f283da5SDan Mick pmem_avail = 26152f283da5SDan Mick &pci_bus_res [res_bus].pmem_avail; 26168fc7923fSDana Myers /* 26178fc7923fSDana Myers * Break out as long as at least 26182f283da5SDan Mick * mem_avail is available 26198fc7923fSDana Myers */ 26202f283da5SDan Mick if ((*pmem_avail && 26218fc7923fSDana Myers (phys_hi & PCI_PREFETCH_B)) || 26222f283da5SDan Mick *mem_avail) 262305f867c3Sgs break; 262405f867c3Sgs } 262505f867c3Sgs } 262605f867c3Sgs 26277c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 26287c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 26297c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 26307c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 26317c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 26327c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 26337c478bd9Sstevel@tonic-gate 26347c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 26357c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 263632b17656SToomas Soome if (base != 0) { 26378fc7923fSDana Myers /* remove from PMEM and MEM space */ 26382f283da5SDan Mick (void) memlist_remove(mem_avail, 26398fc7923fSDana Myers base, len); 26402f283da5SDan Mick (void) memlist_remove(pmem_avail, 26418fc7923fSDana Myers base, len); 26428fc7923fSDana Myers /* only note as used in correct map */ 26438fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) 26442f283da5SDan Mick memlist_insert(pmem_used, 264505f867c3Sgs base, len); 26468fc7923fSDana Myers else 26472f283da5SDan Mick memlist_insert(mem_used, 264886ce93f0SGuoli Shu base, len); 2649ffa17327SGuoli Shu } else { 26507c478bd9Sstevel@tonic-gate reprogram = 1; 2651ffa17327SGuoli Shu } 2652ffa17327SGuoli Shu pci_bus_res[bus].mem_size += len; 265332b17656SToomas Soome } else if ((*mem_avail && base == 0) || 265405f867c3Sgs pci_bus_res[bus].mem_reprogram) { 26558fc7923fSDana Myers /* 26568fc7923fSDana Myers * When desired, attempt a prefetchable 26578fc7923fSDana Myers * allocation first 26588fc7923fSDana Myers */ 26598fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) { 26602f283da5SDan Mick base = (uint_t)memlist_find(pmem_avail, 26618fc7923fSDana Myers len, len); 266232b17656SToomas Soome if (base != 0) { 26632f283da5SDan Mick memlist_insert(pmem_used, 26648fc7923fSDana Myers base, len); 26652f283da5SDan Mick (void) memlist_remove(mem_avail, 266686ce93f0SGuoli Shu base, len); 26678fc7923fSDana Myers } 26688fc7923fSDana Myers } 26698fc7923fSDana Myers /* 26708fc7923fSDana Myers * If prefetchable allocation was not 26718fc7923fSDana Myers * desired, or failed, attempt ordinary 26728fc7923fSDana Myers * memory allocation 26738fc7923fSDana Myers */ 267432b17656SToomas Soome if (base == 0) { 26752f283da5SDan Mick base = (uint_t)memlist_find(mem_avail, 26768fc7923fSDana Myers len, len); 267732b17656SToomas Soome if (base != 0) { 26782f283da5SDan Mick memlist_insert(mem_used, 267986ce93f0SGuoli Shu base, len); 26802f283da5SDan Mick (void) memlist_remove( 26812f283da5SDan Mick pmem_avail, base, len); 268286ce93f0SGuoli Shu } 26838fc7923fSDana Myers } 268432b17656SToomas Soome if (base != 0) { 26857c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 26867c478bd9Sstevel@tonic-gate base | type); 26877c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 26887c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 26898fc7923fSDana Myers } else 26907c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 2691ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 2692b5cf5bc2SHans Rosenfeld " length 0x%"PRIx64, 2693ebf3afa8Sdmick bus, dev, func, offset, len); 26947c478bd9Sstevel@tonic-gate } 26957c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 26967c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26977c478bd9Sstevel@tonic-gate } 26987c478bd9Sstevel@tonic-gate } 26997c478bd9Sstevel@tonic-gate switch (header) { 27007c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 27017c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 27027c478bd9Sstevel@tonic-gate break; 27037c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 27047c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 27057c478bd9Sstevel@tonic-gate break; 27067c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 27077c478bd9Sstevel@tonic-gate goto done; 27087c478bd9Sstevel@tonic-gate } 27097c478bd9Sstevel@tonic-gate 27107c478bd9Sstevel@tonic-gate /* 27117c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 27127c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 27137c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 27147c478bd9Sstevel@tonic-gate */ 27157c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 27167c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 27177c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 27187c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 271970025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 272070025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 272170025d76Sjohnny else 272270025d76Sjohnny value = 0; 27237c478bd9Sstevel@tonic-gate 27247c478bd9Sstevel@tonic-gate if (value != 0) { 2725b5cf5bc2SHans Rosenfeld uint_t len; 2726b5cf5bc2SHans Rosenfeld 27277c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 27287c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 27297c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 27307c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 27317c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 27327c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 27337c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 27347c478bd9Sstevel@tonic-gate nreg++, nasgn++; 273599ed6083Sszhou /* take it out of the memory resource */ 273632b17656SToomas Soome if (base != 0) { 27372f283da5SDan Mick (void) memlist_remove(mem_avail, base, len); 27382f283da5SDan Mick memlist_insert(mem_used, base, len); 27392f283da5SDan Mick pci_bus_res[bus].mem_size += len; 27408fc7923fSDana Myers } 27417c478bd9Sstevel@tonic-gate } 27427c478bd9Sstevel@tonic-gate 27437c478bd9Sstevel@tonic-gate /* 27448fc7923fSDana Myers * Account for "legacy" (alias) video adapter resources 27457c478bd9Sstevel@tonic-gate */ 27467c478bd9Sstevel@tonic-gate 27477c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 27487c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 27497c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 27507c478bd9Sstevel@tonic-gate 27517c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 27527c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 27537c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 27547c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 27557c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 27567c478bd9Sstevel@tonic-gate nreg++, nasgn++; 27572f283da5SDan Mick (void) memlist_remove(io_avail, 0x3b0, 0xc); 27582f283da5SDan Mick memlist_insert(io_used, 0x3b0, 0xc); 27592f283da5SDan Mick pci_bus_res[bus].io_size += 0xc; 27607c478bd9Sstevel@tonic-gate 27617c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 27627c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 27637c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 27647c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 27657c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 27667c478bd9Sstevel@tonic-gate nreg++, nasgn++; 27672f283da5SDan Mick (void) memlist_remove(io_avail, 0x3c0, 0x20); 27682f283da5SDan Mick memlist_insert(io_used, 0x3c0, 0x20); 27692f283da5SDan Mick pci_bus_res[bus].io_size += 0x20; 27707c478bd9Sstevel@tonic-gate 27717c478bd9Sstevel@tonic-gate /* Video memory */ 27727c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 27733e98767bSMax zhen (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 27747c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 27757c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 27767c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 27777c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 27787c478bd9Sstevel@tonic-gate nreg++, nasgn++; 27798fc7923fSDana Myers /* remove from MEM and PMEM space */ 27802f283da5SDan Mick (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 27812f283da5SDan Mick (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 27822f283da5SDan Mick memlist_insert(mem_used, 0xa0000, 0x20000); 27832f283da5SDan Mick pci_bus_res[bus].mem_size += 0x20000; 27847c478bd9Sstevel@tonic-gate } 27857c478bd9Sstevel@tonic-gate 27867c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 27877c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 27889896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 27899896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 27907c478bd9Sstevel@tonic-gate 27917c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 27927c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 27937c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 27947c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 27957c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 27967c478bd9Sstevel@tonic-gate nreg++, nasgn++; 27972f283da5SDan Mick (void) memlist_remove(io_avail, 0x2e8, 0x1); 27982f283da5SDan Mick memlist_insert(io_used, 0x2e8, 0x1); 27992f283da5SDan Mick pci_bus_res[bus].io_size += 0x1; 28007c478bd9Sstevel@tonic-gate 28017c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 28027c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 28037c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 28047c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 28057c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 28067c478bd9Sstevel@tonic-gate nreg++, nasgn++; 28072f283da5SDan Mick (void) memlist_remove(io_avail, 0x2ea, 0x6); 28082f283da5SDan Mick memlist_insert(io_used, 0x2ea, 0x6); 28092f283da5SDan Mick pci_bus_res[bus].io_size += 0x6; 28107c478bd9Sstevel@tonic-gate } 28117c478bd9Sstevel@tonic-gate 28127c478bd9Sstevel@tonic-gate done: 28137c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 28147c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 28157c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 28167c478bd9Sstevel@tonic-gate "assigned-addresses", 28177c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2818c8711d4dSgs 28197c478bd9Sstevel@tonic-gate return (reprogram); 28207c478bd9Sstevel@tonic-gate } 28217c478bd9Sstevel@tonic-gate 28227c478bd9Sstevel@tonic-gate static void 282370025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 282449fbdd30SErwin T Tsaur int pciex, ushort_t is_pci_bridge) 28257c478bd9Sstevel@tonic-gate { 282670025d76Sjohnny char *dev_type; 28277c478bd9Sstevel@tonic-gate int i; 28281f0c5e61SRobert Mustacchi uint_t val; 28291f0c5e61SRobert Mustacchi uint64_t io_range[2], mem_range[2], pmem_range[2]; 28307c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 28317c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 283205f867c3Sgs uchar_t progclass; 283305f867c3Sgs 2834f55ce205Sszhou ASSERT(secbus <= subbus); 28357c478bd9Sstevel@tonic-gate 283605f867c3Sgs /* 283705f867c3Sgs * Check if it's a subtractive PPB. 283805f867c3Sgs */ 283905f867c3Sgs progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 284005f867c3Sgs if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 284105f867c3Sgs pci_bus_res[secbus].subtractive = B_TRUE; 284205f867c3Sgs 2843f55ce205Sszhou /* 2844f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 2845f55ce205Sszhou * such mistakes here 2846f55ce205Sszhou */ 284747310cedSDana Myers if (subbus > pci_bios_maxbus) { 284847310cedSDana Myers pci_bios_maxbus = subbus; 2849f55ce205Sszhou alloc_res_array(); 2850f55ce205Sszhou } 2851f55ce205Sszhou 2852f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 28537c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 28547c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 28557c478bd9Sstevel@tonic-gate 285649fbdd30SErwin T Tsaur dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 285770025d76Sjohnny 28587c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 28597c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 286053273e82Ssethg /* 286153273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 286253273e82Ssethg * for peer busses because there is no other way of determining its 286353273e82Ssethg * subordinate bus number). 286453273e82Ssethg */ 28657c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 28667c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 286753273e82Ssethg /* 286853273e82Ssethg * Loop through subordinate busses, initializing their parent bus 286953273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 287053273e82Ssethg * fields may very well be further refined later, as child bridges 287153273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 287253273e82Ssethg * are not peer busses by changing their par_bus fields to anything 287353273e82Ssethg * other than -1.) 287453273e82Ssethg */ 28757c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 28767c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 28777c478bd9Sstevel@tonic-gate 28787c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 287970025d76Sjohnny "device_type", dev_type); 28807c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 28817c478bd9Sstevel@tonic-gate "#address-cells", 3); 28827c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 28837c478bd9Sstevel@tonic-gate "#size-cells", 2); 28847c478bd9Sstevel@tonic-gate 28857c478bd9Sstevel@tonic-gate /* 28862f283da5SDan Mick * Collect bridge window specifications, and use them to populate 28872f283da5SDan Mick * the "avail" resources for the bus. Not all of those resources will 28882f283da5SDan Mick * end up being available; this is done top-down, and so the initial 28892f283da5SDan Mick * collection of windows populates the 'ranges' property for the 28902f283da5SDan Mick * bus node. Later, as children are found, resources are removed from 28912f283da5SDan Mick * the 'avail' list, so that it becomes the freelist for 28922f283da5SDan Mick * this point in the tree. ranges may be set again after bridge 28932f283da5SDan Mick * reprogramming in fix_ppb_res(), in which case it's set from 28942f283da5SDan Mick * used + avail. 28952f283da5SDan Mick * 28967c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 28977c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 28987c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 28997c478bd9Sstevel@tonic-gate * prefetchable memory. 29007c478bd9Sstevel@tonic-gate */ 29019896aa55Sjveta 29029896aa55Sjveta /* 29039896aa55Sjveta * io range 290405f867c3Sgs * We determine i/o windows that are left unconfigured by BIOS 29059896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 29069896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 29079896aa55Sjveta * later passes by setting the base > limit 29089896aa55Sjveta */ 29099896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 29109896aa55Sjveta if (val & PCI_COMM_IO) { 29119896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 29121f0c5e61SRobert Mustacchi io_range[0] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT); 29139896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 29141f0c5e61SRobert Mustacchi io_range[1] = ((val & PCI_BCNF_IO_MASK) << PCI_BCNF_IO_SHIFT) | 29151f0c5e61SRobert Mustacchi 0xfff; 29161f0c5e61SRobert Mustacchi if ((io_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_IO_32BIT) { 29171f0c5e61SRobert Mustacchi uint16_t io_base_hi, io_limit_hi; 29181f0c5e61SRobert Mustacchi io_base_hi = pci_getw(bus, dev, func, 29191f0c5e61SRobert Mustacchi PCI_BCNF_IO_BASE_HI); 29201f0c5e61SRobert Mustacchi io_limit_hi = pci_getw(bus, dev, func, 29211f0c5e61SRobert Mustacchi PCI_BCNF_IO_LIMIT_HI); 29221f0c5e61SRobert Mustacchi 29231f0c5e61SRobert Mustacchi io_range[0] |= (uint32_t)io_base_hi << 16; 29241f0c5e61SRobert Mustacchi io_range[1] |= (uint32_t)io_limit_hi << 16; 29251f0c5e61SRobert Mustacchi } 29269896aa55Sjveta } else { 29279896aa55Sjveta io_range[0] = 0x9fff; 29289896aa55Sjveta io_range[1] = 0x1000; 29299896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 29309896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 29319896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 29329896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 29339896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 29349896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 29359896aa55Sjveta } 29369896aa55Sjveta 29377c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 29382f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 29391f0c5e61SRobert Mustacchi io_range[0], (io_range[1] - io_range[0] + 1)); 29402f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 29411f0c5e61SRobert Mustacchi io_range[0], (io_range[1] - io_range[0] + 1)); 29422f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 29432f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 29441f0c5e61SRobert Mustacchi io_range[0], (io_range[1] - io_range[0] + 1)); 29457c478bd9Sstevel@tonic-gate } 29461f0c5e61SRobert Mustacchi dcmn_err(CE_NOTE, "bus %d io-range: 0x%" PRIx64 "-%" PRIx64, 29477c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 29487c478bd9Sstevel@tonic-gate } 29497c478bd9Sstevel@tonic-gate 29507c478bd9Sstevel@tonic-gate /* mem range */ 29517c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 29521f0c5e61SRobert Mustacchi mem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 29537c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 29541f0c5e61SRobert Mustacchi mem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 29551f0c5e61SRobert Mustacchi 0xfffff; 29567c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 29572f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 29587c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 29597c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 29602f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 296105f867c3Sgs (uint64_t)mem_range[0], 296205f867c3Sgs (uint64_t)(mem_range[1] - mem_range[0] + 1)); 296386ce93f0SGuoli Shu /* remove from parent resource list */ 29642f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 29658fc7923fSDana Myers (uint64_t)mem_range[0], 29668fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 29672f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 29688fc7923fSDana Myers (uint64_t)mem_range[0], 29698fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 29701f0c5e61SRobert Mustacchi dcmn_err(CE_NOTE, "bus %d mem-range: 0x%" PRIx64 "-%" PRIx64, 29717c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 29727c478bd9Sstevel@tonic-gate } 29737c478bd9Sstevel@tonic-gate 29747c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 29757c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 29761f0c5e61SRobert Mustacchi pmem_range[0] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT); 29777c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 29781f0c5e61SRobert Mustacchi pmem_range[1] = ((val & PCI_BCNF_MEM_MASK) << PCI_BCNF_MEM_SHIFT) | 29791f0c5e61SRobert Mustacchi 0xfffff; 29801f0c5e61SRobert Mustacchi if ((pmem_range[0] & PCI_BCNF_ADDR_MASK) == PCI_BCNF_PF_MEM_64BIT) { 29811f0c5e61SRobert Mustacchi uint32_t pf_addr_hi, pf_limit_hi; 29821f0c5e61SRobert Mustacchi pf_addr_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH); 29831f0c5e61SRobert Mustacchi pf_limit_hi = pci_getl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH); 29841f0c5e61SRobert Mustacchi pmem_range[0] |= (uint64_t)pf_addr_hi << 32; 29851f0c5e61SRobert Mustacchi pmem_range[1] |= (uint64_t)pf_limit_hi << 32; 29861f0c5e61SRobert Mustacchi } 29877c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 29882f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].pmem_avail, 29897c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 29907c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 29912f283da5SDan Mick memlist_insert(&pci_bus_res[bus].pmem_used, 299205f867c3Sgs (uint64_t)pmem_range[0], 299305f867c3Sgs (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 299486ce93f0SGuoli Shu /* remove from parent resource list */ 29952f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 29968fc7923fSDana Myers (uint64_t)pmem_range[0], 29978fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 29982f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 29998fc7923fSDana Myers (uint64_t)pmem_range[0], 30008fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 30011f0c5e61SRobert Mustacchi dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%" PRIx64 "-%" PRIx64, 30027c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 30037c478bd9Sstevel@tonic-gate } 30047c478bd9Sstevel@tonic-gate 30052f283da5SDan Mick /* 30062f283da5SDan Mick * Add VGA legacy resources to the bridge's pci_bus_res if it 30072f283da5SDan Mick * has VGA_ENABLE set. Note that we put them in 'avail', 30082f283da5SDan Mick * because that's used to populate the ranges prop; they'll be 30092f283da5SDan Mick * removed from there by the VGA device once it's found. Also, 30102f283da5SDan Mick * remove them from the parent's available list and note them as 30112f283da5SDan Mick * used in the parent. 30122f283da5SDan Mick */ 30132f283da5SDan Mick 30142f283da5SDan Mick if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 30152f283da5SDan Mick PCI_BCNF_BCNTRL_VGA_ENABLE) { 30162f283da5SDan Mick 30172f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 30182f283da5SDan Mick 30192f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 30202f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 30212f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 30222f283da5SDan Mick 0x3b0, 0xc); 30232f283da5SDan Mick } 30242f283da5SDan Mick 30252f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 30262f283da5SDan Mick 30272f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 30282f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 30292f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 30302f283da5SDan Mick 0x3c0, 0x20); 30312f283da5SDan Mick } 30322f283da5SDan Mick 30332f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 30342f283da5SDan Mick 0x20000); 30352f283da5SDan Mick 30362f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 30372f283da5SDan Mick if (pci_bus_res[bus].mem_avail != NULL) { 30382f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 30392f283da5SDan Mick 0xa0000, 0x20000); 30402f283da5SDan Mick } 30412f283da5SDan Mick } 30427c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 30438fc7923fSDana Myers add_ranges_prop(secbus, 1); 30447c478bd9Sstevel@tonic-gate } 30457c478bd9Sstevel@tonic-gate 304609f67678Sanish extern const struct pci_class_strings_s class_pci[]; 304709f67678Sanish extern int class_pci_items; 30487c478bd9Sstevel@tonic-gate 30497c478bd9Sstevel@tonic-gate static void 30507c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 30517c478bd9Sstevel@tonic-gate { 30527c478bd9Sstevel@tonic-gate const char *desc; 30537c478bd9Sstevel@tonic-gate int i; 30547c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 30557c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 30567c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 30577c478bd9Sstevel@tonic-gate 30587c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 30597c478bd9Sstevel@tonic-gate desc = "IDE controller"; 30607c478bd9Sstevel@tonic-gate } else { 30617c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 30627c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 30637c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 30647c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 306509f67678Sanish desc = class_pci[i].actual_desc; 30667c478bd9Sstevel@tonic-gate break; 30677c478bd9Sstevel@tonic-gate } 30687c478bd9Sstevel@tonic-gate } 306909f67678Sanish if (i == class_pci_items) 30707c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 30717c478bd9Sstevel@tonic-gate } 30727c478bd9Sstevel@tonic-gate 30737c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 30747c478bd9Sstevel@tonic-gate (char *)desc); 30757c478bd9Sstevel@tonic-gate } 30767c478bd9Sstevel@tonic-gate 30777c478bd9Sstevel@tonic-gate static void 30787c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 30797c478bd9Sstevel@tonic-gate { 30807c478bd9Sstevel@tonic-gate int bus_range[2]; 30817c478bd9Sstevel@tonic-gate 30827c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 30837c478bd9Sstevel@tonic-gate return; 30847c478bd9Sstevel@tonic-gate bus_range[0] = bus; 30857c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 30867c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 30877c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 30887c478bd9Sstevel@tonic-gate } 30897c478bd9Sstevel@tonic-gate 3090b1f176e8Sjg /* 3091b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 3092b1f176e8Sjg */ 3093b1f176e8Sjg static void 3094b1f176e8Sjg add_bus_slot_names_prop(int bus) 3095b1f176e8Sjg { 3096b1f176e8Sjg char slotprop[256]; 3097b1f176e8Sjg int len; 30980db3240dSStephen Hanson extern int pci_irq_nroutes; 30990db3240dSStephen Hanson char *slotcap_name; 3100b1f176e8Sjg 31010db3240dSStephen Hanson /* 31020db3240dSStephen Hanson * If no irq routing table, then go with the slot-names as set up 31030db3240dSStephen Hanson * in pciex_slot_names_prop() from slot capability register (if any). 31040db3240dSStephen Hanson */ 31050db3240dSStephen Hanson if (pci_irq_nroutes == 0) 31060db3240dSStephen Hanson return; 31070db3240dSStephen Hanson 31080db3240dSStephen Hanson /* 31090db3240dSStephen Hanson * Otherise delete the slot-names we already have and use the irq 31100db3240dSStephen Hanson * routing table values as returned by pci_slot_names_prop() instead, 31110db3240dSStephen Hanson * but keep any property of value "pcie0" as that can't be represented 31120db3240dSStephen Hanson * in the irq routing table. 31130db3240dSStephen Hanson */ 3114d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 31150db3240dSStephen Hanson if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 31160db3240dSStephen Hanson DDI_PROP_DONTPASS, "slot-names", &slotcap_name) != 31170db3240dSStephen Hanson DDI_SUCCESS || strcmp(slotcap_name, "pcie0") != 0) 31180db3240dSStephen Hanson (void) ndi_prop_remove(DDI_DEV_T_NONE, 31190db3240dSStephen Hanson pci_bus_res[bus].dip, "slot-names"); 3120d57b3b3dSprasad } 3121d57b3b3dSprasad 3122b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 3123b1f176e8Sjg if (len > 0) { 312453273e82Ssethg /* 312553273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 312653273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 312753273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 312853273e82Ssethg * subordinate to any PCI-PCI bridge). 312953273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 313053273e82Ssethg * will remove it later. 313153273e82Ssethg */ 313253273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 313353273e82Ssethg pci_bus_res[bus].dip == NULL) { 313453273e82Ssethg 3135b1f176e8Sjg create_root_bus_dip(bus); 313653273e82Ssethg } 313753273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 313853273e82Ssethg ASSERT((len % sizeof (int)) == 0); 313953273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 314053273e82Ssethg pci_bus_res[bus].dip, "slot-names", 314153273e82Ssethg (int *)slotprop, len / sizeof (int)); 314253273e82Ssethg } else { 314353273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 314453273e82Ssethg "IRQ routing table; Not adding slot-names " 314553273e82Ssethg "property for incorrect bus %d", bus); 314653273e82Ssethg } 3147b1f176e8Sjg } 3148b1f176e8Sjg } 3149b1f176e8Sjg 31508fc7923fSDana Myers /* 31518fc7923fSDana Myers * Handle both PCI root and PCI-PCI bridge range properties; 31528fc7923fSDana Myers * non-zero 'ppb' argument select PCI-PCI bridges versus root. 31538fc7923fSDana Myers */ 31548fc7923fSDana Myers static void 31551f0c5e61SRobert Mustacchi memlist_to_ranges(void **rp, struct memlist *entry, uint_t type, int ppb) 31567c478bd9Sstevel@tonic-gate { 31578fc7923fSDana Myers ppb_ranges_t *ppb_rp = *rp; 31588fc7923fSDana Myers pci_ranges_t *pci_rp = *rp; 31598fc7923fSDana Myers 31608fc7923fSDana Myers while (entry != NULL) { 31611f0c5e61SRobert Mustacchi uint_t atype = type; 31621f0c5e61SRobert Mustacchi if ((type & PCI_REG_ADDR_M) == PCI_ADDR_MEM32 && 31631f0c5e61SRobert Mustacchi (entry->ml_address >= UINT32_MAX || 31641f0c5e61SRobert Mustacchi entry->ml_size >= UINT32_MAX)) { 31651f0c5e61SRobert Mustacchi atype &= ~PCI_ADDR_MEM32; 31661f0c5e61SRobert Mustacchi atype |= PCI_ADDR_MEM64; 31671f0c5e61SRobert Mustacchi } 31688fc7923fSDana Myers if (ppb) { 31691f0c5e61SRobert Mustacchi ppb_rp->child_high = ppb_rp->parent_high = atype; 31708fc7923fSDana Myers ppb_rp->child_mid = ppb_rp->parent_mid = 31711f0c5e61SRobert Mustacchi (uint32_t)(entry->ml_address >> 32); 31728fc7923fSDana Myers ppb_rp->child_low = ppb_rp->parent_low = 317356f33205SJonathan Adams (uint32_t)entry->ml_address; 31748fc7923fSDana Myers ppb_rp->size_high = 31751f0c5e61SRobert Mustacchi (uint32_t)(entry->ml_size >> 32); 317656f33205SJonathan Adams ppb_rp->size_low = (uint32_t)entry->ml_size; 31778fc7923fSDana Myers *rp = ++ppb_rp; 31788fc7923fSDana Myers } else { 31791f0c5e61SRobert Mustacchi pci_rp->child_high = atype; 31808fc7923fSDana Myers pci_rp->child_mid = pci_rp->parent_high = 31811f0c5e61SRobert Mustacchi (uint32_t)(entry->ml_address >> 32); 31828fc7923fSDana Myers pci_rp->child_low = pci_rp->parent_low = 318356f33205SJonathan Adams (uint32_t)entry->ml_address; 31848fc7923fSDana Myers pci_rp->size_high = 31851f0c5e61SRobert Mustacchi (uint32_t)(entry->ml_size >> 32); 318656f33205SJonathan Adams pci_rp->size_low = (uint32_t)entry->ml_size; 31878fc7923fSDana Myers *rp = ++pci_rp; 31888fc7923fSDana Myers } 318956f33205SJonathan Adams entry = entry->ml_next; 31908fc7923fSDana Myers } 31918fc7923fSDana Myers } 31927c478bd9Sstevel@tonic-gate 31938fc7923fSDana Myers static void 31948fc7923fSDana Myers add_ranges_prop(int bus, int ppb) 31958fc7923fSDana Myers { 31968fc7923fSDana Myers int total, alloc_size; 31978fc7923fSDana Myers void *rp, *next_rp; 31982f283da5SDan Mick struct memlist *iolist, *memlist, *pmemlist; 31998fc7923fSDana Myers 3200ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3201ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3202ec0c94e7SDana Myers return; 3203ec0c94e7SDana Myers 32042f283da5SDan Mick iolist = memlist = pmemlist = (struct memlist *)NULL; 32052f283da5SDan Mick 32062f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 32072f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, &iolist); 32082f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 32092f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 32102f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 32112f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 32122f283da5SDan Mick 32132f283da5SDan Mick total = memlist_count(iolist); 32142f283da5SDan Mick total += memlist_count(memlist); 32152f283da5SDan Mick total += memlist_count(pmemlist); 32168fc7923fSDana Myers 32178fc7923fSDana Myers /* no property is created if no ranges are present */ 32188fc7923fSDana Myers if (total == 0) 32198fc7923fSDana Myers return; 32208fc7923fSDana Myers 32218fc7923fSDana Myers alloc_size = total * 32228fc7923fSDana Myers (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 32238fc7923fSDana Myers 32248fc7923fSDana Myers next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 32258fc7923fSDana Myers 32262f283da5SDan Mick memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 32272f283da5SDan Mick memlist_to_ranges(&next_rp, memlist, 32288fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 32292f283da5SDan Mick memlist_to_ranges(&next_rp, pmemlist, 32308fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 32318fc7923fSDana Myers 32328fc7923fSDana Myers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 32338fc7923fSDana Myers "ranges", (int *)rp, alloc_size / sizeof (int)); 32348fc7923fSDana Myers 32358fc7923fSDana Myers kmem_free(rp, alloc_size); 32362f283da5SDan Mick memlist_free_all(&iolist); 32372f283da5SDan Mick memlist_free_all(&memlist); 32382f283da5SDan Mick memlist_free_all(&pmemlist); 32397c478bd9Sstevel@tonic-gate } 32407c478bd9Sstevel@tonic-gate 32417c478bd9Sstevel@tonic-gate static void 32428fc7923fSDana Myers memlist_remove_list(struct memlist **list, struct memlist *remove_list) 32437c478bd9Sstevel@tonic-gate { 32448fc7923fSDana Myers while (list && *list && remove_list) { 324556f33205SJonathan Adams (void) memlist_remove(list, remove_list->ml_address, 324656f33205SJonathan Adams remove_list->ml_size); 324756f33205SJonathan Adams remove_list = remove_list->ml_next; 32488fc7923fSDana Myers } 32497c478bd9Sstevel@tonic-gate } 32507c478bd9Sstevel@tonic-gate 32517c478bd9Sstevel@tonic-gate static int 32527c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 32537c478bd9Sstevel@tonic-gate { 32547c478bd9Sstevel@tonic-gate int i = 0; 32557c478bd9Sstevel@tonic-gate 32567c478bd9Sstevel@tonic-gate while (list) { 32577c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 32587c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 32597c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 326056f33205SJonathan Adams sp->pci_phys_low = (uint32_t)list->ml_address; 32617c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 326256f33205SJonathan Adams sp->pci_size_low = (uint32_t)list->ml_size; 32637c478bd9Sstevel@tonic-gate 326456f33205SJonathan Adams list = list->ml_next; 32657c478bd9Sstevel@tonic-gate sp++, i++; 32667c478bd9Sstevel@tonic-gate } 32677c478bd9Sstevel@tonic-gate return (i); 32687c478bd9Sstevel@tonic-gate } 32697c478bd9Sstevel@tonic-gate 32707c478bd9Sstevel@tonic-gate static void 32717c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 32727c478bd9Sstevel@tonic-gate { 32737c478bd9Sstevel@tonic-gate int i, count; 32747c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 32757c478bd9Sstevel@tonic-gate 3276ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3277ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3278ec0c94e7SDana Myers return; 3279ec0c94e7SDana Myers 32802f283da5SDan Mick count = memlist_count(pci_bus_res[bus].io_avail) + 32812f283da5SDan Mick memlist_count(pci_bus_res[bus].mem_avail) + 32822f283da5SDan Mick memlist_count(pci_bus_res[bus].pmem_avail); 32837c478bd9Sstevel@tonic-gate 32847c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 32857c478bd9Sstevel@tonic-gate return; 32867c478bd9Sstevel@tonic-gate 32877c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 32882f283da5SDan Mick i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 32897c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 32902f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 32917c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 32922f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 32937c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 32947c478bd9Sstevel@tonic-gate ASSERT(i == count); 32957c478bd9Sstevel@tonic-gate 32967c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 32977c478bd9Sstevel@tonic-gate "available", (int *)sp, 32987c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 32997c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 33007c478bd9Sstevel@tonic-gate } 3301f55ce205Sszhou 3302f55ce205Sszhou static void 3303f55ce205Sszhou alloc_res_array(void) 3304f55ce205Sszhou { 33056cbe5a00SPraveen Kumar Dasaraju Rama static int array_size = 0; 33066cbe5a00SPraveen Kumar Dasaraju Rama int old_size; 3307f55ce205Sszhou void *old_res; 3308f55ce205Sszhou 33096cbe5a00SPraveen Kumar Dasaraju Rama if (array_size > pci_bios_maxbus + 1) 3310f55ce205Sszhou return; /* array is big enough */ 3311f55ce205Sszhou 33126cbe5a00SPraveen Kumar Dasaraju Rama old_size = array_size; 3313f55ce205Sszhou old_res = pci_bus_res; 3314f55ce205Sszhou 33156cbe5a00SPraveen Kumar Dasaraju Rama if (array_size == 0) 33166cbe5a00SPraveen Kumar Dasaraju Rama array_size = 16; /* start with a reasonable number */ 3317f55ce205Sszhou 33186cbe5a00SPraveen Kumar Dasaraju Rama while (array_size <= pci_bios_maxbus + 1) 33196cbe5a00SPraveen Kumar Dasaraju Rama array_size <<= 1; 3320f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 33216cbe5a00SPraveen Kumar Dasaraju Rama array_size * sizeof (struct pci_bus_resource), KM_SLEEP); 3322f55ce205Sszhou 3323f55ce205Sszhou if (old_res) { /* copy content and free old array */ 3324f55ce205Sszhou bcopy(old_res, pci_bus_res, 33256cbe5a00SPraveen Kumar Dasaraju Rama old_size * sizeof (struct pci_bus_resource)); 33266cbe5a00SPraveen Kumar Dasaraju Rama kmem_free(old_res, old_size * sizeof (struct pci_bus_resource)); 3327f55ce205Sszhou } 3328f55ce205Sszhou } 3329c8589f13Ssethg 3330c8589f13Ssethg static void 3331c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3332c8589f13Ssethg ushort_t deviceid) 3333c8589f13Ssethg { 3334c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 3335c8589f13Ssethg static int numioapics = 0; 3336c8589f13Ssethg dev_info_t *ioapic_node; 3337c8589f13Ssethg uint64_t physaddr; 3338c8589f13Ssethg uint32_t lobase, hibase = 0; 3339c8589f13Ssethg 3340c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3341c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3342c8589f13Ssethg 3343c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3344c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3345c8589f13Ssethg return; 3346c8589f13Ssethg 3347c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3348c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3349c8589f13Ssethg 3350c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 3351c8589f13Ssethg 3352c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 3353c8589f13Ssethg 3354c8589f13Ssethg /* 3355c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 3356c8589f13Ssethg */ 3357c8589f13Ssethg if (ioapicsnode == NULL) { 3358c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3359c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3360c8589f13Ssethg return; 3361c8589f13Ssethg } 3362c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 3363c8589f13Ssethg } 3364c8589f13Ssethg 3365c8589f13Ssethg /* 3366c8589f13Ssethg * Create a child node for this IOAPIC 3367c8589f13Ssethg */ 3368c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3369c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 3370c8589f13Ssethg if (ioapic_node == NULL) { 3371c8589f13Ssethg return; 3372c8589f13Ssethg } 3373c8589f13Ssethg 3374c8589f13Ssethg /* Vendor and Device ID */ 3375c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3376c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 3377c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3378c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 3379c8589f13Ssethg 3380c8589f13Ssethg /* device_type */ 3381c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3382c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 3383c8589f13Ssethg 3384c8589f13Ssethg /* reg */ 3385c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3386c8589f13Ssethg "reg", physaddr); 3387c8589f13Ssethg } 3388d57b3b3dSprasad 3389d57b3b3dSprasad /* 3390d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 3391d57b3b3dSprasad * information obtained from Slot Capabilities register. 3392d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 3393d57b3b3dSprasad * information in the PCI IRQ table. 3394d57b3b3dSprasad */ 3395d57b3b3dSprasad static void 3396d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3397d57b3b3dSprasad { 3398d57b3b3dSprasad char slotprop[256]; 3399d57b3b3dSprasad int len; 3400d57b3b3dSprasad 3401d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 3402d57b3b3dSprasad 3403d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 3404d57b3b3dSprasad *(uint32_t *)slotprop = 1; 3405d57b3b3dSprasad len = 4; 3406d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3407d57b3b3dSprasad slot_num); 3408d57b3b3dSprasad len += strlen(slotprop + len) + 1; 3409d57b3b3dSprasad len += len % 4; 3410d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3411d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 3412d57b3b3dSprasad } 3413c0da6274SZhi-Jun Robin Fu 3414c0da6274SZhi-Jun Robin Fu /* 3415c0da6274SZhi-Jun Robin Fu * Enable reporting of AER capability next pointer. 3416c0da6274SZhi-Jun Robin Fu * This needs to be done only for CK8-04 devices 3417c0da6274SZhi-Jun Robin Fu * by setting NV_XVR_VEND_CYA1 (offset 0xf40) bit 13 3418c0da6274SZhi-Jun Robin Fu * NOTE: BIOS is disabling this, it needs to be enabled temporarily 3419c0da6274SZhi-Jun Robin Fu * 3420c0da6274SZhi-Jun Robin Fu * This function is adapted from npe_ck804_fix_aer_ptr(), and is 3421c0da6274SZhi-Jun Robin Fu * called from pci_boot.c. 3422c0da6274SZhi-Jun Robin Fu */ 3423c0da6274SZhi-Jun Robin Fu static void 3424c0da6274SZhi-Jun Robin Fu ck804_fix_aer_ptr(dev_info_t *dip, pcie_req_id_t bdf) 3425c0da6274SZhi-Jun Robin Fu { 3426c0da6274SZhi-Jun Robin Fu dev_info_t *rcdip; 3427c0da6274SZhi-Jun Robin Fu ushort_t cya1; 3428c0da6274SZhi-Jun Robin Fu 3429c0da6274SZhi-Jun Robin Fu rcdip = pcie_get_rc_dip(dip); 3430c0da6274SZhi-Jun Robin Fu ASSERT(rcdip != NULL); 3431c0da6274SZhi-Jun Robin Fu 3432c0da6274SZhi-Jun Robin Fu if ((pci_cfgacc_get16(rcdip, bdf, PCI_CONF_VENID) == 3433c0da6274SZhi-Jun Robin Fu NVIDIA_VENDOR_ID) && 3434c0da6274SZhi-Jun Robin Fu (pci_cfgacc_get16(rcdip, bdf, PCI_CONF_DEVID) == 3435c0da6274SZhi-Jun Robin Fu NVIDIA_CK804_DEVICE_ID) && 3436c0da6274SZhi-Jun Robin Fu (pci_cfgacc_get8(rcdip, bdf, PCI_CONF_REVID) >= 3437c0da6274SZhi-Jun Robin Fu NVIDIA_CK804_AER_VALID_REVID)) { 3438c0da6274SZhi-Jun Robin Fu cya1 = pci_cfgacc_get16(rcdip, bdf, NVIDIA_CK804_VEND_CYA1_OFF); 3439c0da6274SZhi-Jun Robin Fu if (!(cya1 & ~NVIDIA_CK804_VEND_CYA1_ERPT_MASK)) 3440c0da6274SZhi-Jun Robin Fu (void) pci_cfgacc_put16(rcdip, bdf, 3441c0da6274SZhi-Jun Robin Fu NVIDIA_CK804_VEND_CYA1_OFF, 3442c0da6274SZhi-Jun Robin Fu cya1 | NVIDIA_CK804_VEND_CYA1_ERPT_VAL); 3443c0da6274SZhi-Jun Robin Fu } 3444c0da6274SZhi-Jun Robin Fu } 3445