1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/stat.h> 31 #include <sys/sunndi.h> 32 #include <sys/pci.h> 33 #include <sys/pci_impl.h> 34 #include <sys/pci_cfgspace.h> 35 #include <sys/memlist.h> 36 #include <sys/bootconf.h> 37 #include "mps_table.h" 38 #include "pci_autoconfig.h" 39 #include "../../../../common/pci/pci_strings.h" 40 41 #define pci_getb (*pci_getb_func) 42 #define pci_getw (*pci_getw_func) 43 #define pci_getl (*pci_getl_func) 44 #define pci_putb (*pci_putb_func) 45 #define pci_putw (*pci_putw_func) 46 #define pci_putl (*pci_putl_func) 47 #define dcmn_err if (pci_boot_debug) cmn_err 48 49 #define CONFIG_INFO 0 50 #define CONFIG_UPDATE 1 51 #define CONFIG_NEW 2 52 #define COMPAT_BUFSIZE 256 53 54 extern int pci_bios_nbus; 55 static uchar_t max_dev_pci = 32; /* PCI standard */ 56 int pci_boot_debug = 0; 57 extern struct memlist *find_bus_res(int, int); 58 59 /* 60 * Module prototypes 61 */ 62 static void enumerate_bus_devs(uchar_t bus, int config_op); 63 static void create_root_bus_dip(uchar_t bus); 64 static dev_info_t *new_func_pci(uchar_t, uchar_t, uchar_t, uchar_t, 65 ushort_t, int); 66 static void add_compatible(dev_info_t *, ushort_t, ushort_t, 67 ushort_t, ushort_t, uchar_t, uint_t); 68 static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 69 static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t); 70 static void add_model_prop(dev_info_t *, uint_t); 71 static void add_bus_range_prop(int); 72 static void add_bus_slot_names_prop(int); 73 static void add_ppb_ranges_prop(int); 74 static void add_bus_available_prop(int); 75 static void alloc_res_array(); 76 77 /* 78 * Enumerate all PCI devices 79 */ 80 void 81 pci_setup_tree() 82 { 83 uchar_t i, root_bus_addr = 0; 84 85 alloc_res_array(); 86 for (i = 0; i <= pci_bios_nbus; i++) { 87 pci_bus_res[i].par_bus = (uchar_t)-1; 88 pci_bus_res[i].root_addr = (uchar_t)-1; 89 pci_bus_res[i].sub_bus = i; 90 } 91 92 pci_bus_res[0].root_addr = root_bus_addr++; 93 create_root_bus_dip(0); 94 enumerate_bus_devs(0, CONFIG_INFO); 95 96 /* 97 * Now enumerate peer busses 98 * 99 * We loop till pci_bios_nbus. On most systems, there is 100 * one more bus at the high end, which implements the ISA 101 * compatibility bus. We don't care about that. 102 * 103 * Note: In the old (bootconf) enumeration, the peer bus 104 * address did not use the bus number, and there were 105 * too many peer busses created. The root_bus_addr is 106 * used to maintain the old peer bus address assignment. 107 * However, we stop enumerating phantom peers with no 108 * device below. 109 */ 110 for (i = 1; i <= pci_bios_nbus; i++) { 111 if (pci_bus_res[i].dip == NULL) { 112 pci_bus_res[i].root_addr = root_bus_addr++; 113 } 114 enumerate_bus_devs(i, CONFIG_INFO); 115 116 /* add slot-names property for named pci hot-plug slots */ 117 add_bus_slot_names_prop(i); 118 } 119 120 /* add bus-range property for root/peer bus nodes */ 121 for (i = 0; i <= pci_bios_nbus; i++) { 122 if (pci_bus_res[i].par_bus == (uchar_t)-1) 123 add_bus_range_prop(i); 124 } 125 } 126 127 void 128 pci_reprogram(void) 129 { 130 int i, pci_reconfig = 1; 131 char *onoff; 132 133 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 134 DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 135 if (strcmp(onoff, "off") == 0) { 136 pci_reconfig = 0; 137 cmn_err(CE_NOTE, "pci device reprogramming disabled"); 138 } 139 ddi_prop_free(onoff); 140 } 141 142 for (i = 0; i <= pci_bios_nbus; i++) { 143 /* configure devices not configured by bios */ 144 if (pci_reconfig) 145 enumerate_bus_devs(i, CONFIG_NEW); 146 /* All dev programmed, so we can create available prop */ 147 add_bus_available_prop(i); 148 } 149 } 150 151 /* 152 * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 153 */ 154 static void 155 create_root_bus_dip(uchar_t bus) 156 { 157 int pci_regs[] = {0, 0, 0}; 158 dev_info_t *dip; 159 160 ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 161 162 ndi_devi_alloc_sleep(ddi_root_node(), "pci", 163 (dnode_t)DEVI_SID_NODEID, &dip); 164 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 165 "device_type", "pci"); 166 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 167 "#address-cells", 3); 168 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 169 "#size-cells", 2); 170 pci_regs[0] = pci_bus_res[bus].root_addr; 171 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 172 "reg", (int *)pci_regs, 3); 173 174 (void) ndi_devi_bind_driver(dip, 0); 175 pci_bus_res[bus].dip = dip; 176 pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE); 177 pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE); 178 pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE); 179 180 if (bus != 0) 181 return; 182 183 /* 184 * Special treatment of bus 0: 185 * If no resource from MPSPEC/HRT, copy pcimem from boot 186 * and make io space the entire range. There is no difference 187 * between prefetchable memory or not. 188 */ 189 if (pci_bus_res[0].mem_space == NULL) 190 pci_bus_res[0].mem_space = 191 memlist_dup(bootops->boot_mem->pcimem); 192 if (pci_bus_res[0].io_ports == NULL) 193 memlist_insert(&pci_bus_res[0].io_ports, 0, 0x10000); 194 } 195 196 /* 197 * For any fixed configuration (often compatability) pci devices 198 * and those with their own expansion rom, create device nodes 199 * to hold the already configured device details. 200 */ 201 void 202 enumerate_bus_devs(uchar_t bus, int config_op) 203 { 204 uchar_t dev, func, nfunc, header; 205 ushort_t venid; 206 dev_info_t *dip; 207 struct pci_devfunc { 208 struct pci_devfunc *next; 209 dev_info_t *dip; 210 uchar_t bus; 211 uchar_t dev; 212 uchar_t func; 213 } *devlist = NULL, *entry; 214 215 if (config_op == CONFIG_NEW) { 216 dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 217 } else 218 dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 219 220 for (dev = 0; dev < max_dev_pci; dev++) { 221 nfunc = 1; 222 for (func = 0; func < nfunc; func++) { 223 int configured; 224 225 dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 226 dev, func); 227 228 venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 229 if ((venid == 0xffff) || (venid == 0)) { 230 /* no function at this address */ 231 continue; 232 } 233 234 configured = pci_getw(bus, dev, func, PCI_CONF_COMM) & 235 (PCI_COMM_IO | PCI_COMM_MAE); 236 if ((!configured && config_op != CONFIG_NEW) || 237 (configured && config_op != CONFIG_INFO)) 238 continue; 239 240 header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 241 if (header == 0xff) { 242 continue; /* illegal value */ 243 } 244 245 /* 246 * according to some mail from Microsoft posted 247 * to the pci-drivers alias, their only requirement 248 * for a multifunction device is for the 1st 249 * function to have to PCI_HEADER_MULTI bit set. 250 */ 251 if ((func == 0) && (header & PCI_HEADER_MULTI)) { 252 nfunc = 8; 253 } 254 dip = new_func_pci(bus, dev, func, header, venid, 255 config_op); 256 /* 257 * If dip isn't null, reprogram the device later. 258 * This only happens for CONFIG_INFO case. 259 */ 260 if (dip) { 261 entry = kmem_alloc(sizeof (*entry), KM_SLEEP); 262 entry->dip = dip; 263 entry->dev = dev; 264 entry->func = func; 265 entry->next = devlist; 266 devlist = entry; 267 } 268 } 269 } 270 271 if (config_op == CONFIG_NEW) { 272 devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 273 while (devlist) { 274 entry = devlist; 275 devlist = entry->next; 276 cmn_err(CE_NOTE, 277 "!reprogram pci device [%d/%d/%d] (%s)", 278 bus, entry->dev, entry->func, 279 ddi_driver_name(entry->dip)); 280 (void) add_reg_props(entry->dip, bus, entry->dev, 281 entry->func, CONFIG_UPDATE, 0); 282 kmem_free(entry, sizeof (*entry)); 283 } 284 pci_bus_res[bus].privdata = NULL; 285 } else { 286 pci_bus_res[bus].privdata = devlist; 287 } 288 } 289 290 static int 291 check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 292 ushort_t subvenid, ushort_t subdevid) 293 { 294 static int prop_exist = -1; 295 static char *pciide_str; 296 char compat[32]; 297 298 if (prop_exist == -1) { 299 prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 300 ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 301 &pciide_str) == DDI_SUCCESS); 302 } 303 304 if (!prop_exist) 305 return (0); 306 307 /* compare property value against various forms of compatible */ 308 if (subvenid) { 309 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 310 venid, devid, subvenid, subdevid, revid); 311 if (strcmp(pciide_str, compat) == 0) 312 return (1); 313 314 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 315 venid, devid, subvenid, subdevid); 316 if (strcmp(pciide_str, compat) == 0) 317 return (1); 318 319 (void) snprintf(compat, sizeof (compat), "pci%x,%x", 320 subvenid, subdevid); 321 if (strcmp(pciide_str, compat) == 0) 322 return (1); 323 } 324 (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 325 venid, devid, revid); 326 if (strcmp(pciide_str, compat) == 0) 327 return (1); 328 329 (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 330 if (strcmp(pciide_str, compat) == 0) 331 return (1); 332 333 return (0); 334 } 335 336 static int 337 is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 338 ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 339 { 340 struct ide_table { /* table for PCI_MASS_OTHER */ 341 ushort_t venid; 342 ushort_t devid; 343 } *entry; 344 345 /* XXX SATA devices: need a way to add dynamically */ 346 static struct ide_table ide_other[] = { 347 {0x1095, 0x3112}, 348 {0x1095, 0x3114}, 349 {0x1095, 0x3512}, 350 {0, 0} 351 }; 352 353 if (basecl != PCI_CLASS_MASS) 354 return (0); 355 356 if (subcl == PCI_MASS_IDE) { 357 return (1); 358 } 359 360 if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 361 return (0); 362 } 363 364 entry = &ide_other[0]; 365 while (entry->venid) { 366 if (entry->venid == venid && entry->devid == devid) 367 return (1); 368 entry++; 369 } 370 return (check_pciide_prop(revid, venid, devid, subvenid, subdevid)); 371 } 372 373 static int 374 is_display(uint_t classcode) 375 { 376 static uint_t disp_classes[] = { 377 0x000100, 378 0x030000, 379 0x030001 380 }; 381 int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 382 383 for (i = 0; i < nclasses; i++) { 384 if (classcode == disp_classes[i]) 385 return (1); 386 } 387 return (0); 388 } 389 390 static dev_info_t * 391 new_func_pci(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 392 ushort_t vendorid, int config_op) 393 { 394 char nodename[32], unitaddr[5]; 395 dev_info_t *dip; 396 uchar_t basecl, subcl, intr, revid; 397 ushort_t subvenid, subdevid, status; 398 uint_t classcode, revclass; 399 int reprogram = 0, pciide; 400 int power[2] = {1, 1}; 401 402 ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 403 404 switch (header & PCI_HEADER_TYPE_M) { 405 case PCI_HEADER_ZERO: 406 subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 407 subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 408 break; 409 case PCI_HEADER_CARDBUS: 410 subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 411 subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 412 break; 413 default: 414 subvenid = 0; 415 subdevid = 0; 416 break; 417 } 418 419 /* XXX should be use generic names? derive from class? */ 420 revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 421 classcode = revclass >> 8; 422 revid = revclass & 0xff; 423 424 /* figure out if this is pci-ide */ 425 basecl = classcode >> 16; 426 subcl = (classcode >> 8) & 0xff; 427 pciide = is_pciide(basecl, subcl, revid, vendorid, deviceid, 428 subvenid, subdevid); 429 430 if (pciide) 431 (void) snprintf(nodename, sizeof (nodename), "pci-ide"); 432 else if (is_display(classcode)) 433 (void) snprintf(nodename, sizeof (nodename), "display"); 434 else if (subvenid != 0) 435 (void) snprintf(nodename, sizeof (nodename), 436 "pci%x,%x", subvenid, subdevid); 437 else 438 (void) snprintf(nodename, sizeof (nodename), 439 "pci%x,%x", vendorid, deviceid); 440 441 /* make sure parent bus dip has been created */ 442 if (pci_bus_res[bus].dip == NULL) { 443 create_root_bus_dip(bus); 444 } 445 446 ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 447 DEVI_SID_NODEID, &dip); 448 449 /* add properties */ 450 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 451 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 452 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 453 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 454 "class-code", classcode); 455 if (func == 0) 456 (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 457 else 458 (void) snprintf(unitaddr, sizeof (unitaddr), 459 "%x,%x", dev, func); 460 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 461 "unit-address", unitaddr); 462 463 /* add special stuff for header type */ 464 if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 465 uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 466 uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 467 468 if (subvenid != 0) { 469 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 470 "subsystem-id", subdevid); 471 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 472 "subsystem-vendor-id", subvenid); 473 } 474 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 475 "min-grant", mingrant); 476 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 477 "max-latency", maxlatency); 478 } 479 480 /* interrupt, record if not 0 */ 481 intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 482 if (intr != 0) 483 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 484 "interrupts", intr); 485 486 /* 487 * Add support for 133 mhz pci eventually 488 */ 489 status = pci_getw(bus, dev, func, PCI_CONF_STAT); 490 491 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 492 "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 493 if (status & PCI_STAT_FBBC) 494 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 495 "fast-back-to-back"); 496 if (status & PCI_STAT_66MHZ) 497 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 498 "66mhz-capable"); 499 if (status & PCI_STAT_UDF) 500 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 501 "udf-supported"); 502 503 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 504 "power-consumption", power, 2); 505 506 if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) { 507 add_ppb_props(dip, bus, dev, func); 508 } 509 510 add_model_prop(dip, classcode); 511 add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 512 revid, classcode); 513 reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 514 (void) ndi_devi_bind_driver(dip, 0); 515 516 /* special handling for pci-ide */ 517 if (pciide) { 518 dev_info_t *cdip; 519 520 /* 521 * Create properties specified by P1275 Working Group 522 * Proposal #414 Version 1 523 */ 524 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 525 "device_type", "pci-ide"); 526 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 527 "#address-cells", 1); 528 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 529 "#size-cells", 0); 530 531 /* allocate two child nodes */ 532 ndi_devi_alloc_sleep(dip, "ide", 533 (dnode_t)DEVI_SID_NODEID, &cdip); 534 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 535 "reg", 0); 536 (void) ndi_devi_bind_driver(cdip, 0); 537 ndi_devi_alloc_sleep(dip, "ide", 538 (dnode_t)DEVI_SID_NODEID, &cdip); 539 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 540 "reg", 1); 541 (void) ndi_devi_bind_driver(cdip, 0); 542 543 reprogram = 0; /* don't reprogram pci-ide bridge */ 544 } 545 546 if (reprogram) 547 return (dip); 548 return (NULL); 549 } 550 551 /* 552 * Set the compatible property to a value compliant with 553 * rev 2.1 of the IEEE1275 PCI binding. 554 * 555 * pciVVVV,DDDD.SSSS.ssss.RR (0) 556 * pciVVVV,DDDD.SSSS.ssss (1) 557 * pciSSSS,ssss (2) 558 * pciVVVV,DDDD.RR (3) 559 * pciVVVV,DDDD (4) 560 * pciclass,CCSSPP (5) 561 * pciclass,CCSS (6) 562 * 563 * The Subsystem (SSSS) forms are not inserted if 564 * subsystem-vendor-id is 0. 565 * 566 * Set with setprop and \x00 between each 567 * to generate the encoded string array form. 568 */ 569 void 570 add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 571 ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode) 572 { 573 int i, size; 574 char *compat[7]; 575 char *buf, *curr; 576 577 #define COMPAT_BUFSIZE 256 578 i = 0; 579 size = COMPAT_BUFSIZE; 580 curr = buf = kmem_alloc(size, KM_SLEEP); 581 582 if (subvenid) { 583 compat[i++] = curr; /* form 0 */ 584 (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 585 vendorid, deviceid, subvenid, subdevid, revid); 586 size -= strlen(curr) + 1; 587 curr += strlen(curr) + 1; 588 589 compat[i++] = curr; /* form 1 */ 590 (void) snprintf(curr, size, "pci%x,%x.%x.%x", 591 vendorid, deviceid, subvenid, subdevid); 592 size -= strlen(curr) + 1; 593 curr += strlen(curr) + 1; 594 595 compat[i++] = curr; /* form 2 */ 596 (void) snprintf(curr, size, "pci%x,%x", 597 subvenid, subdevid); 598 size -= strlen(curr) + 1; 599 curr += strlen(curr) + 1; 600 } 601 compat[i++] = curr; /* form 3 */ 602 (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 603 size -= strlen(curr) + 1; 604 curr += strlen(curr) + 1; 605 606 compat[i++] = curr; /* form 4 */ 607 (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 608 size -= strlen(curr) + 1; 609 curr += strlen(curr) + 1; 610 611 compat[i++] = curr; /* form 5 */ 612 (void) snprintf(curr, size, "pciclass,%06x", classcode); 613 size -= strlen(curr) + 1; 614 curr += strlen(curr) + 1; 615 616 compat[i++] = curr; /* form 6 */ 617 (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 618 619 (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 620 "compatible", compat, i); 621 kmem_free(buf, COMPAT_BUFSIZE); 622 } 623 624 /* 625 * Adjust the reg properties for a dual channel PCI-IDE device. 626 * 627 * NOTE: don't do anything that changes the order of the hard-decodes 628 * and programmed BARs. The kernel driver depends on these values 629 * being in this order regardless of whether they're for a 'native' 630 * mode BAR or not. 631 */ 632 /* 633 * config info for pci-ide devices 634 */ 635 static struct { 636 uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 637 uchar_t bar_offset; /* offset for alt status register */ 638 ushort_t addr; /* compatibility mode base address */ 639 ushort_t length; /* number of ports for this BAR */ 640 } pciide_bar[] = { 641 { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 642 { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 643 { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 644 { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 645 }; 646 647 static int 648 pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 649 { 650 int hard_decode = 0; 651 652 /* 653 * Adjust the base and len for the BARs of the PCI-IDE 654 * device's primary and secondary controllers. The first 655 * two BARs are for the primary controller and the next 656 * two BARs are for the secondary controller. The fifth 657 * and sixth bars are never adjusted. 658 */ 659 if (index >= 0 && index <= 3) { 660 *lenp = pciide_bar[index].length; 661 662 if (progcl & pciide_bar[index].native_mask) { 663 *basep += pciide_bar[index].bar_offset; 664 } else { 665 *basep = pciide_bar[index].addr; 666 hard_decode = 1; 667 } 668 } 669 670 /* 671 * if either base or len is zero make certain both are zero 672 */ 673 if (*basep == 0 || *lenp == 0) { 674 *basep = 0; 675 *lenp = 0; 676 hard_decode = 0; 677 } 678 679 return (hard_decode); 680 } 681 682 683 /* 684 * Add the "reg" and "assigned-addresses" property 685 */ 686 static int 687 add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 688 int config_op, int pciide) 689 { 690 uchar_t baseclass, subclass, progclass, header; 691 ushort_t bar_sz; 692 uint_t value = 0, len, devloc; 693 uint_t base, base_hi, type; 694 ushort_t offset, end; 695 int max_basereg, j, reprogram = 0; 696 uint_t phys_hi; 697 struct memlist **io_res, **mres, **mem_res, **pmem_res; 698 699 pci_regspec_t regs[16] = {{0}}; 700 pci_regspec_t assigned[15] = {{0}}; 701 int nreg, nasgn, configured, enable = 0; 702 703 io_res = &pci_bus_res[bus].io_ports; 704 mem_res = &pci_bus_res[bus].mem_space; 705 if (bus == 0) /* for bus 0, there is only mem_space */ 706 pmem_res = mem_res; 707 else 708 pmem_res = &pci_bus_res[bus].pmem_space; 709 710 devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 711 regs[0].pci_phys_hi = devloc; 712 nreg = 1; /* rest of regs[0] is all zero */ 713 nasgn = 0; 714 715 baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 716 subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 717 progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 718 header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 719 configured = pci_getw(bus, dev, func, PCI_CONF_COMM) & 720 (PCI_COMM_IO | PCI_COMM_MAE); 721 ASSERT(configured || config_op == CONFIG_NEW); 722 723 switch (header) { 724 case PCI_HEADER_ZERO: 725 max_basereg = PCI_BASE_NUM; 726 break; 727 case PCI_HEADER_PPB: 728 max_basereg = PCI_BCNF_BASE_NUM; 729 break; 730 case PCI_HEADER_CARDBUS: 731 max_basereg = PCI_CBUS_BASE_NUM; 732 break; 733 default: 734 max_basereg = 0; 735 break; 736 } 737 738 /* 739 * Create the register property by saving the current 740 * value of the base register. Disable memory/io, then 741 * write 0xffffffff to the base register. Read the 742 * value back to determine the required size of the 743 * address space. Restore the base register 744 * contents. 745 */ 746 end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 747 for (j = 0, offset = PCI_CONF_BASE0; offset < end; 748 j++, offset += bar_sz) { 749 int hard_decode = 0; 750 751 /* determine the size of the address space */ 752 base = pci_getl(bus, dev, func, offset); 753 pci_putl(bus, dev, func, offset, 0xffffffff); 754 value = pci_getl(bus, dev, func, offset); 755 pci_putl(bus, dev, func, offset, base); 756 757 /* construct phys hi,med.lo, size hi, lo */ 758 if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 759 /* i/o space */ 760 bar_sz = PCI_BAR_SZ_32; 761 value &= PCI_BASE_IO_ADDR_M; 762 len = ((value ^ (value-1)) + 1) >> 1; 763 764 /* XXX Adjust first 4 IDE registers */ 765 if (pciide) { 766 if (subclass != PCI_MASS_IDE) 767 progclass = (PCI_IDE_IF_NATIVE_PRI | 768 PCI_IDE_IF_NATIVE_SEC); 769 hard_decode = pciIdeAdjustBAR(progclass, j, 770 &base, &len); 771 } else if (value == 0) { 772 /* skip base regs with size of 0 */ 773 continue; 774 } 775 776 regs[nreg].pci_size_low = 777 assigned[nasgn].pci_size_low = len; 778 if (!hard_decode) { 779 regs[nreg].pci_phys_hi = 780 (PCI_ADDR_IO | devloc) + offset; 781 } else { 782 regs[nreg].pci_phys_hi = 783 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + 784 offset; 785 regs[nreg].pci_phys_low = 786 base & PCI_BASE_IO_ADDR_M; 787 } 788 assigned[nasgn].pci_phys_hi = 789 (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset; 790 type = base & (~PCI_BASE_IO_ADDR_M); 791 base &= PCI_BASE_IO_ADDR_M; 792 793 /* 794 * first pass - gather what's there 795 * update/second pass - adjust/allocate regions 796 * config - allocate regions 797 */ 798 if (config_op == CONFIG_INFO) { /* first pass */ 799 /* take out of the resource map of the bus */ 800 if (*io_res && base != 0) 801 (void) memlist_remove(io_res, 802 (uint64_t)base, (uint64_t)len); 803 else if (*io_res) 804 reprogram = 1; 805 } else if (*io_res && base == 0) { 806 base = (uint_t)memlist_find(io_res, 807 (uint64_t)len, (uint64_t)0x400); 808 if (base != 0) { 809 /* XXX need to worry about 64-bit? */ 810 pci_putl(bus, dev, func, offset, 811 base | type); 812 base = pci_getl(bus, dev, func, offset); 813 base &= PCI_BASE_IO_ADDR_M; 814 } 815 if (base == 0) { 816 cmn_err(CE_WARN, "failed to program" 817 " IO space 0x%x for [%d/%d/%d]", 818 len, bus, dev, func); 819 } else 820 enable = 1; 821 } 822 assigned[nasgn].pci_phys_low = base; 823 nreg++, nasgn++; 824 825 } else { 826 /* memory space */ 827 if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 828 bar_sz = PCI_BAR_SZ_64; 829 base_hi = pci_getl(bus, dev, func, offset + 4); 830 phys_hi = PCI_ADDR_MEM64; 831 } else { 832 bar_sz = PCI_BAR_SZ_32; 833 base_hi = 0; 834 phys_hi = PCI_ADDR_MEM32; 835 } 836 837 /* skip base regs with size of 0 */ 838 value &= PCI_BASE_M_ADDR_M; 839 840 if (value == 0) { 841 continue; 842 } 843 len = ((value ^ (value-1)) + 1) >> 1; 844 regs[nreg].pci_size_low = 845 assigned[nasgn].pci_size_low = len; 846 847 phys_hi |= (devloc | offset); 848 if (base & PCI_BASE_PREF_M) { 849 mres = pmem_res; 850 phys_hi |= PCI_PREFETCH_B; 851 } else { 852 mres = mem_res; 853 } 854 regs[nreg].pci_phys_hi = 855 assigned[nasgn].pci_phys_hi = phys_hi; 856 assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 857 assigned[nasgn].pci_phys_mid = base_hi; 858 type = base & ~PCI_BASE_M_ADDR_M; 859 base &= PCI_BASE_M_ADDR_M; 860 861 if (config_op == CONFIG_INFO) { 862 /* take out of the resource map of the bus */ 863 if (*mres && base != 0) { 864 (void) memlist_remove(mres, 865 (uint64_t)base, (uint64_t)len); 866 } else if (*mres) 867 reprogram = 1; 868 } else if (*mres && base == 0) { 869 base = (uint_t)memlist_find(mres, 870 (uint64_t)len, (uint64_t)0x1000); 871 if (base != NULL) { 872 pci_putl(bus, dev, func, offset, 873 base | type); 874 base = pci_getl(bus, dev, func, offset); 875 base &= PCI_BASE_M_ADDR_M; 876 } 877 878 if (base == 0) { 879 cmn_err(CE_WARN, "failed to program " 880 "mem space 0x%x for [%d/%d/%d]", 881 len, bus, dev, func); 882 } else 883 enable = 1; 884 } 885 assigned[nasgn].pci_phys_low = base; 886 nreg++, nasgn++; 887 } 888 } 889 switch (header) { 890 case PCI_HEADER_ZERO: 891 offset = PCI_CONF_ROM; 892 break; 893 case PCI_HEADER_PPB: 894 offset = PCI_BCNF_ROM; 895 break; 896 default: /* including PCI_HEADER_CARDBUS */ 897 goto done; 898 } 899 900 /* 901 * Add the expansion rom memory space 902 * Determine the size of the ROM base reg; don't write reserved bits 903 * ROM isn't in the PCI memory space. 904 */ 905 base = pci_getl(bus, dev, func, offset); 906 pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 907 value = pci_getl(bus, dev, func, offset); 908 pci_putl(bus, dev, func, offset, base); 909 value &= PCI_BASE_ROM_ADDR_M; 910 911 if (value != 0) { 912 regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 913 assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 914 PCI_ADDR_MEM32 | devloc) + offset; 915 base &= PCI_BASE_ROM_ADDR_M; 916 assigned[nasgn].pci_phys_low = base; 917 len = ((value ^ (value-1)) + 1) >> 1; 918 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 919 nreg++, nasgn++; 920 /* take it out of the memory resource */ 921 if (*mem_res && base != 0) 922 (void) memlist_remove(mem_res, 923 (uint64_t)base, (uint64_t)len); 924 } 925 926 /* 927 * The following are ISA resources. There are not part 928 * of the PCI local bus resources. So don't attempt to 929 * do resource accounting against PCI. 930 */ 931 932 /* add the three hard-decode, aliased address spaces for VGA */ 933 if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 934 (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 935 936 /* VGA hard decode 0x3b0-0x3bb */ 937 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 938 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 939 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 940 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 941 nreg++, nasgn++; 942 943 /* VGA hard decode 0x3c0-0x3df */ 944 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 945 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 946 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 947 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 948 nreg++, nasgn++; 949 950 /* Video memory */ 951 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 952 (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc); 953 regs[nreg].pci_phys_low = 954 assigned[nasgn].pci_phys_low = 0xa0000; 955 regs[nreg].pci_size_low = 956 assigned[nasgn].pci_size_low = 0x20000; 957 nreg++, nasgn++; 958 } 959 960 /* add the hard-decode, aliased address spaces for 8514 */ 961 if ((baseclass == PCI_CLASS_DISPLAY) && 962 (subclass == PCI_DISPLAY_VGA) && 963 (progclass & PCI_DISPLAY_IF_8514)) { 964 965 /* hard decode 0x2e8 */ 966 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 967 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 968 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 969 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 970 nreg++, nasgn++; 971 972 /* hard decode 0x2ea-0x2ef */ 973 regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 974 (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 975 regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 976 regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 977 nreg++, nasgn++; 978 } 979 980 done: 981 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 982 (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 983 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 984 "assigned-addresses", 985 (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 986 if (config_op == CONFIG_NEW && enable) { 987 cmn_err(CE_NOTE, 988 "!enable PCI device [%d/%d/%d]", bus, dev, func); 989 pci_putw(bus, dev, func, PCI_CONF_COMM, 990 pci_getw(bus, dev, func, PCI_CONF_COMM) | 0x7); 991 } 992 return (reprogram); 993 } 994 995 static void 996 add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func) 997 { 998 int i; 999 uint_t val, io_range[2], mem_range[2], pmem_range[2]; 1000 uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 1001 uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 1002 ASSERT(secbus <= subbus); 1003 1004 /* 1005 * Some BIOSes lie about max pci busses, we allow for 1006 * such mistakes here 1007 */ 1008 if (subbus > pci_bios_nbus) { 1009 pci_bios_nbus = subbus; 1010 alloc_res_array(); 1011 } 1012 1013 ASSERT(pci_bus_res[secbus].dip == NULL); 1014 pci_bus_res[secbus].dip = dip; 1015 pci_bus_res[secbus].par_bus = bus; 1016 1017 /* setup bus number hierarchy */ 1018 pci_bus_res[secbus].sub_bus = subbus; 1019 if (subbus > pci_bus_res[bus].sub_bus) 1020 pci_bus_res[bus].sub_bus = subbus; 1021 for (i = secbus + 1; i <= subbus; i++) 1022 pci_bus_res[i].par_bus = bus; 1023 1024 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1025 "device_type", "pci"); 1026 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1027 "#address-cells", 3); 1028 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1029 "#size-cells", 2); 1030 /* XXX need slot names */ 1031 1032 /* 1033 * According to PPB spec, the base register should be programmed 1034 * with a value bigger than the limit register when there are 1035 * no resources available. This applies to io, memory, and 1036 * prefetchable memory. 1037 */ 1038 /* io range */ 1039 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 1040 io_range[0] = ((val & 0xf0) << 8); 1041 val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 1042 io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 1043 if (io_range[0] != 0 && io_range[0] < io_range[1]) { 1044 memlist_insert(&pci_bus_res[secbus].io_ports, 1045 (uint64_t)io_range[0], 1046 (uint64_t)(io_range[1] - io_range[0] + 1)); 1047 if (pci_bus_res[bus].io_ports != NULL) { 1048 (void) memlist_remove(&pci_bus_res[bus].io_ports, 1049 (uint64_t)io_range[0], 1050 (uint64_t)(io_range[1] - io_range[0] + 1)); 1051 } 1052 dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 1053 secbus, io_range[0], io_range[1]); 1054 /* if 32-bit supported, make sure upper bits are not set */ 1055 if ((val & 0xf) == 1 && 1056 pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 1057 cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 1058 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1059 } 1060 } 1061 1062 /* mem range */ 1063 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 1064 mem_range[0] = ((val & 0xFFF0) << 16); 1065 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1066 mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1067 if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 1068 memlist_insert(&pci_bus_res[secbus].mem_space, 1069 (uint64_t)mem_range[0], 1070 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1071 /* remove from parent resouce list */ 1072 if (pci_bus_res[bus].mem_space != NULL) { 1073 (void) memlist_remove(&pci_bus_res[bus].mem_space, 1074 (uint64_t)mem_range[0], 1075 (uint64_t)(mem_range[1] - mem_range[0] + 1)); 1076 } 1077 dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 1078 secbus, mem_range[0], mem_range[1]); 1079 } 1080 1081 /* prefetchable memory range */ 1082 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 1083 pmem_range[0] = ((val & 0xFFF0) << 16); 1084 val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 1085 pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 1086 if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 1087 memlist_insert(&pci_bus_res[secbus].pmem_space, 1088 (uint64_t)pmem_range[0], 1089 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1090 if (pci_bus_res[bus].pmem_space != NULL) { 1091 (void) memlist_remove(&pci_bus_res[bus].pmem_space, 1092 (uint64_t)pmem_range[0], 1093 (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 1094 } 1095 dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 1096 secbus, pmem_range[0], pmem_range[1]); 1097 /* if 64-bit supported, make sure upper bits are not set */ 1098 if ((val & 0xf) == 1 && 1099 pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 1100 cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 1101 " pci-pci bridge [%d/%d/%d]", bus, dev, func); 1102 } 1103 } 1104 1105 add_bus_range_prop(secbus); 1106 add_ppb_ranges_prop(secbus); 1107 } 1108 1109 extern const struct pci_class_strings_s class_pci[]; 1110 extern int class_pci_items; 1111 1112 static void 1113 add_model_prop(dev_info_t *dip, uint_t classcode) 1114 { 1115 const char *desc; 1116 int i; 1117 uchar_t baseclass = classcode >> 16; 1118 uchar_t subclass = (classcode >> 8) & 0xff; 1119 uchar_t progclass = classcode & 0xff; 1120 1121 if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 1122 desc = "IDE controller"; 1123 } else { 1124 for (desc = 0, i = 0; i < class_pci_items; i++) { 1125 if ((baseclass == class_pci[i].base_class) && 1126 (subclass == class_pci[i].sub_class) && 1127 (progclass == class_pci[i].prog_class)) { 1128 desc = class_pci[i].actual_desc; 1129 break; 1130 } 1131 } 1132 if (i == class_pci_items) 1133 desc = "Unknown class of pci/pnpbios device"; 1134 } 1135 1136 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 1137 (char *)desc); 1138 } 1139 1140 static void 1141 add_bus_range_prop(int bus) 1142 { 1143 int bus_range[2]; 1144 1145 if (pci_bus_res[bus].dip == NULL) 1146 return; 1147 bus_range[0] = bus; 1148 bus_range[1] = pci_bus_res[bus].sub_bus; 1149 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1150 "bus-range", (int *)bus_range, 2); 1151 } 1152 1153 /* 1154 * Add slot-names property for any named pci hot-plug slots 1155 */ 1156 static void 1157 add_bus_slot_names_prop(int bus) 1158 { 1159 char slotprop[256]; 1160 int len; 1161 1162 len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 1163 if (len > 0) { 1164 if (pci_bus_res[bus].dip == NULL) 1165 create_root_bus_dip(bus); 1166 ASSERT(pci_bus_res[bus].dip); 1167 ASSERT((len % sizeof (int)) == 0); 1168 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1169 pci_bus_res[bus].dip, "slot-names", 1170 (int *)slotprop, len / sizeof (int)); 1171 } 1172 } 1173 1174 /* this should be in some header file, shared with pcicfg */ 1175 struct pcicfg_range { 1176 uint32_t child_hi; 1177 uint32_t child_mid; 1178 uint32_t child_lo; 1179 uint32_t parent_hi; 1180 uint32_t parent_mid; 1181 uint32_t parent_lo; 1182 uint32_t size_hi; 1183 uint32_t size_lo; 1184 }; 1185 1186 static int 1187 memlist_to_range(struct pcicfg_range *rp, struct memlist *entry, int type) 1188 { 1189 if (entry == NULL) 1190 return (0); 1191 1192 /* assume 32-bit addresses */ 1193 rp->child_hi = rp->parent_hi = type; 1194 rp->child_mid = rp->parent_mid = 0; 1195 rp->child_lo = rp->parent_lo = (uint32_t)entry->address; 1196 rp->size_hi = 0; 1197 rp->size_lo = (uint32_t)entry->size; 1198 return (1); 1199 } 1200 1201 static void 1202 add_ppb_ranges_prop(int bus) 1203 { 1204 int i = 0; 1205 struct pcicfg_range *rp; 1206 1207 rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP); 1208 1209 i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports, 1210 PCI_ADDR_IO | PCI_REG_REL_M); 1211 i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space, 1212 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1213 i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space, 1214 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1215 1216 if (i != 0) 1217 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1218 pci_bus_res[bus].dip, "ranges", (int *)rp, 1219 i * sizeof (struct pcicfg_range) / sizeof (int)); 1220 kmem_free(rp, 3 * sizeof (*rp)); 1221 } 1222 1223 static int 1224 memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 1225 { 1226 int i = 0; 1227 1228 while (list) { 1229 /* assume 32-bit addresses */ 1230 sp->pci_phys_hi = type; 1231 sp->pci_phys_mid = 0; 1232 sp->pci_phys_low = (uint32_t)list->address; 1233 sp->pci_size_hi = 0; 1234 sp->pci_size_low = (uint32_t)list->size; 1235 1236 list = list->next; 1237 sp++, i++; 1238 } 1239 return (i); 1240 } 1241 1242 static void 1243 add_bus_available_prop(int bus) 1244 { 1245 int i, count; 1246 struct pci_phys_spec *sp; 1247 1248 count = memlist_count(pci_bus_res[bus].io_ports) + 1249 memlist_count(pci_bus_res[bus].mem_space) + 1250 memlist_count(pci_bus_res[bus].pmem_space); 1251 1252 if (count == 0) /* nothing available */ 1253 return; 1254 1255 sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 1256 i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports, 1257 PCI_ADDR_IO | PCI_REG_REL_M); 1258 i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space, 1259 PCI_ADDR_MEM32 | PCI_REG_REL_M); 1260 i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space, 1261 PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 1262 ASSERT(i == count); 1263 1264 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1265 "available", (int *)sp, 1266 i * sizeof (struct pci_phys_spec) / sizeof (int)); 1267 kmem_free(sp, count * sizeof (*sp)); 1268 } 1269 1270 static void 1271 alloc_res_array(void) 1272 { 1273 static int array_max = 0; 1274 int old_max; 1275 void *old_res; 1276 1277 if (array_max > pci_bios_nbus + 1) 1278 return; /* array is big enough */ 1279 1280 old_max = array_max; 1281 old_res = pci_bus_res; 1282 1283 if (array_max == 0) 1284 array_max = 16; /* start with a reasonable number */ 1285 1286 while (array_max < pci_bios_nbus + 1) 1287 array_max <<= 1; 1288 pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 1289 array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 1290 1291 if (old_res) { /* copy content and free old array */ 1292 bcopy(old_res, pci_bus_res, 1293 old_max * sizeof (struct pci_bus_resource)); 1294 kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 1295 } 1296 } 1297