xref: /illumos-gate/usr/src/uts/intel/io/pci/pci_boot.c (revision 94f1124e)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
575bcd456Sjg  * Common Development and Distribution License (the "License").
675bcd456Sjg  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
2205f867c3Sgs  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #include <sys/types.h>
277c478bd9Sstevel@tonic-gate #include <sys/stat.h>
287c478bd9Sstevel@tonic-gate #include <sys/sunndi.h>
297c478bd9Sstevel@tonic-gate #include <sys/pci.h>
307c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h>
317c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h>
327c478bd9Sstevel@tonic-gate #include <sys/memlist.h>
337c478bd9Sstevel@tonic-gate #include <sys/bootconf.h>
3470025d76Sjohnny #include <io/pci/mps_table.h>
35c88420b3Sdmick #include <sys/pci_cfgspace.h>
36c88420b3Sdmick #include <sys/pci_cfgspace_impl.h>
37c88420b3Sdmick #include <sys/psw.h>
3809f67678Sanish #include "../../../../common/pci/pci_strings.h"
39c8589f13Ssethg #include <sys/apic.h>
408a5a0d1eSanish #include <io/pciex/pcie_nvidia.h>
415af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h>
4225145214Smyers #include <sys/acpi/acpi.h>
4325145214Smyers #include <sys/acpica.h>
4486c1f4dcSVikram Hegde #include <sys/intel_iommu.h>
45*94f1124eSVikram Hegde #include <sys/iommulib.h>
467c478bd9Sstevel@tonic-gate 
477c478bd9Sstevel@tonic-gate #define	pci_getb	(*pci_getb_func)
487c478bd9Sstevel@tonic-gate #define	pci_getw	(*pci_getw_func)
497c478bd9Sstevel@tonic-gate #define	pci_getl	(*pci_getl_func)
507c478bd9Sstevel@tonic-gate #define	pci_putb	(*pci_putb_func)
517c478bd9Sstevel@tonic-gate #define	pci_putw	(*pci_putw_func)
527c478bd9Sstevel@tonic-gate #define	pci_putl	(*pci_putl_func)
537c478bd9Sstevel@tonic-gate #define	dcmn_err	if (pci_boot_debug) cmn_err
547c478bd9Sstevel@tonic-gate 
557c478bd9Sstevel@tonic-gate #define	CONFIG_INFO	0
567c478bd9Sstevel@tonic-gate #define	CONFIG_UPDATE	1
577c478bd9Sstevel@tonic-gate #define	CONFIG_NEW	2
58bd87be88Ssethg #define	CONFIG_FIX	3
5970025d76Sjohnny #define	COMPAT_BUFSIZE	512
607c478bd9Sstevel@tonic-gate 
6105f867c3Sgs #define	PPB_IO_ALIGNMENT	0x1000		/* 4K aligned */
6205f867c3Sgs #define	PPB_MEM_ALIGNMENT	0x100000	/* 1M aligned */
6305f867c3Sgs 
64bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */
65bd87be88Ssethg #define	LPC_IO_CONTROL_REG_1	0x40
66bd87be88Ssethg #define	AMD8111_ENABLENMI	(uint8_t)0x80
67bd87be88Ssethg #define	DEVID_AMD8111_LPC	0x7468
68bd87be88Ssethg 
69bd87be88Ssethg struct pci_fixundo {
70bd87be88Ssethg 	uint8_t			bus;
71bd87be88Ssethg 	uint8_t			dev;
72bd87be88Ssethg 	uint8_t			fn;
73bd87be88Ssethg 	void			(*undofn)(uint8_t, uint8_t, uint8_t);
74bd87be88Ssethg 	struct pci_fixundo	*next;
75bd87be88Ssethg };
76bd87be88Ssethg 
7705f867c3Sgs struct pci_devfunc {
7805f867c3Sgs 	struct pci_devfunc *next;
7905f867c3Sgs 	dev_info_t *dip;
8005f867c3Sgs 	uchar_t dev;
8105f867c3Sgs 	uchar_t func;
8205f867c3Sgs 	boolean_t reprogram;	/* this device needs to be reprogrammed */
8305f867c3Sgs };
8405f867c3Sgs 
857c478bd9Sstevel@tonic-gate extern int pci_bios_nbus;
867c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32;	/* PCI standard */
877c478bd9Sstevel@tonic-gate int pci_boot_debug = 0;
887c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int);
89bd87be88Ssethg static struct pci_fixundo *undolist = NULL;
9005f867c3Sgs static int num_root_bus = 0;	/* count of root buses */
917c478bd9Sstevel@tonic-gate 
927c478bd9Sstevel@tonic-gate /*
937c478bd9Sstevel@tonic-gate  * Module prototypes
947c478bd9Sstevel@tonic-gate  */
957c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op);
967c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus);
9705f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t,
987c478bd9Sstevel@tonic-gate     ushort_t, int);
997c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t,
10070025d76Sjohnny     ushort_t, ushort_t, uchar_t, uint_t, int);
1017c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int);
10249fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int,
10349fbdd30SErwin T Tsaur     ushort_t);
1047c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t);
1057c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int);
106b1f176e8Sjg static void add_bus_slot_names_prop(int);
1077c478bd9Sstevel@tonic-gate static void add_ppb_ranges_prop(int);
1087c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int);
10949fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id);
11005f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t);
111f55ce205Sszhou static void alloc_res_array();
112c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
113c8589f13Ssethg     ushort_t deviceid);
114d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t);
1157c478bd9Sstevel@tonic-gate 
11675bcd456Sjg extern int pci_slot_names_prop(int, char *, int);
11775bcd456Sjg 
118ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */
11925145214Smyers int pci_bus_always_renumber = 0;
12025145214Smyers 
121fc396574Srw /* get the subordinate bus # for a root/peer bus */
122fc396574Srw static int
123fc396574Srw pci_root_subbus(int bus, uchar_t *subbus)
124fc396574Srw {
125fc396574Srw 	ACPI_HANDLE	hdl;
126fc396574Srw 	ACPI_BUFFER	rb;
127fc396574Srw 	ACPI_RESOURCE	*rp;
128fc396574Srw 	int	rv;
129fc396574Srw 
130fc396574Srw 	if (pci_bus_res[bus].dip == NULL) {
131fc396574Srw 		/* non-used bus # */
132fc396574Srw 		return (AE_ERROR);
133fc396574Srw 	}
1345cff7825Smh 	if (acpica_get_handle(pci_bus_res[bus].dip, &hdl) != AE_OK) {
135fc396574Srw 		cmn_err(CE_WARN, "!No ACPI obj for bus%d, ACPI OFF?\n", bus);
136fc396574Srw 		return (AE_ERROR);
137fc396574Srw 	}
138fc396574Srw 
139fc396574Srw 	rb.Length = ACPI_ALLOCATE_BUFFER;
140fc396574Srw 	if (AcpiGetCurrentResources(hdl, &rb) != AE_OK) {
141fc396574Srw 		cmn_err(CE_WARN, "!_CRS failed on pci%d\n", bus);
142fc396574Srw 		return (AE_ERROR);
143fc396574Srw 	}
144fc396574Srw 
145fc396574Srw 	rv = AE_ERROR;
146fc396574Srw 
147fc396574Srw 	for (rp = rb.Pointer; rp->Type != ACPI_RESOURCE_TYPE_END_TAG;
148fc396574Srw 	    rp = ACPI_NEXT_RESOURCE(rp)) {
149fc396574Srw 
150fc396574Srw 		switch (rp->Type) {
1519896aa55Sjveta 		case ACPI_RESOURCE_TYPE_ADDRESS16:
1529896aa55Sjveta 			if (rp->Data.Address.ResourceType !=
1539896aa55Sjveta 			    ACPI_BUS_NUMBER_RANGE)
1549896aa55Sjveta 				continue;
1559896aa55Sjveta 			*subbus = (uchar_t)rp->Data.Address16.Maximum;
1569896aa55Sjveta 			dcmn_err(CE_NOTE, "Address16,subbus=%d\n", *subbus);
1579896aa55Sjveta 			break;
1589896aa55Sjveta 		case ACPI_RESOURCE_TYPE_ADDRESS32:
1599896aa55Sjveta 			if (rp->Data.Address.ResourceType !=
1609896aa55Sjveta 			    ACPI_BUS_NUMBER_RANGE)
1619896aa55Sjveta 				continue;
1629896aa55Sjveta 			*subbus = (uchar_t)rp->Data.Address32.Maximum;
1639896aa55Sjveta 			dcmn_err(CE_NOTE, "Address32,subbus=%d\n", *subbus);
1649896aa55Sjveta 			break;
1659896aa55Sjveta 		case ACPI_RESOURCE_TYPE_ADDRESS64:
1669896aa55Sjveta 			if (rp->Data.Address.ResourceType !=
1679896aa55Sjveta 			    ACPI_BUS_NUMBER_RANGE)
1689896aa55Sjveta 				continue;
1699896aa55Sjveta 			*subbus = (uchar_t)rp->Data.Address64.Maximum;
1709896aa55Sjveta 			dcmn_err(CE_NOTE, "Address64,subbus=%d\n", *subbus);
1719896aa55Sjveta 			break;
1729896aa55Sjveta 		case ACPI_RESOURCE_TYPE_EXTENDED_ADDRESS64:
1739896aa55Sjveta 			if (rp->Data.Address.ResourceType !=
1749896aa55Sjveta 			    ACPI_BUS_NUMBER_RANGE)
1759896aa55Sjveta 				continue;
1769896aa55Sjveta 			*subbus = (uchar_t)rp->Data.ExtAddress64.Maximum;
1779896aa55Sjveta 			dcmn_err(CE_NOTE, "ExtAdr64,subbus=%d\n", *subbus);
1789896aa55Sjveta 			break;
1799896aa55Sjveta 		default:
1809896aa55Sjveta 			dcmn_err(CE_NOTE, "rp->Type=%d\n", rp->Type);
1819896aa55Sjveta 			continue;
182fc396574Srw 		}
183fc396574Srw 
184fc396574Srw 		/* found the bus-range resource */
185fc396574Srw 		dcmn_err(CE_NOTE, "pci%d, subbus=%d\n", bus, *subbus);
186fc396574Srw 		rv = AE_OK;
187fc396574Srw 
188fc396574Srw 		/* This breaks out of the resource scanning loop */
189fc396574Srw 		break;
190fc396574Srw 	}
191fc396574Srw 
192fc396574Srw 	AcpiOsFree(rb.Pointer);
193fc396574Srw 	if (rv != AE_OK)
194fc396574Srw 		cmn_err(CE_NOTE, "!No bus-range resource for pci%d\n", bus);
195fc396574Srw 
196fc396574Srw 	return (rv);
197fc396574Srw 
198fc396574Srw }
199fc396574Srw 
2007c478bd9Sstevel@tonic-gate /*
2017c478bd9Sstevel@tonic-gate  * Enumerate all PCI devices
2027c478bd9Sstevel@tonic-gate  */
2037c478bd9Sstevel@tonic-gate void
2047c478bd9Sstevel@tonic-gate pci_setup_tree()
2057c478bd9Sstevel@tonic-gate {
2067c478bd9Sstevel@tonic-gate 	uchar_t i, root_bus_addr = 0;
2077c478bd9Sstevel@tonic-gate 
208f55ce205Sszhou 	alloc_res_array();
2097c478bd9Sstevel@tonic-gate 	for (i = 0; i <= pci_bios_nbus; i++) {
2107c478bd9Sstevel@tonic-gate 		pci_bus_res[i].par_bus = (uchar_t)-1;
2117c478bd9Sstevel@tonic-gate 		pci_bus_res[i].root_addr = (uchar_t)-1;
2127c478bd9Sstevel@tonic-gate 		pci_bus_res[i].sub_bus = i;
2137c478bd9Sstevel@tonic-gate 	}
2147c478bd9Sstevel@tonic-gate 
2157c478bd9Sstevel@tonic-gate 	pci_bus_res[0].root_addr = root_bus_addr++;
2167c478bd9Sstevel@tonic-gate 	create_root_bus_dip(0);
2177c478bd9Sstevel@tonic-gate 	enumerate_bus_devs(0, CONFIG_INFO);
2187c478bd9Sstevel@tonic-gate 
2197c478bd9Sstevel@tonic-gate 	/*
2207c478bd9Sstevel@tonic-gate 	 * Now enumerate peer busses
2217c478bd9Sstevel@tonic-gate 	 *
2227c478bd9Sstevel@tonic-gate 	 * We loop till pci_bios_nbus. On most systems, there is
2237c478bd9Sstevel@tonic-gate 	 * one more bus at the high end, which implements the ISA
2247c478bd9Sstevel@tonic-gate 	 * compatibility bus. We don't care about that.
2257c478bd9Sstevel@tonic-gate 	 *
2267c478bd9Sstevel@tonic-gate 	 * Note: In the old (bootconf) enumeration, the peer bus
2277c478bd9Sstevel@tonic-gate 	 *	address did not use the bus number, and there were
2287c478bd9Sstevel@tonic-gate 	 *	too many peer busses created. The root_bus_addr is
2297c478bd9Sstevel@tonic-gate 	 *	used to maintain the old peer bus address assignment.
2307c478bd9Sstevel@tonic-gate 	 *	However, we stop enumerating phantom peers with no
2317c478bd9Sstevel@tonic-gate 	 *	device below.
2327c478bd9Sstevel@tonic-gate 	 */
2337c478bd9Sstevel@tonic-gate 	for (i = 1; i <= pci_bios_nbus; i++) {
2347c478bd9Sstevel@tonic-gate 		if (pci_bus_res[i].dip == NULL) {
2357c478bd9Sstevel@tonic-gate 			pci_bus_res[i].root_addr = root_bus_addr++;
2367c478bd9Sstevel@tonic-gate 		}
2377c478bd9Sstevel@tonic-gate 		enumerate_bus_devs(i, CONFIG_INFO);
238b1f176e8Sjg 
239b1f176e8Sjg 		/* add slot-names property for named pci hot-plug slots */
240b1f176e8Sjg 		add_bus_slot_names_prop(i);
2417c478bd9Sstevel@tonic-gate 	}
2427c478bd9Sstevel@tonic-gate 
2437c478bd9Sstevel@tonic-gate }
2447c478bd9Sstevel@tonic-gate 
24525145214Smyers /*
24625145214Smyers  * >0 = present, 0 = not present, <0 = error
24725145214Smyers  */
24825145214Smyers static int
24925145214Smyers pci_bbn_present(int bus)
25025145214Smyers {
25125145214Smyers 	ACPI_HANDLE	hdl;
25225145214Smyers 	int	rv;
25325145214Smyers 
25425145214Smyers 	/* no dip means no _BBN */
25525145214Smyers 	if (pci_bus_res[bus].dip == NULL)
25625145214Smyers 		return (0);
25725145214Smyers 
258db2bae30SDana Myers 	rv = -1;	/* default return value in case of error below */
259db2bae30SDana Myers 	if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) {
260db2bae30SDana Myers 		switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) {
261db2bae30SDana Myers 		case AE_OK:
262db2bae30SDana Myers 			rv = 1;
263db2bae30SDana Myers 			break;
264db2bae30SDana Myers 		case AE_NOT_FOUND:
265db2bae30SDana Myers 			rv = 0;
266db2bae30SDana Myers 			break;
267db2bae30SDana Myers 		default:
268db2bae30SDana Myers 			break;
269db2bae30SDana Myers 		}
270db2bae30SDana Myers 	}
27125145214Smyers 
272db2bae30SDana Myers 	return (rv);
27325145214Smyers }
27425145214Smyers 
27525145214Smyers /*
27625145214Smyers  * Return non-zero if any PCI bus in the system has an associated
27725145214Smyers  * _BBN object, 0 otherwise.
27825145214Smyers  */
27925145214Smyers static int
28025145214Smyers pci_roots_have_bbn(void)
28125145214Smyers {
28225145214Smyers 	int	i;
28325145214Smyers 
28425145214Smyers 	/*
28525145214Smyers 	 * Scan the PCI busses and look for at least 1 _BBN
28625145214Smyers 	 */
28725145214Smyers 	for (i = 0; i <= pci_bios_nbus; i++) {
28825145214Smyers 		/* skip non-root (peer) PCI busses */
28925145214Smyers 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
29025145214Smyers 			continue;
29125145214Smyers 
29225145214Smyers 		if (pci_bbn_present(i) > 0)
29325145214Smyers 			return (1);
29425145214Smyers 	}
29525145214Smyers 	return (0);
29625145214Smyers 
29725145214Smyers }
29825145214Smyers 
29925145214Smyers /*
30025145214Smyers  * return non-zero if the machine is one on which we renumber
30125145214Smyers  * the internal pci unit-addresses
30225145214Smyers  */
30325145214Smyers static int
30425145214Smyers pci_bus_renumber()
30525145214Smyers {
306ee8c1d4aSdm 	ACPI_TABLE_HEADER *fadt;
30725145214Smyers 
308ee8c1d4aSdm 	if (pci_bus_always_renumber)
30925145214Smyers 		return (1);
310ee8c1d4aSdm 
311ee8c1d4aSdm 	/* get the FADT */
312db2bae30SDana Myers 	if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) !=
313db2bae30SDana Myers 	    AE_OK)
31425145214Smyers 		return (0);
31525145214Smyers 
316ee8c1d4aSdm 	/* compare OEM Table ID to "SUNm31" */
317ee8c1d4aSdm 	if (strncmp("SUNm31", fadt->OemId, 6))
318ee8c1d4aSdm 		return (0);
319ee8c1d4aSdm 	else
320ee8c1d4aSdm 		return (1);
32125145214Smyers }
32225145214Smyers 
32325145214Smyers /*
32425145214Smyers  * Initial enumeration of the physical PCI bus hierarchy can
32525145214Smyers  * leave 'gaps' in the order of peer PCI bus unit-addresses.
32625145214Smyers  * Systems with more than one peer PCI bus *must* have an ACPI
32725145214Smyers  * _BBN object associated with each peer bus; use the presence
32825145214Smyers  * of this object to remove gaps in the numbering of the peer
32925145214Smyers  * PCI bus unit-addresses - only peer busses with an associated
33025145214Smyers  * _BBN are counted.
33125145214Smyers  */
33225145214Smyers static void
33325145214Smyers pci_renumber_root_busses(void)
33425145214Smyers {
33525145214Smyers 	int pci_regs[] = {0, 0, 0};
33625145214Smyers 	int	i, root_addr = 0;
33725145214Smyers 
338ee8c1d4aSdm 	/*
339ee8c1d4aSdm 	 * Currently, we only enable the re-numbering on specific
340ee8c1d4aSdm 	 * Sun machines; this is a work-around for the more complicated
341ee8c1d4aSdm 	 * issue of upgrade changing physical device paths
342ee8c1d4aSdm 	 */
34325145214Smyers 	if (!pci_bus_renumber())
34425145214Smyers 		return;
34525145214Smyers 
34625145214Smyers 	/*
34725145214Smyers 	 * If we find no _BBN objects at all, we either don't need
34825145214Smyers 	 * to do anything or can't do anything anyway
34925145214Smyers 	 */
35025145214Smyers 	if (!pci_roots_have_bbn())
35125145214Smyers 		return;
35225145214Smyers 
35325145214Smyers 	for (i = 0; i <= pci_bios_nbus; i++) {
35425145214Smyers 		/* skip non-root (peer) PCI busses */
35525145214Smyers 		if (pci_bus_res[i].par_bus != (uchar_t)-1)
35625145214Smyers 			continue;
35725145214Smyers 
35825145214Smyers 		if (pci_bbn_present(i) < 1) {
35925145214Smyers 			pci_bus_res[i].root_addr = (uchar_t)-1;
36025145214Smyers 			continue;
36125145214Smyers 		}
36225145214Smyers 
36325145214Smyers 		ASSERT(pci_bus_res[i].dip != NULL);
36425145214Smyers 		if (pci_bus_res[i].root_addr != root_addr) {
36525145214Smyers 			/* update reg property for node */
36625145214Smyers 			pci_bus_res[i].root_addr = root_addr;
36725145214Smyers 			pci_regs[0] = pci_bus_res[i].root_addr;
36825145214Smyers 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
36925145214Smyers 			    pci_bus_res[i].dip, "reg", (int *)pci_regs, 3);
37025145214Smyers 		}
37125145214Smyers 		root_addr++;
37225145214Smyers 	}
37325145214Smyers }
37425145214Smyers 
375aaba6dfeSmyers static void
376aaba6dfeSmyers remove_resource_range(struct memlist **list, int *ranges, int range_count)
377aaba6dfeSmyers {
378aaba6dfeSmyers 	struct range {
379aaba6dfeSmyers 		uint32_t base;
380aaba6dfeSmyers 		uint32_t len;
381aaba6dfeSmyers 	};
382aaba6dfeSmyers 	int index;
383aaba6dfeSmyers 
384aaba6dfeSmyers 	for (index = 0; index < range_count; index++) {
385328364c0Smyers 		/* all done if list is or has become empty */
386328364c0Smyers 		if (*list == NULL)
387328364c0Smyers 			break;
388aaba6dfeSmyers 		(void) memlist_remove(list,
389aaba6dfeSmyers 		    (uint64_t)((struct range *)ranges)[index].base,
390aaba6dfeSmyers 		    (uint64_t)((struct range *)ranges)[index].len);
391aaba6dfeSmyers 	}
392aaba6dfeSmyers }
393aaba6dfeSmyers 
394aaba6dfeSmyers static void
395aaba6dfeSmyers remove_used_resources()
396aaba6dfeSmyers {
397aaba6dfeSmyers 	dev_info_t *used;
398aaba6dfeSmyers 	int	*narray;
399aaba6dfeSmyers 	uint_t	ncount;
400aaba6dfeSmyers 	int	status;
401aaba6dfeSmyers 	int	bus;
402aaba6dfeSmyers 
403aaba6dfeSmyers 	used = ddi_find_devinfo("used-resources", -1, 0);
404328364c0Smyers 	if (used == NULL)
405aaba6dfeSmyers 		return;
406aaba6dfeSmyers 
407aaba6dfeSmyers 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
408aaba6dfeSmyers 	    DDI_PROP_DONTPASS, "io-space", &narray, &ncount);
409aaba6dfeSmyers 	if (status == DDI_PROP_SUCCESS) {
410aaba6dfeSmyers 		for (bus = 0; bus <= pci_bios_nbus; bus++)
411328364c0Smyers 			remove_resource_range(&pci_bus_res[bus].io_ports,
412328364c0Smyers 			    narray, ncount / 2);
413aaba6dfeSmyers 		ddi_prop_free(narray);
414aaba6dfeSmyers 	}
415aaba6dfeSmyers 
416aaba6dfeSmyers 	status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, used,
417aaba6dfeSmyers 	    DDI_PROP_DONTPASS, "device-memory", &narray, &ncount);
418aaba6dfeSmyers 	if (status == DDI_PROP_SUCCESS) {
419aaba6dfeSmyers 		for (bus = 0; bus <= pci_bios_nbus; bus++)
420328364c0Smyers 			remove_resource_range(&pci_bus_res[bus].mem_space,
4219896aa55Sjveta 			    narray, ncount / 2);
422aaba6dfeSmyers 		ddi_prop_free(narray);
423aaba6dfeSmyers 	}
424aaba6dfeSmyers }
425aaba6dfeSmyers 
4265af4ae46Sjveta /*
42705f867c3Sgs  * Remove the resources which are already used by devices under a subtractive
42805f867c3Sgs  * bridge from the bus's resources lists, because they're not available, and
42905f867c3Sgs  * shouldn't be allocated to other buses.  This is necessary because tracking
43005f867c3Sgs  * resources for subtractive bridges is not complete.  (Subtractive bridges only
43105f867c3Sgs  * track some of their claimed resources, not "the rest of the address space" as
43205f867c3Sgs  * they should, so that allocation to peer non-subtractive PPBs is easier.  We
43305f867c3Sgs  * need a fully-capable global resource allocator).
4345af4ae46Sjveta  */
43505f867c3Sgs static void
43605f867c3Sgs remove_subtractive_res()
4375af4ae46Sjveta {
43805f867c3Sgs 	int i, j;
43905f867c3Sgs 	struct memlist *list;
4405af4ae46Sjveta 
44105f867c3Sgs 	for (i = 0; i <= pci_bios_nbus; i++) {
44205f867c3Sgs 		if (pci_bus_res[i].subtractive) {
44305f867c3Sgs 			/* remove used io ports */
44405f867c3Sgs 			list = pci_bus_res[i].io_ports_used;
44505f867c3Sgs 			while (list) {
44605f867c3Sgs 				for (j = 0; j <= pci_bios_nbus; j++) {
44705f867c3Sgs 					if (pci_bus_res[j].io_ports)
44805f867c3Sgs 						(void) memlist_remove(
44905f867c3Sgs 						    &pci_bus_res[j].io_ports,
45005f867c3Sgs 						    list->address, list->size);
45105f867c3Sgs 				}
45205f867c3Sgs 				list = list->next;
45305f867c3Sgs 			}
45405f867c3Sgs 			/* remove used mem resource */
45505f867c3Sgs 			list = pci_bus_res[i].mem_space_used;
45605f867c3Sgs 			while (list) {
45705f867c3Sgs 				for (j = 0; j <= pci_bios_nbus; j++) {
45805f867c3Sgs 					if (pci_bus_res[j].mem_space)
45905f867c3Sgs 						(void) memlist_remove(
46005f867c3Sgs 						    &pci_bus_res[j].mem_space,
46105f867c3Sgs 						    list->address, list->size);
46286ce93f0SGuoli Shu 					if (pci_bus_res[j].pmem_space)
46386ce93f0SGuoli Shu 						(void) memlist_remove(
46486ce93f0SGuoli Shu 						    &pci_bus_res[j].pmem_space,
46586ce93f0SGuoli Shu 						    list->address, list->size);
46605f867c3Sgs 				}
46705f867c3Sgs 				list = list->next;
46805f867c3Sgs 			}
46905f867c3Sgs 			/* remove used prefetchable mem resource */
47005f867c3Sgs 			list = pci_bus_res[i].pmem_space_used;
47105f867c3Sgs 			while (list) {
47205f867c3Sgs 				for (j = 0; j <= pci_bios_nbus; j++) {
47305f867c3Sgs 					if (pci_bus_res[j].pmem_space)
47405f867c3Sgs 						(void) memlist_remove(
47505f867c3Sgs 						    &pci_bus_res[j].pmem_space,
47605f867c3Sgs 						    list->address, list->size);
47786ce93f0SGuoli Shu 					if (pci_bus_res[j].mem_space)
47886ce93f0SGuoli Shu 						(void) memlist_remove(
47986ce93f0SGuoli Shu 						    &pci_bus_res[j].mem_space,
48086ce93f0SGuoli Shu 						    list->address, list->size);
48105f867c3Sgs 				}
48205f867c3Sgs 				list = list->next;
48305f867c3Sgs 			}
4845af4ae46Sjveta 		}
48505f867c3Sgs 	}
48605f867c3Sgs }
48705f867c3Sgs 
48805f867c3Sgs /* Set up this bus's "bus_space" resource list */
48905f867c3Sgs static void
49005f867c3Sgs setup_bus_res(int bus)
49105f867c3Sgs {
49205f867c3Sgs 	uchar_t par_bus;
49305f867c3Sgs 	uchar_t sub_bus;
49405f867c3Sgs 
49505f867c3Sgs 	if (pci_bus_res[bus].dip == NULL)	/* unused bus */
49605f867c3Sgs 		return;
49705f867c3Sgs 
49805f867c3Sgs 	sub_bus = pci_bus_res[bus].sub_bus;
49905f867c3Sgs 	ASSERT(sub_bus >= bus);
50005f867c3Sgs 	ASSERT(pci_bus_res[bus].bus_space == NULL);
50105f867c3Sgs 	if (sub_bus > bus) {
50205f867c3Sgs 		/*
50305f867c3Sgs 		 * Keep the remaining available bus range in bus_space.
50405f867c3Sgs 		 * ('bus' is already allocated)
50505f867c3Sgs 		 */
50605f867c3Sgs 		memlist_insert(&pci_bus_res[bus].bus_space, bus + 1,
50705f867c3Sgs 		    sub_bus - bus);
50805f867c3Sgs 	}
5095af4ae46Sjveta 
51005f867c3Sgs 	/*
51105f867c3Sgs 	 * Remove resources from parent bus node if this is not a
51205f867c3Sgs 	 * root bus.
51305f867c3Sgs 	 */
51405f867c3Sgs 	par_bus = pci_bus_res[bus].par_bus;
51505f867c3Sgs 	if (par_bus != (uchar_t)-1) {
51605f867c3Sgs 		ASSERT(pci_bus_res[par_bus].bus_space != NULL);
51705f867c3Sgs 		(void) memlist_remove(&pci_bus_res[par_bus].bus_space,
51805f867c3Sgs 		    bus, sub_bus - bus + 1);
51905f867c3Sgs 	}
5205af4ae46Sjveta }
5215af4ae46Sjveta 
52205f867c3Sgs static uint64_t
52305f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
5245af4ae46Sjveta {
52505f867c3Sgs 	uint64_t addr = 0;
52605f867c3Sgs 	uchar_t res_bus;
5275af4ae46Sjveta 
52805f867c3Sgs 	/*
52905f867c3Sgs 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
53005f867c3Sgs 	 * the initial resources set on each root bus might not be correctly
53105f867c3Sgs 	 * accounted for.  (We need to read resources from ACPI as well as
53205f867c3Sgs 	 * the MP tables and hotplug tables.)
53305f867c3Sgs 	 */
53405f867c3Sgs 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
53505f867c3Sgs 	    (num_root_bus > 1))
5365af4ae46Sjveta 		return (0);
5375af4ae46Sjveta 
53805f867c3Sgs 	res_bus = parbus;
53905f867c3Sgs 	while (pci_bus_res[res_bus].subtractive) {
54005f867c3Sgs 		if (pci_bus_res[res_bus].io_ports)
54105f867c3Sgs 			break;
54205f867c3Sgs 		res_bus = pci_bus_res[res_bus].par_bus;
54305f867c3Sgs 		if (res_bus == (uchar_t)-1)
54405f867c3Sgs 			break; /* root bus already */
54505f867c3Sgs 	}
5465af4ae46Sjveta 
54705f867c3Sgs 	if (pci_bus_res[res_bus].io_ports) {
54805f867c3Sgs 		addr = memlist_find(&pci_bus_res[res_bus].io_ports,
54905f867c3Sgs 		    size, align);
55005f867c3Sgs 		if (addr) {
55105f867c3Sgs 			memlist_insert(&pci_bus_res[res_bus].io_ports_used,
55205f867c3Sgs 			    addr, size);
55305f867c3Sgs 			/* free the old resource */
55405f867c3Sgs 			memlist_free_all(&pci_bus_res[bus].io_ports);
55505f867c3Sgs 			/* add the new resource */
55605f867c3Sgs 			memlist_insert(&pci_bus_res[bus].io_ports, addr, size);
55705f867c3Sgs 		}
5585af4ae46Sjveta 	}
5595af4ae46Sjveta 
56005f867c3Sgs 	return (addr);
56105f867c3Sgs }
56205f867c3Sgs 
56305f867c3Sgs static uint64_t
56405f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align)
56505f867c3Sgs {
56605f867c3Sgs 	uint64_t addr = 0;
56705f867c3Sgs 	uchar_t res_bus;
5685af4ae46Sjveta 
5695af4ae46Sjveta 	/*
57005f867c3Sgs 	 * Skip root(peer) buses in multiple-root-bus systems, as currently
57105f867c3Sgs 	 * the initial resources set on each root bus might not be correctly
57205f867c3Sgs 	 * accounted for.  (We need to read resources from ACPI as well as
57305f867c3Sgs 	 * the MP tables and hotplug tables.)
5745af4ae46Sjveta 	 */
57505f867c3Sgs 	if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) &&
57605f867c3Sgs 	    (num_root_bus > 1))
5775af4ae46Sjveta 		return (0);
5785af4ae46Sjveta 
57905f867c3Sgs 	res_bus = parbus;
58005f867c3Sgs 	while (pci_bus_res[res_bus].subtractive) {
58105f867c3Sgs 		if (pci_bus_res[res_bus].mem_space)
58205f867c3Sgs 			break;
58305f867c3Sgs 		res_bus = pci_bus_res[res_bus].par_bus;
58405f867c3Sgs 		if (res_bus == (uchar_t)-1)
58505f867c3Sgs 			break; /* root bus already */
58605f867c3Sgs 	}
58705f867c3Sgs 
58805f867c3Sgs 	if (pci_bus_res[res_bus].mem_space) {
58905f867c3Sgs 		addr = memlist_find(&pci_bus_res[res_bus].mem_space,
59005f867c3Sgs 		    size, align);
59105f867c3Sgs 		if (addr) {
59205f867c3Sgs 			memlist_insert(&pci_bus_res[res_bus].mem_space_used,
59305f867c3Sgs 			    addr, size);
59486ce93f0SGuoli Shu 			/* remove it from PMEM resource also */
59586ce93f0SGuoli Shu 			if (pci_bus_res[res_bus].pmem_space)
59686ce93f0SGuoli Shu 				(void) memlist_remove(
59786ce93f0SGuoli Shu 				    &pci_bus_res[res_bus].pmem_space,
59886ce93f0SGuoli Shu 				    addr, size);
59905f867c3Sgs 			/* free the old resource */
60005f867c3Sgs 			memlist_free_all(&pci_bus_res[bus].mem_space);
60105f867c3Sgs 			/* add the new resource */
60205f867c3Sgs 			memlist_insert(&pci_bus_res[bus].mem_space, addr, size);
60305f867c3Sgs 		}
60405f867c3Sgs 	}
60505f867c3Sgs 
60605f867c3Sgs 	return (addr);
6075af4ae46Sjveta }
6085af4ae46Sjveta 
60949fbdd30SErwin T Tsaur /*
61049fbdd30SErwin T Tsaur  * given a cap_id, return its cap_id location in config space
61149fbdd30SErwin T Tsaur  */
61249fbdd30SErwin T Tsaur static int
61349fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id)
61449fbdd30SErwin T Tsaur {
61549fbdd30SErwin T Tsaur 	uint8_t curcap, cap_id_loc;
61649fbdd30SErwin T Tsaur 	uint16_t status;
61749fbdd30SErwin T Tsaur 	int location = -1;
61849fbdd30SErwin T Tsaur 
61949fbdd30SErwin T Tsaur 	/*
62049fbdd30SErwin T Tsaur 	 * Need to check the Status register for ECP support first.
62149fbdd30SErwin T Tsaur 	 * Also please note that for type 1 devices, the
62249fbdd30SErwin T Tsaur 	 * offset could change. Should support type 1 next.
62349fbdd30SErwin T Tsaur 	 */
62449fbdd30SErwin T Tsaur 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
62549fbdd30SErwin T Tsaur 	if (!(status & PCI_STAT_CAP)) {
62649fbdd30SErwin T Tsaur 		return (-1);
62749fbdd30SErwin T Tsaur 	}
62849fbdd30SErwin T Tsaur 	cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
62949fbdd30SErwin T Tsaur 
63049fbdd30SErwin T Tsaur 	/* Walk the list of capabilities */
63149fbdd30SErwin T Tsaur 	while (cap_id_loc && cap_id_loc != (uint8_t)-1) {
63249fbdd30SErwin T Tsaur 		curcap = pci_getb(bus, dev, func, cap_id_loc);
63349fbdd30SErwin T Tsaur 
63449fbdd30SErwin T Tsaur 		if (curcap == cap_id) {
63549fbdd30SErwin T Tsaur 			location = cap_id_loc;
63649fbdd30SErwin T Tsaur 			break;
63749fbdd30SErwin T Tsaur 		}
63849fbdd30SErwin T Tsaur 		cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1);
63949fbdd30SErwin T Tsaur 	}
64049fbdd30SErwin T Tsaur 	return (location);
64149fbdd30SErwin T Tsaur }
64249fbdd30SErwin T Tsaur 
6439896aa55Sjveta /*
64405f867c3Sgs  * Assign valid resources to unconfigured pci(e) bridges. We are trying
64505f867c3Sgs  * to reprogram the bridge when its
64605f867c3Sgs  * 		i)   SECBUS == SUBBUS	||
64705f867c3Sgs  * 		ii)  IOBASE > IOLIM	||
64805f867c3Sgs  * 		iii) MEMBASE > MEMLIM
64905f867c3Sgs  * This must be done after one full pass through the PCI tree to collect
65005f867c3Sgs  * all BIOS-configured resources, so that we know what resources are
65105f867c3Sgs  * free and available to assign to the unconfigured PPBs.
6529896aa55Sjveta  */
6539896aa55Sjveta static void
65405f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub)
6559896aa55Sjveta {
6569896aa55Sjveta 	uchar_t bus, dev, func;
65705f867c3Sgs 	uchar_t parbus, subbus;
65805f867c3Sgs 	uint_t io_base, io_limit, mem_base, mem_limit;
65905f867c3Sgs 	uint_t io_size, mem_size;
66005f867c3Sgs 	uint64_t addr = 0;
6615af4ae46Sjveta 	int *regp = NULL;
6629896aa55Sjveta 	uint_t reglen;
6635af4ae46Sjveta 	int rv, cap_ptr, physhi;
6649896aa55Sjveta 	dev_info_t *dip;
66505f867c3Sgs 	uint16_t cmd_reg;
66605f867c3Sgs 	struct memlist *list;
66705f867c3Sgs 
66805f867c3Sgs 	/* skip root (peer) PCI busses */
66905f867c3Sgs 	if (pci_bus_res[secbus].par_bus == (uchar_t)-1)
67005f867c3Sgs 		return;
67105f867c3Sgs 
67205f867c3Sgs 	/* skip subtractive PPB when prog_sub is not TRUE */
67305f867c3Sgs 	if (pci_bus_res[secbus].subtractive && !prog_sub)
67405f867c3Sgs 		return;
6759896aa55Sjveta 
6769896aa55Sjveta 	/* some entries may be empty due to discontiguous bus numbering */
6775af4ae46Sjveta 	dip = pci_bus_res[secbus].dip;
6789896aa55Sjveta 	if (dip == NULL)
6799896aa55Sjveta 		return;
6809896aa55Sjveta 
6819896aa55Sjveta 	rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
6829896aa55Sjveta 	    "reg", &regp, &reglen);
6835af4ae46Sjveta 	ASSERT(rv == DDI_PROP_SUCCESS && reglen > 0);
6845af4ae46Sjveta 	physhi = regp[0];
6855af4ae46Sjveta 	ddi_prop_free(regp);
6869896aa55Sjveta 
6875af4ae46Sjveta 	func = (uchar_t)PCI_REG_FUNC_G(physhi);
6885af4ae46Sjveta 	dev = (uchar_t)PCI_REG_DEV_G(physhi);
6895af4ae46Sjveta 	bus = (uchar_t)PCI_REG_BUS_G(physhi);
6909896aa55Sjveta 
6919896aa55Sjveta 	/*
69205f867c3Sgs 	 * If pcie bridge, check to see if link is enabled
6939896aa55Sjveta 	 */
69449fbdd30SErwin T Tsaur 	cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E);
69549fbdd30SErwin T Tsaur 	if (cap_ptr != -1) {
69605f867c3Sgs 		cmd_reg = pci_getw(bus, dev, func,
69705f867c3Sgs 		    (uint16_t)cap_ptr + PCIE_LINKCTL);
69805f867c3Sgs 		if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) {
69905f867c3Sgs 			dcmn_err(CE_NOTE,
70005f867c3Sgs 			    "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n",
70105f867c3Sgs 			    bus, dev, func);
70205f867c3Sgs 			return;
70305f867c3Sgs 		}
70405f867c3Sgs 	}
7059896aa55Sjveta 
70605f867c3Sgs 	subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
70705f867c3Sgs 	parbus = pci_bus_res[secbus].par_bus;
70805f867c3Sgs 	ASSERT(parbus == bus);
709707a5600Sgs 	cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM);
7109896aa55Sjveta 
7115af4ae46Sjveta 	/*
71205f867c3Sgs 	 * If we have a Cardbus bridge, but no bus space
7135af4ae46Sjveta 	 */
71405f867c3Sgs 	if (pci_bus_res[secbus].num_cbb != 0 &&
71505f867c3Sgs 	    pci_bus_res[secbus].bus_space == NULL) {
71605f867c3Sgs 		uchar_t range;
7175af4ae46Sjveta 
71805f867c3Sgs 		/* normally there are 2 buses under a cardbus bridge */
71905f867c3Sgs 		range = pci_bus_res[secbus].num_cbb * 2;
72005f867c3Sgs 
72105f867c3Sgs 		/*
72205f867c3Sgs 		 * Try to find and allocate a bus-range starting at subbus+1
72305f867c3Sgs 		 * from the parent of the PPB.
72405f867c3Sgs 		 */
72505f867c3Sgs 		for (; range != 0; range--) {
72605f867c3Sgs 			if (memlist_find_with_startaddr(
72705f867c3Sgs 			    &pci_bus_res[parbus].bus_space,
72805f867c3Sgs 			    subbus + 1, range, 1) != NULL)
72905f867c3Sgs 				break; /* find bus range resource at parent */
73005f867c3Sgs 		}
73105f867c3Sgs 		if (range != 0) {
73205f867c3Sgs 			memlist_insert(&pci_bus_res[secbus].bus_space,
73305f867c3Sgs 			    subbus + 1, range);
73405f867c3Sgs 			subbus = subbus + range;
73505f867c3Sgs 			pci_bus_res[secbus].sub_bus = subbus;
73605f867c3Sgs 			pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus);
73705f867c3Sgs 			add_bus_range_prop(secbus);
73805f867c3Sgs 
73905f867c3Sgs 			cmn_err(CE_NOTE, "!reprogram bus-range on ppb"
74005f867c3Sgs 			    "[%x/%x/%x]: %x ~ %x\n", bus, dev, func,
74105f867c3Sgs 			    secbus, subbus);
74205f867c3Sgs 		}
74305f867c3Sgs 	}
74405f867c3Sgs 
74505f867c3Sgs 	/*
74605f867c3Sgs 	 * Calculate required IO size
74705f867c3Sgs 	 * We are going to assign 512 bytes per bus. The size needs to be
74805f867c3Sgs 	 * 4K aligned and the maximum size is 16K.
74905f867c3Sgs 	 */
75005f867c3Sgs 	io_size = (subbus - secbus + 1) * 0x200;
75105f867c3Sgs 	io_size = (io_size + PPB_IO_ALIGNMENT) & (~(PPB_IO_ALIGNMENT - 1));
75205f867c3Sgs 	if (io_size > 0x4 * PPB_IO_ALIGNMENT)
75305f867c3Sgs 		io_size = 0x4 * PPB_IO_ALIGNMENT;
7545af4ae46Sjveta 	/*
75505f867c3Sgs 	 * Calculate required MEM size
75605f867c3Sgs 	 * We are going to assign 1M bytes per bus. The size needs to be
75705f867c3Sgs 	 * 1M aligned and the maximum size is 8M.
7585af4ae46Sjveta 	 */
75905f867c3Sgs 	mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT;
76005f867c3Sgs 	if (mem_size > 0x8 * PPB_MEM_ALIGNMENT)
76105f867c3Sgs 		mem_size = 0x8 * PPB_MEM_ALIGNMENT;
76205f867c3Sgs 
76305f867c3Sgs 	/* Subtractive bridge */
76405f867c3Sgs 	if (pci_bus_res[secbus].subtractive && prog_sub) {
76505f867c3Sgs 		/*
76605f867c3Sgs 		 * We program an arbitrary amount of I/O and memory resource
76705f867c3Sgs 		 * for the subtractive bridge so that child dynamic-resource-
76805f867c3Sgs 		 * allocating devices (such as Cardbus bridges) have a chance
76905f867c3Sgs 		 * of success.  Until we have full-tree resource rebalancing,
77005f867c3Sgs 		 * dynamic resource allocation (thru busra) only looks at the
77105f867c3Sgs 		 * parent bridge, so all PPBs must have some allocatable
77205f867c3Sgs 		 * resource.  For non-subtractive bridges, the resources come
77305f867c3Sgs 		 * from the base/limit register "windows", but subtractive
77405f867c3Sgs 		 * bridges often don't program those (since they don't need to).
77505f867c3Sgs 		 * If we put all the remaining resources on the subtractive
77605f867c3Sgs 		 * bridge, then peer non-subtractive bridges can't allocate
77705f867c3Sgs 		 * more space (even though this is probably most correct).
77805f867c3Sgs 		 * If we put the resources only on the parent, then allocations
77905f867c3Sgs 		 * from children of subtractive bridges will fail without
78005f867c3Sgs 		 * special-case code for bypassing the subtractive bridge.
78105f867c3Sgs 		 * This solution is the middle-ground temporary solution until
78205f867c3Sgs 		 * we have fully-capable resource allocation.
78305f867c3Sgs 		 */
78405f867c3Sgs 
78505f867c3Sgs 		/*
78605f867c3Sgs 		 * Add an arbitrary I/O resource to the subtractive PPB
78705f867c3Sgs 		 */
78805f867c3Sgs 		if (pci_bus_res[secbus].io_ports == NULL) {
78905f867c3Sgs 			addr = get_parbus_io_res(parbus, secbus, io_size,
79005f867c3Sgs 			    PPB_IO_ALIGNMENT);
79105f867c3Sgs 			if (addr) {
79205f867c3Sgs 				add_ppb_ranges_prop(secbus);
79305f867c3Sgs 				pci_bus_res[secbus].io_reprogram =
79405f867c3Sgs 				    pci_bus_res[parbus].io_reprogram;
79505f867c3Sgs 
79605f867c3Sgs 				cmn_err(CE_NOTE, "!add io-range on subtractive"
79705f867c3Sgs 				    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
79805f867c3Sgs 				    bus, dev, func, (uint32_t)addr,
79905f867c3Sgs 				    (uint32_t)addr + io_size - 1);
80005f867c3Sgs 			}
80105f867c3Sgs 		}
80205f867c3Sgs 		/*
80305f867c3Sgs 		 * Add an arbitrary memory resource to the subtractive PPB
80405f867c3Sgs 		 */
80505f867c3Sgs 		if (pci_bus_res[secbus].mem_space == NULL) {
80605f867c3Sgs 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
80705f867c3Sgs 			    PPB_MEM_ALIGNMENT);
80805f867c3Sgs 			if (addr) {
80905f867c3Sgs 				add_ppb_ranges_prop(secbus);
81005f867c3Sgs 				pci_bus_res[secbus].mem_reprogram =
81105f867c3Sgs 				    pci_bus_res[parbus].mem_reprogram;
81205f867c3Sgs 
81305f867c3Sgs 				cmn_err(CE_NOTE, "!add mem-range on "
81405f867c3Sgs 				    "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
81505f867c3Sgs 				    bus, dev, func, (uint32_t)addr,
81605f867c3Sgs 				    (uint32_t)addr + mem_size - 1);
81705f867c3Sgs 			}
81805f867c3Sgs 		}
81905f867c3Sgs 
82005f867c3Sgs 		goto cmd_enable;
8215af4ae46Sjveta 	}
82205f867c3Sgs 
82305f867c3Sgs 	/*
824707a5600Sgs 	 * Check to see if we need to reprogram I/O space, either because the
825707a5600Sgs 	 * parent bus needed reprogramming and so do we, or because I/O space is
826707a5600Sgs 	 * disabled in base/limit or command register.
82705f867c3Sgs 	 */
82805f867c3Sgs 	io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
82905f867c3Sgs 	io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
83005f867c3Sgs 	io_base = (io_base & 0xf0) << 8;
83105f867c3Sgs 	io_limit = ((io_limit & 0xf0) << 8) | 0xfff;
83205f867c3Sgs 
833707a5600Sgs 	if (pci_bus_res[parbus].io_reprogram || (io_base > io_limit) ||
834707a5600Sgs 	    (!(cmd_reg & PCI_COMM_IO))) {
83505f867c3Sgs 		if (pci_bus_res[secbus].io_ports_used) {
83605f867c3Sgs 			memlist_merge(&pci_bus_res[secbus].io_ports_used,
83705f867c3Sgs 			    &pci_bus_res[secbus].io_ports);
83805f867c3Sgs 		}
83905f867c3Sgs 		if (pci_bus_res[secbus].io_ports &&
84005f867c3Sgs 		    (!pci_bus_res[parbus].io_reprogram) &&
84105f867c3Sgs 		    (!pci_bus_res[parbus].subtractive)) {
84205f867c3Sgs 			/* rechoose old io ports info */
84305f867c3Sgs 			list = pci_bus_res[secbus].io_ports;
84405f867c3Sgs 			io_base = (uint_t)list->address;
84505f867c3Sgs 			/* 4K aligned */
84605f867c3Sgs 			io_base = io_base & (~(PPB_IO_ALIGNMENT - 1));
84705f867c3Sgs 			io_limit = (uint_t)(list->address + list->size);
84805f867c3Sgs 			while (list->next) {
84905f867c3Sgs 				list = list->next;
85005f867c3Sgs 				if ((list->address + list->size) > io_limit)
85105f867c3Sgs 					io_limit = (uint_t)
85205f867c3Sgs 					    (list->address + list->size);
85305f867c3Sgs 			}
85405f867c3Sgs 			io_limit = io_limit - 1;
85505f867c3Sgs 			/* 4K aligned */
85605f867c3Sgs 			io_limit = (io_limit + PPB_IO_ALIGNMENT) &
85705f867c3Sgs 			    (~(PPB_IO_ALIGNMENT - 1));
85805f867c3Sgs 			io_size = io_limit - io_base;
85905f867c3Sgs 			io_limit = io_limit - 1;
86005f867c3Sgs 			ASSERT(io_base <= io_limit);
86105f867c3Sgs 			memlist_free_all(&pci_bus_res[secbus].io_ports);
86205f867c3Sgs 			memlist_insert(&pci_bus_res[secbus].io_ports,
86305f867c3Sgs 			    io_base, io_size);
86405f867c3Sgs 			memlist_insert(&pci_bus_res[parbus].io_ports_used,
86505f867c3Sgs 			    io_base, io_size);
86605f867c3Sgs 			if (pci_bus_res[parbus].io_ports)
86705f867c3Sgs 				(void) memlist_remove(
86805f867c3Sgs 				    &pci_bus_res[parbus].io_ports,
86905f867c3Sgs 				    io_base, io_size);
87005f867c3Sgs 			pci_bus_res[secbus].io_reprogram = B_TRUE;
87105f867c3Sgs 		} else {
87205f867c3Sgs 			/* get new io ports from parent bus */
87305f867c3Sgs 			addr = get_parbus_io_res(parbus, secbus, io_size,
87405f867c3Sgs 			    PPB_IO_ALIGNMENT);
87505f867c3Sgs 			if (addr) {
87605f867c3Sgs 				io_base = addr;
87705f867c3Sgs 				io_limit = addr + io_size - 1;
87805f867c3Sgs 				pci_bus_res[secbus].io_reprogram = B_TRUE;
87905f867c3Sgs 			}
88005f867c3Sgs 		}
88105f867c3Sgs 		if (pci_bus_res[secbus].io_reprogram) {
88205f867c3Sgs 			/* reprogram PPB regs */
88305f867c3Sgs 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
88405f867c3Sgs 			    (uchar_t)((io_base>>8) & 0xf0));
88505f867c3Sgs 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
88605f867c3Sgs 			    (uchar_t)((io_limit>>8) & 0xf0));
88705f867c3Sgs 			pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
88805f867c3Sgs 			pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
88905f867c3Sgs 			add_ppb_ranges_prop(secbus);
89005f867c3Sgs 
89105f867c3Sgs 			cmn_err(CE_NOTE, "!reprogram io-range on"
89205f867c3Sgs 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
89305f867c3Sgs 			    bus, dev, func, io_base, io_limit);
89405f867c3Sgs 		}
8959896aa55Sjveta 	}
8969896aa55Sjveta 
8975af4ae46Sjveta 	/*
898707a5600Sgs 	 * Check memory space as we did I/O space.
8995af4ae46Sjveta 	 */
90005f867c3Sgs 	mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
90105f867c3Sgs 	mem_base = (mem_base & 0xfff0) << 16;
90205f867c3Sgs 	mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
903707a5600Sgs 	mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff;
904707a5600Sgs 
905707a5600Sgs 	if (pci_bus_res[parbus].mem_reprogram || (mem_base > mem_limit) ||
906707a5600Sgs 	    (!(cmd_reg & PCI_COMM_MAE))) {
90705f867c3Sgs 		if (pci_bus_res[secbus].mem_space_used) {
90805f867c3Sgs 			memlist_merge(&pci_bus_res[secbus].mem_space_used,
90905f867c3Sgs 			    &pci_bus_res[secbus].mem_space);
91005f867c3Sgs 		}
91105f867c3Sgs 		if (pci_bus_res[secbus].mem_space &&
91205f867c3Sgs 		    (!pci_bus_res[parbus].mem_reprogram) &&
91305f867c3Sgs 		    (!pci_bus_res[parbus].subtractive)) {
91405f867c3Sgs 			/* rechoose old mem resource */
91505f867c3Sgs 			list = pci_bus_res[secbus].mem_space;
91605f867c3Sgs 			mem_base = (uint_t)list->address;
91705f867c3Sgs 			/* 1M aligned */
91805f867c3Sgs 			mem_base = mem_base & (~0xfffff);
91905f867c3Sgs 			mem_limit = (uint_t)(list->address + list->size);
92005f867c3Sgs 			while (list->next) {
92105f867c3Sgs 				list = list->next;
92205f867c3Sgs 				if ((list->address + list->size) > mem_limit)
92305f867c3Sgs 					mem_limit = (uint_t)
92405f867c3Sgs 					    (list->address + list->size);
92505f867c3Sgs 			}
92605f867c3Sgs 			mem_limit = mem_limit - 1;
92705f867c3Sgs 			/* 1M aligned */
92805f867c3Sgs 			mem_limit = (mem_limit + PPB_MEM_ALIGNMENT) &
92905f867c3Sgs 			    (~(PPB_MEM_ALIGNMENT - 1));
93005f867c3Sgs 			mem_size = mem_limit - mem_base;
93105f867c3Sgs 			mem_limit = mem_limit - 1;
93205f867c3Sgs 			ASSERT(mem_base <= mem_limit);
93305f867c3Sgs 			memlist_free_all(&pci_bus_res[secbus].mem_space);
93405f867c3Sgs 			memlist_insert(&pci_bus_res[secbus].mem_space,
93505f867c3Sgs 			    mem_base, mem_size);
93605f867c3Sgs 			memlist_insert(&pci_bus_res[parbus].mem_space_used,
93705f867c3Sgs 			    mem_base, mem_size);
93805f867c3Sgs 			if (pci_bus_res[parbus].mem_space)
93905f867c3Sgs 				(void) memlist_remove(
94005f867c3Sgs 				    &pci_bus_res[parbus].mem_space,
94105f867c3Sgs 				    mem_base, mem_size);
94205f867c3Sgs 			pci_bus_res[secbus].mem_reprogram = B_TRUE;
94305f867c3Sgs 		} else {
94405f867c3Sgs 			/* get new mem resource from parent bus */
94505f867c3Sgs 			addr = get_parbus_mem_res(parbus, secbus, mem_size,
94605f867c3Sgs 			    PPB_MEM_ALIGNMENT);
94705f867c3Sgs 			if (addr) {
94805f867c3Sgs 				mem_base = addr;
94905f867c3Sgs 				mem_limit = addr + mem_size - 1;
95005f867c3Sgs 				pci_bus_res[secbus].mem_reprogram = B_TRUE;
95105f867c3Sgs 			}
95205f867c3Sgs 		}
95305f867c3Sgs 
95405f867c3Sgs 		if (pci_bus_res[secbus].mem_reprogram) {
95505f867c3Sgs 			/* reprogram PPB regs */
95605f867c3Sgs 			pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE,
95705f867c3Sgs 			    (uint16_t)((mem_base>>16) & 0xfff0));
95805f867c3Sgs 			pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT,
95905f867c3Sgs 			    (uint16_t)((mem_limit>>16) & 0xfff0));
96005f867c3Sgs 			add_ppb_ranges_prop(secbus);
96105f867c3Sgs 
96205f867c3Sgs 			cmn_err(CE_NOTE, "!reprogram mem-range on"
96305f867c3Sgs 			    " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n",
96405f867c3Sgs 			    bus, dev, func, mem_base, mem_limit);
96505f867c3Sgs 		}
96605f867c3Sgs 	}
96705f867c3Sgs 
96805f867c3Sgs cmd_enable:
96905f867c3Sgs 	if (pci_bus_res[secbus].io_ports)
97005f867c3Sgs 		cmd_reg |= PCI_COMM_IO | PCI_COMM_ME;
97105f867c3Sgs 	if (pci_bus_res[secbus].mem_space)
97205f867c3Sgs 		cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME;
97305f867c3Sgs 	pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg);
9749896aa55Sjveta }
9759896aa55Sjveta 
9767c478bd9Sstevel@tonic-gate void
9777c478bd9Sstevel@tonic-gate pci_reprogram(void)
9787c478bd9Sstevel@tonic-gate {
9797c478bd9Sstevel@tonic-gate 	int i, pci_reconfig = 1;
9807c478bd9Sstevel@tonic-gate 	char *onoff;
9817c478bd9Sstevel@tonic-gate 
98225145214Smyers 	/*
98325145214Smyers 	 * Excise phantom roots if possible
98425145214Smyers 	 */
98525145214Smyers 	pci_renumber_root_busses();
98625145214Smyers 
987fc396574Srw 	/* add bus-range property for root/peer bus nodes */
988fc396574Srw 	for (i = 0; i <= pci_bios_nbus; i++) {
989fc396574Srw 		if (pci_bus_res[i].par_bus == (uchar_t)-1) {
990fc396574Srw 			uchar_t subbus;
991fc396574Srw 			if (pci_root_subbus(i, &subbus) == AE_OK)
9929896aa55Sjveta 				pci_bus_res[i].sub_bus = subbus;
993fc396574Srw 			add_bus_range_prop(i);
994fc396574Srw 		}
99505f867c3Sgs 		/* setup bus range resource on each bus */
99605f867c3Sgs 		setup_bus_res(i);
997fc396574Srw 	}
998fc396574Srw 
9997c478bd9Sstevel@tonic-gate 	if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(),
10007c478bd9Sstevel@tonic-gate 	    DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) {
10017c478bd9Sstevel@tonic-gate 		if (strcmp(onoff, "off") == 0) {
10027c478bd9Sstevel@tonic-gate 			pci_reconfig = 0;
10037c478bd9Sstevel@tonic-gate 			cmn_err(CE_NOTE, "pci device reprogramming disabled");
10047c478bd9Sstevel@tonic-gate 		}
10057c478bd9Sstevel@tonic-gate 		ddi_prop_free(onoff);
10067c478bd9Sstevel@tonic-gate 	}
10077c478bd9Sstevel@tonic-gate 
1008aaba6dfeSmyers 	/* remove used-resources from PCI resource maps */
1009aaba6dfeSmyers 	remove_used_resources();
101005f867c3Sgs 	remove_subtractive_res();
101105f867c3Sgs 
101205f867c3Sgs 	/* reprogram the non-subtractive PPB */
101305f867c3Sgs 	if (pci_reconfig)
101405f867c3Sgs 		for (i = 0; i <= pci_bios_nbus; i++)
101505f867c3Sgs 			fix_ppb_res(i, B_FALSE);
1016aaba6dfeSmyers 
10177c478bd9Sstevel@tonic-gate 	for (i = 0; i <= pci_bios_nbus; i++) {
101805f867c3Sgs 		/* configure devices not configured by BIOS */
10199896aa55Sjveta 		if (pci_reconfig) {
102005f867c3Sgs 			/*
102105f867c3Sgs 			 * Reprogram the subtractive PPB. At this time, all its
102205f867c3Sgs 			 * siblings should have got their resources already.
102305f867c3Sgs 			 */
102405f867c3Sgs 			if (pci_bus_res[i].subtractive)
102505f867c3Sgs 				fix_ppb_res(i, B_TRUE);
10267c478bd9Sstevel@tonic-gate 			enumerate_bus_devs(i, CONFIG_NEW);
10279896aa55Sjveta 		}
10287c478bd9Sstevel@tonic-gate 		/* All dev programmed, so we can create available prop */
10297c478bd9Sstevel@tonic-gate 		add_bus_available_prop(i);
10307c478bd9Sstevel@tonic-gate 	}
10317c478bd9Sstevel@tonic-gate }
10327c478bd9Sstevel@tonic-gate 
10337c478bd9Sstevel@tonic-gate /*
10347c478bd9Sstevel@tonic-gate  * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0...
10357c478bd9Sstevel@tonic-gate  */
10367c478bd9Sstevel@tonic-gate static void
10377c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus)
10387c478bd9Sstevel@tonic-gate {
10397c478bd9Sstevel@tonic-gate 	int pci_regs[] = {0, 0, 0};
10407c478bd9Sstevel@tonic-gate 	dev_info_t *dip;
10417c478bd9Sstevel@tonic-gate 
10427c478bd9Sstevel@tonic-gate 	ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1);
10437c478bd9Sstevel@tonic-gate 
104405f867c3Sgs 	num_root_bus++;
10457c478bd9Sstevel@tonic-gate 	ndi_devi_alloc_sleep(ddi_root_node(), "pci",
1046fa9e4066Sahrens 	    (pnode_t)DEVI_SID_NODEID, &dip);
10477c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
10487c478bd9Sstevel@tonic-gate 	    "#address-cells", 3);
10497c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
10507c478bd9Sstevel@tonic-gate 	    "#size-cells", 2);
10517c478bd9Sstevel@tonic-gate 	pci_regs[0] = pci_bus_res[bus].root_addr;
10527c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
10537c478bd9Sstevel@tonic-gate 	    "reg", (int *)pci_regs, 3);
10547c478bd9Sstevel@tonic-gate 
105570025d76Sjohnny 	/*
105670025d76Sjohnny 	 * If system has PCIe bus, then create different properties
105770025d76Sjohnny 	 */
105870025d76Sjohnny 	if (create_pcie_root_bus(bus, dip) == B_FALSE)
105970025d76Sjohnny 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
106070025d76Sjohnny 		    "device_type", "pci");
106170025d76Sjohnny 
10627c478bd9Sstevel@tonic-gate 	(void) ndi_devi_bind_driver(dip, 0);
10637c478bd9Sstevel@tonic-gate 	pci_bus_res[bus].dip = dip;
10647c478bd9Sstevel@tonic-gate 	pci_bus_res[bus].pmem_space = find_bus_res(bus, PREFETCH_TYPE);
10657c478bd9Sstevel@tonic-gate 	pci_bus_res[bus].mem_space = find_bus_res(bus, MEM_TYPE);
10667c478bd9Sstevel@tonic-gate 	pci_bus_res[bus].io_ports = find_bus_res(bus, IO_TYPE);
10677c478bd9Sstevel@tonic-gate 
10687c478bd9Sstevel@tonic-gate 	if (bus != 0)
10697c478bd9Sstevel@tonic-gate 		return;
10707c478bd9Sstevel@tonic-gate 
10717c478bd9Sstevel@tonic-gate 	/*
10727c478bd9Sstevel@tonic-gate 	 * Special treatment of bus 0:
10737c478bd9Sstevel@tonic-gate 	 * If no resource from MPSPEC/HRT, copy pcimem from boot
1074aaba6dfeSmyers 	 * and make I/O space the entire range starting at 0x100. There
1075aaba6dfeSmyers 	 * is no difference between prefetchable memory or not.
10767c478bd9Sstevel@tonic-gate 	 */
10777c478bd9Sstevel@tonic-gate 	if (pci_bus_res[0].mem_space == NULL)
10787c478bd9Sstevel@tonic-gate 		pci_bus_res[0].mem_space =
10797c478bd9Sstevel@tonic-gate 		    memlist_dup(bootops->boot_mem->pcimem);
1080aaba6dfeSmyers 	/* Exclude 0x00 to 0xff of the I/O space, used by all PCs */
10817c478bd9Sstevel@tonic-gate 	if (pci_bus_res[0].io_ports == NULL)
10825af4ae46Sjveta 		memlist_insert(&pci_bus_res[0].io_ports, 0x100, 0xffff);
10837c478bd9Sstevel@tonic-gate }
10847c478bd9Sstevel@tonic-gate 
10857c478bd9Sstevel@tonic-gate /*
10867c478bd9Sstevel@tonic-gate  * For any fixed configuration (often compatability) pci devices
10877c478bd9Sstevel@tonic-gate  * and those with their own expansion rom, create device nodes
10887c478bd9Sstevel@tonic-gate  * to hold the already configured device details.
10897c478bd9Sstevel@tonic-gate  */
10907c478bd9Sstevel@tonic-gate void
10917c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op)
10927c478bd9Sstevel@tonic-gate {
10937c478bd9Sstevel@tonic-gate 	uchar_t dev, func, nfunc, header;
10947c478bd9Sstevel@tonic-gate 	ushort_t venid;
109505f867c3Sgs 	struct pci_devfunc *devlist = NULL, *entry;
10967c478bd9Sstevel@tonic-gate 
10977c478bd9Sstevel@tonic-gate 	if (config_op == CONFIG_NEW) {
10987c478bd9Sstevel@tonic-gate 		dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus);
1099bd87be88Ssethg 	} else if (config_op == CONFIG_FIX) {
1100bd87be88Ssethg 		dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus);
11017c478bd9Sstevel@tonic-gate 	} else
11027c478bd9Sstevel@tonic-gate 		dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus);
11037c478bd9Sstevel@tonic-gate 
11047c478bd9Sstevel@tonic-gate 	for (dev = 0; dev < max_dev_pci; dev++) {
11057c478bd9Sstevel@tonic-gate 		nfunc = 1;
11067c478bd9Sstevel@tonic-gate 		for (func = 0; func < nfunc; func++) {
11077c478bd9Sstevel@tonic-gate 
11087c478bd9Sstevel@tonic-gate 			dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x",
11097c478bd9Sstevel@tonic-gate 			    dev, func);
11107c478bd9Sstevel@tonic-gate 
11117c478bd9Sstevel@tonic-gate 			venid = pci_getw(bus, dev, func, PCI_CONF_VENID);
1112bd87be88Ssethg 
11137c478bd9Sstevel@tonic-gate 			if ((venid == 0xffff) || (venid == 0)) {
11147c478bd9Sstevel@tonic-gate 				/* no function at this address */
11157c478bd9Sstevel@tonic-gate 				continue;
11167c478bd9Sstevel@tonic-gate 			}
11177c478bd9Sstevel@tonic-gate 
11187c478bd9Sstevel@tonic-gate 			header = pci_getb(bus, dev, func, PCI_CONF_HEADER);
11197c478bd9Sstevel@tonic-gate 			if (header == 0xff) {
11207c478bd9Sstevel@tonic-gate 				continue; /* illegal value */
11217c478bd9Sstevel@tonic-gate 			}
11227c478bd9Sstevel@tonic-gate 
11237c478bd9Sstevel@tonic-gate 			/*
11247c478bd9Sstevel@tonic-gate 			 * according to some mail from Microsoft posted
11257c478bd9Sstevel@tonic-gate 			 * to the pci-drivers alias, their only requirement
11267c478bd9Sstevel@tonic-gate 			 * for a multifunction device is for the 1st
11277c478bd9Sstevel@tonic-gate 			 * function to have to PCI_HEADER_MULTI bit set.
11287c478bd9Sstevel@tonic-gate 			 */
11297c478bd9Sstevel@tonic-gate 			if ((func == 0) && (header & PCI_HEADER_MULTI)) {
11307c478bd9Sstevel@tonic-gate 				nfunc = 8;
11317c478bd9Sstevel@tonic-gate 			}
113246e9e839Smyers 
113305f867c3Sgs 			if (config_op == CONFIG_FIX ||
113405f867c3Sgs 			    config_op == CONFIG_INFO) {
1135ebf3afa8Sdmick 				/*
1136ebf3afa8Sdmick 				 * Create the node, unconditionally, on the
1137ebf3afa8Sdmick 				 * first pass only.  It may still need
1138ebf3afa8Sdmick 				 * resource assignment, which will be
1139ebf3afa8Sdmick 				 * done on the second, CONFIG_NEW, pass.
1140ebf3afa8Sdmick 				 */
114105f867c3Sgs 				process_devfunc(bus, dev, func, header,
1142ebf3afa8Sdmick 				    venid, config_op);
1143db063408Sdmick 
11447c478bd9Sstevel@tonic-gate 			}
11457c478bd9Sstevel@tonic-gate 		}
11467c478bd9Sstevel@tonic-gate 	}
11477c478bd9Sstevel@tonic-gate 
11487c478bd9Sstevel@tonic-gate 	if (config_op == CONFIG_NEW) {
11497c478bd9Sstevel@tonic-gate 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
11507c478bd9Sstevel@tonic-gate 		while (devlist) {
11517c478bd9Sstevel@tonic-gate 			entry = devlist;
11527c478bd9Sstevel@tonic-gate 			devlist = entry->next;
115305f867c3Sgs 			if (entry->reprogram ||
115405f867c3Sgs 			    pci_bus_res[bus].io_reprogram ||
115505f867c3Sgs 			    pci_bus_res[bus].mem_reprogram) {
115605f867c3Sgs 				/* reprogram device(s) */
115705f867c3Sgs 				(void) add_reg_props(entry->dip, bus,
115805f867c3Sgs 				    entry->dev, entry->func, CONFIG_NEW, 0);
115905f867c3Sgs 			}
11607c478bd9Sstevel@tonic-gate 			kmem_free(entry, sizeof (*entry));
11617c478bd9Sstevel@tonic-gate 		}
11627c478bd9Sstevel@tonic-gate 		pci_bus_res[bus].privdata = NULL;
11637c478bd9Sstevel@tonic-gate 	}
11647c478bd9Sstevel@tonic-gate }
11657c478bd9Sstevel@tonic-gate 
11667c478bd9Sstevel@tonic-gate static int
11677c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid,
11687c478bd9Sstevel@tonic-gate     ushort_t subvenid, ushort_t subdevid)
11697c478bd9Sstevel@tonic-gate {
11707c478bd9Sstevel@tonic-gate 	static int prop_exist = -1;
11717c478bd9Sstevel@tonic-gate 	static char *pciide_str;
11727c478bd9Sstevel@tonic-gate 	char compat[32];
11737c478bd9Sstevel@tonic-gate 
11747c478bd9Sstevel@tonic-gate 	if (prop_exist == -1) {
11757c478bd9Sstevel@tonic-gate 		prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY,
11767c478bd9Sstevel@tonic-gate 		    ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide",
11777c478bd9Sstevel@tonic-gate 		    &pciide_str) == DDI_SUCCESS);
11787c478bd9Sstevel@tonic-gate 	}
11797c478bd9Sstevel@tonic-gate 
11807c478bd9Sstevel@tonic-gate 	if (!prop_exist)
11817c478bd9Sstevel@tonic-gate 		return (0);
11827c478bd9Sstevel@tonic-gate 
11837c478bd9Sstevel@tonic-gate 	/* compare property value against various forms of compatible */
11847c478bd9Sstevel@tonic-gate 	if (subvenid) {
11857c478bd9Sstevel@tonic-gate 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x",
11867c478bd9Sstevel@tonic-gate 		    venid, devid, subvenid, subdevid, revid);
11877c478bd9Sstevel@tonic-gate 		if (strcmp(pciide_str, compat) == 0)
11887c478bd9Sstevel@tonic-gate 			return (1);
11897c478bd9Sstevel@tonic-gate 
11907c478bd9Sstevel@tonic-gate 		(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x",
11917c478bd9Sstevel@tonic-gate 		    venid, devid, subvenid, subdevid);
11927c478bd9Sstevel@tonic-gate 		if (strcmp(pciide_str, compat) == 0)
11937c478bd9Sstevel@tonic-gate 			return (1);
11947c478bd9Sstevel@tonic-gate 
11957c478bd9Sstevel@tonic-gate 		(void) snprintf(compat, sizeof (compat), "pci%x,%x",
11967c478bd9Sstevel@tonic-gate 		    subvenid, subdevid);
11977c478bd9Sstevel@tonic-gate 		if (strcmp(pciide_str, compat) == 0)
11987c478bd9Sstevel@tonic-gate 			return (1);
11997c478bd9Sstevel@tonic-gate 	}
12007c478bd9Sstevel@tonic-gate 	(void) snprintf(compat, sizeof (compat), "pci%x,%x.%x",
12017c478bd9Sstevel@tonic-gate 	    venid, devid, revid);
12027c478bd9Sstevel@tonic-gate 	if (strcmp(pciide_str, compat) == 0)
12037c478bd9Sstevel@tonic-gate 		return (1);
12047c478bd9Sstevel@tonic-gate 
12057c478bd9Sstevel@tonic-gate 	(void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid);
12067c478bd9Sstevel@tonic-gate 	if (strcmp(pciide_str, compat) == 0)
12077c478bd9Sstevel@tonic-gate 		return (1);
12087c478bd9Sstevel@tonic-gate 
12097c478bd9Sstevel@tonic-gate 	return (0);
12107c478bd9Sstevel@tonic-gate }
12117c478bd9Sstevel@tonic-gate 
12127c478bd9Sstevel@tonic-gate static int
12137c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid,
12147c478bd9Sstevel@tonic-gate     ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid)
12157c478bd9Sstevel@tonic-gate {
12167c478bd9Sstevel@tonic-gate 	struct ide_table {	/* table for PCI_MASS_OTHER */
12177c478bd9Sstevel@tonic-gate 		ushort_t venid;
12187c478bd9Sstevel@tonic-gate 		ushort_t devid;
12197c478bd9Sstevel@tonic-gate 	} *entry;
12207c478bd9Sstevel@tonic-gate 
1221334edc48Sml 	/* XXX SATA and other devices: need a way to add dynamically */
12227c478bd9Sstevel@tonic-gate 	static struct ide_table ide_other[] = {
12237c478bd9Sstevel@tonic-gate 		{0x1095, 0x3112},
12247c478bd9Sstevel@tonic-gate 		{0x1095, 0x3114},
12257c478bd9Sstevel@tonic-gate 		{0x1095, 0x3512},
1226d01a0451Stt 		{0x1095, 0x680},	/* Sil0680 */
1227334edc48Sml 		{0x1283, 0x8211},	/* ITE 8211F is subcl PCI_MASS_OTHER */
12287c478bd9Sstevel@tonic-gate 		{0, 0}
12297c478bd9Sstevel@tonic-gate 	};
12307c478bd9Sstevel@tonic-gate 
12317c478bd9Sstevel@tonic-gate 	if (basecl != PCI_CLASS_MASS)
12327c478bd9Sstevel@tonic-gate 		return (0);
12337c478bd9Sstevel@tonic-gate 
12347c478bd9Sstevel@tonic-gate 	if (subcl == PCI_MASS_IDE) {
12357c478bd9Sstevel@tonic-gate 		return (1);
12367c478bd9Sstevel@tonic-gate 	}
12377c478bd9Sstevel@tonic-gate 
1238d01a0451Stt 	if (check_pciide_prop(revid, venid, devid, subvenid, subdevid))
1239d01a0451Stt 		return (1);
1240d01a0451Stt 
12417c478bd9Sstevel@tonic-gate 	if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) {
12427c478bd9Sstevel@tonic-gate 		return (0);
12437c478bd9Sstevel@tonic-gate 	}
12447c478bd9Sstevel@tonic-gate 
12457c478bd9Sstevel@tonic-gate 	entry = &ide_other[0];
12467c478bd9Sstevel@tonic-gate 	while (entry->venid) {
12477c478bd9Sstevel@tonic-gate 		if (entry->venid == venid && entry->devid == devid)
12487c478bd9Sstevel@tonic-gate 			return (1);
12497c478bd9Sstevel@tonic-gate 		entry++;
12507c478bd9Sstevel@tonic-gate 	}
1251d01a0451Stt 	return (0);
12527c478bd9Sstevel@tonic-gate }
12537c478bd9Sstevel@tonic-gate 
12547c478bd9Sstevel@tonic-gate static int
12557c478bd9Sstevel@tonic-gate is_display(uint_t classcode)
12567c478bd9Sstevel@tonic-gate {
12577c478bd9Sstevel@tonic-gate 	static uint_t disp_classes[] = {
12587c478bd9Sstevel@tonic-gate 		0x000100,
12597c478bd9Sstevel@tonic-gate 		0x030000,
12607c478bd9Sstevel@tonic-gate 		0x030001
12617c478bd9Sstevel@tonic-gate 	};
12627c478bd9Sstevel@tonic-gate 	int i, nclasses = sizeof (disp_classes) / sizeof (uint_t);
12637c478bd9Sstevel@tonic-gate 
12647c478bd9Sstevel@tonic-gate 	for (i = 0; i < nclasses; i++) {
12657c478bd9Sstevel@tonic-gate 		if (classcode == disp_classes[i])
12667c478bd9Sstevel@tonic-gate 			return (1);
12677c478bd9Sstevel@tonic-gate 	}
12687c478bd9Sstevel@tonic-gate 	return (0);
12697c478bd9Sstevel@tonic-gate }
12707c478bd9Sstevel@tonic-gate 
1271bd87be88Ssethg static void
1272bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn,
1273bd87be88Ssethg     void (*undofn)(uint8_t, uint8_t, uint8_t))
1274bd87be88Ssethg {
1275bd87be88Ssethg 	struct pci_fixundo *newundo;
1276bd87be88Ssethg 
1277bd87be88Ssethg 	newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP);
1278bd87be88Ssethg 
1279bd87be88Ssethg 	/*
1280bd87be88Ssethg 	 * Adding an item to this list means that we must turn its NMIENABLE
1281bd87be88Ssethg 	 * bit back on at a later time.
1282bd87be88Ssethg 	 */
1283bd87be88Ssethg 	newundo->bus = bus;
1284bd87be88Ssethg 	newundo->dev = dev;
1285bd87be88Ssethg 	newundo->fn = fn;
1286bd87be88Ssethg 	newundo->undofn = undofn;
1287bd87be88Ssethg 	newundo->next = undolist;
1288bd87be88Ssethg 
1289bd87be88Ssethg 	/* add to the undo list in LIFO order */
1290bd87be88Ssethg 	undolist = newundo;
1291bd87be88Ssethg }
1292bd87be88Ssethg 
1293bd87be88Ssethg void
1294bd87be88Ssethg add_pci_fixes(void)
1295bd87be88Ssethg {
1296bd87be88Ssethg 	int i;
1297bd87be88Ssethg 
1298bd87be88Ssethg 	for (i = 0; i <= pci_bios_nbus; i++) {
1299bd87be88Ssethg 		/*
1300bd87be88Ssethg 		 * For each bus, apply needed fixes to the appropriate devices.
1301bd87be88Ssethg 		 * This must be done before the main enumeration loop because
1302bd87be88Ssethg 		 * some fixes must be applied to devices normally encountered
1303bd87be88Ssethg 		 * later in the pci scan (e.g. if a fix to device 7 must be
1304bd87be88Ssethg 		 * applied before scanning device 6, applying fixes in the
1305bd87be88Ssethg 		 * normal enumeration loop would obviously be too late).
1306bd87be88Ssethg 		 */
1307bd87be88Ssethg 		enumerate_bus_devs(i, CONFIG_FIX);
1308bd87be88Ssethg 	}
1309bd87be88Ssethg }
1310bd87be88Ssethg 
1311bd87be88Ssethg void
1312bd87be88Ssethg undo_pci_fixes(void)
1313bd87be88Ssethg {
1314bd87be88Ssethg 	struct pci_fixundo *nextundo;
1315bd87be88Ssethg 	uint8_t bus, dev, fn;
1316bd87be88Ssethg 
1317bd87be88Ssethg 	/*
1318bd87be88Ssethg 	 * All fixes in the undo list are performed unconditionally.  Future
1319bd87be88Ssethg 	 * fixes may require selective undo.
1320bd87be88Ssethg 	 */
1321bd87be88Ssethg 	while (undolist != NULL) {
1322bd87be88Ssethg 
1323bd87be88Ssethg 		bus = undolist->bus;
1324bd87be88Ssethg 		dev = undolist->dev;
1325bd87be88Ssethg 		fn = undolist->fn;
1326bd87be88Ssethg 
1327bd87be88Ssethg 		(*(undolist->undofn))(bus, dev, fn);
1328bd87be88Ssethg 
1329bd87be88Ssethg 		nextundo = undolist->next;
1330bd87be88Ssethg 		kmem_free(undolist, sizeof (struct pci_fixundo));
1331bd87be88Ssethg 		undolist = nextundo;
1332bd87be88Ssethg 	}
1333bd87be88Ssethg }
1334bd87be88Ssethg 
1335bd87be88Ssethg static void
1336bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn)
1337bd87be88Ssethg {
1338bd87be88Ssethg 	uint8_t val8;
1339bd87be88Ssethg 
1340bd87be88Ssethg 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1341bd87be88Ssethg 	/*
1342bd87be88Ssethg 	 * The NMIONERR bit is turned back on to allow the SMM BIOS
1343bd87be88Ssethg 	 * to handle more critical PCI errors (e.g. PERR#).
1344bd87be88Ssethg 	 */
1345bd87be88Ssethg 	val8 |= AMD8111_ENABLENMI;
1346bd87be88Ssethg 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1347bd87be88Ssethg }
1348bd87be88Ssethg 
1349bd87be88Ssethg static void
1350bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn)
1351bd87be88Ssethg {
1352bd87be88Ssethg 	uint8_t val8;
1353bd87be88Ssethg 
1354bd87be88Ssethg 	val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1);
1355bd87be88Ssethg 
1356bd87be88Ssethg 	if ((val8 & AMD8111_ENABLENMI) == 0)
1357bd87be88Ssethg 		return;
1358bd87be88Ssethg 
1359bd87be88Ssethg 	/*
1360bd87be88Ssethg 	 * We reset NMIONERR in the LPC because master-abort on the PCI
1361bd87be88Ssethg 	 * bridge side of the 8111 will cause NMI, which might cause SMI,
1362bd87be88Ssethg 	 * which sometimes prevents all devices from being enumerated.
1363bd87be88Ssethg 	 */
1364bd87be88Ssethg 	val8 &= ~AMD8111_ENABLENMI;
1365bd87be88Ssethg 
1366bd87be88Ssethg 	pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8);
1367bd87be88Ssethg 
1368bd87be88Ssethg 	add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix);
1369bd87be88Ssethg }
1370bd87be88Ssethg 
1371c8711d4dSgs static void
1372c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func)
1373c8711d4dSgs {
1374c8711d4dSgs 	uint16_t status;
1375c8711d4dSgs 	uint8_t header;
1376c8711d4dSgs 	uint8_t cap_ptr;
1377c8711d4dSgs 	uint8_t cap_id;
1378c8711d4dSgs 	uint16_t pmcsr;
1379c8711d4dSgs 
1380c8711d4dSgs 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
1381c8711d4dSgs 	if (!(status & PCI_STAT_CAP))
1382c8711d4dSgs 		return;	/* No capabilities list */
1383c8711d4dSgs 
1384c8711d4dSgs 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
1385c8711d4dSgs 	if (header == PCI_HEADER_CARDBUS)
1386c8711d4dSgs 		cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_RESERVED1);
1387c8711d4dSgs 	else
1388c8711d4dSgs 		cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR);
1389c8711d4dSgs 	/*
1390c8711d4dSgs 	 * Walk the capabilities list searching for a PM entry.
1391c8711d4dSgs 	 */
1392c8711d4dSgs 	while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) {
1393c8711d4dSgs 		cap_ptr &= PCI_CAP_PTR_MASK;
1394c8711d4dSgs 		cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID);
1395c8711d4dSgs 		if (cap_id == PCI_CAP_ID_PM) {
1396c8711d4dSgs 			pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR);
1397c8711d4dSgs 			pmcsr &= ~(PCI_PMCSR_STATE_MASK);
1398c8711d4dSgs 			pmcsr |= PCI_PMCSR_D0; /* D0 state */
1399c8711d4dSgs 			pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr);
1400c8711d4dSgs 			break;
1401c8711d4dSgs 		}
1402c8711d4dSgs 		cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR);
1403c8711d4dSgs 	}
1404c8711d4dSgs 
1405c8711d4dSgs }
1406c8711d4dSgs 
140705f867c3Sgs static void
1408bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header,
14097c478bd9Sstevel@tonic-gate     ushort_t vendorid, int config_op)
14107c478bd9Sstevel@tonic-gate {
14117c478bd9Sstevel@tonic-gate 	char nodename[32], unitaddr[5];
14127c478bd9Sstevel@tonic-gate 	dev_info_t *dip;
1413c8589f13Ssethg 	uchar_t basecl, subcl, progcl, intr, revid;
14147c478bd9Sstevel@tonic-gate 	ushort_t subvenid, subdevid, status;
141570025d76Sjohnny 	ushort_t slot_num;
14167c478bd9Sstevel@tonic-gate 	uint_t classcode, revclass;
14178d483882Smlf 	int reprogram = 0, pciide = 0;
14187c478bd9Sstevel@tonic-gate 	int power[2] = {1, 1};
141970025d76Sjohnny 	int pciex = 0;
142070025d76Sjohnny 	ushort_t is_pci_bridge = 0;
142105f867c3Sgs 	struct pci_devfunc *devlist = NULL, *entry = NULL;
142286c1f4dcSVikram Hegde 	iommu_private_t *private;
1423*94f1124eSVikram Hegde 	gfx_entry_t *gfxp;
14247c478bd9Sstevel@tonic-gate 
14257c478bd9Sstevel@tonic-gate 	ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID);
14267c478bd9Sstevel@tonic-gate 
14277c478bd9Sstevel@tonic-gate 	switch (header & PCI_HEADER_TYPE_M) {
14287c478bd9Sstevel@tonic-gate 	case PCI_HEADER_ZERO:
14297c478bd9Sstevel@tonic-gate 		subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID);
14307c478bd9Sstevel@tonic-gate 		subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID);
14317c478bd9Sstevel@tonic-gate 		break;
14327c478bd9Sstevel@tonic-gate 	case PCI_HEADER_CARDBUS:
14337c478bd9Sstevel@tonic-gate 		subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID);
14347c478bd9Sstevel@tonic-gate 		subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID);
143505f867c3Sgs 		/* Record the # of cardbus bridges found on the bus */
143605f867c3Sgs 		if (config_op == CONFIG_INFO)
143705f867c3Sgs 			pci_bus_res[bus].num_cbb++;
14387c478bd9Sstevel@tonic-gate 		break;
14397c478bd9Sstevel@tonic-gate 	default:
14407c478bd9Sstevel@tonic-gate 		subvenid = 0;
14417c478bd9Sstevel@tonic-gate 		subdevid = 0;
14427c478bd9Sstevel@tonic-gate 		break;
14437c478bd9Sstevel@tonic-gate 	}
14447c478bd9Sstevel@tonic-gate 
1445bd87be88Ssethg 	if (config_op == CONFIG_FIX) {
1446bd87be88Ssethg 		if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) {
1447bd87be88Ssethg 			pci_fix_amd8111(bus, dev, func);
1448bd87be88Ssethg 		}
144905f867c3Sgs 		return;
1450bd87be88Ssethg 	}
1451bd87be88Ssethg 
14527c478bd9Sstevel@tonic-gate 	/* XXX should be use generic names? derive from class? */
14537c478bd9Sstevel@tonic-gate 	revclass = pci_getl(bus, dev, func, PCI_CONF_REVID);
14547c478bd9Sstevel@tonic-gate 	classcode = revclass >> 8;
14557c478bd9Sstevel@tonic-gate 	revid = revclass & 0xff;
14567c478bd9Sstevel@tonic-gate 
14577c478bd9Sstevel@tonic-gate 	/* figure out if this is pci-ide */
14587c478bd9Sstevel@tonic-gate 	basecl = classcode >> 16;
14597c478bd9Sstevel@tonic-gate 	subcl = (classcode >> 8) & 0xff;
1460c8589f13Ssethg 	progcl = classcode & 0xff;
14617c478bd9Sstevel@tonic-gate 
14628d483882Smlf 
14638d483882Smlf 	if (is_display(classcode))
14647c478bd9Sstevel@tonic-gate 		(void) snprintf(nodename, sizeof (nodename), "display");
14657c478bd9Sstevel@tonic-gate 	else if (subvenid != 0)
14667c478bd9Sstevel@tonic-gate 		(void) snprintf(nodename, sizeof (nodename),
14677c478bd9Sstevel@tonic-gate 		    "pci%x,%x", subvenid, subdevid);
14687c478bd9Sstevel@tonic-gate 	else
14697c478bd9Sstevel@tonic-gate 		(void) snprintf(nodename, sizeof (nodename),
14707c478bd9Sstevel@tonic-gate 		    "pci%x,%x", vendorid, deviceid);
14717c478bd9Sstevel@tonic-gate 
14727c478bd9Sstevel@tonic-gate 	/* make sure parent bus dip has been created */
14737c478bd9Sstevel@tonic-gate 	if (pci_bus_res[bus].dip == NULL) {
14747c478bd9Sstevel@tonic-gate 		create_root_bus_dip(bus);
14757c478bd9Sstevel@tonic-gate 	}
14767c478bd9Sstevel@tonic-gate 
14777c478bd9Sstevel@tonic-gate 	ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename,
14787c478bd9Sstevel@tonic-gate 	    DEVI_SID_NODEID, &dip);
14797c478bd9Sstevel@tonic-gate 
148000d0963fSdilpreet 	if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num,
148100d0963fSdilpreet 	    &is_pci_bridge) == B_TRUE)
148200d0963fSdilpreet 		pciex = 1;
148300d0963fSdilpreet 
14847c478bd9Sstevel@tonic-gate 	/* add properties */
14857c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid);
14867c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid);
14877c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid);
14887c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
14897c478bd9Sstevel@tonic-gate 	    "class-code", classcode);
14907c478bd9Sstevel@tonic-gate 	if (func == 0)
14917c478bd9Sstevel@tonic-gate 		(void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev);
14927c478bd9Sstevel@tonic-gate 	else
14937c478bd9Sstevel@tonic-gate 		(void) snprintf(unitaddr, sizeof (unitaddr),
14947c478bd9Sstevel@tonic-gate 		    "%x,%x", dev, func);
14957c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
14967c478bd9Sstevel@tonic-gate 	    "unit-address", unitaddr);
14977c478bd9Sstevel@tonic-gate 
1498ebf3afa8Sdmick 	/* add device_type for display nodes */
1499ebf3afa8Sdmick 	if (is_display(classcode)) {
1500ebf3afa8Sdmick 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
1501ebf3afa8Sdmick 		    "device_type", "display");
1502ebf3afa8Sdmick 	}
15037c478bd9Sstevel@tonic-gate 	/* add special stuff for header type */
15047c478bd9Sstevel@tonic-gate 	if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) {
15057c478bd9Sstevel@tonic-gate 		uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G);
15067c478bd9Sstevel@tonic-gate 		uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L);
15077c478bd9Sstevel@tonic-gate 
15087c478bd9Sstevel@tonic-gate 		if (subvenid != 0) {
15097c478bd9Sstevel@tonic-gate 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
15107c478bd9Sstevel@tonic-gate 			    "subsystem-id", subdevid);
15117c478bd9Sstevel@tonic-gate 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
15127c478bd9Sstevel@tonic-gate 			    "subsystem-vendor-id", subvenid);
15137c478bd9Sstevel@tonic-gate 		}
151470025d76Sjohnny 		if (!pciex)
151570025d76Sjohnny 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
151670025d76Sjohnny 			    "min-grant", mingrant);
151770025d76Sjohnny 		if (!pciex)
151870025d76Sjohnny 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
151970025d76Sjohnny 			    "max-latency", maxlatency);
15207c478bd9Sstevel@tonic-gate 	}
15217c478bd9Sstevel@tonic-gate 
15227c478bd9Sstevel@tonic-gate 	/* interrupt, record if not 0 */
15237c478bd9Sstevel@tonic-gate 	intr = pci_getb(bus, dev, func, PCI_CONF_IPIN);
15247c478bd9Sstevel@tonic-gate 	if (intr != 0)
15257c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
15267c478bd9Sstevel@tonic-gate 		    "interrupts", intr);
15277c478bd9Sstevel@tonic-gate 
15287c478bd9Sstevel@tonic-gate 	/*
15297c478bd9Sstevel@tonic-gate 	 * Add support for 133 mhz pci eventually
15307c478bd9Sstevel@tonic-gate 	 */
15317c478bd9Sstevel@tonic-gate 	status = pci_getw(bus, dev, func, PCI_CONF_STAT);
15327c478bd9Sstevel@tonic-gate 
15337c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
15347c478bd9Sstevel@tonic-gate 	    "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9);
153570025d76Sjohnny 	if (!pciex && (status & PCI_STAT_FBBC))
15367c478bd9Sstevel@tonic-gate 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
15377c478bd9Sstevel@tonic-gate 		    "fast-back-to-back");
153870025d76Sjohnny 	if (!pciex && (status & PCI_STAT_66MHZ))
15397c478bd9Sstevel@tonic-gate 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
15407c478bd9Sstevel@tonic-gate 		    "66mhz-capable");
15417c478bd9Sstevel@tonic-gate 	if (status & PCI_STAT_UDF)
15427c478bd9Sstevel@tonic-gate 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip,
15437c478bd9Sstevel@tonic-gate 		    "udf-supported");
1544d57b3b3dSprasad 	if (pciex && slot_num) {
154570025d76Sjohnny 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
154670025d76Sjohnny 		    "physical-slot#", slot_num);
1547d57b3b3dSprasad 		if (!is_pci_bridge)
1548d57b3b3dSprasad 			pciex_slot_names_prop(dip, slot_num);
1549d57b3b3dSprasad 	}
15507c478bd9Sstevel@tonic-gate 
15517c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
15527c478bd9Sstevel@tonic-gate 	    "power-consumption", power, 2);
15537c478bd9Sstevel@tonic-gate 
1554c8711d4dSgs 	/* Set the device PM state to D0 */
1555c8711d4dSgs 	set_devpm_d0(bus, dev, func);
1556c8711d4dSgs 
155770025d76Sjohnny 	if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI))
155849fbdd30SErwin T Tsaur 		add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge);
155905f867c3Sgs 	else {
156005f867c3Sgs 		/*
156105f867c3Sgs 		 * Record the non-PPB devices on the bus for possible
156205f867c3Sgs 		 * reprogramming at 2nd bus enumeration.
156305f867c3Sgs 		 * Note: PPB reprogramming is done in fix_ppb_res()
156405f867c3Sgs 		 */
156505f867c3Sgs 		devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata;
156605f867c3Sgs 		entry = kmem_zalloc(sizeof (*entry), KM_SLEEP);
156705f867c3Sgs 		entry->dip = dip;
156805f867c3Sgs 		entry->dev = dev;
156905f867c3Sgs 		entry->func = func;
157005f867c3Sgs 		entry->next = devlist;
157105f867c3Sgs 		pci_bus_res[bus].privdata = entry;
157205f867c3Sgs 	}
157370025d76Sjohnny 
1574c8589f13Ssethg 	if (config_op == CONFIG_INFO &&
1575c8589f13Ssethg 	    IS_CLASS_IOAPIC(basecl, subcl, progcl)) {
1576c8589f13Ssethg 		create_ioapic_node(bus, dev, func, vendorid, deviceid);
1577c8589f13Ssethg 	}
1578c8589f13Ssethg 
157970025d76Sjohnny 	/* check for ck8-04 based PCI ISA bridge only */
158070025d76Sjohnny 	if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) &&
158170025d76Sjohnny 	    (func == 0))
15828a5a0d1eSanish 		add_nvidia_isa_bridge_props(dip, bus, dev, func);
158370025d76Sjohnny 
158470025d76Sjohnny 	if (pciex && is_pci_bridge)
158570025d76Sjohnny 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
158670025d76Sjohnny 		    (char *)"PCIe-PCI bridge");
158770025d76Sjohnny 	else
158870025d76Sjohnny 		add_model_prop(dip, classcode);
15897c478bd9Sstevel@tonic-gate 
15907c478bd9Sstevel@tonic-gate 	add_compatible(dip, subvenid, subdevid, vendorid, deviceid,
159170025d76Sjohnny 	    revid, classcode, pciex);
15928d483882Smlf 
15938d483882Smlf 	/*
15948d483882Smlf 	 * See if this device is a controller that advertises
15958d483882Smlf 	 * itself to be a standard ATA task file controller, or one that
15968d483882Smlf 	 * has been hard coded.
15978d483882Smlf 	 *
15988d483882Smlf 	 * If it is, check if any other higher precedence driver listed in
15998d483882Smlf 	 * driver_aliases will claim the node by calling
16008d483882Smlf 	 * ddi_compatibile_driver_major.  If so, clear pciide and do not
16018d483882Smlf 	 * create a pci-ide node or any other special handling.
16028d483882Smlf 	 *
16038d483882Smlf 	 * If another driver does not bind, set the node name to pci-ide
16048d483882Smlf 	 * and then let the special pci-ide handling for registers and
16058d483882Smlf 	 * child pci-ide nodes proceed below.
16068d483882Smlf 	 */
16078d483882Smlf 	if (is_pciide(basecl, subcl, revid, vendorid, deviceid,
16088d483882Smlf 	    subvenid, subdevid) == 1) {
16098d483882Smlf 		if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) {
16108d483882Smlf 			(void) ndi_devi_set_nodename(dip, "pci-ide", 0);
16118d483882Smlf 			pciide = 1;
16128d483882Smlf 		}
16138d483882Smlf 	}
16148d483882Smlf 
16157c478bd9Sstevel@tonic-gate 	reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide);
16167c478bd9Sstevel@tonic-gate 	(void) ndi_devi_bind_driver(dip, 0);
16177c478bd9Sstevel@tonic-gate 
16187c478bd9Sstevel@tonic-gate 	/* special handling for pci-ide */
16197c478bd9Sstevel@tonic-gate 	if (pciide) {
16207c478bd9Sstevel@tonic-gate 		dev_info_t *cdip;
16217c478bd9Sstevel@tonic-gate 
16227c478bd9Sstevel@tonic-gate 		/*
16237c478bd9Sstevel@tonic-gate 		 * Create properties specified by P1275 Working Group
16247c478bd9Sstevel@tonic-gate 		 * Proposal #414 Version 1
16257c478bd9Sstevel@tonic-gate 		 */
16267c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
16277c478bd9Sstevel@tonic-gate 		    "device_type", "pci-ide");
16287c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
16297c478bd9Sstevel@tonic-gate 		    "#address-cells", 1);
16307c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
16317c478bd9Sstevel@tonic-gate 		    "#size-cells", 0);
16327c478bd9Sstevel@tonic-gate 
16337c478bd9Sstevel@tonic-gate 		/* allocate two child nodes */
16347c478bd9Sstevel@tonic-gate 		ndi_devi_alloc_sleep(dip, "ide",
1635fa9e4066Sahrens 		    (pnode_t)DEVI_SID_NODEID, &cdip);
16367c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
16377c478bd9Sstevel@tonic-gate 		    "reg", 0);
16387c478bd9Sstevel@tonic-gate 		(void) ndi_devi_bind_driver(cdip, 0);
16397c478bd9Sstevel@tonic-gate 		ndi_devi_alloc_sleep(dip, "ide",
1640fa9e4066Sahrens 		    (pnode_t)DEVI_SID_NODEID, &cdip);
16417c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip,
16427c478bd9Sstevel@tonic-gate 		    "reg", 1);
16437c478bd9Sstevel@tonic-gate 		(void) ndi_devi_bind_driver(cdip, 0);
16447c478bd9Sstevel@tonic-gate 
16457c478bd9Sstevel@tonic-gate 		reprogram = 0;	/* don't reprogram pci-ide bridge */
16467c478bd9Sstevel@tonic-gate 	}
16477c478bd9Sstevel@tonic-gate 
164886c1f4dcSVikram Hegde 	/* allocate and set up iommu private */
164986c1f4dcSVikram Hegde 	private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP);
165086c1f4dcSVikram Hegde 	private->idp_seg = 0;
165186c1f4dcSVikram Hegde 	private->idp_bus = bus;
165286c1f4dcSVikram Hegde 	private->idp_devfn = (dev << 3) | func;
165386c1f4dcSVikram Hegde 	private->idp_sec = 0;
165486c1f4dcSVikram Hegde 	private->idp_sub = 0;
165586c1f4dcSVikram Hegde 	private->idp_bbp_type = IOMMU_PPB_NONE;
165686c1f4dcSVikram Hegde 	/* record the bridge */
165786c1f4dcSVikram Hegde 	private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) &&
165886c1f4dcSVikram Hegde 	    (subcl == PCI_BRIDGE_PCI));
165986c1f4dcSVikram Hegde 	if (private->idp_is_bridge) {
166086c1f4dcSVikram Hegde 		private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
166186c1f4dcSVikram Hegde 		private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
166286c1f4dcSVikram Hegde 		if (pciex && is_pci_bridge)
166386c1f4dcSVikram Hegde 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCI;
166486c1f4dcSVikram Hegde 		else if (pciex)
166586c1f4dcSVikram Hegde 			private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE;
166686c1f4dcSVikram Hegde 		else
166786c1f4dcSVikram Hegde 			private->idp_bbp_type = IOMMU_PPB_PCI_PCI;
166886c1f4dcSVikram Hegde 	}
166986c1f4dcSVikram Hegde 	/* record the special devices */
167086c1f4dcSVikram Hegde 	private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE);
167186c1f4dcSVikram Hegde 	private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) &&
167286c1f4dcSVikram Hegde 	    (subcl == PCI_BRIDGE_ISA));
1673*94f1124eSVikram Hegde 	private->idp_intel_domain = NULL;
167486c1f4dcSVikram Hegde 	/* hook the private to dip */
167586c1f4dcSVikram Hegde 	DEVI(dip)->devi_iommu_private = private;
167686c1f4dcSVikram Hegde 
1677*94f1124eSVikram Hegde 	if (private->idp_is_display == B_TRUE) {
1678*94f1124eSVikram Hegde 		gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP);
1679*94f1124eSVikram Hegde 		gfxp->g_dip = dip;
1680*94f1124eSVikram Hegde 		gfxp->g_prev = NULL;
1681*94f1124eSVikram Hegde 		gfxp->g_next = gfx_devinfo_list;
1682*94f1124eSVikram Hegde 		gfx_devinfo_list = gfxp;
1683*94f1124eSVikram Hegde 		if (gfxp->g_next)
1684*94f1124eSVikram Hegde 			gfxp->g_next->g_prev = gfxp;
1685*94f1124eSVikram Hegde 	}
1686*94f1124eSVikram Hegde 
168705f867c3Sgs 	if (reprogram && (entry != NULL))
168805f867c3Sgs 		entry->reprogram = B_TRUE;
16897c478bd9Sstevel@tonic-gate }
16907c478bd9Sstevel@tonic-gate 
16917c478bd9Sstevel@tonic-gate /*
16927c478bd9Sstevel@tonic-gate  * Set the compatible property to a value compliant with
16937c478bd9Sstevel@tonic-gate  * rev 2.1 of the IEEE1275 PCI binding.
169470025d76Sjohnny  * (Also used for PCI-Express devices).
16957c478bd9Sstevel@tonic-gate  *
16967c478bd9Sstevel@tonic-gate  *   pciVVVV,DDDD.SSSS.ssss.RR	(0)
16977c478bd9Sstevel@tonic-gate  *   pciVVVV,DDDD.SSSS.ssss	(1)
16987c478bd9Sstevel@tonic-gate  *   pciSSSS,ssss		(2)
16997c478bd9Sstevel@tonic-gate  *   pciVVVV,DDDD.RR		(3)
17007c478bd9Sstevel@tonic-gate  *   pciVVVV,DDDD		(4)
17017c478bd9Sstevel@tonic-gate  *   pciclass,CCSSPP		(5)
17027c478bd9Sstevel@tonic-gate  *   pciclass,CCSS		(6)
17037c478bd9Sstevel@tonic-gate  *
17047c478bd9Sstevel@tonic-gate  * The Subsystem (SSSS) forms are not inserted if
17057c478bd9Sstevel@tonic-gate  * subsystem-vendor-id is 0.
17067c478bd9Sstevel@tonic-gate  *
170770025d76Sjohnny  * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above
170870025d76Sjohnny  * property 2 is not created as per "1275 bindings for PCI Express Interconnect"
170970025d76Sjohnny  *
17107c478bd9Sstevel@tonic-gate  * Set with setprop and \x00 between each
17117c478bd9Sstevel@tonic-gate  * to generate the encoded string array form.
17127c478bd9Sstevel@tonic-gate  */
17137c478bd9Sstevel@tonic-gate void
17147c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid,
171570025d76Sjohnny     ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode,
171670025d76Sjohnny     int pciex)
17177c478bd9Sstevel@tonic-gate {
171870025d76Sjohnny 	int i = 0;
171970025d76Sjohnny 	int size = COMPAT_BUFSIZE;
172070025d76Sjohnny 	char *compat[13];
17217c478bd9Sstevel@tonic-gate 	char *buf, *curr;
17227c478bd9Sstevel@tonic-gate 
17237c478bd9Sstevel@tonic-gate 	curr = buf = kmem_alloc(size, KM_SLEEP);
17247c478bd9Sstevel@tonic-gate 
172570025d76Sjohnny 	if (pciex) {
172670025d76Sjohnny 		if (subvenid) {
172770025d76Sjohnny 			compat[i++] = curr;	/* form 0 */
172870025d76Sjohnny 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x",
172970025d76Sjohnny 			    vendorid, deviceid, subvenid, subdevid, revid);
173070025d76Sjohnny 			size -= strlen(curr) + 1;
173170025d76Sjohnny 			curr += strlen(curr) + 1;
173270025d76Sjohnny 
173370025d76Sjohnny 			compat[i++] = curr;	/* form 1 */
173470025d76Sjohnny 			(void) snprintf(curr, size, "pciex%x,%x.%x.%x",
173570025d76Sjohnny 			    vendorid, deviceid, subvenid, subdevid);
173670025d76Sjohnny 			size -= strlen(curr) + 1;
173770025d76Sjohnny 			curr += strlen(curr) + 1;
173870025d76Sjohnny 
173970025d76Sjohnny 		}
174070025d76Sjohnny 		compat[i++] = curr;	/* form 3 */
174170025d76Sjohnny 		(void) snprintf(curr, size, "pciex%x,%x.%x",
174270025d76Sjohnny 		    vendorid, deviceid, revid);
174370025d76Sjohnny 		size -= strlen(curr) + 1;
174470025d76Sjohnny 		curr += strlen(curr) + 1;
174570025d76Sjohnny 
174670025d76Sjohnny 		compat[i++] = curr;	/* form 4 */
174770025d76Sjohnny 		(void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid);
174870025d76Sjohnny 		size -= strlen(curr) + 1;
174970025d76Sjohnny 		curr += strlen(curr) + 1;
175070025d76Sjohnny 
175170025d76Sjohnny 		compat[i++] = curr;	/* form 5 */
175270025d76Sjohnny 		(void) snprintf(curr, size, "pciexclass,%06x", classcode);
175370025d76Sjohnny 		size -= strlen(curr) + 1;
175470025d76Sjohnny 		curr += strlen(curr) + 1;
175570025d76Sjohnny 
175670025d76Sjohnny 		compat[i++] = curr;	/* form 6 */
175770025d76Sjohnny 		(void) snprintf(curr, size, "pciexclass,%04x",
175870025d76Sjohnny 		    (classcode >> 8));
175970025d76Sjohnny 		size -= strlen(curr) + 1;
176070025d76Sjohnny 		curr += strlen(curr) + 1;
176170025d76Sjohnny 	}
176270025d76Sjohnny 
17637c478bd9Sstevel@tonic-gate 	if (subvenid) {
17647c478bd9Sstevel@tonic-gate 		compat[i++] = curr;	/* form 0 */
17657c478bd9Sstevel@tonic-gate 		(void) snprintf(curr, size, "pci%x,%x.%x.%x.%x",
17667c478bd9Sstevel@tonic-gate 		    vendorid, deviceid, subvenid, subdevid, revid);
17677c478bd9Sstevel@tonic-gate 		size -= strlen(curr) + 1;
17687c478bd9Sstevel@tonic-gate 		curr += strlen(curr) + 1;
17697c478bd9Sstevel@tonic-gate 
17707c478bd9Sstevel@tonic-gate 		compat[i++] = curr;	/* form 1 */
17717c478bd9Sstevel@tonic-gate 		(void) snprintf(curr, size, "pci%x,%x.%x.%x",
17727c478bd9Sstevel@tonic-gate 		    vendorid, deviceid, subvenid, subdevid);
17737c478bd9Sstevel@tonic-gate 		size -= strlen(curr) + 1;
17747c478bd9Sstevel@tonic-gate 		curr += strlen(curr) + 1;
17757c478bd9Sstevel@tonic-gate 
17767c478bd9Sstevel@tonic-gate 		compat[i++] = curr;	/* form 2 */
177770025d76Sjohnny 		(void) snprintf(curr, size, "pci%x,%x", subvenid, subdevid);
17787c478bd9Sstevel@tonic-gate 		size -= strlen(curr) + 1;
17797c478bd9Sstevel@tonic-gate 		curr += strlen(curr) + 1;
17807c478bd9Sstevel@tonic-gate 	}
17817c478bd9Sstevel@tonic-gate 	compat[i++] = curr;	/* form 3 */
17827c478bd9Sstevel@tonic-gate 	(void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid);
17837c478bd9Sstevel@tonic-gate 	size -= strlen(curr) + 1;
17847c478bd9Sstevel@tonic-gate 	curr += strlen(curr) + 1;
17857c478bd9Sstevel@tonic-gate 
17867c478bd9Sstevel@tonic-gate 	compat[i++] = curr;	/* form 4 */
17877c478bd9Sstevel@tonic-gate 	(void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid);
17887c478bd9Sstevel@tonic-gate 	size -= strlen(curr) + 1;
17897c478bd9Sstevel@tonic-gate 	curr += strlen(curr) + 1;
17907c478bd9Sstevel@tonic-gate 
17917c478bd9Sstevel@tonic-gate 	compat[i++] = curr;	/* form 5 */
17927c478bd9Sstevel@tonic-gate 	(void) snprintf(curr, size, "pciclass,%06x", classcode);
17937c478bd9Sstevel@tonic-gate 	size -= strlen(curr) + 1;
17947c478bd9Sstevel@tonic-gate 	curr += strlen(curr) + 1;
17957c478bd9Sstevel@tonic-gate 
17967c478bd9Sstevel@tonic-gate 	compat[i++] = curr;	/* form 6 */
17977c478bd9Sstevel@tonic-gate 	(void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8));
179870025d76Sjohnny 	size -= strlen(curr) + 1;
179970025d76Sjohnny 	curr += strlen(curr) + 1;
18007c478bd9Sstevel@tonic-gate 
18017c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip,
18027c478bd9Sstevel@tonic-gate 	    "compatible", compat, i);
18037c478bd9Sstevel@tonic-gate 	kmem_free(buf, COMPAT_BUFSIZE);
18047c478bd9Sstevel@tonic-gate }
18057c478bd9Sstevel@tonic-gate 
18067c478bd9Sstevel@tonic-gate /*
18077c478bd9Sstevel@tonic-gate  * Adjust the reg properties for a dual channel PCI-IDE device.
18087c478bd9Sstevel@tonic-gate  *
18097c478bd9Sstevel@tonic-gate  * NOTE: don't do anything that changes the order of the hard-decodes
18107c478bd9Sstevel@tonic-gate  * and programmed BARs. The kernel driver depends on these values
18117c478bd9Sstevel@tonic-gate  * being in this order regardless of whether they're for a 'native'
18127c478bd9Sstevel@tonic-gate  * mode BAR or not.
18137c478bd9Sstevel@tonic-gate  */
18147c478bd9Sstevel@tonic-gate /*
18157c478bd9Sstevel@tonic-gate  * config info for pci-ide devices
18167c478bd9Sstevel@tonic-gate  */
18177c478bd9Sstevel@tonic-gate static struct {
18187c478bd9Sstevel@tonic-gate 	uchar_t  native_mask;	/* 0 == 'compatibility' mode, 1 == native */
18197c478bd9Sstevel@tonic-gate 	uchar_t  bar_offset;	/* offset for alt status register */
18207c478bd9Sstevel@tonic-gate 	ushort_t addr;		/* compatibility mode base address */
18217c478bd9Sstevel@tonic-gate 	ushort_t length;	/* number of ports for this BAR */
18227c478bd9Sstevel@tonic-gate } pciide_bar[] = {
18237c478bd9Sstevel@tonic-gate 	{ 0x01, 0, 0x1f0, 8 },	/* primary lower BAR */
18247c478bd9Sstevel@tonic-gate 	{ 0x01, 2, 0x3f6, 1 },	/* primary upper BAR */
18257c478bd9Sstevel@tonic-gate 	{ 0x04, 0, 0x170, 8 },	/* secondary lower BAR */
18267c478bd9Sstevel@tonic-gate 	{ 0x04, 2, 0x376, 1 }	/* secondary upper BAR */
18277c478bd9Sstevel@tonic-gate };
18287c478bd9Sstevel@tonic-gate 
18297c478bd9Sstevel@tonic-gate static int
18307c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp)
18317c478bd9Sstevel@tonic-gate {
18327c478bd9Sstevel@tonic-gate 	int hard_decode = 0;
18337c478bd9Sstevel@tonic-gate 
18347c478bd9Sstevel@tonic-gate 	/*
18357c478bd9Sstevel@tonic-gate 	 * Adjust the base and len for the BARs of the PCI-IDE
18367c478bd9Sstevel@tonic-gate 	 * device's primary and secondary controllers. The first
18377c478bd9Sstevel@tonic-gate 	 * two BARs are for the primary controller and the next
18387c478bd9Sstevel@tonic-gate 	 * two BARs are for the secondary controller. The fifth
18397c478bd9Sstevel@tonic-gate 	 * and sixth bars are never adjusted.
18407c478bd9Sstevel@tonic-gate 	 */
18417c478bd9Sstevel@tonic-gate 	if (index >= 0 && index <= 3) {
18427c478bd9Sstevel@tonic-gate 		*lenp = pciide_bar[index].length;
18437c478bd9Sstevel@tonic-gate 
18447c478bd9Sstevel@tonic-gate 		if (progcl & pciide_bar[index].native_mask) {
18457c478bd9Sstevel@tonic-gate 			*basep += pciide_bar[index].bar_offset;
18467c478bd9Sstevel@tonic-gate 		} else {
18477c478bd9Sstevel@tonic-gate 			*basep = pciide_bar[index].addr;
18487c478bd9Sstevel@tonic-gate 			hard_decode = 1;
18497c478bd9Sstevel@tonic-gate 		}
18507c478bd9Sstevel@tonic-gate 	}
18517c478bd9Sstevel@tonic-gate 
18527c478bd9Sstevel@tonic-gate 	/*
18537c478bd9Sstevel@tonic-gate 	 * if either base or len is zero make certain both are zero
18547c478bd9Sstevel@tonic-gate 	 */
18557c478bd9Sstevel@tonic-gate 	if (*basep == 0 || *lenp == 0) {
18567c478bd9Sstevel@tonic-gate 		*basep = 0;
18577c478bd9Sstevel@tonic-gate 		*lenp = 0;
18587c478bd9Sstevel@tonic-gate 		hard_decode = 0;
18597c478bd9Sstevel@tonic-gate 	}
18607c478bd9Sstevel@tonic-gate 
18617c478bd9Sstevel@tonic-gate 	return (hard_decode);
18627c478bd9Sstevel@tonic-gate }
18637c478bd9Sstevel@tonic-gate 
18647c478bd9Sstevel@tonic-gate 
18657c478bd9Sstevel@tonic-gate /*
18667c478bd9Sstevel@tonic-gate  * Add the "reg" and "assigned-addresses" property
18677c478bd9Sstevel@tonic-gate  */
18687c478bd9Sstevel@tonic-gate static int
18697c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
18707c478bd9Sstevel@tonic-gate     int config_op, int pciide)
18717c478bd9Sstevel@tonic-gate {
18727c478bd9Sstevel@tonic-gate 	uchar_t baseclass, subclass, progclass, header;
18737c478bd9Sstevel@tonic-gate 	ushort_t bar_sz;
18747c478bd9Sstevel@tonic-gate 	uint_t value = 0, len, devloc;
18757c478bd9Sstevel@tonic-gate 	uint_t base, base_hi, type;
18767c478bd9Sstevel@tonic-gate 	ushort_t offset, end;
18777c478bd9Sstevel@tonic-gate 	int max_basereg, j, reprogram = 0;
18787c478bd9Sstevel@tonic-gate 	uint_t phys_hi;
18797c478bd9Sstevel@tonic-gate 	struct memlist **io_res, **mres, **mem_res, **pmem_res;
188005f867c3Sgs 	struct memlist **io_res_used, **mres_used;
188105f867c3Sgs 	struct memlist **mem_res_used, **pmem_res_used;
188205f867c3Sgs 	uchar_t res_bus;
18837c478bd9Sstevel@tonic-gate 
18847c478bd9Sstevel@tonic-gate 	pci_regspec_t regs[16] = {{0}};
18857c478bd9Sstevel@tonic-gate 	pci_regspec_t assigned[15] = {{0}};
1886c8711d4dSgs 	int nreg, nasgn;
18877c478bd9Sstevel@tonic-gate 
18887c478bd9Sstevel@tonic-gate 	io_res = &pci_bus_res[bus].io_ports;
188905f867c3Sgs 	io_res_used = &pci_bus_res[bus].io_ports_used;
18907c478bd9Sstevel@tonic-gate 	mem_res = &pci_bus_res[bus].mem_space;
189105f867c3Sgs 	mem_res_used = &pci_bus_res[bus].mem_space_used;
189205f867c3Sgs 	if (bus == 0) {	/* for bus 0, there is only mem_space */
18937c478bd9Sstevel@tonic-gate 		pmem_res = mem_res;
189405f867c3Sgs 		pmem_res_used = mem_res_used;
189505f867c3Sgs 	} else {
18967c478bd9Sstevel@tonic-gate 		pmem_res = &pci_bus_res[bus].pmem_space;
189705f867c3Sgs 		pmem_res_used = &pci_bus_res[bus].pmem_space_used;
189805f867c3Sgs 	}
18997c478bd9Sstevel@tonic-gate 
19007c478bd9Sstevel@tonic-gate 	devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8;
19017c478bd9Sstevel@tonic-gate 	regs[0].pci_phys_hi = devloc;
19027c478bd9Sstevel@tonic-gate 	nreg = 1;	/* rest of regs[0] is all zero */
19037c478bd9Sstevel@tonic-gate 	nasgn = 0;
19047c478bd9Sstevel@tonic-gate 
19057c478bd9Sstevel@tonic-gate 	baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS);
19067c478bd9Sstevel@tonic-gate 	subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS);
19077c478bd9Sstevel@tonic-gate 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
19087c478bd9Sstevel@tonic-gate 	header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M;
19097c478bd9Sstevel@tonic-gate 
19107c478bd9Sstevel@tonic-gate 	switch (header) {
19117c478bd9Sstevel@tonic-gate 	case PCI_HEADER_ZERO:
19127c478bd9Sstevel@tonic-gate 		max_basereg = PCI_BASE_NUM;
19137c478bd9Sstevel@tonic-gate 		break;
19147c478bd9Sstevel@tonic-gate 	case PCI_HEADER_PPB:
19157c478bd9Sstevel@tonic-gate 		max_basereg = PCI_BCNF_BASE_NUM;
19167c478bd9Sstevel@tonic-gate 		break;
19177c478bd9Sstevel@tonic-gate 	case PCI_HEADER_CARDBUS:
19187c478bd9Sstevel@tonic-gate 		max_basereg = PCI_CBUS_BASE_NUM;
19197c478bd9Sstevel@tonic-gate 		break;
19207c478bd9Sstevel@tonic-gate 	default:
19217c478bd9Sstevel@tonic-gate 		max_basereg = 0;
19227c478bd9Sstevel@tonic-gate 		break;
19237c478bd9Sstevel@tonic-gate 	}
19247c478bd9Sstevel@tonic-gate 
19257c478bd9Sstevel@tonic-gate 	/*
19267c478bd9Sstevel@tonic-gate 	 * Create the register property by saving the current
19278d34f104Smyers 	 * value of the base register. Write 0xffffffff to the
19288d34f104Smyers 	 * base register.  Read the value back to determine the
19298d34f104Smyers 	 * required size of the address space.  Restore the base
19308d34f104Smyers 	 * register contents.
19318d34f104Smyers 	 *
19328d34f104Smyers 	 * Do not disable I/O and memory access; this isn't necessary
19338d34f104Smyers 	 * since no driver is yet attached to this device, and disabling
19348d34f104Smyers 	 * I/O and memory access has the side-effect of disabling PCI-PCI
19358d34f104Smyers 	 * bridge mappings, which makes the bridge transparent to secondary-
19368d34f104Smyers 	 * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge
19378d34f104Smyers 	 * Spec V1.2).
19387c478bd9Sstevel@tonic-gate 	 */
19397c478bd9Sstevel@tonic-gate 	end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t);
19407c478bd9Sstevel@tonic-gate 	for (j = 0, offset = PCI_CONF_BASE0; offset < end;
19417c478bd9Sstevel@tonic-gate 	    j++, offset += bar_sz) {
19427c478bd9Sstevel@tonic-gate 		int hard_decode = 0;
19437c478bd9Sstevel@tonic-gate 
19447c478bd9Sstevel@tonic-gate 		/* determine the size of the address space */
19457c478bd9Sstevel@tonic-gate 		base = pci_getl(bus, dev, func, offset);
19467c478bd9Sstevel@tonic-gate 		pci_putl(bus, dev, func, offset, 0xffffffff);
19477c478bd9Sstevel@tonic-gate 		value = pci_getl(bus, dev, func, offset);
19487c478bd9Sstevel@tonic-gate 		pci_putl(bus, dev, func, offset, base);
19497c478bd9Sstevel@tonic-gate 
19507c478bd9Sstevel@tonic-gate 		/* construct phys hi,med.lo, size hi, lo */
19517c478bd9Sstevel@tonic-gate 		if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) {
19527c478bd9Sstevel@tonic-gate 			/* i/o space */
19537c478bd9Sstevel@tonic-gate 			bar_sz = PCI_BAR_SZ_32;
19547c478bd9Sstevel@tonic-gate 			value &= PCI_BASE_IO_ADDR_M;
19557c478bd9Sstevel@tonic-gate 			len = ((value ^ (value-1)) + 1) >> 1;
19567c478bd9Sstevel@tonic-gate 
19577c478bd9Sstevel@tonic-gate 			/* XXX Adjust first 4 IDE registers */
19587c478bd9Sstevel@tonic-gate 			if (pciide) {
1959f088817aSyt 				if (subclass != PCI_MASS_IDE)
19607c478bd9Sstevel@tonic-gate 					progclass = (PCI_IDE_IF_NATIVE_PRI |
19617c478bd9Sstevel@tonic-gate 					    PCI_IDE_IF_NATIVE_SEC);
19627c478bd9Sstevel@tonic-gate 				hard_decode = pciIdeAdjustBAR(progclass, j,
19637c478bd9Sstevel@tonic-gate 				    &base, &len);
19647c478bd9Sstevel@tonic-gate 			} else if (value == 0) {
19657c478bd9Sstevel@tonic-gate 				/* skip base regs with size of 0 */
19667c478bd9Sstevel@tonic-gate 				continue;
19677c478bd9Sstevel@tonic-gate 			}
19687c478bd9Sstevel@tonic-gate 
19697c478bd9Sstevel@tonic-gate 			regs[nreg].pci_size_low =
19707c478bd9Sstevel@tonic-gate 			    assigned[nasgn].pci_size_low = len;
19717c478bd9Sstevel@tonic-gate 			if (!hard_decode) {
19727c478bd9Sstevel@tonic-gate 				regs[nreg].pci_phys_hi =
19737c478bd9Sstevel@tonic-gate 				    (PCI_ADDR_IO | devloc) + offset;
19747c478bd9Sstevel@tonic-gate 			} else {
19757c478bd9Sstevel@tonic-gate 				regs[nreg].pci_phys_hi =
19767c478bd9Sstevel@tonic-gate 				    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) +
19777c478bd9Sstevel@tonic-gate 				    offset;
19787c478bd9Sstevel@tonic-gate 				regs[nreg].pci_phys_low =
19797c478bd9Sstevel@tonic-gate 				    base & PCI_BASE_IO_ADDR_M;
19807c478bd9Sstevel@tonic-gate 			}
19817c478bd9Sstevel@tonic-gate 			assigned[nasgn].pci_phys_hi =
19827c478bd9Sstevel@tonic-gate 			    (PCI_RELOCAT_B | PCI_ADDR_IO | devloc) + offset;
19837c478bd9Sstevel@tonic-gate 			type = base & (~PCI_BASE_IO_ADDR_M);
19847c478bd9Sstevel@tonic-gate 			base &= PCI_BASE_IO_ADDR_M;
198505f867c3Sgs 			/*
198605f867c3Sgs 			 * A device under a subtractive PPB can allocate
198705f867c3Sgs 			 * resources from its parent bus if there is no resource
198805f867c3Sgs 			 * available on its own bus.
198905f867c3Sgs 			 */
199005f867c3Sgs 			if ((config_op == CONFIG_NEW) && (*io_res == NULL)) {
199105f867c3Sgs 				res_bus = bus;
199205f867c3Sgs 				while (pci_bus_res[res_bus].subtractive) {
199305f867c3Sgs 					res_bus = pci_bus_res[res_bus].par_bus;
199405f867c3Sgs 					if (res_bus == (uchar_t)-1)
199505f867c3Sgs 						break; /* root bus already */
199605f867c3Sgs 					if (pci_bus_res[res_bus].io_ports) {
199705f867c3Sgs 						io_res = &pci_bus_res
199805f867c3Sgs 						    [res_bus].io_ports;
199905f867c3Sgs 						break;
200005f867c3Sgs 					}
200105f867c3Sgs 				}
200205f867c3Sgs 			}
20037c478bd9Sstevel@tonic-gate 
20047c478bd9Sstevel@tonic-gate 			/*
20057c478bd9Sstevel@tonic-gate 			 * first pass - gather what's there
20067c478bd9Sstevel@tonic-gate 			 * update/second pass - adjust/allocate regions
20077c478bd9Sstevel@tonic-gate 			 *	config - allocate regions
20087c478bd9Sstevel@tonic-gate 			 */
20097c478bd9Sstevel@tonic-gate 			if (config_op == CONFIG_INFO) {	/* first pass */
20107c478bd9Sstevel@tonic-gate 				/* take out of the resource map of the bus */
201105f867c3Sgs 				if (base != 0) {
201205f867c3Sgs 					if (*io_res)
201305f867c3Sgs 						(void) memlist_remove(io_res,
201405f867c3Sgs 						    base, len);
201505f867c3Sgs 					memlist_insert(io_res_used, base, len);
201605f867c3Sgs 				} else
20177c478bd9Sstevel@tonic-gate 					reprogram = 1;
201805f867c3Sgs 			} else if ((*io_res && base == 0) ||
201905f867c3Sgs 			    pci_bus_res[bus].io_reprogram) {
2020c8711d4dSgs 				base = (uint_t)memlist_find(io_res, len, len);
20217c478bd9Sstevel@tonic-gate 				if (base != 0) {
202205f867c3Sgs 					memlist_insert(io_res_used, base, len);
20237c478bd9Sstevel@tonic-gate 					/* XXX need to worry about 64-bit? */
20247c478bd9Sstevel@tonic-gate 					pci_putl(bus, dev, func, offset,
20257c478bd9Sstevel@tonic-gate 					    base | type);
20267c478bd9Sstevel@tonic-gate 					base = pci_getl(bus, dev, func, offset);
20277c478bd9Sstevel@tonic-gate 					base &= PCI_BASE_IO_ADDR_M;
20287c478bd9Sstevel@tonic-gate 				}
20297c478bd9Sstevel@tonic-gate 				if (base == 0) {
20307c478bd9Sstevel@tonic-gate 					cmn_err(CE_WARN, "failed to program"
2031db063408Sdmick 					    " IO space [%d/%d/%d] BAR@0x%x"
2032db063408Sdmick 					    " length 0x%x",
2033ebf3afa8Sdmick 					    bus, dev, func, offset, len);
2034c8711d4dSgs 				}
20357c478bd9Sstevel@tonic-gate 			}
20367c478bd9Sstevel@tonic-gate 			assigned[nasgn].pci_phys_low = base;
20377c478bd9Sstevel@tonic-gate 			nreg++, nasgn++;
20387c478bd9Sstevel@tonic-gate 
20397c478bd9Sstevel@tonic-gate 		} else {
20407c478bd9Sstevel@tonic-gate 			/* memory space */
20417c478bd9Sstevel@tonic-gate 			if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) {
20427c478bd9Sstevel@tonic-gate 				bar_sz = PCI_BAR_SZ_64;
20437c478bd9Sstevel@tonic-gate 				base_hi = pci_getl(bus, dev, func, offset + 4);
20447c478bd9Sstevel@tonic-gate 				phys_hi = PCI_ADDR_MEM64;
20457c478bd9Sstevel@tonic-gate 			} else {
20467c478bd9Sstevel@tonic-gate 				bar_sz = PCI_BAR_SZ_32;
20477c478bd9Sstevel@tonic-gate 				base_hi = 0;
20487c478bd9Sstevel@tonic-gate 				phys_hi = PCI_ADDR_MEM32;
20497c478bd9Sstevel@tonic-gate 			}
20507c478bd9Sstevel@tonic-gate 
20517c478bd9Sstevel@tonic-gate 			/* skip base regs with size of 0 */
20527c478bd9Sstevel@tonic-gate 			value &= PCI_BASE_M_ADDR_M;
20537c478bd9Sstevel@tonic-gate 
20547c478bd9Sstevel@tonic-gate 			if (value == 0) {
20557c478bd9Sstevel@tonic-gate 				continue;
20567c478bd9Sstevel@tonic-gate 			}
20577c478bd9Sstevel@tonic-gate 			len = ((value ^ (value-1)) + 1) >> 1;
20587c478bd9Sstevel@tonic-gate 			regs[nreg].pci_size_low =
20597c478bd9Sstevel@tonic-gate 			    assigned[nasgn].pci_size_low = len;
20607c478bd9Sstevel@tonic-gate 
20617c478bd9Sstevel@tonic-gate 			phys_hi |= (devloc | offset);
20627c478bd9Sstevel@tonic-gate 			if (base & PCI_BASE_PREF_M) {
20637c478bd9Sstevel@tonic-gate 				mres = pmem_res;
206405f867c3Sgs 				mres_used = pmem_res_used;
20657c478bd9Sstevel@tonic-gate 				phys_hi |= PCI_PREFETCH_B;
20667c478bd9Sstevel@tonic-gate 			} else {
20677c478bd9Sstevel@tonic-gate 				mres = mem_res;
206805f867c3Sgs 				mres_used = mem_res_used;
20697c478bd9Sstevel@tonic-gate 			}
207005f867c3Sgs 			/*
207105f867c3Sgs 			 * A device under a subtractive PPB can allocate
207205f867c3Sgs 			 * resources from its parent bus if there is no resource
207305f867c3Sgs 			 * available on its own bus.
207405f867c3Sgs 			 */
207505f867c3Sgs 			if ((config_op == CONFIG_NEW) && (*mres == NULL)) {
207605f867c3Sgs 				res_bus = bus;
207705f867c3Sgs 				while (pci_bus_res[res_bus].subtractive) {
207805f867c3Sgs 					res_bus = pci_bus_res[res_bus].par_bus;
207905f867c3Sgs 					if (res_bus == (uchar_t)-1)
208005f867c3Sgs 						break; /* root bus already */
208186ce93f0SGuoli Shu 					mem_res =
208286ce93f0SGuoli Shu 					    &pci_bus_res[res_bus].mem_space;
208386ce93f0SGuoli Shu 					if (res_bus == 0)
208486ce93f0SGuoli Shu 						pmem_res = mem_res;
208586ce93f0SGuoli Shu 					else
208686ce93f0SGuoli Shu 						pmem_res = &pci_bus_res
208705f867c3Sgs 						    [res_bus].pmem_space;
208886ce93f0SGuoli Shu 					if (phys_hi & PCI_PREFETCH_B)
208986ce93f0SGuoli Shu 						mres = pmem_res;
209005f867c3Sgs 					else
209186ce93f0SGuoli Shu 						mres = mem_res;
209205f867c3Sgs 					if (*mres)
209305f867c3Sgs 						break;
209405f867c3Sgs 				}
209505f867c3Sgs 			}
209605f867c3Sgs 
20977c478bd9Sstevel@tonic-gate 			regs[nreg].pci_phys_hi =
20987c478bd9Sstevel@tonic-gate 			    assigned[nasgn].pci_phys_hi = phys_hi;
20997c478bd9Sstevel@tonic-gate 			assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B;
21007c478bd9Sstevel@tonic-gate 			assigned[nasgn].pci_phys_mid = base_hi;
21017c478bd9Sstevel@tonic-gate 			type = base & ~PCI_BASE_M_ADDR_M;
21027c478bd9Sstevel@tonic-gate 			base &= PCI_BASE_M_ADDR_M;
21037c478bd9Sstevel@tonic-gate 
21047c478bd9Sstevel@tonic-gate 			if (config_op == CONFIG_INFO) {
21057c478bd9Sstevel@tonic-gate 				/* take out of the resource map of the bus */
210605f867c3Sgs 				if (base != 0) {
210786ce93f0SGuoli Shu 					if (*mem_res) {
210886ce93f0SGuoli Shu 						/* remove it from MEM space */
210986ce93f0SGuoli Shu 						(void) memlist_remove(mem_res,
211005f867c3Sgs 						    base, len);
211186ce93f0SGuoli Shu 					}
211286ce93f0SGuoli Shu 					if (mem_res != pmem_res && *pmem_res) {
211386ce93f0SGuoli Shu 						/* remove it from PMEM space */
211486ce93f0SGuoli Shu 						(void) memlist_remove(pmem_res,
211586ce93f0SGuoli Shu 						    base, len);
211686ce93f0SGuoli Shu 					}
211705f867c3Sgs 					memlist_insert(mres_used, base, len);
211805f867c3Sgs 				} else
21197c478bd9Sstevel@tonic-gate 					reprogram = 1;
212005f867c3Sgs 			} else if ((*mres && base == 0) ||
212105f867c3Sgs 			    pci_bus_res[bus].mem_reprogram) {
2122c8711d4dSgs 				base = (uint_t)memlist_find(mres, len, len);
21237c478bd9Sstevel@tonic-gate 				if (base != NULL) {
212486ce93f0SGuoli Shu 					if (mres != mem_res && *mem_res) {
212586ce93f0SGuoli Shu 						/* remove it from MEM space */
212686ce93f0SGuoli Shu 						(void) memlist_remove(mem_res,
212786ce93f0SGuoli Shu 						    base, len);
212886ce93f0SGuoli Shu 					} else if (mres != pmem_res &&
212986ce93f0SGuoli Shu 					    *pmem_res) {
213086ce93f0SGuoli Shu 						/* remove it from PMEM space */
213186ce93f0SGuoli Shu 						(void) memlist_remove(pmem_res,
213286ce93f0SGuoli Shu 						    base, len);
213386ce93f0SGuoli Shu 					}
213405f867c3Sgs 					memlist_insert(mres_used, base, len);
21357c478bd9Sstevel@tonic-gate 					pci_putl(bus, dev, func, offset,
21367c478bd9Sstevel@tonic-gate 					    base | type);
21377c478bd9Sstevel@tonic-gate 					base = pci_getl(bus, dev, func, offset);
21387c478bd9Sstevel@tonic-gate 					base &= PCI_BASE_M_ADDR_M;
21397c478bd9Sstevel@tonic-gate 				}
21407c478bd9Sstevel@tonic-gate 
21417c478bd9Sstevel@tonic-gate 				if (base == 0) {
21427c478bd9Sstevel@tonic-gate 					cmn_err(CE_WARN, "failed to program "
2143ebf3afa8Sdmick 					    "mem space [%d/%d/%d] BAR@0x%x"
2144db063408Sdmick 					    " length 0x%x",
2145ebf3afa8Sdmick 					    bus, dev, func, offset, len);
2146c8711d4dSgs 				}
21477c478bd9Sstevel@tonic-gate 			}
21487c478bd9Sstevel@tonic-gate 			assigned[nasgn].pci_phys_low = base;
21497c478bd9Sstevel@tonic-gate 			nreg++, nasgn++;
21507c478bd9Sstevel@tonic-gate 		}
21517c478bd9Sstevel@tonic-gate 	}
21527c478bd9Sstevel@tonic-gate 	switch (header) {
21537c478bd9Sstevel@tonic-gate 	case PCI_HEADER_ZERO:
21547c478bd9Sstevel@tonic-gate 		offset = PCI_CONF_ROM;
21557c478bd9Sstevel@tonic-gate 		break;
21567c478bd9Sstevel@tonic-gate 	case PCI_HEADER_PPB:
21577c478bd9Sstevel@tonic-gate 		offset = PCI_BCNF_ROM;
21587c478bd9Sstevel@tonic-gate 		break;
21597c478bd9Sstevel@tonic-gate 	default: /* including PCI_HEADER_CARDBUS */
21607c478bd9Sstevel@tonic-gate 		goto done;
21617c478bd9Sstevel@tonic-gate 	}
21627c478bd9Sstevel@tonic-gate 
21637c478bd9Sstevel@tonic-gate 	/*
21647c478bd9Sstevel@tonic-gate 	 * Add the expansion rom memory space
21657c478bd9Sstevel@tonic-gate 	 * Determine the size of the ROM base reg; don't write reserved bits
21667c478bd9Sstevel@tonic-gate 	 * ROM isn't in the PCI memory space.
21677c478bd9Sstevel@tonic-gate 	 */
21687c478bd9Sstevel@tonic-gate 	base = pci_getl(bus, dev, func, offset);
21697c478bd9Sstevel@tonic-gate 	pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M);
21707c478bd9Sstevel@tonic-gate 	value = pci_getl(bus, dev, func, offset);
21717c478bd9Sstevel@tonic-gate 	pci_putl(bus, dev, func, offset, base);
217270025d76Sjohnny 	if (value & PCI_BASE_ROM_ENABLE)
217370025d76Sjohnny 		value &= PCI_BASE_ROM_ADDR_M;
217470025d76Sjohnny 	else
217570025d76Sjohnny 		value = 0;
21767c478bd9Sstevel@tonic-gate 
21777c478bd9Sstevel@tonic-gate 	if (value != 0) {
21787c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset;
21797c478bd9Sstevel@tonic-gate 		assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B |
21807c478bd9Sstevel@tonic-gate 		    PCI_ADDR_MEM32 | devloc) + offset;
21817c478bd9Sstevel@tonic-gate 		base &= PCI_BASE_ROM_ADDR_M;
21827c478bd9Sstevel@tonic-gate 		assigned[nasgn].pci_phys_low = base;
21837c478bd9Sstevel@tonic-gate 		len = ((value ^ (value-1)) + 1) >> 1;
21847c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len;
21857c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
218699ed6083Sszhou 		/* take it out of the memory resource */
218799ed6083Sszhou 		if (*mem_res && base != 0)
218805f867c3Sgs 			(void) memlist_remove(mem_res, base, len);
218905f867c3Sgs 		if (base != 0)
219005f867c3Sgs 			memlist_insert(mem_res, base, len);
21917c478bd9Sstevel@tonic-gate 	}
21927c478bd9Sstevel@tonic-gate 
21937c478bd9Sstevel@tonic-gate 	/*
21947c478bd9Sstevel@tonic-gate 	 * The following are ISA resources. There are not part
21957c478bd9Sstevel@tonic-gate 	 * of the PCI local bus resources. So don't attempt to
21967c478bd9Sstevel@tonic-gate 	 * do resource accounting against PCI.
21977c478bd9Sstevel@tonic-gate 	 */
21987c478bd9Sstevel@tonic-gate 
21997c478bd9Sstevel@tonic-gate 	/* add the three hard-decode, aliased address spaces for VGA */
22007c478bd9Sstevel@tonic-gate 	if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) ||
22017c478bd9Sstevel@tonic-gate 	    (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) {
22027c478bd9Sstevel@tonic-gate 
22037c478bd9Sstevel@tonic-gate 		/* VGA hard decode 0x3b0-0x3bb */
22047c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
22057c478bd9Sstevel@tonic-gate 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
22067c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0;
22077c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc;
22087c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
22097c478bd9Sstevel@tonic-gate 
22107c478bd9Sstevel@tonic-gate 		/* VGA hard decode 0x3c0-0x3df */
22117c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
22127c478bd9Sstevel@tonic-gate 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
22137c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0;
22147c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20;
22157c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
22167c478bd9Sstevel@tonic-gate 
22177c478bd9Sstevel@tonic-gate 		/* Video memory */
22187c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
22197c478bd9Sstevel@tonic-gate 		    (PCI_RELOCAT_B | PCI_ADDR_MEM32 | devloc);
22207c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_low =
22217c478bd9Sstevel@tonic-gate 		    assigned[nasgn].pci_phys_low = 0xa0000;
22227c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low =
22237c478bd9Sstevel@tonic-gate 		    assigned[nasgn].pci_size_low = 0x20000;
22247c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
22257c478bd9Sstevel@tonic-gate 	}
22267c478bd9Sstevel@tonic-gate 
22277c478bd9Sstevel@tonic-gate 	/* add the hard-decode, aliased address spaces for 8514 */
22287c478bd9Sstevel@tonic-gate 	if ((baseclass == PCI_CLASS_DISPLAY) &&
22299896aa55Sjveta 	    (subclass == PCI_DISPLAY_VGA) &&
22309896aa55Sjveta 	    (progclass & PCI_DISPLAY_IF_8514)) {
22317c478bd9Sstevel@tonic-gate 
22327c478bd9Sstevel@tonic-gate 		/* hard decode 0x2e8 */
22337c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
22347c478bd9Sstevel@tonic-gate 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
22357c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8;
22367c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1;
22377c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
22387c478bd9Sstevel@tonic-gate 
22397c478bd9Sstevel@tonic-gate 		/* hard decode 0x2ea-0x2ef */
22407c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi =
22417c478bd9Sstevel@tonic-gate 		    (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc);
22427c478bd9Sstevel@tonic-gate 		regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea;
22437c478bd9Sstevel@tonic-gate 		regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6;
22447c478bd9Sstevel@tonic-gate 		nreg++, nasgn++;
22457c478bd9Sstevel@tonic-gate 	}
22467c478bd9Sstevel@tonic-gate 
22477c478bd9Sstevel@tonic-gate done:
22487c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
22497c478bd9Sstevel@tonic-gate 	    (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int));
22507c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
22517c478bd9Sstevel@tonic-gate 	    "assigned-addresses",
22527c478bd9Sstevel@tonic-gate 	    (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int));
2253c8711d4dSgs 
22547c478bd9Sstevel@tonic-gate 	return (reprogram);
22557c478bd9Sstevel@tonic-gate }
22567c478bd9Sstevel@tonic-gate 
22577c478bd9Sstevel@tonic-gate static void
225870025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func,
225949fbdd30SErwin T Tsaur     int pciex, ushort_t is_pci_bridge)
22607c478bd9Sstevel@tonic-gate {
226170025d76Sjohnny 	char *dev_type;
22627c478bd9Sstevel@tonic-gate 	int i;
22637c478bd9Sstevel@tonic-gate 	uint_t val, io_range[2], mem_range[2], pmem_range[2];
22647c478bd9Sstevel@tonic-gate 	uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS);
22657c478bd9Sstevel@tonic-gate 	uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS);
226605f867c3Sgs 	uchar_t progclass;
226705f867c3Sgs 
2268f55ce205Sszhou 	ASSERT(secbus <= subbus);
22697c478bd9Sstevel@tonic-gate 
227005f867c3Sgs 	/*
227105f867c3Sgs 	 * Check if it's a subtractive PPB.
227205f867c3Sgs 	 */
227305f867c3Sgs 	progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS);
227405f867c3Sgs 	if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE)
227505f867c3Sgs 		pci_bus_res[secbus].subtractive = B_TRUE;
227605f867c3Sgs 
2277f55ce205Sszhou 	/*
2278f55ce205Sszhou 	 * Some BIOSes lie about max pci busses, we allow for
2279f55ce205Sszhou 	 * such mistakes here
2280f55ce205Sszhou 	 */
2281f55ce205Sszhou 	if (subbus > pci_bios_nbus) {
2282f55ce205Sszhou 		pci_bios_nbus = subbus;
2283f55ce205Sszhou 		alloc_res_array();
2284f55ce205Sszhou 	}
2285f55ce205Sszhou 
2286f55ce205Sszhou 	ASSERT(pci_bus_res[secbus].dip == NULL);
22877c478bd9Sstevel@tonic-gate 	pci_bus_res[secbus].dip = dip;
22887c478bd9Sstevel@tonic-gate 	pci_bus_res[secbus].par_bus = bus;
22897c478bd9Sstevel@tonic-gate 
229049fbdd30SErwin T Tsaur 	dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci";
229170025d76Sjohnny 
22927c478bd9Sstevel@tonic-gate 	/* setup bus number hierarchy */
22937c478bd9Sstevel@tonic-gate 	pci_bus_res[secbus].sub_bus = subbus;
229453273e82Ssethg 	/*
229553273e82Ssethg 	 * Keep track of the largest subordinate bus number (this is essential
229653273e82Ssethg 	 * for peer busses because there is no other way of determining its
229753273e82Ssethg 	 * subordinate bus number).
229853273e82Ssethg 	 */
22997c478bd9Sstevel@tonic-gate 	if (subbus > pci_bus_res[bus].sub_bus)
23007c478bd9Sstevel@tonic-gate 		pci_bus_res[bus].sub_bus = subbus;
230153273e82Ssethg 	/*
230253273e82Ssethg 	 * Loop through subordinate busses, initializing their parent bus
230353273e82Ssethg 	 * field to this bridge's parent.  The subordinate busses' parent
230453273e82Ssethg 	 * fields may very well be further refined later, as child bridges
230553273e82Ssethg 	 * are enumerated.  (The value is to note that the subordinate busses
230653273e82Ssethg 	 * are not peer busses by changing their par_bus fields to anything
230753273e82Ssethg 	 * other than -1.)
230853273e82Ssethg 	 */
23097c478bd9Sstevel@tonic-gate 	for (i = secbus + 1; i <= subbus; i++)
23107c478bd9Sstevel@tonic-gate 		pci_bus_res[i].par_bus = bus;
23117c478bd9Sstevel@tonic-gate 
23127c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
231370025d76Sjohnny 	    "device_type", dev_type);
23147c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
23157c478bd9Sstevel@tonic-gate 	    "#address-cells", 3);
23167c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
23177c478bd9Sstevel@tonic-gate 	    "#size-cells", 2);
23187c478bd9Sstevel@tonic-gate 
23197c478bd9Sstevel@tonic-gate 	/*
23207c478bd9Sstevel@tonic-gate 	 * According to PPB spec, the base register should be programmed
23217c478bd9Sstevel@tonic-gate 	 * with a value bigger than the limit register when there are
23227c478bd9Sstevel@tonic-gate 	 * no resources available. This applies to io, memory, and
23237c478bd9Sstevel@tonic-gate 	 * prefetchable memory.
23247c478bd9Sstevel@tonic-gate 	 */
23259896aa55Sjveta 
23269896aa55Sjveta 	/*
23279896aa55Sjveta 	 * io range
232805f867c3Sgs 	 * We determine i/o windows that are left unconfigured by BIOS
23299896aa55Sjveta 	 * through its i/o enable bit as Microsoft recommends OEMs to do.
23309896aa55Sjveta 	 * If it is unset, we disable i/o and mark it for reconfiguration in
23319896aa55Sjveta 	 * later passes by setting the base > limit
23329896aa55Sjveta 	 */
23339896aa55Sjveta 	val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM);
23349896aa55Sjveta 	if (val & PCI_COMM_IO) {
23359896aa55Sjveta 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW);
23369896aa55Sjveta 		io_range[0] = ((val & 0xf0) << 8);
23379896aa55Sjveta 		val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW);
23389896aa55Sjveta 		io_range[1]  = ((val & 0xf0) << 8) | 0xFFF;
23399896aa55Sjveta 	} else {
23409896aa55Sjveta 		io_range[0] = 0x9fff;
23419896aa55Sjveta 		io_range[1] = 0x1000;
23429896aa55Sjveta 		pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW,
23439896aa55Sjveta 		    (uint8_t)((io_range[0] >> 8) & 0xf0));
23449896aa55Sjveta 		pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW,
23459896aa55Sjveta 		    (uint8_t)((io_range[1] >> 8) & 0xf0));
23469896aa55Sjveta 		pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0);
23479896aa55Sjveta 		pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0);
23489896aa55Sjveta 	}
23499896aa55Sjveta 
23507c478bd9Sstevel@tonic-gate 	if (io_range[0] != 0 && io_range[0] < io_range[1]) {
23517c478bd9Sstevel@tonic-gate 		memlist_insert(&pci_bus_res[secbus].io_ports,
23527c478bd9Sstevel@tonic-gate 		    (uint64_t)io_range[0],
23537c478bd9Sstevel@tonic-gate 		    (uint64_t)(io_range[1] - io_range[0] + 1));
235405f867c3Sgs 		memlist_insert(&pci_bus_res[bus].io_ports_used,
235505f867c3Sgs 		    (uint64_t)io_range[0],
235605f867c3Sgs 		    (uint64_t)(io_range[1] - io_range[0] + 1));
23577c478bd9Sstevel@tonic-gate 		if (pci_bus_res[bus].io_ports != NULL) {
23587c478bd9Sstevel@tonic-gate 			(void) memlist_remove(&pci_bus_res[bus].io_ports,
23597c478bd9Sstevel@tonic-gate 			    (uint64_t)io_range[0],
23607c478bd9Sstevel@tonic-gate 			    (uint64_t)(io_range[1] - io_range[0] + 1));
23617c478bd9Sstevel@tonic-gate 		}
23627c478bd9Sstevel@tonic-gate 		dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x",
23637c478bd9Sstevel@tonic-gate 		    secbus, io_range[0], io_range[1]);
23642269adc8Sszhou 		/* if 32-bit supported, make sure upper bits are not set */
23652269adc8Sszhou 		if ((val & 0xf) == 1 &&
23662269adc8Sszhou 		    pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) {
23672269adc8Sszhou 			cmn_err(CE_NOTE, "unsupported 32-bit IO address on"
23682269adc8Sszhou 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
23692269adc8Sszhou 		}
23707c478bd9Sstevel@tonic-gate 	}
23717c478bd9Sstevel@tonic-gate 
23727c478bd9Sstevel@tonic-gate 	/* mem range */
23737c478bd9Sstevel@tonic-gate 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE);
23747c478bd9Sstevel@tonic-gate 	mem_range[0] = ((val & 0xFFF0) << 16);
23757c478bd9Sstevel@tonic-gate 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT);
23767c478bd9Sstevel@tonic-gate 	mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
23777c478bd9Sstevel@tonic-gate 	if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) {
23787c478bd9Sstevel@tonic-gate 		memlist_insert(&pci_bus_res[secbus].mem_space,
23797c478bd9Sstevel@tonic-gate 		    (uint64_t)mem_range[0],
23807c478bd9Sstevel@tonic-gate 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
238105f867c3Sgs 		memlist_insert(&pci_bus_res[bus].mem_space_used,
238205f867c3Sgs 		    (uint64_t)mem_range[0],
238305f867c3Sgs 		    (uint64_t)(mem_range[1] - mem_range[0] + 1));
238486ce93f0SGuoli Shu 		/* remove from parent resource list */
23857c478bd9Sstevel@tonic-gate 		if (pci_bus_res[bus].mem_space != NULL) {
23867c478bd9Sstevel@tonic-gate 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
23877c478bd9Sstevel@tonic-gate 			    (uint64_t)mem_range[0],
23887c478bd9Sstevel@tonic-gate 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
23897c478bd9Sstevel@tonic-gate 		}
239086ce93f0SGuoli Shu 		if (pci_bus_res[bus].pmem_space != NULL) {
239186ce93f0SGuoli Shu 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
239286ce93f0SGuoli Shu 			    (uint64_t)mem_range[0],
239386ce93f0SGuoli Shu 			    (uint64_t)(mem_range[1] - mem_range[0] + 1));
239486ce93f0SGuoli Shu 		}
23957c478bd9Sstevel@tonic-gate 		dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x",
23967c478bd9Sstevel@tonic-gate 		    secbus, mem_range[0], mem_range[1]);
23977c478bd9Sstevel@tonic-gate 	}
23987c478bd9Sstevel@tonic-gate 
23997c478bd9Sstevel@tonic-gate 	/* prefetchable memory range */
24007c478bd9Sstevel@tonic-gate 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW);
24017c478bd9Sstevel@tonic-gate 	pmem_range[0] = ((val & 0xFFF0) << 16);
24027c478bd9Sstevel@tonic-gate 	val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW);
24037c478bd9Sstevel@tonic-gate 	pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF;
24047c478bd9Sstevel@tonic-gate 	if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) {
24057c478bd9Sstevel@tonic-gate 		memlist_insert(&pci_bus_res[secbus].pmem_space,
24067c478bd9Sstevel@tonic-gate 		    (uint64_t)pmem_range[0],
24077c478bd9Sstevel@tonic-gate 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
240805f867c3Sgs 		memlist_insert(&pci_bus_res[bus].pmem_space_used,
240905f867c3Sgs 		    (uint64_t)pmem_range[0],
241005f867c3Sgs 		    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
241186ce93f0SGuoli Shu 		/* remove from parent resource list */
24127c478bd9Sstevel@tonic-gate 		if (pci_bus_res[bus].pmem_space != NULL) {
24137c478bd9Sstevel@tonic-gate 			(void) memlist_remove(&pci_bus_res[bus].pmem_space,
24147c478bd9Sstevel@tonic-gate 			    (uint64_t)pmem_range[0],
24157c478bd9Sstevel@tonic-gate 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
24167c478bd9Sstevel@tonic-gate 		}
241786ce93f0SGuoli Shu 		if (pci_bus_res[bus].mem_space != NULL) {
241886ce93f0SGuoli Shu 			(void) memlist_remove(&pci_bus_res[bus].mem_space,
241986ce93f0SGuoli Shu 			    (uint64_t)pmem_range[0],
242086ce93f0SGuoli Shu 			    (uint64_t)(pmem_range[1] - pmem_range[0] + 1));
242186ce93f0SGuoli Shu 		}
24227c478bd9Sstevel@tonic-gate 		dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x",
24237c478bd9Sstevel@tonic-gate 		    secbus, pmem_range[0], pmem_range[1]);
24242269adc8Sszhou 		/* if 64-bit supported, make sure upper bits are not set */
24252269adc8Sszhou 		if ((val & 0xf) == 1 &&
24262269adc8Sszhou 		    pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) {
24272269adc8Sszhou 			cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on"
24282269adc8Sszhou 			    " pci-pci bridge [%d/%d/%d]", bus, dev, func);
24292269adc8Sszhou 		}
24307c478bd9Sstevel@tonic-gate 	}
24317c478bd9Sstevel@tonic-gate 
24327c478bd9Sstevel@tonic-gate 	add_bus_range_prop(secbus);
24337c478bd9Sstevel@tonic-gate 	add_ppb_ranges_prop(secbus);
24347c478bd9Sstevel@tonic-gate }
24357c478bd9Sstevel@tonic-gate 
243609f67678Sanish extern const struct pci_class_strings_s class_pci[];
243709f67678Sanish extern int class_pci_items;
24387c478bd9Sstevel@tonic-gate 
24397c478bd9Sstevel@tonic-gate static void
24407c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode)
24417c478bd9Sstevel@tonic-gate {
24427c478bd9Sstevel@tonic-gate 	const char *desc;
24437c478bd9Sstevel@tonic-gate 	int i;
24447c478bd9Sstevel@tonic-gate 	uchar_t baseclass = classcode >> 16;
24457c478bd9Sstevel@tonic-gate 	uchar_t subclass = (classcode >> 8) & 0xff;
24467c478bd9Sstevel@tonic-gate 	uchar_t progclass = classcode & 0xff;
24477c478bd9Sstevel@tonic-gate 
24487c478bd9Sstevel@tonic-gate 	if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) {
24497c478bd9Sstevel@tonic-gate 		desc = "IDE controller";
24507c478bd9Sstevel@tonic-gate 	} else {
24517c478bd9Sstevel@tonic-gate 		for (desc = 0, i = 0; i < class_pci_items; i++) {
24527c478bd9Sstevel@tonic-gate 			if ((baseclass == class_pci[i].base_class) &&
24537c478bd9Sstevel@tonic-gate 			    (subclass == class_pci[i].sub_class) &&
24547c478bd9Sstevel@tonic-gate 			    (progclass == class_pci[i].prog_class)) {
245509f67678Sanish 				desc = class_pci[i].actual_desc;
24567c478bd9Sstevel@tonic-gate 				break;
24577c478bd9Sstevel@tonic-gate 			}
24587c478bd9Sstevel@tonic-gate 		}
245909f67678Sanish 		if (i == class_pci_items)
24607c478bd9Sstevel@tonic-gate 			desc = "Unknown class of pci/pnpbios device";
24617c478bd9Sstevel@tonic-gate 	}
24627c478bd9Sstevel@tonic-gate 
24637c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
24647c478bd9Sstevel@tonic-gate 	    (char *)desc);
24657c478bd9Sstevel@tonic-gate }
24667c478bd9Sstevel@tonic-gate 
24677c478bd9Sstevel@tonic-gate static void
24687c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus)
24697c478bd9Sstevel@tonic-gate {
24707c478bd9Sstevel@tonic-gate 	int bus_range[2];
24717c478bd9Sstevel@tonic-gate 
24727c478bd9Sstevel@tonic-gate 	if (pci_bus_res[bus].dip == NULL)
24737c478bd9Sstevel@tonic-gate 		return;
24747c478bd9Sstevel@tonic-gate 	bus_range[0] = bus;
24757c478bd9Sstevel@tonic-gate 	bus_range[1] = pci_bus_res[bus].sub_bus;
24767c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
24777c478bd9Sstevel@tonic-gate 	    "bus-range", (int *)bus_range, 2);
24787c478bd9Sstevel@tonic-gate }
24797c478bd9Sstevel@tonic-gate 
2480b1f176e8Sjg /*
2481b1f176e8Sjg  * Add slot-names property for any named pci hot-plug slots
2482b1f176e8Sjg  */
2483b1f176e8Sjg static void
2484b1f176e8Sjg add_bus_slot_names_prop(int bus)
2485b1f176e8Sjg {
2486b1f176e8Sjg 	char slotprop[256];
2487b1f176e8Sjg 	int len;
2488b1f176e8Sjg 
2489d57b3b3dSprasad 	if (pci_bus_res[bus].dip != NULL) {
2490d57b3b3dSprasad 		/* simply return if the property is already defined */
2491d57b3b3dSprasad 		if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip,
2492d57b3b3dSprasad 		    DDI_PROP_DONTPASS, "slot-names"))
2493d57b3b3dSprasad 			return;
2494d57b3b3dSprasad 	}
2495d57b3b3dSprasad 
2496b1f176e8Sjg 	len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop));
2497b1f176e8Sjg 	if (len > 0) {
249853273e82Ssethg 		/*
249953273e82Ssethg 		 * Only create a peer bus node if this bus may be a peer bus.
250053273e82Ssethg 		 * It may be a peer bus if the dip is NULL and if par_bus is
250153273e82Ssethg 		 * -1 (par_bus is -1 if this bus was not found to be
250253273e82Ssethg 		 * subordinate to any PCI-PCI bridge).
250353273e82Ssethg 		 * If it's not a peer bus, then the ACPI BBN-handling code
250453273e82Ssethg 		 * will remove it later.
250553273e82Ssethg 		 */
250653273e82Ssethg 		if (pci_bus_res[bus].par_bus == (uchar_t)-1 &&
250753273e82Ssethg 		    pci_bus_res[bus].dip == NULL) {
250853273e82Ssethg 
2509b1f176e8Sjg 			create_root_bus_dip(bus);
251053273e82Ssethg 		}
251153273e82Ssethg 		if (pci_bus_res[bus].dip != NULL) {
251253273e82Ssethg 			ASSERT((len % sizeof (int)) == 0);
251353273e82Ssethg 			(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
251453273e82Ssethg 			    pci_bus_res[bus].dip, "slot-names",
251553273e82Ssethg 			    (int *)slotprop, len / sizeof (int));
251653273e82Ssethg 		} else {
251753273e82Ssethg 			cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI "
251853273e82Ssethg 			    "IRQ routing table; Not adding slot-names "
251953273e82Ssethg 			    "property for incorrect bus %d", bus);
252053273e82Ssethg 		}
2521b1f176e8Sjg 	}
2522b1f176e8Sjg }
2523b1f176e8Sjg 
25247c478bd9Sstevel@tonic-gate static int
252500d0963fSdilpreet memlist_to_range(ppb_ranges_t *rp, struct memlist *entry, int type)
25267c478bd9Sstevel@tonic-gate {
25277c478bd9Sstevel@tonic-gate 	if (entry == NULL)
25287c478bd9Sstevel@tonic-gate 		return (0);
25297c478bd9Sstevel@tonic-gate 
25307c478bd9Sstevel@tonic-gate 	/* assume 32-bit addresses */
253100d0963fSdilpreet 	rp->child_high = rp->parent_high = type;
25327c478bd9Sstevel@tonic-gate 	rp->child_mid = rp->parent_mid = 0;
253300d0963fSdilpreet 	rp->child_low = rp->parent_low = (uint32_t)entry->address;
253400d0963fSdilpreet 	rp->size_high = 0;
253500d0963fSdilpreet 	rp->size_low = (uint32_t)entry->size;
25367c478bd9Sstevel@tonic-gate 	return (1);
25377c478bd9Sstevel@tonic-gate }
25387c478bd9Sstevel@tonic-gate 
25397c478bd9Sstevel@tonic-gate static void
25407c478bd9Sstevel@tonic-gate add_ppb_ranges_prop(int bus)
25417c478bd9Sstevel@tonic-gate {
25427c478bd9Sstevel@tonic-gate 	int i = 0;
254300d0963fSdilpreet 	ppb_ranges_t *rp;
25447c478bd9Sstevel@tonic-gate 
25457c478bd9Sstevel@tonic-gate 	rp = kmem_alloc(3 * sizeof (*rp), KM_SLEEP);
25467c478bd9Sstevel@tonic-gate 
25477c478bd9Sstevel@tonic-gate 	i = memlist_to_range(&rp[0], pci_bus_res[bus].io_ports,
25487c478bd9Sstevel@tonic-gate 	    PCI_ADDR_IO | PCI_REG_REL_M);
25497c478bd9Sstevel@tonic-gate 	i += memlist_to_range(&rp[i], pci_bus_res[bus].mem_space,
25507c478bd9Sstevel@tonic-gate 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
25517c478bd9Sstevel@tonic-gate 	i += memlist_to_range(&rp[i], pci_bus_res[bus].pmem_space,
25527c478bd9Sstevel@tonic-gate 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
25537c478bd9Sstevel@tonic-gate 
25547c478bd9Sstevel@tonic-gate 	if (i != 0)
25557c478bd9Sstevel@tonic-gate 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE,
25567c478bd9Sstevel@tonic-gate 		    pci_bus_res[bus].dip, "ranges", (int *)rp,
255700d0963fSdilpreet 		    i * sizeof (ppb_ranges_t) / sizeof (int));
25587c478bd9Sstevel@tonic-gate 	kmem_free(rp, 3 * sizeof (*rp));
25597c478bd9Sstevel@tonic-gate }
25607c478bd9Sstevel@tonic-gate 
25617c478bd9Sstevel@tonic-gate static int
25627c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type)
25637c478bd9Sstevel@tonic-gate {
25647c478bd9Sstevel@tonic-gate 	int i = 0;
25657c478bd9Sstevel@tonic-gate 
25667c478bd9Sstevel@tonic-gate 	while (list) {
25677c478bd9Sstevel@tonic-gate 		/* assume 32-bit addresses */
25687c478bd9Sstevel@tonic-gate 		sp->pci_phys_hi = type;
25697c478bd9Sstevel@tonic-gate 		sp->pci_phys_mid = 0;
25707c478bd9Sstevel@tonic-gate 		sp->pci_phys_low = (uint32_t)list->address;
25717c478bd9Sstevel@tonic-gate 		sp->pci_size_hi = 0;
25727c478bd9Sstevel@tonic-gate 		sp->pci_size_low = (uint32_t)list->size;
25737c478bd9Sstevel@tonic-gate 
25747c478bd9Sstevel@tonic-gate 		list = list->next;
25757c478bd9Sstevel@tonic-gate 		sp++, i++;
25767c478bd9Sstevel@tonic-gate 	}
25777c478bd9Sstevel@tonic-gate 	return (i);
25787c478bd9Sstevel@tonic-gate }
25797c478bd9Sstevel@tonic-gate 
25807c478bd9Sstevel@tonic-gate static void
25817c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus)
25827c478bd9Sstevel@tonic-gate {
25837c478bd9Sstevel@tonic-gate 	int i, count;
25847c478bd9Sstevel@tonic-gate 	struct pci_phys_spec *sp;
25857c478bd9Sstevel@tonic-gate 
25867c478bd9Sstevel@tonic-gate 	count = memlist_count(pci_bus_res[bus].io_ports) +
25877c478bd9Sstevel@tonic-gate 	    memlist_count(pci_bus_res[bus].mem_space) +
25887c478bd9Sstevel@tonic-gate 	    memlist_count(pci_bus_res[bus].pmem_space);
25897c478bd9Sstevel@tonic-gate 
25907c478bd9Sstevel@tonic-gate 	if (count == 0)		/* nothing available */
25917c478bd9Sstevel@tonic-gate 		return;
25927c478bd9Sstevel@tonic-gate 
25937c478bd9Sstevel@tonic-gate 	sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP);
25947c478bd9Sstevel@tonic-gate 	i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_ports,
25957c478bd9Sstevel@tonic-gate 	    PCI_ADDR_IO | PCI_REG_REL_M);
25967c478bd9Sstevel@tonic-gate 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_space,
25977c478bd9Sstevel@tonic-gate 	    PCI_ADDR_MEM32 | PCI_REG_REL_M);
25987c478bd9Sstevel@tonic-gate 	i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_space,
25997c478bd9Sstevel@tonic-gate 	    PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M);
26007c478bd9Sstevel@tonic-gate 	ASSERT(i == count);
26017c478bd9Sstevel@tonic-gate 
26027c478bd9Sstevel@tonic-gate 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip,
26037c478bd9Sstevel@tonic-gate 	    "available", (int *)sp,
26047c478bd9Sstevel@tonic-gate 	    i * sizeof (struct pci_phys_spec) / sizeof (int));
26057c478bd9Sstevel@tonic-gate 	kmem_free(sp, count * sizeof (*sp));
26067c478bd9Sstevel@tonic-gate }
2607f55ce205Sszhou 
2608f55ce205Sszhou static void
2609f55ce205Sszhou alloc_res_array(void)
2610f55ce205Sszhou {
2611f55ce205Sszhou 	static int array_max = 0;
2612f55ce205Sszhou 	int old_max;
2613f55ce205Sszhou 	void *old_res;
2614f55ce205Sszhou 
2615f55ce205Sszhou 	if (array_max > pci_bios_nbus + 1)
2616f55ce205Sszhou 		return;	/* array is big enough */
2617f55ce205Sszhou 
2618f55ce205Sszhou 	old_max = array_max;
2619f55ce205Sszhou 	old_res = pci_bus_res;
2620f55ce205Sszhou 
2621f55ce205Sszhou 	if (array_max == 0)
2622f55ce205Sszhou 		array_max = 16;	/* start with a reasonable number */
2623f55ce205Sszhou 
2624f55ce205Sszhou 	while (array_max < pci_bios_nbus + 1)
2625f55ce205Sszhou 		array_max <<= 1;
2626f55ce205Sszhou 	pci_bus_res = (struct pci_bus_resource *)kmem_zalloc(
2627f55ce205Sszhou 	    array_max * sizeof (struct pci_bus_resource), KM_SLEEP);
2628f55ce205Sszhou 
2629f55ce205Sszhou 	if (old_res) {	/* copy content and free old array */
2630f55ce205Sszhou 		bcopy(old_res, pci_bus_res,
2631f55ce205Sszhou 		    old_max * sizeof (struct pci_bus_resource));
2632f55ce205Sszhou 		kmem_free(old_res, old_max * sizeof (struct pci_bus_resource));
2633f55ce205Sszhou 	}
2634f55ce205Sszhou }
2635c8589f13Ssethg 
2636c8589f13Ssethg static void
2637c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid,
2638c8589f13Ssethg     ushort_t deviceid)
2639c8589f13Ssethg {
2640c8589f13Ssethg 	static dev_info_t *ioapicsnode = NULL;
2641c8589f13Ssethg 	static int numioapics = 0;
2642c8589f13Ssethg 	dev_info_t *ioapic_node;
2643c8589f13Ssethg 	uint64_t physaddr;
2644c8589f13Ssethg 	uint32_t lobase, hibase = 0;
2645c8589f13Ssethg 
2646c8589f13Ssethg 	/* BAR 0 contains the IOAPIC's memory-mapped I/O address */
2647c8589f13Ssethg 	lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0);
2648c8589f13Ssethg 
2649c8589f13Ssethg 	/* We (and the rest of the world) only support memory-mapped IOAPICs */
2650c8589f13Ssethg 	if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM)
2651c8589f13Ssethg 		return;
2652c8589f13Ssethg 
2653c8589f13Ssethg 	if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL)
2654c8589f13Ssethg 		hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4);
2655c8589f13Ssethg 
2656c8589f13Ssethg 	lobase &= PCI_BASE_M_ADDR_M;
2657c8589f13Ssethg 
2658c8589f13Ssethg 	physaddr = (((uint64_t)hibase) << 32) | lobase;
2659c8589f13Ssethg 
2660c8589f13Ssethg 	/*
2661c8589f13Ssethg 	 * Create a nexus node for all IOAPICs under the root node.
2662c8589f13Ssethg 	 */
2663c8589f13Ssethg 	if (ioapicsnode == NULL) {
2664c8589f13Ssethg 		if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME,
2665c8589f13Ssethg 		    (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) {
2666c8589f13Ssethg 			return;
2667c8589f13Ssethg 		}
2668c8589f13Ssethg 		(void) ndi_devi_online(ioapicsnode, 0);
2669c8589f13Ssethg 	}
2670c8589f13Ssethg 
2671c8589f13Ssethg 	/*
2672c8589f13Ssethg 	 * Create a child node for this IOAPIC
2673c8589f13Ssethg 	 */
2674c8589f13Ssethg 	ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME,
2675c8589f13Ssethg 	    DEVI_SID_NODEID, numioapics++);
2676c8589f13Ssethg 	if (ioapic_node == NULL) {
2677c8589f13Ssethg 		return;
2678c8589f13Ssethg 	}
2679c8589f13Ssethg 
2680c8589f13Ssethg 	/* Vendor and Device ID */
2681c8589f13Ssethg 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2682c8589f13Ssethg 	    IOAPICS_PROP_VENID, vendorid);
2683c8589f13Ssethg 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node,
2684c8589f13Ssethg 	    IOAPICS_PROP_DEVID, deviceid);
2685c8589f13Ssethg 
2686c8589f13Ssethg 	/* device_type */
2687c8589f13Ssethg 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node,
2688c8589f13Ssethg 	    "device_type", IOAPICS_DEV_TYPE);
2689c8589f13Ssethg 
2690c8589f13Ssethg 	/* reg */
2691c8589f13Ssethg 	(void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node,
2692c8589f13Ssethg 	    "reg", physaddr);
2693c8589f13Ssethg }
2694d57b3b3dSprasad 
2695d57b3b3dSprasad /*
2696d57b3b3dSprasad  * NOTE: For PCIe slots, the name is generated from the slot number
2697d57b3b3dSprasad  * information obtained from Slot Capabilities register.
2698d57b3b3dSprasad  * For non-PCIe slots, it is generated based on the slot number
2699d57b3b3dSprasad  * information in the PCI IRQ table.
2700d57b3b3dSprasad  */
2701d57b3b3dSprasad static void
2702d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num)
2703d57b3b3dSprasad {
2704d57b3b3dSprasad 	char slotprop[256];
2705d57b3b3dSprasad 	int len;
2706d57b3b3dSprasad 
2707d57b3b3dSprasad 	bzero(slotprop, sizeof (slotprop));
2708d57b3b3dSprasad 
2709d57b3b3dSprasad 	/* set mask to 1 as there is only one slot (i.e dev 0) */
2710d57b3b3dSprasad 	*(uint32_t *)slotprop = 1;
2711d57b3b3dSprasad 	len = 4;
2712d57b3b3dSprasad 	(void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d",
2713d57b3b3dSprasad 	    slot_num);
2714d57b3b3dSprasad 	len += strlen(slotprop + len) + 1;
2715d57b3b3dSprasad 	len += len % 4;
2716d57b3b3dSprasad 	(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names",
2717d57b3b3dSprasad 	    (int *)slotprop, len / sizeof (int));
2718d57b3b3dSprasad }
2719