17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22ec0c94e7SDana Myers * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/stat.h> 28ffa17327SGuoli Shu #include <sys/sysmacros.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 307c478bd9Sstevel@tonic-gate #include <sys/pci.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 337c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 347c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3570025d76Sjohnny #include <io/pci/mps_table.h> 36c88420b3Sdmick #include <sys/pci_cfgspace.h> 37c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 38c88420b3Sdmick #include <sys/psw.h> 3909f67678Sanish #include "../../../../common/pci/pci_strings.h" 40c8589f13Ssethg #include <sys/apic.h> 418a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 425af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h> 4325145214Smyers #include <sys/acpi/acpi.h> 4425145214Smyers #include <sys/acpica.h> 4586c1f4dcSVikram Hegde #include <sys/intel_iommu.h> 4694f1124eSVikram Hegde #include <sys/iommulib.h> 4700dfdf4aSDana Myers #include <sys/devcache.h> 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 507c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 517c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 527c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 537c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 547c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 557c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 587c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 597c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 60bd87be88Ssethg #define CONFIG_FIX 3 6170025d76Sjohnny #define COMPAT_BUFSIZE 512 627c478bd9Sstevel@tonic-gate 6305f867c3Sgs #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 6405f867c3Sgs #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 65ffa17327SGuoli Shu /* round down to nearest power of two */ 66ffa17327SGuoli Shu #define P2LE(align) \ 67ffa17327SGuoli Shu { \ 68ffa17327SGuoli Shu int i = 0; \ 69ffa17327SGuoli Shu while (align >>= 1) \ 70ffa17327SGuoli Shu i ++; \ 71ffa17327SGuoli Shu align = 1 << i; \ 72ffa17327SGuoli Shu } \ 7305f867c3Sgs 742f283da5SDan Mick /* for is_vga and list_is_vga_only */ 752f283da5SDan Mick 762f283da5SDan Mick enum io_mem { 772f283da5SDan Mick IO, 782f283da5SDan Mick MEM 792f283da5SDan Mick }; 802f283da5SDan Mick 81bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 82bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 83bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 84bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 85bd87be88Ssethg 86bd87be88Ssethg struct pci_fixundo { 87bd87be88Ssethg uint8_t bus; 88bd87be88Ssethg uint8_t dev; 89bd87be88Ssethg uint8_t fn; 90bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 91bd87be88Ssethg struct pci_fixundo *next; 92bd87be88Ssethg }; 93bd87be88Ssethg 9405f867c3Sgs struct pci_devfunc { 9505f867c3Sgs struct pci_devfunc *next; 9605f867c3Sgs dev_info_t *dip; 9705f867c3Sgs uchar_t dev; 9805f867c3Sgs uchar_t func; 9905f867c3Sgs boolean_t reprogram; /* this device needs to be reprogrammed */ 10005f867c3Sgs }; 10105f867c3Sgs 10278323854SJudy Chen extern int pseudo_isa; 103*47310cedSDana Myers extern int pci_bios_maxbus; 1047c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 1057c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 1067c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 107bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 10805f867c3Sgs static int num_root_bus = 0; /* count of root buses */ 1098fc7923fSDana Myers extern volatile int acpi_resource_discovery; 1107c478bd9Sstevel@tonic-gate 1117c478bd9Sstevel@tonic-gate /* 1127c478bd9Sstevel@tonic-gate * Module prototypes 1137c478bd9Sstevel@tonic-gate */ 1147c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 1157c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 11605f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 1177c478bd9Sstevel@tonic-gate ushort_t, int); 1187c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 11970025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 1207c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 12149fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 12249fbdd30SErwin T Tsaur ushort_t); 1237c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 1247c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 125b1f176e8Sjg static void add_bus_slot_names_prop(int); 1268fc7923fSDana Myers static void add_ranges_prop(int, int); 1277c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 12849fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 12905f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t); 130f55ce205Sszhou static void alloc_res_array(); 131c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 132c8589f13Ssethg ushort_t deviceid); 133d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1348fc7923fSDana Myers static void populate_bus_res(uchar_t bus); 1358fc7923fSDana Myers static void memlist_remove_list(struct memlist **list, 1368fc7923fSDana Myers struct memlist *remove_list); 1377c478bd9Sstevel@tonic-gate 13800dfdf4aSDana Myers static void pci_scan_bbn(void); 13900dfdf4aSDana Myers static int pci_unitaddr_cache_valid(void); 14000dfdf4aSDana Myers static int pci_bus_unitaddr(int); 14100dfdf4aSDana Myers static void pci_unitaddr_cache_create(void); 14200dfdf4aSDana Myers 14300dfdf4aSDana Myers static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 14400dfdf4aSDana Myers static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 14500dfdf4aSDana Myers static void pci_cache_free_list(nvf_handle_t); 14600dfdf4aSDana Myers 14775bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 14875bcd456Sjg 149ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 15025145214Smyers int pci_bus_always_renumber = 0; 15125145214Smyers 1521d6b7b34SJudy Chen /* 1531d6b7b34SJudy Chen * used to register ISA resource usage which must not be made 1541d6b7b34SJudy Chen * "available" from other PCI node' resource maps 1551d6b7b34SJudy Chen */ 1561d6b7b34SJudy Chen static struct { 1572f283da5SDan Mick struct memlist *io_used; 1582f283da5SDan Mick struct memlist *mem_used; 1591d6b7b34SJudy Chen } isa_res; 1601d6b7b34SJudy Chen 16100dfdf4aSDana Myers /* 16200dfdf4aSDana Myers * PCI unit-address cache management 16300dfdf4aSDana Myers */ 16400dfdf4aSDana Myers static nvf_ops_t pci_unitaddr_cache_ops = { 16500dfdf4aSDana Myers "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 16600dfdf4aSDana Myers pci_cache_unpack_nvlist, /* read in nvlist form */ 16700dfdf4aSDana Myers pci_cache_pack_nvlist, /* convert to nvlist form */ 16800dfdf4aSDana Myers pci_cache_free_list, /* free data list */ 16900dfdf4aSDana Myers NULL /* write complete callback */ 17000dfdf4aSDana Myers }; 17100dfdf4aSDana Myers 17200dfdf4aSDana Myers typedef struct { 17300dfdf4aSDana Myers list_node_t pua_nodes; 17400dfdf4aSDana Myers int pua_index; 17500dfdf4aSDana Myers int pua_addr; 17600dfdf4aSDana Myers } pua_node_t; 17700dfdf4aSDana Myers 17800dfdf4aSDana Myers nvf_handle_t puafd_handle; 17900dfdf4aSDana Myers int pua_cache_valid = 0; 18000dfdf4aSDana Myers 18100dfdf4aSDana Myers 18200dfdf4aSDana Myers /*ARGSUSED*/ 18300dfdf4aSDana Myers static ACPI_STATUS 18400dfdf4aSDana Myers pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) 18500dfdf4aSDana Myers { 18600dfdf4aSDana Myers ACPI_BUFFER rb; 18700dfdf4aSDana Myers ACPI_OBJECT ro; 18800dfdf4aSDana Myers ACPI_DEVICE_INFO *adi; 18900dfdf4aSDana Myers 19000dfdf4aSDana Myers /* 19100dfdf4aSDana Myers * Use AcpiGetObjectInfo() to find the device _HID 19200dfdf4aSDana Myers * If not a PCI root-bus, ignore this device and continue 19300dfdf4aSDana Myers * the walk 19400dfdf4aSDana Myers */ 19500dfdf4aSDana Myers 19600dfdf4aSDana Myers rb.Length = ACPI_ALLOCATE_BUFFER; 19700dfdf4aSDana Myers if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &rb))) 19800dfdf4aSDana Myers return (AE_OK); 19900dfdf4aSDana Myers 20000dfdf4aSDana Myers adi = rb.Pointer; 20100dfdf4aSDana Myers if (!(adi->Valid & ACPI_VALID_HID)) { 20200dfdf4aSDana Myers AcpiOsFree(adi); 20300dfdf4aSDana Myers return (AE_OK); 20400dfdf4aSDana Myers } 20500dfdf4aSDana Myers 20600dfdf4aSDana Myers if (strncmp(adi->HardwareId.Value, PCI_ROOT_HID_STRING, 20700dfdf4aSDana Myers sizeof (PCI_ROOT_HID_STRING)) && 20800dfdf4aSDana Myers strncmp(adi->HardwareId.Value, PCI_EXPRESS_ROOT_HID_STRING, 20900dfdf4aSDana Myers sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { 21000dfdf4aSDana Myers AcpiOsFree(adi); 21100dfdf4aSDana Myers return (AE_OK); 21200dfdf4aSDana Myers } 21300dfdf4aSDana Myers 21400dfdf4aSDana Myers AcpiOsFree(adi); 21500dfdf4aSDana Myers 21600dfdf4aSDana Myers /* 21700dfdf4aSDana Myers * XXX: ancient Big Bear broken _BBN will result in two 21800dfdf4aSDana Myers * bus 0 _BBNs being found, so we need to handle duplicate 21900dfdf4aSDana Myers * bus 0 gracefully. However, broken _BBN does not 22000dfdf4aSDana Myers * hide a childless root-bridge so no need to work-around it 22100dfdf4aSDana Myers * here 22200dfdf4aSDana Myers */ 22300dfdf4aSDana Myers rb.Pointer = &ro; 22400dfdf4aSDana Myers rb.Length = sizeof (ro); 22500dfdf4aSDana Myers if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", 22600dfdf4aSDana Myers NULL, &rb, ACPI_TYPE_INTEGER))) { 22700dfdf4aSDana Myers /* PCI with _BBN, process it, go no deeper */ 22800dfdf4aSDana Myers if (pci_bus_res[ro.Integer.Value].par_bus == (uchar_t)-1 && 22900dfdf4aSDana Myers pci_bus_res[ro.Integer.Value].dip == NULL) 23000dfdf4aSDana Myers create_root_bus_dip((uchar_t)ro.Integer.Value); 23100dfdf4aSDana Myers return (AE_CTRL_DEPTH); 23200dfdf4aSDana Myers } 23300dfdf4aSDana Myers 23400dfdf4aSDana Myers /* PCI and no _BBN, continue walk */ 23500dfdf4aSDana Myers return (AE_OK); 23600dfdf4aSDana Myers } 23700dfdf4aSDana Myers 23800dfdf4aSDana Myers /* 23900dfdf4aSDana Myers * Scan the ACPI namespace for all top-level instances of _BBN 24000dfdf4aSDana Myers * in order to discover childless root-bridges (which enumeration 24100dfdf4aSDana Myers * may not find; root-bridges are inferred by the existence of 24200dfdf4aSDana Myers * children). This scan should find all root-bridges that have 24300dfdf4aSDana Myers * been enumerated, and any childless root-bridges not enumerated. 24400dfdf4aSDana Myers * Root-bridge for bus 0 may not have a _BBN object. 24500dfdf4aSDana Myers */ 24600dfdf4aSDana Myers static void 24700dfdf4aSDana Myers pci_scan_bbn() 24800dfdf4aSDana Myers { 24900dfdf4aSDana Myers void *rv; 25000dfdf4aSDana Myers 25100dfdf4aSDana Myers (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); 25200dfdf4aSDana Myers } 25300dfdf4aSDana Myers 25400dfdf4aSDana Myers static void 25500dfdf4aSDana Myers pci_unitaddr_cache_init(void) 25600dfdf4aSDana Myers { 25700dfdf4aSDana Myers 25800dfdf4aSDana Myers puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 25900dfdf4aSDana Myers ASSERT(puafd_handle); 26000dfdf4aSDana Myers 26100dfdf4aSDana Myers list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 26200dfdf4aSDana Myers offsetof(pua_node_t, pua_nodes)); 26300dfdf4aSDana Myers 26400dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 26500dfdf4aSDana Myers (void) nvf_read_file(puafd_handle); 26600dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 26700dfdf4aSDana Myers } 26800dfdf4aSDana Myers 26900dfdf4aSDana Myers /* 27000dfdf4aSDana Myers * Format of /etc/devices/pci_unitaddr_persistent: 27100dfdf4aSDana Myers * 27200dfdf4aSDana Myers * The persistent record of unit-address assignments contains 27300dfdf4aSDana Myers * a list of name/value pairs, where name is a string representation 27400dfdf4aSDana Myers * of the "index value" of the PCI root-bus and the value is 27500dfdf4aSDana Myers * the assigned unit-address. 27600dfdf4aSDana Myers * 27700dfdf4aSDana Myers * The "index value" is simply the zero-based index of the PCI 27800dfdf4aSDana Myers * root-buses ordered by physical bus number; first PCI bus is 0, 27900dfdf4aSDana Myers * second is 1, and so on. 28000dfdf4aSDana Myers */ 28100dfdf4aSDana Myers 282e07545cfSDana Myers /*ARGSUSED*/ 28300dfdf4aSDana Myers static int 28400dfdf4aSDana Myers pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 28500dfdf4aSDana Myers { 28600dfdf4aSDana Myers long index; 28700dfdf4aSDana Myers int32_t value; 28800dfdf4aSDana Myers nvpair_t *np; 28900dfdf4aSDana Myers pua_node_t *node; 29000dfdf4aSDana Myers 29100dfdf4aSDana Myers np = NULL; 29200dfdf4aSDana Myers while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 29300dfdf4aSDana Myers /* name of nvpair is index value */ 29400dfdf4aSDana Myers if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 29500dfdf4aSDana Myers continue; 29600dfdf4aSDana Myers 29700dfdf4aSDana Myers if (nvpair_value_int32(np, &value) != 0) 29800dfdf4aSDana Myers continue; 29900dfdf4aSDana Myers 30000dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 30100dfdf4aSDana Myers node->pua_index = index; 30200dfdf4aSDana Myers node->pua_addr = value; 30300dfdf4aSDana Myers list_insert_tail(nvf_list(hdl), node); 30400dfdf4aSDana Myers } 30500dfdf4aSDana Myers 30600dfdf4aSDana Myers pua_cache_valid = 1; 30700dfdf4aSDana Myers return (DDI_SUCCESS); 30800dfdf4aSDana Myers } 30900dfdf4aSDana Myers 31000dfdf4aSDana Myers static int 31100dfdf4aSDana Myers pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 31200dfdf4aSDana Myers { 31300dfdf4aSDana Myers int rval; 31400dfdf4aSDana Myers nvlist_t *nvl, *sub_nvl; 31500dfdf4aSDana Myers list_t *listp; 31600dfdf4aSDana Myers pua_node_t *pua; 31700dfdf4aSDana Myers char buf[13]; 31800dfdf4aSDana Myers 31900dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 32000dfdf4aSDana Myers 32100dfdf4aSDana Myers rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 32200dfdf4aSDana Myers if (rval != DDI_SUCCESS) { 32300dfdf4aSDana Myers nvf_error("%s: nvlist alloc error %d\n", 32400dfdf4aSDana Myers nvf_cache_name(hdl), rval); 32500dfdf4aSDana Myers return (DDI_FAILURE); 32600dfdf4aSDana Myers } 32700dfdf4aSDana Myers 32800dfdf4aSDana Myers sub_nvl = NULL; 32900dfdf4aSDana Myers rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 33000dfdf4aSDana Myers if (rval != DDI_SUCCESS) 33100dfdf4aSDana Myers goto error; 33200dfdf4aSDana Myers 33300dfdf4aSDana Myers listp = nvf_list(hdl); 33400dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 33500dfdf4aSDana Myers pua = list_next(listp, pua)) { 336e07545cfSDana Myers (void) snprintf(buf, sizeof (buf), "%d", pua->pua_index); 33700dfdf4aSDana Myers rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 33800dfdf4aSDana Myers if (rval != DDI_SUCCESS) 33900dfdf4aSDana Myers goto error; 34000dfdf4aSDana Myers } 34100dfdf4aSDana Myers 34200dfdf4aSDana Myers rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 34300dfdf4aSDana Myers if (rval != DDI_SUCCESS) 34400dfdf4aSDana Myers goto error; 34500dfdf4aSDana Myers nvlist_free(sub_nvl); 34600dfdf4aSDana Myers 34700dfdf4aSDana Myers *ret_nvl = nvl; 34800dfdf4aSDana Myers return (DDI_SUCCESS); 34900dfdf4aSDana Myers 35000dfdf4aSDana Myers error: 35100dfdf4aSDana Myers if (sub_nvl) 35200dfdf4aSDana Myers nvlist_free(sub_nvl); 35300dfdf4aSDana Myers ASSERT(nvl); 35400dfdf4aSDana Myers nvlist_free(nvl); 35500dfdf4aSDana Myers *ret_nvl = NULL; 35600dfdf4aSDana Myers return (DDI_FAILURE); 35700dfdf4aSDana Myers } 35800dfdf4aSDana Myers 35900dfdf4aSDana Myers static void 36000dfdf4aSDana Myers pci_cache_free_list(nvf_handle_t hdl) 36100dfdf4aSDana Myers { 36200dfdf4aSDana Myers list_t *listp; 36300dfdf4aSDana Myers pua_node_t *pua; 36400dfdf4aSDana Myers 36500dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 36600dfdf4aSDana Myers 36700dfdf4aSDana Myers listp = nvf_list(hdl); 36800dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 36900dfdf4aSDana Myers pua = list_next(listp, pua)) { 37000dfdf4aSDana Myers list_remove(listp, pua); 37100dfdf4aSDana Myers kmem_free(pua, sizeof (pua_node_t)); 37200dfdf4aSDana Myers } 37300dfdf4aSDana Myers } 37400dfdf4aSDana Myers 37500dfdf4aSDana Myers 37600dfdf4aSDana Myers static int 37700dfdf4aSDana Myers pci_unitaddr_cache_valid(void) 37800dfdf4aSDana Myers { 37900dfdf4aSDana Myers 38000dfdf4aSDana Myers /* read only, no need for rw lock */ 38100dfdf4aSDana Myers return (pua_cache_valid); 38200dfdf4aSDana Myers } 38300dfdf4aSDana Myers 38400dfdf4aSDana Myers 38500dfdf4aSDana Myers static int 38600dfdf4aSDana Myers pci_bus_unitaddr(int index) 38700dfdf4aSDana Myers { 38800dfdf4aSDana Myers pua_node_t *pua; 38900dfdf4aSDana Myers list_t *listp; 39000dfdf4aSDana Myers int addr; 39100dfdf4aSDana Myers 39200dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_READER); 39300dfdf4aSDana Myers 39400dfdf4aSDana Myers addr = -1; /* default return if no match */ 39500dfdf4aSDana Myers listp = nvf_list(puafd_handle); 39600dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 39700dfdf4aSDana Myers pua = list_next(listp, pua)) { 39800dfdf4aSDana Myers if (pua->pua_index == index) { 39900dfdf4aSDana Myers addr = pua->pua_addr; 40000dfdf4aSDana Myers break; 40100dfdf4aSDana Myers } 40200dfdf4aSDana Myers } 40300dfdf4aSDana Myers 40400dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 40500dfdf4aSDana Myers return (addr); 40600dfdf4aSDana Myers } 40700dfdf4aSDana Myers 40800dfdf4aSDana Myers static void 40900dfdf4aSDana Myers pci_unitaddr_cache_create(void) 41000dfdf4aSDana Myers { 41100dfdf4aSDana Myers int i, index; 41200dfdf4aSDana Myers pua_node_t *node; 41300dfdf4aSDana Myers list_t *listp; 41400dfdf4aSDana Myers 41500dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 41600dfdf4aSDana Myers 41700dfdf4aSDana Myers index = 0; 41800dfdf4aSDana Myers listp = nvf_list(puafd_handle); 419*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 42000dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 42100dfdf4aSDana Myers if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 42200dfdf4aSDana Myers (pci_bus_res[i].dip == NULL)) 42300dfdf4aSDana Myers continue; 42400dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 42500dfdf4aSDana Myers node->pua_index = index++; 42600dfdf4aSDana Myers node->pua_addr = pci_bus_res[i].root_addr; 42700dfdf4aSDana Myers list_insert_tail(listp, node); 42800dfdf4aSDana Myers } 42900dfdf4aSDana Myers 43000dfdf4aSDana Myers (void) nvf_mark_dirty(puafd_handle); 43100dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 43200dfdf4aSDana Myers nvf_wake_daemon(); 43300dfdf4aSDana Myers } 43400dfdf4aSDana Myers 43500dfdf4aSDana Myers 4367c478bd9Sstevel@tonic-gate /* 4377c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 4387c478bd9Sstevel@tonic-gate */ 4397c478bd9Sstevel@tonic-gate void 44000dfdf4aSDana Myers pci_setup_tree(void) 4417c478bd9Sstevel@tonic-gate { 44205043691Sjames north - Sun Microsystems - Austin United States uint_t i, root_bus_addr = 0; 4437c478bd9Sstevel@tonic-gate 444f55ce205Sszhou alloc_res_array(); 445*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 4467c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 4477c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 4487c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 4497c478bd9Sstevel@tonic-gate } 4507c478bd9Sstevel@tonic-gate 4517c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 4527c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 4537c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 4547c478bd9Sstevel@tonic-gate 4557c478bd9Sstevel@tonic-gate /* 4567c478bd9Sstevel@tonic-gate * Now enumerate peer busses 4577c478bd9Sstevel@tonic-gate * 458*47310cedSDana Myers * We loop till pci_bios_maxbus. On most systems, there is 4597c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 4607c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 4617c478bd9Sstevel@tonic-gate * 4627c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 4637c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 4647c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 4657c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 4667c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 4677c478bd9Sstevel@tonic-gate * device below. 4687c478bd9Sstevel@tonic-gate */ 469*47310cedSDana Myers for (i = 1; i <= pci_bios_maxbus; i++) { 4707c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 4717c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 4727c478bd9Sstevel@tonic-gate } 4737c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 474b1f176e8Sjg 475b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 476b1f176e8Sjg add_bus_slot_names_prop(i); 4777c478bd9Sstevel@tonic-gate } 4787c478bd9Sstevel@tonic-gate 4797c478bd9Sstevel@tonic-gate } 4807c478bd9Sstevel@tonic-gate 48125145214Smyers /* 48225145214Smyers * >0 = present, 0 = not present, <0 = error 48325145214Smyers */ 48425145214Smyers static int 48525145214Smyers pci_bbn_present(int bus) 48625145214Smyers { 48725145214Smyers ACPI_HANDLE hdl; 48825145214Smyers int rv; 48925145214Smyers 49025145214Smyers /* no dip means no _BBN */ 49125145214Smyers if (pci_bus_res[bus].dip == NULL) 49225145214Smyers return (0); 49325145214Smyers 494db2bae30SDana Myers rv = -1; /* default return value in case of error below */ 495db2bae30SDana Myers if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 496db2bae30SDana Myers switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 497db2bae30SDana Myers case AE_OK: 498db2bae30SDana Myers rv = 1; 499db2bae30SDana Myers break; 500db2bae30SDana Myers case AE_NOT_FOUND: 501db2bae30SDana Myers rv = 0; 502db2bae30SDana Myers break; 503db2bae30SDana Myers default: 504db2bae30SDana Myers break; 505db2bae30SDana Myers } 506db2bae30SDana Myers } 50725145214Smyers 508db2bae30SDana Myers return (rv); 50925145214Smyers } 51025145214Smyers 51125145214Smyers /* 51225145214Smyers * Return non-zero if any PCI bus in the system has an associated 51325145214Smyers * _BBN object, 0 otherwise. 51425145214Smyers */ 51525145214Smyers static int 51625145214Smyers pci_roots_have_bbn(void) 51725145214Smyers { 51825145214Smyers int i; 51925145214Smyers 52025145214Smyers /* 52125145214Smyers * Scan the PCI busses and look for at least 1 _BBN 52225145214Smyers */ 523*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 52425145214Smyers /* skip non-root (peer) PCI busses */ 52525145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 52625145214Smyers continue; 52725145214Smyers 52825145214Smyers if (pci_bbn_present(i) > 0) 52925145214Smyers return (1); 53025145214Smyers } 53125145214Smyers return (0); 53225145214Smyers 53325145214Smyers } 53425145214Smyers 53525145214Smyers /* 53625145214Smyers * return non-zero if the machine is one on which we renumber 53725145214Smyers * the internal pci unit-addresses 53825145214Smyers */ 53925145214Smyers static int 54025145214Smyers pci_bus_renumber() 54125145214Smyers { 542ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 54325145214Smyers 544ee8c1d4aSdm if (pci_bus_always_renumber) 54525145214Smyers return (1); 546ee8c1d4aSdm 547ee8c1d4aSdm /* get the FADT */ 548db2bae30SDana Myers if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 549db2bae30SDana Myers AE_OK) 55025145214Smyers return (0); 55125145214Smyers 552ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 553ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 554ee8c1d4aSdm return (0); 555ee8c1d4aSdm else 556ee8c1d4aSdm return (1); 55725145214Smyers } 55825145214Smyers 55925145214Smyers /* 56025145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 56125145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 56225145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 56325145214Smyers * _BBN object associated with each peer bus; use the presence 56425145214Smyers * of this object to remove gaps in the numbering of the peer 56525145214Smyers * PCI bus unit-addresses - only peer busses with an associated 56625145214Smyers * _BBN are counted. 56725145214Smyers */ 56825145214Smyers static void 56925145214Smyers pci_renumber_root_busses(void) 57025145214Smyers { 57125145214Smyers int pci_regs[] = {0, 0, 0}; 57225145214Smyers int i, root_addr = 0; 57325145214Smyers 574ee8c1d4aSdm /* 575ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 576ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 577ee8c1d4aSdm * issue of upgrade changing physical device paths 578ee8c1d4aSdm */ 57925145214Smyers if (!pci_bus_renumber()) 58025145214Smyers return; 58125145214Smyers 58225145214Smyers /* 58325145214Smyers * If we find no _BBN objects at all, we either don't need 58425145214Smyers * to do anything or can't do anything anyway 58525145214Smyers */ 58625145214Smyers if (!pci_roots_have_bbn()) 58725145214Smyers return; 58825145214Smyers 589*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 59025145214Smyers /* skip non-root (peer) PCI busses */ 59125145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 59225145214Smyers continue; 59325145214Smyers 59425145214Smyers if (pci_bbn_present(i) < 1) { 59525145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 59625145214Smyers continue; 59725145214Smyers } 59825145214Smyers 59925145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 60025145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 60125145214Smyers /* update reg property for node */ 60225145214Smyers pci_bus_res[i].root_addr = root_addr; 60325145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 60425145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 60525145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 60625145214Smyers } 60725145214Smyers root_addr++; 60825145214Smyers } 60925145214Smyers } 61025145214Smyers 61178323854SJudy Chen void 6121d6b7b34SJudy Chen pci_register_isa_resources(int type, uint32_t base, uint32_t size) 613aaba6dfeSmyers { 6141d6b7b34SJudy Chen (void) memlist_insert( 6152f283da5SDan Mick (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 6161d6b7b34SJudy Chen base, size); 617aaba6dfeSmyers } 618aaba6dfeSmyers 6195af4ae46Sjveta /* 62005f867c3Sgs * Remove the resources which are already used by devices under a subtractive 62105f867c3Sgs * bridge from the bus's resources lists, because they're not available, and 62205f867c3Sgs * shouldn't be allocated to other buses. This is necessary because tracking 62305f867c3Sgs * resources for subtractive bridges is not complete. (Subtractive bridges only 62405f867c3Sgs * track some of their claimed resources, not "the rest of the address space" as 62505f867c3Sgs * they should, so that allocation to peer non-subtractive PPBs is easier. We 62605f867c3Sgs * need a fully-capable global resource allocator). 6275af4ae46Sjveta */ 62805f867c3Sgs static void 62905f867c3Sgs remove_subtractive_res() 6305af4ae46Sjveta { 63105f867c3Sgs int i, j; 63205f867c3Sgs struct memlist *list; 6335af4ae46Sjveta 634*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 63505f867c3Sgs if (pci_bus_res[i].subtractive) { 63605f867c3Sgs /* remove used io ports */ 6372f283da5SDan Mick list = pci_bus_res[i].io_used; 63805f867c3Sgs while (list) { 639*47310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) 6408fc7923fSDana Myers (void) memlist_remove( 6412f283da5SDan Mick &pci_bus_res[j].io_avail, 6428fc7923fSDana Myers list->address, list->size); 64305f867c3Sgs list = list->next; 64405f867c3Sgs } 64505f867c3Sgs /* remove used mem resource */ 6462f283da5SDan Mick list = pci_bus_res[i].mem_used; 64705f867c3Sgs while (list) { 648*47310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) { 6498fc7923fSDana Myers (void) memlist_remove( 6502f283da5SDan Mick &pci_bus_res[j].mem_avail, 6518fc7923fSDana Myers list->address, list->size); 6528fc7923fSDana Myers (void) memlist_remove( 6532f283da5SDan Mick &pci_bus_res[j].pmem_avail, 6548fc7923fSDana Myers list->address, list->size); 65505f867c3Sgs } 65605f867c3Sgs list = list->next; 65705f867c3Sgs } 65805f867c3Sgs /* remove used prefetchable mem resource */ 6592f283da5SDan Mick list = pci_bus_res[i].pmem_used; 66005f867c3Sgs while (list) { 661*47310cedSDana Myers for (j = 0; j <= pci_bios_maxbus; j++) { 6628fc7923fSDana Myers (void) memlist_remove( 6632f283da5SDan Mick &pci_bus_res[j].pmem_avail, 6648fc7923fSDana Myers list->address, list->size); 6658fc7923fSDana Myers (void) memlist_remove( 6662f283da5SDan Mick &pci_bus_res[j].mem_avail, 6678fc7923fSDana Myers list->address, list->size); 66805f867c3Sgs } 66905f867c3Sgs list = list->next; 67005f867c3Sgs } 6715af4ae46Sjveta } 67205f867c3Sgs } 67305f867c3Sgs } 67405f867c3Sgs 6758fc7923fSDana Myers /* 6762f283da5SDan Mick * Set up (or complete the setup of) the bus_avail resource list 6778fc7923fSDana Myers */ 67805f867c3Sgs static void 67905f867c3Sgs setup_bus_res(int bus) 68005f867c3Sgs { 68105f867c3Sgs uchar_t par_bus; 68205f867c3Sgs 68305f867c3Sgs if (pci_bus_res[bus].dip == NULL) /* unused bus */ 68405f867c3Sgs return; 68505f867c3Sgs 6868fc7923fSDana Myers /* 6872f283da5SDan Mick * Set up bus_avail if not already filled in by populate_bus_res() 6888fc7923fSDana Myers */ 6892f283da5SDan Mick if (pci_bus_res[bus].bus_avail == NULL) { 6908fc7923fSDana Myers ASSERT(pci_bus_res[bus].sub_bus >= bus); 6912f283da5SDan Mick memlist_insert(&pci_bus_res[bus].bus_avail, bus, 6928fc7923fSDana Myers pci_bus_res[bus].sub_bus - bus + 1); 69305f867c3Sgs } 6945af4ae46Sjveta 6952f283da5SDan Mick ASSERT(pci_bus_res[bus].bus_avail != NULL); 6968fc7923fSDana Myers 69705f867c3Sgs /* 69805f867c3Sgs * Remove resources from parent bus node if this is not a 69905f867c3Sgs * root bus. 70005f867c3Sgs */ 70105f867c3Sgs par_bus = pci_bus_res[bus].par_bus; 70205f867c3Sgs if (par_bus != (uchar_t)-1) { 7032f283da5SDan Mick ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 7042f283da5SDan Mick memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 7052f283da5SDan Mick pci_bus_res[bus].bus_avail); 70605f867c3Sgs } 7078fc7923fSDana Myers 7082f283da5SDan Mick /* remove self from bus_avail */; 7092f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 7105af4ae46Sjveta } 7115af4ae46Sjveta 71205f867c3Sgs static uint64_t 71305f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 7145af4ae46Sjveta { 71505f867c3Sgs uint64_t addr = 0; 71605f867c3Sgs uchar_t res_bus; 7175af4ae46Sjveta 71805f867c3Sgs /* 7198fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7208fc7923fSDana Myers * ACPI resource discovery was not successfully done. 72105f867c3Sgs */ 72205f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7238fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7245af4ae46Sjveta return (0); 7255af4ae46Sjveta 72605f867c3Sgs res_bus = parbus; 72705f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7282f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) 72905f867c3Sgs break; 73005f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 73105f867c3Sgs if (res_bus == (uchar_t)-1) 73205f867c3Sgs break; /* root bus already */ 73305f867c3Sgs } 7345af4ae46Sjveta 7352f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 7362f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].io_avail, 73705f867c3Sgs size, align); 73805f867c3Sgs if (addr) { 7392f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].io_used, 74005f867c3Sgs addr, size); 7418fc7923fSDana Myers 74205f867c3Sgs /* free the old resource */ 7432f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_avail); 7442f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_used); 7458fc7923fSDana Myers 74605f867c3Sgs /* add the new resource */ 7472f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 74805f867c3Sgs } 7495af4ae46Sjveta } 7505af4ae46Sjveta 75105f867c3Sgs return (addr); 75205f867c3Sgs } 75305f867c3Sgs 75405f867c3Sgs static uint64_t 75505f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 75605f867c3Sgs { 75705f867c3Sgs uint64_t addr = 0; 75805f867c3Sgs uchar_t res_bus; 7595af4ae46Sjveta 7605af4ae46Sjveta /* 7618fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7628fc7923fSDana Myers * ACPI resource discovery was not successfully done. 7635af4ae46Sjveta */ 76405f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7658fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7665af4ae46Sjveta return (0); 7675af4ae46Sjveta 76805f867c3Sgs res_bus = parbus; 76905f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7702f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) 77105f867c3Sgs break; 77205f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 77305f867c3Sgs if (res_bus == (uchar_t)-1) 77405f867c3Sgs break; /* root bus already */ 77505f867c3Sgs } 77605f867c3Sgs 7772f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) { 7782f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 77905f867c3Sgs size, align); 78005f867c3Sgs if (addr) { 7812f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].mem_used, 78205f867c3Sgs addr, size); 7832f283da5SDan Mick (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 7848fc7923fSDana Myers addr, size); 7858fc7923fSDana Myers 78605f867c3Sgs /* free the old resource */ 7872f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_avail); 7882f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_used); 7898fc7923fSDana Myers 79005f867c3Sgs /* add the new resource */ 7912f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 79205f867c3Sgs } 79305f867c3Sgs } 79405f867c3Sgs 79505f867c3Sgs return (addr); 7965af4ae46Sjveta } 7975af4ae46Sjveta 79849fbdd30SErwin T Tsaur /* 79949fbdd30SErwin T Tsaur * given a cap_id, return its cap_id location in config space 80049fbdd30SErwin T Tsaur */ 80149fbdd30SErwin T Tsaur static int 80249fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 80349fbdd30SErwin T Tsaur { 80449fbdd30SErwin T Tsaur uint8_t curcap, cap_id_loc; 80549fbdd30SErwin T Tsaur uint16_t status; 80649fbdd30SErwin T Tsaur int location = -1; 80749fbdd30SErwin T Tsaur 80849fbdd30SErwin T Tsaur /* 80949fbdd30SErwin T Tsaur * Need to check the Status register for ECP support first. 81049fbdd30SErwin T Tsaur * Also please note that for type 1 devices, the 81149fbdd30SErwin T Tsaur * offset could change. Should support type 1 next. 81249fbdd30SErwin T Tsaur */ 81349fbdd30SErwin T Tsaur status = pci_getw(bus, dev, func, PCI_CONF_STAT); 81449fbdd30SErwin T Tsaur if (!(status & PCI_STAT_CAP)) { 81549fbdd30SErwin T Tsaur return (-1); 81649fbdd30SErwin T Tsaur } 81749fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 81849fbdd30SErwin T Tsaur 81949fbdd30SErwin T Tsaur /* Walk the list of capabilities */ 82049fbdd30SErwin T Tsaur while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 82149fbdd30SErwin T Tsaur curcap = pci_getb(bus, dev, func, cap_id_loc); 82249fbdd30SErwin T Tsaur 82349fbdd30SErwin T Tsaur if (curcap == cap_id) { 82449fbdd30SErwin T Tsaur location = cap_id_loc; 82549fbdd30SErwin T Tsaur break; 82649fbdd30SErwin T Tsaur } 82749fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 82849fbdd30SErwin T Tsaur } 82949fbdd30SErwin T Tsaur return (location); 83049fbdd30SErwin T Tsaur } 83149fbdd30SErwin T Tsaur 8322f283da5SDan Mick /* 8332f283da5SDan Mick * Does this resource element live in the legacy VGA range? 8342f283da5SDan Mick */ 8352f283da5SDan Mick 8362f283da5SDan Mick int 8372f283da5SDan Mick is_vga(struct memlist *elem, enum io_mem io) 8382f283da5SDan Mick { 8392f283da5SDan Mick 8402f283da5SDan Mick if (io == IO) { 8412f283da5SDan Mick if ((elem->address == 0x3b0 && elem->size == 0xc) || 8422f283da5SDan Mick (elem->address == 0x3c0 && elem->size == 0x20)) 8432f283da5SDan Mick return (1); 8442f283da5SDan Mick } else { 8452f283da5SDan Mick if (elem->address == 0xa0000 && elem->size == 0x20000) 8462f283da5SDan Mick return (1); 8472f283da5SDan Mick } 8482f283da5SDan Mick return (0); 8492f283da5SDan Mick } 8502f283da5SDan Mick 8512f283da5SDan Mick /* 8522f283da5SDan Mick * Does this entire resource list consist only of legacy VGA resources? 8532f283da5SDan Mick */ 8542f283da5SDan Mick 8552f283da5SDan Mick int 8562f283da5SDan Mick list_is_vga_only(struct memlist *l, enum io_mem io) 8572f283da5SDan Mick { 8582f283da5SDan Mick do { 8592f283da5SDan Mick if (!is_vga(l, io)) 8602f283da5SDan Mick return (0); 8612f283da5SDan Mick } while ((l = l->next) != NULL); 8622f283da5SDan Mick return (1); 8632f283da5SDan Mick } 8642f283da5SDan Mick 8659896aa55Sjveta /* 86605f867c3Sgs * Assign valid resources to unconfigured pci(e) bridges. We are trying 86705f867c3Sgs * to reprogram the bridge when its 86805f867c3Sgs * i) SECBUS == SUBBUS || 86905f867c3Sgs * ii) IOBASE > IOLIM || 87005f867c3Sgs * iii) MEMBASE > MEMLIM 87105f867c3Sgs * This must be done after one full pass through the PCI tree to collect 87205f867c3Sgs * all BIOS-configured resources, so that we know what resources are 87305f867c3Sgs * free and available to assign to the unconfigured PPBs. 8749896aa55Sjveta */ 8759896aa55Sjveta static void 87605f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 8779896aa55Sjveta { 8789896aa55Sjveta uchar_t bus, dev, func; 87905f867c3Sgs uchar_t parbus, subbus; 88005f867c3Sgs uint_t io_base, io_limit, mem_base, mem_limit; 881ffa17327SGuoli Shu uint_t io_size, mem_size, io_align, mem_align; 88205f867c3Sgs uint64_t addr = 0; 8835af4ae46Sjveta int *regp = NULL; 8849896aa55Sjveta uint_t reglen; 8855af4ae46Sjveta int rv, cap_ptr, physhi; 8869896aa55Sjveta dev_info_t *dip; 88705f867c3Sgs uint16_t cmd_reg; 88842e542bcSDan Mick struct memlist *list, *scratch_list; 88905f867c3Sgs 89005f867c3Sgs /* skip root (peer) PCI busses */ 89105f867c3Sgs if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 89205f867c3Sgs return; 89305f867c3Sgs 89405f867c3Sgs /* skip subtractive PPB when prog_sub is not TRUE */ 89505f867c3Sgs if (pci_bus_res[secbus].subtractive && !prog_sub) 89605f867c3Sgs return; 8979896aa55Sjveta 8989896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 8995af4ae46Sjveta dip = pci_bus_res[secbus].dip; 9009896aa55Sjveta if (dip == NULL) 9019896aa55Sjveta return; 9029896aa55Sjveta 9039896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 9049896aa55Sjveta "reg", ®p, ®len); 9052f283da5SDan Mick if (rv != DDI_PROP_SUCCESS || reglen == 0) 9062f283da5SDan Mick return; 9075af4ae46Sjveta physhi = regp[0]; 9085af4ae46Sjveta ddi_prop_free(regp); 9099896aa55Sjveta 9105af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 9115af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 9125af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 9139896aa55Sjveta 9149896aa55Sjveta /* 91505f867c3Sgs * If pcie bridge, check to see if link is enabled 9169896aa55Sjveta */ 91749fbdd30SErwin T Tsaur cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 91849fbdd30SErwin T Tsaur if (cap_ptr != -1) { 91905f867c3Sgs cmd_reg = pci_getw(bus, dev, func, 92005f867c3Sgs (uint16_t)cap_ptr + PCIE_LINKCTL); 92105f867c3Sgs if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 92205f867c3Sgs dcmn_err(CE_NOTE, 92305f867c3Sgs "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 92405f867c3Sgs bus, dev, func); 92505f867c3Sgs return; 92605f867c3Sgs } 92705f867c3Sgs } 9289896aa55Sjveta 92905f867c3Sgs subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 93005f867c3Sgs parbus = pci_bus_res[secbus].par_bus; 93105f867c3Sgs ASSERT(parbus == bus); 932707a5600Sgs cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 9339896aa55Sjveta 9345af4ae46Sjveta /* 93505f867c3Sgs * If we have a Cardbus bridge, but no bus space 9365af4ae46Sjveta */ 93705f867c3Sgs if (pci_bus_res[secbus].num_cbb != 0 && 9382f283da5SDan Mick pci_bus_res[secbus].bus_avail == NULL) { 93905f867c3Sgs uchar_t range; 9405af4ae46Sjveta 94105f867c3Sgs /* normally there are 2 buses under a cardbus bridge */ 94205f867c3Sgs range = pci_bus_res[secbus].num_cbb * 2; 94305f867c3Sgs 94405f867c3Sgs /* 94505f867c3Sgs * Try to find and allocate a bus-range starting at subbus+1 94605f867c3Sgs * from the parent of the PPB. 94705f867c3Sgs */ 94805f867c3Sgs for (; range != 0; range--) { 94905f867c3Sgs if (memlist_find_with_startaddr( 9502f283da5SDan Mick &pci_bus_res[parbus].bus_avail, 95105f867c3Sgs subbus + 1, range, 1) != NULL) 95205f867c3Sgs break; /* find bus range resource at parent */ 95305f867c3Sgs } 95405f867c3Sgs if (range != 0) { 9552f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].bus_avail, 95605f867c3Sgs subbus + 1, range); 95705f867c3Sgs subbus = subbus + range; 95805f867c3Sgs pci_bus_res[secbus].sub_bus = subbus; 95905f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 96005f867c3Sgs add_bus_range_prop(secbus); 96105f867c3Sgs 96205f867c3Sgs cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 96305f867c3Sgs "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 96405f867c3Sgs secbus, subbus); 96505f867c3Sgs } 96605f867c3Sgs } 96705f867c3Sgs 96805f867c3Sgs /* 969ffa17327SGuoli Shu * Calculate required IO size and alignment 970ffa17327SGuoli Shu * If bus io_size is zero, we are going to assign 512 bytes per bus, 971ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 972ffa17327SGuoli Shu * bus io_size. The size needs to be 4K aligned. 973ffa17327SGuoli Shu * 974ffa17327SGuoli Shu * We calculate alignment as the largest power of two less than the 975ffa17327SGuoli Shu * the sum of all children's IO size requirements, because this will 976ffa17327SGuoli Shu * align to the size of the largest child request within that size 977ffa17327SGuoli Shu * (which is always a power of two). 97805f867c3Sgs */ 97905f867c3Sgs io_size = (subbus - secbus + 1) * 0x200; 980ffa17327SGuoli Shu if (io_size < pci_bus_res[secbus].io_size) 981ffa17327SGuoli Shu io_size = pci_bus_res[secbus].io_size; 982ffa17327SGuoli Shu io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 983ffa17327SGuoli Shu io_align = io_size; 984ffa17327SGuoli Shu P2LE(io_align); 985ffa17327SGuoli Shu 9865af4ae46Sjveta /* 987ffa17327SGuoli Shu * Calculate required MEM size and alignment 988ffa17327SGuoli Shu * If bus mem_size is zero, we are going to assign 1M bytes per bus, 989ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 990ffa17327SGuoli Shu * bus mem_size. The size needs to be 1M aligned. 991ffa17327SGuoli Shu * 992ffa17327SGuoli Shu * For the alignment, refer to the I/O comment above. 9935af4ae46Sjveta */ 99405f867c3Sgs mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 995ffa17327SGuoli Shu if (mem_size < pci_bus_res[secbus].mem_size) { 996ffa17327SGuoli Shu mem_size = pci_bus_res[secbus].mem_size; 997ffa17327SGuoli Shu mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 998ffa17327SGuoli Shu } 999ffa17327SGuoli Shu mem_align = mem_size; 1000ffa17327SGuoli Shu P2LE(mem_align); 100105f867c3Sgs 100205f867c3Sgs /* Subtractive bridge */ 100305f867c3Sgs if (pci_bus_res[secbus].subtractive && prog_sub) { 100405f867c3Sgs /* 100505f867c3Sgs * We program an arbitrary amount of I/O and memory resource 100605f867c3Sgs * for the subtractive bridge so that child dynamic-resource- 100705f867c3Sgs * allocating devices (such as Cardbus bridges) have a chance 100805f867c3Sgs * of success. Until we have full-tree resource rebalancing, 100905f867c3Sgs * dynamic resource allocation (thru busra) only looks at the 101005f867c3Sgs * parent bridge, so all PPBs must have some allocatable 101105f867c3Sgs * resource. For non-subtractive bridges, the resources come 101205f867c3Sgs * from the base/limit register "windows", but subtractive 101305f867c3Sgs * bridges often don't program those (since they don't need to). 101405f867c3Sgs * If we put all the remaining resources on the subtractive 101505f867c3Sgs * bridge, then peer non-subtractive bridges can't allocate 101605f867c3Sgs * more space (even though this is probably most correct). 101705f867c3Sgs * If we put the resources only on the parent, then allocations 101805f867c3Sgs * from children of subtractive bridges will fail without 101905f867c3Sgs * special-case code for bypassing the subtractive bridge. 102005f867c3Sgs * This solution is the middle-ground temporary solution until 102105f867c3Sgs * we have fully-capable resource allocation. 102205f867c3Sgs */ 102305f867c3Sgs 102405f867c3Sgs /* 102505f867c3Sgs * Add an arbitrary I/O resource to the subtractive PPB 102605f867c3Sgs */ 10272f283da5SDan Mick if (pci_bus_res[secbus].io_avail == NULL) { 102805f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1029ffa17327SGuoli Shu io_align); 103005f867c3Sgs if (addr) { 10318fc7923fSDana Myers add_ranges_prop(secbus, 1); 103205f867c3Sgs pci_bus_res[secbus].io_reprogram = 103305f867c3Sgs pci_bus_res[parbus].io_reprogram; 103405f867c3Sgs 103505f867c3Sgs cmn_err(CE_NOTE, "!add io-range on subtractive" 103605f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 103705f867c3Sgs bus, dev, func, (uint32_t)addr, 103805f867c3Sgs (uint32_t)addr + io_size - 1); 103905f867c3Sgs } 104005f867c3Sgs } 104105f867c3Sgs /* 104205f867c3Sgs * Add an arbitrary memory resource to the subtractive PPB 104305f867c3Sgs */ 10442f283da5SDan Mick if (pci_bus_res[secbus].mem_avail == NULL) { 104505f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1046ffa17327SGuoli Shu mem_align); 104705f867c3Sgs if (addr) { 10488fc7923fSDana Myers add_ranges_prop(secbus, 1); 104905f867c3Sgs pci_bus_res[secbus].mem_reprogram = 105005f867c3Sgs pci_bus_res[parbus].mem_reprogram; 105105f867c3Sgs 105205f867c3Sgs cmn_err(CE_NOTE, "!add mem-range on " 105305f867c3Sgs "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 105405f867c3Sgs bus, dev, func, (uint32_t)addr, 105505f867c3Sgs (uint32_t)addr + mem_size - 1); 105605f867c3Sgs } 105705f867c3Sgs } 105805f867c3Sgs 105905f867c3Sgs goto cmd_enable; 10605af4ae46Sjveta } 106105f867c3Sgs 106205f867c3Sgs /* 1063707a5600Sgs * Check to see if we need to reprogram I/O space, either because the 1064707a5600Sgs * parent bus needed reprogramming and so do we, or because I/O space is 1065707a5600Sgs * disabled in base/limit or command register. 106605f867c3Sgs */ 106705f867c3Sgs io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 106805f867c3Sgs io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 106905f867c3Sgs io_base = (io_base & 0xf0) << 8; 107005f867c3Sgs io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 107105f867c3Sgs 10722f283da5SDan Mick /* Form list of all resources passed (avail + used) */ 107342e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 107442e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 10752f283da5SDan Mick 10762f283da5SDan Mick if ((pci_bus_res[parbus].io_reprogram || 10772f283da5SDan Mick (io_base > io_limit) || 10782f283da5SDan Mick (!(cmd_reg & PCI_COMM_IO))) && 107942e542bcSDan Mick !list_is_vga_only(scratch_list, IO)) { 10802f283da5SDan Mick if (pci_bus_res[secbus].io_used) { 10812f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].io_used, 10822f283da5SDan Mick &pci_bus_res[secbus].io_avail); 108305f867c3Sgs } 10842f283da5SDan Mick if (pci_bus_res[secbus].io_avail && 108505f867c3Sgs (!pci_bus_res[parbus].io_reprogram) && 108605f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 108705f867c3Sgs /* rechoose old io ports info */ 10882f283da5SDan Mick list = pci_bus_res[secbus].io_avail; 10892f283da5SDan Mick io_base = 0; 10902f283da5SDan Mick do { 10912f283da5SDan Mick if (is_vga(list, IO)) 10922f283da5SDan Mick continue; 10932f283da5SDan Mick if (!io_base) { 10942f283da5SDan Mick io_base = (uint_t)list->address; 109505f867c3Sgs io_limit = (uint_t) 10962f283da5SDan Mick list->address + list->size - 1; 10972f283da5SDan Mick io_base = 10982f283da5SDan Mick P2ALIGN(io_base, PPB_IO_ALIGNMENT); 10992f283da5SDan Mick } else { 11002f283da5SDan Mick if (list->address + list->size > 11012f283da5SDan Mick io_limit) { 11022f283da5SDan Mick io_limit = (uint_t) 11032f283da5SDan Mick (list->address + 11042f283da5SDan Mick list->size - 1); 11052f283da5SDan Mick } 11062f283da5SDan Mick } 11072f283da5SDan Mick } while ((list = list->next) != NULL); 110805f867c3Sgs /* 4K aligned */ 11092f283da5SDan Mick io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 11102f283da5SDan Mick io_size = io_limit - io_base + 1; 111105f867c3Sgs ASSERT(io_base <= io_limit); 11122f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].io_avail); 11132f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 111405f867c3Sgs io_base, io_size); 11152f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].io_used, 111605f867c3Sgs io_base, io_size); 11172f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].io_avail, 11188fc7923fSDana Myers io_base, io_size); 111905f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 112005f867c3Sgs } else { 112105f867c3Sgs /* get new io ports from parent bus */ 112205f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1123ffa17327SGuoli Shu io_align); 112405f867c3Sgs if (addr) { 112505f867c3Sgs io_base = addr; 112605f867c3Sgs io_limit = addr + io_size - 1; 112705f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 112805f867c3Sgs } 112905f867c3Sgs } 113005f867c3Sgs if (pci_bus_res[secbus].io_reprogram) { 113105f867c3Sgs /* reprogram PPB regs */ 113205f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 113305f867c3Sgs (uchar_t)((io_base>>8) & 0xf0)); 113405f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 113505f867c3Sgs (uchar_t)((io_limit>>8) & 0xf0)); 113605f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 113705f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 11388fc7923fSDana Myers add_ranges_prop(secbus, 1); 113905f867c3Sgs 114005f867c3Sgs cmn_err(CE_NOTE, "!reprogram io-range on" 114105f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 114205f867c3Sgs bus, dev, func, io_base, io_limit); 114305f867c3Sgs } 11449896aa55Sjveta } 114542e542bcSDan Mick memlist_free_all(&scratch_list); 11469896aa55Sjveta 11475af4ae46Sjveta /* 1148707a5600Sgs * Check memory space as we did I/O space. 11495af4ae46Sjveta */ 115005f867c3Sgs mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 115105f867c3Sgs mem_base = (mem_base & 0xfff0) << 16; 115205f867c3Sgs mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1153707a5600Sgs mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 1154707a5600Sgs 115542e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 115642e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 11572f283da5SDan Mick 11582f283da5SDan Mick if ((pci_bus_res[parbus].mem_reprogram || 11592f283da5SDan Mick (mem_base > mem_limit) || 11602f283da5SDan Mick (!(cmd_reg & PCI_COMM_MAE))) && 116142e542bcSDan Mick !list_is_vga_only(scratch_list, MEM)) { 11622f283da5SDan Mick if (pci_bus_res[secbus].mem_used) { 11632f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].mem_used, 11642f283da5SDan Mick &pci_bus_res[secbus].mem_avail); 116505f867c3Sgs } 11662f283da5SDan Mick if (pci_bus_res[secbus].mem_avail && 116705f867c3Sgs (!pci_bus_res[parbus].mem_reprogram) && 116805f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 116905f867c3Sgs /* rechoose old mem resource */ 11702f283da5SDan Mick list = pci_bus_res[secbus].mem_avail; 11712f283da5SDan Mick mem_base = 0; 11722f283da5SDan Mick do { 11732f283da5SDan Mick if (is_vga(list, MEM)) 11742f283da5SDan Mick continue; 11752f283da5SDan Mick if (mem_base == 0) { 11762f283da5SDan Mick mem_base = (uint_t)list->address; 11772f283da5SDan Mick mem_base = P2ALIGN(mem_base, 11782f283da5SDan Mick PPB_MEM_ALIGNMENT); 117905f867c3Sgs mem_limit = (uint_t) 11802f283da5SDan Mick (list->address + list->size - 1); 11812f283da5SDan Mick } else { 11822f283da5SDan Mick if ((list->address + list->size) > 11832f283da5SDan Mick mem_limit) { 11842f283da5SDan Mick mem_limit = (uint_t) 11852f283da5SDan Mick (list->address + 11862f283da5SDan Mick list->size - 1); 11872f283da5SDan Mick } 11882f283da5SDan Mick } 11892f283da5SDan Mick } while ((list = list->next) != NULL); 11902f283da5SDan Mick mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 11912f283da5SDan Mick mem_size = mem_limit + 1 - mem_base; 119205f867c3Sgs ASSERT(mem_base <= mem_limit); 11932f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].mem_avail); 11942f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 119505f867c3Sgs mem_base, mem_size); 11962f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].mem_used, 119705f867c3Sgs mem_base, mem_size); 11982f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 11998fc7923fSDana Myers mem_base, mem_size); 120005f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 120105f867c3Sgs } else { 120205f867c3Sgs /* get new mem resource from parent bus */ 120305f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1204ffa17327SGuoli Shu mem_align); 120505f867c3Sgs if (addr) { 120605f867c3Sgs mem_base = addr; 120705f867c3Sgs mem_limit = addr + mem_size - 1; 120805f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 120905f867c3Sgs } 121005f867c3Sgs } 121105f867c3Sgs 121205f867c3Sgs if (pci_bus_res[secbus].mem_reprogram) { 121302c2c4edSGuoli Shu /* reprogram PPB MEM regs */ 121405f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 121505f867c3Sgs (uint16_t)((mem_base>>16) & 0xfff0)); 121605f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 121705f867c3Sgs (uint16_t)((mem_limit>>16) & 0xfff0)); 121802c2c4edSGuoli Shu /* 121902c2c4edSGuoli Shu * Disable PMEM window by setting base > limit. 122002c2c4edSGuoli Shu * We currently don't reprogram the PMEM like we've 122102c2c4edSGuoli Shu * done for I/O and MEM. (Devices that support prefetch 122202c2c4edSGuoli Shu * can use non-prefetch MEM.) Anyway, if the MEM access 122302c2c4edSGuoli Shu * bit is initially disabled by BIOS, we disable the 122402c2c4edSGuoli Shu * PMEM window manually by setting PMEM base > PMEM 122502c2c4edSGuoli Shu * limit here, in case there are incorrect values in 122602c2c4edSGuoli Shu * them from BIOS, so that we won't get in trouble once 122702c2c4edSGuoli Shu * the MEM access bit is enabled at the end of this 122802c2c4edSGuoli Shu * function. 122902c2c4edSGuoli Shu */ 123002c2c4edSGuoli Shu if (!(cmd_reg & PCI_COMM_MAE)) { 123102c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 123202c2c4edSGuoli Shu 0xfff0); 123302c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 123402c2c4edSGuoli Shu 0x0); 123502c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 123602c2c4edSGuoli Shu 0xffffffff); 123702c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 123802c2c4edSGuoli Shu 0x0); 123902c2c4edSGuoli Shu } 124002c2c4edSGuoli Shu 12418fc7923fSDana Myers add_ranges_prop(secbus, 1); 124205f867c3Sgs 124305f867c3Sgs cmn_err(CE_NOTE, "!reprogram mem-range on" 124405f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 124505f867c3Sgs bus, dev, func, mem_base, mem_limit); 124605f867c3Sgs } 124705f867c3Sgs } 124842e542bcSDan Mick memlist_free_all(&scratch_list); 124905f867c3Sgs 125005f867c3Sgs cmd_enable: 12512f283da5SDan Mick if (pci_bus_res[secbus].io_avail) 125205f867c3Sgs cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 12532f283da5SDan Mick if (pci_bus_res[secbus].mem_avail) 125405f867c3Sgs cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 125505f867c3Sgs pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 12569896aa55Sjveta } 12579896aa55Sjveta 12587c478bd9Sstevel@tonic-gate void 12597c478bd9Sstevel@tonic-gate pci_reprogram(void) 12607c478bd9Sstevel@tonic-gate { 12617c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 12627c478bd9Sstevel@tonic-gate char *onoff; 12638fc7923fSDana Myers int bus; 12647c478bd9Sstevel@tonic-gate 126525145214Smyers /* 126600dfdf4aSDana Myers * Scan ACPI namespace for _BBN objects, make sure that 126700dfdf4aSDana Myers * childless root-bridges appear in devinfo tree 126825145214Smyers */ 126900dfdf4aSDana Myers pci_scan_bbn(); 127000dfdf4aSDana Myers pci_unitaddr_cache_init(); 127100dfdf4aSDana Myers 127200dfdf4aSDana Myers /* 127300dfdf4aSDana Myers * Fix-up unit-address assignments if cache is available 127400dfdf4aSDana Myers */ 127500dfdf4aSDana Myers if (pci_unitaddr_cache_valid()) { 127600dfdf4aSDana Myers int pci_regs[] = {0, 0, 0}; 127700dfdf4aSDana Myers int new_addr; 127800dfdf4aSDana Myers int index = 0; 127900dfdf4aSDana Myers 1280*47310cedSDana Myers for (bus = 0; bus <= pci_bios_maxbus; bus++) { 128100dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 128200dfdf4aSDana Myers if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 128300dfdf4aSDana Myers (pci_bus_res[bus].dip == NULL)) 128400dfdf4aSDana Myers continue; 128500dfdf4aSDana Myers 128600dfdf4aSDana Myers new_addr = pci_bus_unitaddr(index); 128700dfdf4aSDana Myers if (pci_bus_res[bus].root_addr != new_addr) { 128800dfdf4aSDana Myers /* update reg property for node */ 128900dfdf4aSDana Myers pci_regs[0] = pci_bus_res[bus].root_addr = 129000dfdf4aSDana Myers new_addr; 129100dfdf4aSDana Myers (void) ndi_prop_update_int_array( 129200dfdf4aSDana Myers DDI_DEV_T_NONE, pci_bus_res[bus].dip, 129300dfdf4aSDana Myers "reg", (int *)pci_regs, 3); 129400dfdf4aSDana Myers } 129500dfdf4aSDana Myers index++; 129600dfdf4aSDana Myers } 129700dfdf4aSDana Myers } else { 129800dfdf4aSDana Myers /* perform legacy processing */ 129900dfdf4aSDana Myers pci_renumber_root_busses(); 130000dfdf4aSDana Myers pci_unitaddr_cache_create(); 130100dfdf4aSDana Myers } 130225145214Smyers 13038fc7923fSDana Myers /* 13048fc7923fSDana Myers * Do root-bus resource discovery 13058fc7923fSDana Myers */ 1306*47310cedSDana Myers for (bus = 0; bus <= pci_bios_maxbus; bus++) { 13078fc7923fSDana Myers /* skip non-root (peer) PCI busses */ 13088fc7923fSDana Myers if (pci_bus_res[bus].par_bus != (uchar_t)-1) 13098fc7923fSDana Myers continue; 13108fc7923fSDana Myers 13118fc7923fSDana Myers /* 13128fc7923fSDana Myers * 1. find resources associated with this root bus 13138fc7923fSDana Myers */ 13148fc7923fSDana Myers populate_bus_res(bus); 13158fc7923fSDana Myers 13168fc7923fSDana Myers 13178fc7923fSDana Myers /* 13181d6b7b34SJudy Chen * 2. Remove used PCI and ISA resources from bus resource map 13198fc7923fSDana Myers */ 13208fc7923fSDana Myers 13212f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13222f283da5SDan Mick pci_bus_res[bus].io_used); 13232f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13242f283da5SDan Mick pci_bus_res[bus].mem_used); 13252f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13262f283da5SDan Mick pci_bus_res[bus].pmem_used); 13272f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13282f283da5SDan Mick pci_bus_res[bus].pmem_used); 13292f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13302f283da5SDan Mick pci_bus_res[bus].mem_used); 13311d6b7b34SJudy Chen 13322f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13332f283da5SDan Mick isa_res.io_used); 13342f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13352f283da5SDan Mick isa_res.mem_used); 13368fc7923fSDana Myers } 13378fc7923fSDana Myers 13382f283da5SDan Mick memlist_free_all(&isa_res.io_used); 13392f283da5SDan Mick memlist_free_all(&isa_res.mem_used); 13408fc7923fSDana Myers 1341fc396574Srw /* add bus-range property for root/peer bus nodes */ 1342*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 13438fc7923fSDana Myers /* create bus-range property on root/peer buses */ 13448fc7923fSDana Myers if (pci_bus_res[i].par_bus == (uchar_t)-1) 1345fc396574Srw add_bus_range_prop(i); 13468fc7923fSDana Myers 134705f867c3Sgs /* setup bus range resource on each bus */ 134805f867c3Sgs setup_bus_res(i); 1349fc396574Srw } 1350fc396574Srw 13517c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 13527c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 13537c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 13547c478bd9Sstevel@tonic-gate pci_reconfig = 0; 13557c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 13567c478bd9Sstevel@tonic-gate } 13577c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 13587c478bd9Sstevel@tonic-gate } 13597c478bd9Sstevel@tonic-gate 136005f867c3Sgs remove_subtractive_res(); 136105f867c3Sgs 136205f867c3Sgs /* reprogram the non-subtractive PPB */ 136305f867c3Sgs if (pci_reconfig) 1364*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) 136505f867c3Sgs fix_ppb_res(i, B_FALSE); 1366aaba6dfeSmyers 1367*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 136805f867c3Sgs /* configure devices not configured by BIOS */ 13699896aa55Sjveta if (pci_reconfig) { 137005f867c3Sgs /* 137105f867c3Sgs * Reprogram the subtractive PPB. At this time, all its 137205f867c3Sgs * siblings should have got their resources already. 137305f867c3Sgs */ 137405f867c3Sgs if (pci_bus_res[i].subtractive) 137505f867c3Sgs fix_ppb_res(i, B_TRUE); 13767c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 13779896aa55Sjveta } 13788fc7923fSDana Myers } 13798fc7923fSDana Myers 13808fc7923fSDana Myers /* All dev programmed, so we can create available prop */ 1381*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) 13827c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 13838fc7923fSDana Myers } 13848fc7923fSDana Myers 13858fc7923fSDana Myers /* 13868fc7923fSDana Myers * populate bus resources 13878fc7923fSDana Myers */ 13888fc7923fSDana Myers static void 13898fc7923fSDana Myers populate_bus_res(uchar_t bus) 13908fc7923fSDana Myers { 13918fc7923fSDana Myers 13928fc7923fSDana Myers /* scan BIOS structures */ 13932f283da5SDan Mick pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 13942f283da5SDan Mick pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 13952f283da5SDan Mick pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 13962f283da5SDan Mick pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 13978fc7923fSDana Myers 13986b57bdc9SDana Myers /* 13996b57bdc9SDana Myers * attempt to initialize sub_bus from the largest range-end 14002f283da5SDan Mick * in the bus_avail list 14016b57bdc9SDana Myers */ 14022f283da5SDan Mick if (pci_bus_res[bus].bus_avail != NULL) { 14036b57bdc9SDana Myers struct memlist *entry; 14046b57bdc9SDana Myers int current; 14056b57bdc9SDana Myers 14062f283da5SDan Mick entry = pci_bus_res[bus].bus_avail; 14076b57bdc9SDana Myers while (entry != NULL) { 14086b57bdc9SDana Myers current = entry->address + entry->size - 1; 14096b57bdc9SDana Myers if (current > pci_bus_res[bus].sub_bus) 14106b57bdc9SDana Myers pci_bus_res[bus].sub_bus = current; 14116b57bdc9SDana Myers entry = entry->next; 14126b57bdc9SDana Myers } 14136b57bdc9SDana Myers } 14146b57bdc9SDana Myers 14158fc7923fSDana Myers if (bus == 0) { 14168fc7923fSDana Myers /* 14178fc7923fSDana Myers * Special treatment of bus 0: 14188fc7923fSDana Myers * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 14198fc7923fSDana Myers * pcimem from boot and make I/O space the entire range 14206b57bdc9SDana Myers * starting at 0x100. 14218fc7923fSDana Myers */ 14222f283da5SDan Mick if (pci_bus_res[0].mem_avail == NULL) 14232f283da5SDan Mick pci_bus_res[0].mem_avail = 14248fc7923fSDana Myers memlist_dup(bootops->boot_mem->pcimem); 14258fc7923fSDana Myers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 14262f283da5SDan Mick if (pci_bus_res[0].io_avail == NULL) 14272f283da5SDan Mick memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 14287c478bd9Sstevel@tonic-gate } 14298fc7923fSDana Myers 14308fc7923fSDana Myers /* 14318fc7923fSDana Myers * Create 'ranges' property here before any resources are 14328fc7923fSDana Myers * removed from the resource lists 14338fc7923fSDana Myers */ 14348fc7923fSDana Myers add_ranges_prop(bus, 0); 14357c478bd9Sstevel@tonic-gate } 14367c478bd9Sstevel@tonic-gate 14378fc7923fSDana Myers 14387c478bd9Sstevel@tonic-gate /* 14397c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 14407c478bd9Sstevel@tonic-gate */ 14417c478bd9Sstevel@tonic-gate static void 14427c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 14437c478bd9Sstevel@tonic-gate { 14447c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 14457c478bd9Sstevel@tonic-gate dev_info_t *dip; 14467c478bd9Sstevel@tonic-gate 14477c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 14487c478bd9Sstevel@tonic-gate 144905f867c3Sgs num_root_bus++; 14507c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1451fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 14527c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14537c478bd9Sstevel@tonic-gate "#address-cells", 3); 14547c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14557c478bd9Sstevel@tonic-gate "#size-cells", 2); 14567c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 14577c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 14587c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 14597c478bd9Sstevel@tonic-gate 146070025d76Sjohnny /* 146170025d76Sjohnny * If system has PCIe bus, then create different properties 146270025d76Sjohnny */ 146370025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 146470025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 146570025d76Sjohnny "device_type", "pci"); 146670025d76Sjohnny 14677c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 14687c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 14697c478bd9Sstevel@tonic-gate } 14707c478bd9Sstevel@tonic-gate 14717c478bd9Sstevel@tonic-gate /* 14727c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 14737c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 14747c478bd9Sstevel@tonic-gate * to hold the already configured device details. 14757c478bd9Sstevel@tonic-gate */ 14767c478bd9Sstevel@tonic-gate void 14777c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 14787c478bd9Sstevel@tonic-gate { 14797c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 14807c478bd9Sstevel@tonic-gate ushort_t venid; 148105f867c3Sgs struct pci_devfunc *devlist = NULL, *entry; 14827c478bd9Sstevel@tonic-gate 14837c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 14847c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1485bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 1486bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 14877c478bd9Sstevel@tonic-gate } else 14887c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 14897c478bd9Sstevel@tonic-gate 14908fc7923fSDana Myers if (config_op == CONFIG_NEW) { 14918fc7923fSDana Myers devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 14928fc7923fSDana Myers while (devlist) { 14938fc7923fSDana Myers entry = devlist; 14948fc7923fSDana Myers devlist = entry->next; 14958fc7923fSDana Myers if (entry->reprogram || 14968fc7923fSDana Myers pci_bus_res[bus].io_reprogram || 14978fc7923fSDana Myers pci_bus_res[bus].mem_reprogram) { 14988fc7923fSDana Myers /* reprogram device(s) */ 14998fc7923fSDana Myers (void) add_reg_props(entry->dip, bus, 15008fc7923fSDana Myers entry->dev, entry->func, CONFIG_NEW, 0); 15018fc7923fSDana Myers } 15028fc7923fSDana Myers kmem_free(entry, sizeof (*entry)); 15038fc7923fSDana Myers } 15048fc7923fSDana Myers pci_bus_res[bus].privdata = NULL; 15058fc7923fSDana Myers return; 15068fc7923fSDana Myers } 15078fc7923fSDana Myers 15087c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 15097c478bd9Sstevel@tonic-gate nfunc = 1; 15107c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 15117c478bd9Sstevel@tonic-gate 15127c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 15137c478bd9Sstevel@tonic-gate dev, func); 15147c478bd9Sstevel@tonic-gate 15157c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1516bd87be88Ssethg 15177c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 15187c478bd9Sstevel@tonic-gate /* no function at this address */ 15197c478bd9Sstevel@tonic-gate continue; 15207c478bd9Sstevel@tonic-gate } 15217c478bd9Sstevel@tonic-gate 15227c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 15237c478bd9Sstevel@tonic-gate if (header == 0xff) { 15247c478bd9Sstevel@tonic-gate continue; /* illegal value */ 15257c478bd9Sstevel@tonic-gate } 15267c478bd9Sstevel@tonic-gate 15277c478bd9Sstevel@tonic-gate /* 15287c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 15297c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 15307c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 15317c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 15327c478bd9Sstevel@tonic-gate */ 15337c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 15347c478bd9Sstevel@tonic-gate nfunc = 8; 15357c478bd9Sstevel@tonic-gate } 153646e9e839Smyers 153705f867c3Sgs if (config_op == CONFIG_FIX || 153805f867c3Sgs config_op == CONFIG_INFO) { 1539ebf3afa8Sdmick /* 1540ebf3afa8Sdmick * Create the node, unconditionally, on the 1541ebf3afa8Sdmick * first pass only. It may still need 1542ebf3afa8Sdmick * resource assignment, which will be 1543ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 1544ebf3afa8Sdmick */ 154505f867c3Sgs process_devfunc(bus, dev, func, header, 1546ebf3afa8Sdmick venid, config_op); 1547db063408Sdmick 15487c478bd9Sstevel@tonic-gate } 15497c478bd9Sstevel@tonic-gate } 15507c478bd9Sstevel@tonic-gate } 15517c478bd9Sstevel@tonic-gate 15528fc7923fSDana Myers /* percolate bus used resources up through parents to root */ 15538fc7923fSDana Myers if (config_op == CONFIG_INFO) { 15548fc7923fSDana Myers int par_bus; 15558fc7923fSDana Myers 15568fc7923fSDana Myers par_bus = pci_bus_res[bus].par_bus; 15578fc7923fSDana Myers while (par_bus != (uchar_t)-1) { 1558ffa17327SGuoli Shu pci_bus_res[par_bus].io_size += 1559ffa17327SGuoli Shu pci_bus_res[bus].io_size; 1560ffa17327SGuoli Shu pci_bus_res[par_bus].mem_size += 1561ffa17327SGuoli Shu pci_bus_res[bus].mem_size; 15628fc7923fSDana Myers 15632f283da5SDan Mick if (pci_bus_res[bus].io_used) 15642f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, 15652f283da5SDan Mick &pci_bus_res[par_bus].io_used); 15668fc7923fSDana Myers 15672f283da5SDan Mick if (pci_bus_res[bus].mem_used) 15682f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, 15692f283da5SDan Mick &pci_bus_res[par_bus].mem_used); 15708fc7923fSDana Myers 15712f283da5SDan Mick if (pci_bus_res[bus].pmem_used) 15722f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, 15732f283da5SDan Mick &pci_bus_res[par_bus].pmem_used); 15748fc7923fSDana Myers 15752f283da5SDan Mick bus = par_bus; 15768fc7923fSDana Myers par_bus = pci_bus_res[par_bus].par_bus; 15777c478bd9Sstevel@tonic-gate } 15787c478bd9Sstevel@tonic-gate } 15797c478bd9Sstevel@tonic-gate } 15807c478bd9Sstevel@tonic-gate 15817c478bd9Sstevel@tonic-gate static int 15827c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 15837c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 15847c478bd9Sstevel@tonic-gate { 15857c478bd9Sstevel@tonic-gate static int prop_exist = -1; 15867c478bd9Sstevel@tonic-gate static char *pciide_str; 15877c478bd9Sstevel@tonic-gate char compat[32]; 15887c478bd9Sstevel@tonic-gate 15897c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 15907c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 15917c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 15927c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 15937c478bd9Sstevel@tonic-gate } 15947c478bd9Sstevel@tonic-gate 15957c478bd9Sstevel@tonic-gate if (!prop_exist) 15967c478bd9Sstevel@tonic-gate return (0); 15977c478bd9Sstevel@tonic-gate 15987c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 15997c478bd9Sstevel@tonic-gate if (subvenid) { 16007c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 16017c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 16027c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16037c478bd9Sstevel@tonic-gate return (1); 16047c478bd9Sstevel@tonic-gate 16057c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 16067c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 16077c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16087c478bd9Sstevel@tonic-gate return (1); 16097c478bd9Sstevel@tonic-gate 16107c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 16117c478bd9Sstevel@tonic-gate subvenid, subdevid); 16127c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16137c478bd9Sstevel@tonic-gate return (1); 16147c478bd9Sstevel@tonic-gate } 16157c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 16167c478bd9Sstevel@tonic-gate venid, devid, revid); 16177c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16187c478bd9Sstevel@tonic-gate return (1); 16197c478bd9Sstevel@tonic-gate 16207c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 16217c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16227c478bd9Sstevel@tonic-gate return (1); 16237c478bd9Sstevel@tonic-gate 16247c478bd9Sstevel@tonic-gate return (0); 16257c478bd9Sstevel@tonic-gate } 16267c478bd9Sstevel@tonic-gate 16277c478bd9Sstevel@tonic-gate static int 16287c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 16297c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 16307c478bd9Sstevel@tonic-gate { 16317c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 16327c478bd9Sstevel@tonic-gate ushort_t venid; 16337c478bd9Sstevel@tonic-gate ushort_t devid; 16347c478bd9Sstevel@tonic-gate } *entry; 16357c478bd9Sstevel@tonic-gate 1636334edc48Sml /* XXX SATA and other devices: need a way to add dynamically */ 16377c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 16387c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 16397c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 16407c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 1641d01a0451Stt {0x1095, 0x680}, /* Sil0680 */ 1642334edc48Sml {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 16437c478bd9Sstevel@tonic-gate {0, 0} 16447c478bd9Sstevel@tonic-gate }; 16457c478bd9Sstevel@tonic-gate 16467c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 16477c478bd9Sstevel@tonic-gate return (0); 16487c478bd9Sstevel@tonic-gate 16497c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 16507c478bd9Sstevel@tonic-gate return (1); 16517c478bd9Sstevel@tonic-gate } 16527c478bd9Sstevel@tonic-gate 1653d01a0451Stt if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1654d01a0451Stt return (1); 1655d01a0451Stt 16567c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 16577c478bd9Sstevel@tonic-gate return (0); 16587c478bd9Sstevel@tonic-gate } 16597c478bd9Sstevel@tonic-gate 16607c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 16617c478bd9Sstevel@tonic-gate while (entry->venid) { 16627c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 16637c478bd9Sstevel@tonic-gate return (1); 16647c478bd9Sstevel@tonic-gate entry++; 16657c478bd9Sstevel@tonic-gate } 1666d01a0451Stt return (0); 16677c478bd9Sstevel@tonic-gate } 16687c478bd9Sstevel@tonic-gate 16697c478bd9Sstevel@tonic-gate static int 16707c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 16717c478bd9Sstevel@tonic-gate { 16727c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 16737c478bd9Sstevel@tonic-gate 0x000100, 16747c478bd9Sstevel@tonic-gate 0x030000, 16757c478bd9Sstevel@tonic-gate 0x030001 16767c478bd9Sstevel@tonic-gate }; 16777c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 16787c478bd9Sstevel@tonic-gate 16797c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 16807c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 16817c478bd9Sstevel@tonic-gate return (1); 16827c478bd9Sstevel@tonic-gate } 16837c478bd9Sstevel@tonic-gate return (0); 16847c478bd9Sstevel@tonic-gate } 16857c478bd9Sstevel@tonic-gate 1686bd87be88Ssethg static void 1687bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1688bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 1689bd87be88Ssethg { 1690bd87be88Ssethg struct pci_fixundo *newundo; 1691bd87be88Ssethg 1692bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1693bd87be88Ssethg 1694bd87be88Ssethg /* 1695bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 1696bd87be88Ssethg * bit back on at a later time. 1697bd87be88Ssethg */ 1698bd87be88Ssethg newundo->bus = bus; 1699bd87be88Ssethg newundo->dev = dev; 1700bd87be88Ssethg newundo->fn = fn; 1701bd87be88Ssethg newundo->undofn = undofn; 1702bd87be88Ssethg newundo->next = undolist; 1703bd87be88Ssethg 1704bd87be88Ssethg /* add to the undo list in LIFO order */ 1705bd87be88Ssethg undolist = newundo; 1706bd87be88Ssethg } 1707bd87be88Ssethg 1708bd87be88Ssethg void 1709bd87be88Ssethg add_pci_fixes(void) 1710bd87be88Ssethg { 1711bd87be88Ssethg int i; 1712bd87be88Ssethg 1713*47310cedSDana Myers for (i = 0; i <= pci_bios_maxbus; i++) { 1714bd87be88Ssethg /* 1715bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 1716bd87be88Ssethg * This must be done before the main enumeration loop because 1717bd87be88Ssethg * some fixes must be applied to devices normally encountered 1718bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 1719bd87be88Ssethg * applied before scanning device 6, applying fixes in the 1720bd87be88Ssethg * normal enumeration loop would obviously be too late). 1721bd87be88Ssethg */ 1722bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 1723bd87be88Ssethg } 1724bd87be88Ssethg } 1725bd87be88Ssethg 1726bd87be88Ssethg void 1727bd87be88Ssethg undo_pci_fixes(void) 1728bd87be88Ssethg { 1729bd87be88Ssethg struct pci_fixundo *nextundo; 1730bd87be88Ssethg uint8_t bus, dev, fn; 1731bd87be88Ssethg 1732bd87be88Ssethg /* 1733bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 1734bd87be88Ssethg * fixes may require selective undo. 1735bd87be88Ssethg */ 1736bd87be88Ssethg while (undolist != NULL) { 1737bd87be88Ssethg 1738bd87be88Ssethg bus = undolist->bus; 1739bd87be88Ssethg dev = undolist->dev; 1740bd87be88Ssethg fn = undolist->fn; 1741bd87be88Ssethg 1742bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 1743bd87be88Ssethg 1744bd87be88Ssethg nextundo = undolist->next; 1745bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 1746bd87be88Ssethg undolist = nextundo; 1747bd87be88Ssethg } 1748bd87be88Ssethg } 1749bd87be88Ssethg 1750bd87be88Ssethg static void 1751bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1752bd87be88Ssethg { 1753bd87be88Ssethg uint8_t val8; 1754bd87be88Ssethg 1755bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1756bd87be88Ssethg /* 1757bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 1758bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 1759bd87be88Ssethg */ 1760bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 1761bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1762bd87be88Ssethg } 1763bd87be88Ssethg 1764bd87be88Ssethg static void 1765bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1766bd87be88Ssethg { 1767bd87be88Ssethg uint8_t val8; 1768bd87be88Ssethg 1769bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1770bd87be88Ssethg 1771bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 1772bd87be88Ssethg return; 1773bd87be88Ssethg 1774bd87be88Ssethg /* 1775bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 1776bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 1777bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 1778bd87be88Ssethg */ 1779bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 1780bd87be88Ssethg 1781bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1782bd87be88Ssethg 1783bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1784bd87be88Ssethg } 1785bd87be88Ssethg 1786c8711d4dSgs static void 1787c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1788c8711d4dSgs { 1789c8711d4dSgs uint16_t status; 1790c8711d4dSgs uint8_t header; 1791c8711d4dSgs uint8_t cap_ptr; 1792c8711d4dSgs uint8_t cap_id; 1793c8711d4dSgs uint16_t pmcsr; 1794c8711d4dSgs 1795c8711d4dSgs status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1796c8711d4dSgs if (!(status & PCI_STAT_CAP)) 1797c8711d4dSgs return; /* No capabilities list */ 1798c8711d4dSgs 1799c8711d4dSgs header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1800c8711d4dSgs if (header == PCI_HEADER_CARDBUS) 1801fb66942fSCasper H.S. Dik cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1802c8711d4dSgs else 1803c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1804c8711d4dSgs /* 1805c8711d4dSgs * Walk the capabilities list searching for a PM entry. 1806c8711d4dSgs */ 1807c8711d4dSgs while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1808c8711d4dSgs cap_ptr &= PCI_CAP_PTR_MASK; 1809c8711d4dSgs cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1810c8711d4dSgs if (cap_id == PCI_CAP_ID_PM) { 1811c8711d4dSgs pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1812c8711d4dSgs pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1813c8711d4dSgs pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1814c8711d4dSgs pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1815c8711d4dSgs break; 1816c8711d4dSgs } 1817c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1818c8711d4dSgs } 1819c8711d4dSgs 1820c8711d4dSgs } 1821c8711d4dSgs 182278323854SJudy Chen #define is_isa(bc, sc) \ 182378323854SJudy Chen (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 182478323854SJudy Chen 182505f867c3Sgs static void 1826bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 18277c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 18287c478bd9Sstevel@tonic-gate { 18297c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 18307c478bd9Sstevel@tonic-gate dev_info_t *dip; 1831c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 18327c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 183370025d76Sjohnny ushort_t slot_num; 18347c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 18358d483882Smlf int reprogram = 0, pciide = 0; 18367c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 183770025d76Sjohnny int pciex = 0; 183870025d76Sjohnny ushort_t is_pci_bridge = 0; 183905f867c3Sgs struct pci_devfunc *devlist = NULL, *entry = NULL; 184094f1124eSVikram Hegde gfx_entry_t *gfxp; 18417c478bd9Sstevel@tonic-gate 18427c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 18437c478bd9Sstevel@tonic-gate 18447c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 18457c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 18467c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 18477c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 18487c478bd9Sstevel@tonic-gate break; 18497c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 18507c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 18517c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 185205f867c3Sgs /* Record the # of cardbus bridges found on the bus */ 185305f867c3Sgs if (config_op == CONFIG_INFO) 185405f867c3Sgs pci_bus_res[bus].num_cbb++; 18557c478bd9Sstevel@tonic-gate break; 18567c478bd9Sstevel@tonic-gate default: 18577c478bd9Sstevel@tonic-gate subvenid = 0; 18587c478bd9Sstevel@tonic-gate subdevid = 0; 18597c478bd9Sstevel@tonic-gate break; 18607c478bd9Sstevel@tonic-gate } 18617c478bd9Sstevel@tonic-gate 1862bd87be88Ssethg if (config_op == CONFIG_FIX) { 1863bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1864bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 1865bd87be88Ssethg } 186605f867c3Sgs return; 1867bd87be88Ssethg } 1868bd87be88Ssethg 18697c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 18707c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 18717c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 18727c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 18737c478bd9Sstevel@tonic-gate 18747c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 18757c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 18767c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1877c8589f13Ssethg progcl = classcode & 0xff; 18787c478bd9Sstevel@tonic-gate 18798d483882Smlf 18808d483882Smlf if (is_display(classcode)) 18817c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 188278323854SJudy Chen else if (!pseudo_isa && is_isa(basecl, subcl)) 188378323854SJudy Chen (void) snprintf(nodename, sizeof (nodename), "isa"); 18847c478bd9Sstevel@tonic-gate else if (subvenid != 0) 18857c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 18867c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 18877c478bd9Sstevel@tonic-gate else 18887c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 18897c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 18907c478bd9Sstevel@tonic-gate 18917c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 18928fc7923fSDana Myers if (pci_bus_res[bus].dip == NULL) 18937c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 18947c478bd9Sstevel@tonic-gate 18957c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 18967c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 18977c478bd9Sstevel@tonic-gate 189800d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 189900d0963fSdilpreet &is_pci_bridge) == B_TRUE) 190000d0963fSdilpreet pciex = 1; 190100d0963fSdilpreet 19027c478bd9Sstevel@tonic-gate /* add properties */ 19037c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 19047c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 19057c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 19067c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19077c478bd9Sstevel@tonic-gate "class-code", classcode); 19087c478bd9Sstevel@tonic-gate if (func == 0) 19097c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 19107c478bd9Sstevel@tonic-gate else 19117c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 19127c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 19137c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 19147c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 19157c478bd9Sstevel@tonic-gate 1916ebf3afa8Sdmick /* add device_type for display nodes */ 1917ebf3afa8Sdmick if (is_display(classcode)) { 1918ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1919ebf3afa8Sdmick "device_type", "display"); 1920ebf3afa8Sdmick } 19217c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 19227c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 19237c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 19247c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 19257c478bd9Sstevel@tonic-gate 19267c478bd9Sstevel@tonic-gate if (subvenid != 0) { 19277c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19287c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 19297c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19307c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 19317c478bd9Sstevel@tonic-gate } 193270025d76Sjohnny if (!pciex) 193370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 193470025d76Sjohnny "min-grant", mingrant); 193570025d76Sjohnny if (!pciex) 193670025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 193770025d76Sjohnny "max-latency", maxlatency); 19387c478bd9Sstevel@tonic-gate } 19397c478bd9Sstevel@tonic-gate 19407c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 19417c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 19427c478bd9Sstevel@tonic-gate if (intr != 0) 19437c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19447c478bd9Sstevel@tonic-gate "interrupts", intr); 19457c478bd9Sstevel@tonic-gate 19467c478bd9Sstevel@tonic-gate /* 19477c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 19487c478bd9Sstevel@tonic-gate */ 19497c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 19507c478bd9Sstevel@tonic-gate 19517c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19527c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 195370025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 19547c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19557c478bd9Sstevel@tonic-gate "fast-back-to-back"); 195670025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 19577c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19587c478bd9Sstevel@tonic-gate "66mhz-capable"); 19597c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 19607c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19617c478bd9Sstevel@tonic-gate "udf-supported"); 1962d57b3b3dSprasad if (pciex && slot_num) { 196370025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 196470025d76Sjohnny "physical-slot#", slot_num); 1965d57b3b3dSprasad if (!is_pci_bridge) 1966d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 1967d57b3b3dSprasad } 19687c478bd9Sstevel@tonic-gate 19697c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 19707c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 19717c478bd9Sstevel@tonic-gate 1972c8711d4dSgs /* Set the device PM state to D0 */ 1973c8711d4dSgs set_devpm_d0(bus, dev, func); 1974c8711d4dSgs 197570025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 197649fbdd30SErwin T Tsaur add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 197705f867c3Sgs else { 197805f867c3Sgs /* 197905f867c3Sgs * Record the non-PPB devices on the bus for possible 198005f867c3Sgs * reprogramming at 2nd bus enumeration. 198105f867c3Sgs * Note: PPB reprogramming is done in fix_ppb_res() 198205f867c3Sgs */ 198305f867c3Sgs devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 198405f867c3Sgs entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 198505f867c3Sgs entry->dip = dip; 198605f867c3Sgs entry->dev = dev; 198705f867c3Sgs entry->func = func; 198805f867c3Sgs entry->next = devlist; 198905f867c3Sgs pci_bus_res[bus].privdata = entry; 199005f867c3Sgs } 199170025d76Sjohnny 1992c8589f13Ssethg if (config_op == CONFIG_INFO && 1993c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1994c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 1995c8589f13Ssethg } 1996c8589f13Ssethg 199770025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 199870025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 199970025d76Sjohnny (func == 0)) 20008a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 200170025d76Sjohnny 200270025d76Sjohnny if (pciex && is_pci_bridge) 200370025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 200470025d76Sjohnny (char *)"PCIe-PCI bridge"); 200570025d76Sjohnny else 200670025d76Sjohnny add_model_prop(dip, classcode); 20077c478bd9Sstevel@tonic-gate 20087c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 200970025d76Sjohnny revid, classcode, pciex); 20108d483882Smlf 20118d483882Smlf /* 20128d483882Smlf * See if this device is a controller that advertises 20138d483882Smlf * itself to be a standard ATA task file controller, or one that 20148d483882Smlf * has been hard coded. 20158d483882Smlf * 20168d483882Smlf * If it is, check if any other higher precedence driver listed in 20178d483882Smlf * driver_aliases will claim the node by calling 20188d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 20198d483882Smlf * create a pci-ide node or any other special handling. 20208d483882Smlf * 20218d483882Smlf * If another driver does not bind, set the node name to pci-ide 20228d483882Smlf * and then let the special pci-ide handling for registers and 20238d483882Smlf * child pci-ide nodes proceed below. 20248d483882Smlf */ 20258d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 20268d483882Smlf subvenid, subdevid) == 1) { 20278d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 20288d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 20298d483882Smlf pciide = 1; 20308d483882Smlf } 20318d483882Smlf } 20328d483882Smlf 20337c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 20347c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 20357c478bd9Sstevel@tonic-gate 20367c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 20377c478bd9Sstevel@tonic-gate if (pciide) { 20387c478bd9Sstevel@tonic-gate dev_info_t *cdip; 20397c478bd9Sstevel@tonic-gate 20407c478bd9Sstevel@tonic-gate /* 20417c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 20427c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 20437c478bd9Sstevel@tonic-gate */ 20447c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 20457c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 20467c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20477c478bd9Sstevel@tonic-gate "#address-cells", 1); 20487c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20497c478bd9Sstevel@tonic-gate "#size-cells", 0); 20507c478bd9Sstevel@tonic-gate 20517c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 20527c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2053fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 20547c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 20557c478bd9Sstevel@tonic-gate "reg", 0); 20567c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 20577c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2058fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 20597c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 20607c478bd9Sstevel@tonic-gate "reg", 1); 20617c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 20627c478bd9Sstevel@tonic-gate 20637c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 20647c478bd9Sstevel@tonic-gate } 20657c478bd9Sstevel@tonic-gate 20667e301000SVikram Hegde if (is_display(classcode)) { 206794f1124eSVikram Hegde gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 206894f1124eSVikram Hegde gfxp->g_dip = dip; 206994f1124eSVikram Hegde gfxp->g_prev = NULL; 207094f1124eSVikram Hegde gfxp->g_next = gfx_devinfo_list; 207194f1124eSVikram Hegde gfx_devinfo_list = gfxp; 207294f1124eSVikram Hegde if (gfxp->g_next) 207394f1124eSVikram Hegde gfxp->g_next->g_prev = gfxp; 207494f1124eSVikram Hegde } 207594f1124eSVikram Hegde 207678323854SJudy Chen /* special handling for isa */ 207778323854SJudy Chen if (!pseudo_isa && is_isa(basecl, subcl)) { 207878323854SJudy Chen /* add device_type */ 207978323854SJudy Chen (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 208078323854SJudy Chen "device_type", "isa"); 208178323854SJudy Chen } 208278323854SJudy Chen 208305f867c3Sgs if (reprogram && (entry != NULL)) 208405f867c3Sgs entry->reprogram = B_TRUE; 20857e301000SVikram Hegde 20867c478bd9Sstevel@tonic-gate } 20877c478bd9Sstevel@tonic-gate 2088c2de8625SScott Carter, SD IOSW /* 2089c2de8625SScott Carter, SD IOSW * Some vendors do not use unique subsystem IDs in their products, which 2090c2de8625SScott Carter, SD IOSW * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2091c2de8625SScott Carter, SD IOSW * Allow for these compatible forms to be excluded on a per-device basis. 2092c2de8625SScott Carter, SD IOSW */ 2093c2de8625SScott Carter, SD IOSW /*ARGSUSED*/ 2094c2de8625SScott Carter, SD IOSW static boolean_t 2095c2de8625SScott Carter, SD IOSW subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2096c2de8625SScott Carter, SD IOSW ushort_t subdevid, uchar_t revid, uint_t classcode) 2097c2de8625SScott Carter, SD IOSW { 2098c2de8625SScott Carter, SD IOSW /* Nvidia display adapters */ 2099c2de8625SScott Carter, SD IOSW if ((venid == 0x10de) && (is_display(classcode))) 2100c2de8625SScott Carter, SD IOSW return (B_TRUE); 2101c2de8625SScott Carter, SD IOSW 2102c2de8625SScott Carter, SD IOSW return (B_FALSE); 2103c2de8625SScott Carter, SD IOSW } 2104c2de8625SScott Carter, SD IOSW 21057c478bd9Sstevel@tonic-gate /* 21067c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 21077c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 210870025d76Sjohnny * (Also used for PCI-Express devices). 21097c478bd9Sstevel@tonic-gate * 21107c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 21117c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 21127c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 21137c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 21147c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 21157c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 21167c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 21177c478bd9Sstevel@tonic-gate * 21187c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 21197c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 21207c478bd9Sstevel@tonic-gate * 212170025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 212270025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 212370025d76Sjohnny * 21247c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 21257c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 21267c478bd9Sstevel@tonic-gate */ 21277c478bd9Sstevel@tonic-gate void 21287c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 212970025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 213070025d76Sjohnny int pciex) 21317c478bd9Sstevel@tonic-gate { 213270025d76Sjohnny int i = 0; 213370025d76Sjohnny int size = COMPAT_BUFSIZE; 213470025d76Sjohnny char *compat[13]; 21357c478bd9Sstevel@tonic-gate char *buf, *curr; 21367c478bd9Sstevel@tonic-gate 21377c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 21387c478bd9Sstevel@tonic-gate 213970025d76Sjohnny if (pciex) { 214070025d76Sjohnny if (subvenid) { 214170025d76Sjohnny compat[i++] = curr; /* form 0 */ 214270025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 214370025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 214470025d76Sjohnny size -= strlen(curr) + 1; 214570025d76Sjohnny curr += strlen(curr) + 1; 214670025d76Sjohnny 214770025d76Sjohnny compat[i++] = curr; /* form 1 */ 214870025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 214970025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 215070025d76Sjohnny size -= strlen(curr) + 1; 215170025d76Sjohnny curr += strlen(curr) + 1; 215270025d76Sjohnny 215370025d76Sjohnny } 215470025d76Sjohnny compat[i++] = curr; /* form 3 */ 215570025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 215670025d76Sjohnny vendorid, deviceid, revid); 215770025d76Sjohnny size -= strlen(curr) + 1; 215870025d76Sjohnny curr += strlen(curr) + 1; 215970025d76Sjohnny 216070025d76Sjohnny compat[i++] = curr; /* form 4 */ 216170025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 216270025d76Sjohnny size -= strlen(curr) + 1; 216370025d76Sjohnny curr += strlen(curr) + 1; 216470025d76Sjohnny 216570025d76Sjohnny compat[i++] = curr; /* form 5 */ 216670025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 216770025d76Sjohnny size -= strlen(curr) + 1; 216870025d76Sjohnny curr += strlen(curr) + 1; 216970025d76Sjohnny 217070025d76Sjohnny compat[i++] = curr; /* form 6 */ 217170025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 217270025d76Sjohnny (classcode >> 8)); 217370025d76Sjohnny size -= strlen(curr) + 1; 217470025d76Sjohnny curr += strlen(curr) + 1; 217570025d76Sjohnny } 217670025d76Sjohnny 21777c478bd9Sstevel@tonic-gate if (subvenid) { 21787c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 21797c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 21807c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 21817c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 21827c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 21837c478bd9Sstevel@tonic-gate 21847c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 21857c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 21867c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 21877c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 21887c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 21897c478bd9Sstevel@tonic-gate 2190c2de8625SScott Carter, SD IOSW if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2191c2de8625SScott Carter, SD IOSW subdevid, revid, classcode) == B_FALSE) { 2192c2de8625SScott Carter, SD IOSW compat[i++] = curr; /* form 2 */ 2193c2de8625SScott Carter, SD IOSW (void) snprintf(curr, size, "pci%x,%x", subvenid, 2194c2de8625SScott Carter, SD IOSW subdevid); 2195c2de8625SScott Carter, SD IOSW size -= strlen(curr) + 1; 2196c2de8625SScott Carter, SD IOSW curr += strlen(curr) + 1; 2197c2de8625SScott Carter, SD IOSW } 21987c478bd9Sstevel@tonic-gate } 21997c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 22007c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 22017c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22027c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22037c478bd9Sstevel@tonic-gate 22047c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 22057c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 22067c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22077c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22087c478bd9Sstevel@tonic-gate 22097c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 22107c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 22117c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22127c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22137c478bd9Sstevel@tonic-gate 22147c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 22157c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 221670025d76Sjohnny size -= strlen(curr) + 1; 221770025d76Sjohnny curr += strlen(curr) + 1; 22187c478bd9Sstevel@tonic-gate 22197c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 22207c478bd9Sstevel@tonic-gate "compatible", compat, i); 22217c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 22227c478bd9Sstevel@tonic-gate } 22237c478bd9Sstevel@tonic-gate 22247c478bd9Sstevel@tonic-gate /* 22257c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 22267c478bd9Sstevel@tonic-gate * 22277c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 22287c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 22297c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 22307c478bd9Sstevel@tonic-gate * mode BAR or not. 22317c478bd9Sstevel@tonic-gate */ 22327c478bd9Sstevel@tonic-gate /* 22337c478bd9Sstevel@tonic-gate * config info for pci-ide devices 22347c478bd9Sstevel@tonic-gate */ 22357c478bd9Sstevel@tonic-gate static struct { 22367c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 22377c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 22387c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 22397c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 22407c478bd9Sstevel@tonic-gate } pciide_bar[] = { 22417c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 22427c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 22437c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 22447c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 22457c478bd9Sstevel@tonic-gate }; 22467c478bd9Sstevel@tonic-gate 22477c478bd9Sstevel@tonic-gate static int 22487c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 22497c478bd9Sstevel@tonic-gate { 22507c478bd9Sstevel@tonic-gate int hard_decode = 0; 22517c478bd9Sstevel@tonic-gate 22527c478bd9Sstevel@tonic-gate /* 22537c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 22547c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 22557c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 22567c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 22577c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 22587c478bd9Sstevel@tonic-gate */ 22597c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 22607c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 22617c478bd9Sstevel@tonic-gate 22627c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 22637c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 22647c478bd9Sstevel@tonic-gate } else { 22657c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 22667c478bd9Sstevel@tonic-gate hard_decode = 1; 22677c478bd9Sstevel@tonic-gate } 22687c478bd9Sstevel@tonic-gate } 22697c478bd9Sstevel@tonic-gate 22707c478bd9Sstevel@tonic-gate /* 22717c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 22727c478bd9Sstevel@tonic-gate */ 22737c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 22747c478bd9Sstevel@tonic-gate *basep = 0; 22757c478bd9Sstevel@tonic-gate *lenp = 0; 22767c478bd9Sstevel@tonic-gate hard_decode = 0; 22777c478bd9Sstevel@tonic-gate } 22787c478bd9Sstevel@tonic-gate 22797c478bd9Sstevel@tonic-gate return (hard_decode); 22807c478bd9Sstevel@tonic-gate } 22817c478bd9Sstevel@tonic-gate 22827c478bd9Sstevel@tonic-gate 22837c478bd9Sstevel@tonic-gate /* 22847c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 22857c478bd9Sstevel@tonic-gate */ 22867c478bd9Sstevel@tonic-gate static int 22877c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 22887c478bd9Sstevel@tonic-gate int config_op, int pciide) 22897c478bd9Sstevel@tonic-gate { 22907c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 22917c478bd9Sstevel@tonic-gate ushort_t bar_sz; 22927c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 22937c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 22947c478bd9Sstevel@tonic-gate ushort_t offset, end; 22957c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 22967c478bd9Sstevel@tonic-gate uint_t phys_hi; 22972f283da5SDan Mick struct memlist **io_avail, **io_used; 22982f283da5SDan Mick struct memlist **mem_avail, **mem_used; 22992f283da5SDan Mick struct memlist **pmem_avail, **pmem_used; 230005f867c3Sgs uchar_t res_bus; 23017c478bd9Sstevel@tonic-gate 23027c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 23037c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 2304c8711d4dSgs int nreg, nasgn; 23057c478bd9Sstevel@tonic-gate 23062f283da5SDan Mick io_avail = &pci_bus_res[bus].io_avail; 23072f283da5SDan Mick io_used = &pci_bus_res[bus].io_used; 23082f283da5SDan Mick mem_avail = &pci_bus_res[bus].mem_avail; 23092f283da5SDan Mick mem_used = &pci_bus_res[bus].mem_used; 23102f283da5SDan Mick pmem_avail = &pci_bus_res[bus].pmem_avail; 23112f283da5SDan Mick pmem_used = &pci_bus_res[bus].pmem_used; 23127c478bd9Sstevel@tonic-gate 23137c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 23147c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 23157c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 23167c478bd9Sstevel@tonic-gate nasgn = 0; 23177c478bd9Sstevel@tonic-gate 23187c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 23197c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 23207c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 23217c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 23227c478bd9Sstevel@tonic-gate 23237c478bd9Sstevel@tonic-gate switch (header) { 23247c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 23257c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 23267c478bd9Sstevel@tonic-gate break; 23277c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 23287c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 23297c478bd9Sstevel@tonic-gate break; 23307c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 23317c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 2332ffa17327SGuoli Shu reprogram = 1; 23337c478bd9Sstevel@tonic-gate break; 23347c478bd9Sstevel@tonic-gate default: 23357c478bd9Sstevel@tonic-gate max_basereg = 0; 23367c478bd9Sstevel@tonic-gate break; 23377c478bd9Sstevel@tonic-gate } 23387c478bd9Sstevel@tonic-gate 23397c478bd9Sstevel@tonic-gate /* 23407c478bd9Sstevel@tonic-gate * Create the register property by saving the current 23418d34f104Smyers * value of the base register. Write 0xffffffff to the 23428d34f104Smyers * base register. Read the value back to determine the 23438d34f104Smyers * required size of the address space. Restore the base 23448d34f104Smyers * register contents. 23458d34f104Smyers * 23468d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 23478d34f104Smyers * since no driver is yet attached to this device, and disabling 23488d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 23498d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 23508d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 23518d34f104Smyers * Spec V1.2). 23527c478bd9Sstevel@tonic-gate */ 23537c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 23547c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 23557c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 23567c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 23577c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 23587c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 23597c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 23607c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 23617c478bd9Sstevel@tonic-gate 23627c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 23637c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 23643e98767bSMax zhen int hard_decode = 0; 23653e98767bSMax zhen 23667c478bd9Sstevel@tonic-gate /* i/o space */ 23677c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 23687c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 23697c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 23707c478bd9Sstevel@tonic-gate 23717c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 23727c478bd9Sstevel@tonic-gate if (pciide) { 2373f088817aSyt if (subclass != PCI_MASS_IDE) 23747c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 23757c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 23767c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 23777c478bd9Sstevel@tonic-gate &base, &len); 23787c478bd9Sstevel@tonic-gate } else if (value == 0) { 23797c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 23807c478bd9Sstevel@tonic-gate continue; 23817c478bd9Sstevel@tonic-gate } 23827c478bd9Sstevel@tonic-gate 23833e98767bSMax zhen regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 23843e98767bSMax zhen (hard_decode ? PCI_RELOCAT_B : offset); 23853e98767bSMax zhen regs[nreg].pci_phys_low = hard_decode ? 23863e98767bSMax zhen base & PCI_BASE_IO_ADDR_M : 0; 23873e98767bSMax zhen assigned[nasgn].pci_phys_hi = 23883e98767bSMax zhen PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 23897c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 23907c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 23917c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 23927c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 239305f867c3Sgs /* 239405f867c3Sgs * A device under a subtractive PPB can allocate 239505f867c3Sgs * resources from its parent bus if there is no resource 239605f867c3Sgs * available on its own bus. 239705f867c3Sgs */ 23982f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 239905f867c3Sgs res_bus = bus; 240005f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 240105f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 240205f867c3Sgs if (res_bus == (uchar_t)-1) 240305f867c3Sgs break; /* root bus already */ 24042f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 24052f283da5SDan Mick io_avail = &pci_bus_res 24062f283da5SDan Mick [res_bus].io_avail; 240705f867c3Sgs break; 240805f867c3Sgs } 240905f867c3Sgs } 241005f867c3Sgs } 24117c478bd9Sstevel@tonic-gate 24127c478bd9Sstevel@tonic-gate /* 24137c478bd9Sstevel@tonic-gate * first pass - gather what's there 24147c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 24157c478bd9Sstevel@tonic-gate * config - allocate regions 24167c478bd9Sstevel@tonic-gate */ 24177c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 24187c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 241905f867c3Sgs if (base != 0) { 24202f283da5SDan Mick (void) memlist_remove(io_avail, base, 24218fc7923fSDana Myers len); 24222f283da5SDan Mick memlist_insert(io_used, base, len); 2423ffa17327SGuoli Shu } else { 24247c478bd9Sstevel@tonic-gate reprogram = 1; 2425ffa17327SGuoli Shu } 2426ffa17327SGuoli Shu pci_bus_res[bus].io_size += len; 24272f283da5SDan Mick } else if ((*io_avail && base == 0) || 242805f867c3Sgs pci_bus_res[bus].io_reprogram) { 24292f283da5SDan Mick base = (uint_t)memlist_find(io_avail, len, len); 24307c478bd9Sstevel@tonic-gate if (base != 0) { 24312f283da5SDan Mick memlist_insert(io_used, base, len); 24327c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 24337c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 24347c478bd9Sstevel@tonic-gate base | type); 24357c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 24367c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 24377c478bd9Sstevel@tonic-gate } 24387c478bd9Sstevel@tonic-gate if (base == 0) { 24397c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 2440db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 2441db063408Sdmick " length 0x%x", 2442ebf3afa8Sdmick bus, dev, func, offset, len); 2443c8711d4dSgs } 24447c478bd9Sstevel@tonic-gate } 24457c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 24467c478bd9Sstevel@tonic-gate nreg++, nasgn++; 24477c478bd9Sstevel@tonic-gate 24487c478bd9Sstevel@tonic-gate } else { 24497c478bd9Sstevel@tonic-gate /* memory space */ 24507c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 24517c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 24527c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 24537c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 24547c478bd9Sstevel@tonic-gate } else { 24557c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 24567c478bd9Sstevel@tonic-gate base_hi = 0; 24577c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 24587c478bd9Sstevel@tonic-gate } 24597c478bd9Sstevel@tonic-gate 24607c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 24617c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 24627c478bd9Sstevel@tonic-gate 24638fc7923fSDana Myers if (value == 0) 24647c478bd9Sstevel@tonic-gate continue; 24658fc7923fSDana Myers 24667c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 24677c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 24687c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 24697c478bd9Sstevel@tonic-gate 24707c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 24718fc7923fSDana Myers if (base & PCI_BASE_PREF_M) 24727c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 24738fc7923fSDana Myers 247405f867c3Sgs /* 247505f867c3Sgs * A device under a subtractive PPB can allocate 247605f867c3Sgs * resources from its parent bus if there is no resource 247705f867c3Sgs * available on its own bus. 247805f867c3Sgs */ 24792f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 248005f867c3Sgs res_bus = bus; 248105f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 248205f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 248305f867c3Sgs if (res_bus == (uchar_t)-1) 248405f867c3Sgs break; /* root bus already */ 24852f283da5SDan Mick mem_avail = 24862f283da5SDan Mick &pci_bus_res[res_bus].mem_avail; 24872f283da5SDan Mick pmem_avail = 24882f283da5SDan Mick &pci_bus_res [res_bus].pmem_avail; 24898fc7923fSDana Myers /* 24908fc7923fSDana Myers * Break out as long as at least 24912f283da5SDan Mick * mem_avail is available 24928fc7923fSDana Myers */ 24932f283da5SDan Mick if ((*pmem_avail && 24948fc7923fSDana Myers (phys_hi & PCI_PREFETCH_B)) || 24952f283da5SDan Mick *mem_avail) 249605f867c3Sgs break; 249705f867c3Sgs } 249805f867c3Sgs } 249905f867c3Sgs 25007c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 25017c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 25027c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 25037c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 25047c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 25057c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 25067c478bd9Sstevel@tonic-gate 25077c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 25087c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 25098fc7923fSDana Myers if (base != NULL) { 25108fc7923fSDana Myers /* remove from PMEM and MEM space */ 25112f283da5SDan Mick (void) memlist_remove(mem_avail, 25128fc7923fSDana Myers base, len); 25132f283da5SDan Mick (void) memlist_remove(pmem_avail, 25148fc7923fSDana Myers base, len); 25158fc7923fSDana Myers /* only note as used in correct map */ 25168fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) 25172f283da5SDan Mick memlist_insert(pmem_used, 251805f867c3Sgs base, len); 25198fc7923fSDana Myers else 25202f283da5SDan Mick memlist_insert(mem_used, 252186ce93f0SGuoli Shu base, len); 2522ffa17327SGuoli Shu } else { 25237c478bd9Sstevel@tonic-gate reprogram = 1; 2524ffa17327SGuoli Shu } 2525ffa17327SGuoli Shu pci_bus_res[bus].mem_size += len; 25262f283da5SDan Mick } else if ((*mem_avail && base == NULL) || 252705f867c3Sgs pci_bus_res[bus].mem_reprogram) { 25288fc7923fSDana Myers /* 25298fc7923fSDana Myers * When desired, attempt a prefetchable 25308fc7923fSDana Myers * allocation first 25318fc7923fSDana Myers */ 25328fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) { 25332f283da5SDan Mick base = (uint_t)memlist_find(pmem_avail, 25348fc7923fSDana Myers len, len); 25358fc7923fSDana Myers if (base != NULL) { 25362f283da5SDan Mick memlist_insert(pmem_used, 25378fc7923fSDana Myers base, len); 25382f283da5SDan Mick (void) memlist_remove(mem_avail, 253986ce93f0SGuoli Shu base, len); 25408fc7923fSDana Myers } 25418fc7923fSDana Myers } 25428fc7923fSDana Myers /* 25438fc7923fSDana Myers * If prefetchable allocation was not 25448fc7923fSDana Myers * desired, or failed, attempt ordinary 25458fc7923fSDana Myers * memory allocation 25468fc7923fSDana Myers */ 25478fc7923fSDana Myers if (base == NULL) { 25482f283da5SDan Mick base = (uint_t)memlist_find(mem_avail, 25498fc7923fSDana Myers len, len); 25508fc7923fSDana Myers if (base != NULL) { 25512f283da5SDan Mick memlist_insert(mem_used, 255286ce93f0SGuoli Shu base, len); 25532f283da5SDan Mick (void) memlist_remove( 25542f283da5SDan Mick pmem_avail, base, len); 255586ce93f0SGuoli Shu } 25568fc7923fSDana Myers } 25578fc7923fSDana Myers if (base != NULL) { 25587c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 25597c478bd9Sstevel@tonic-gate base | type); 25607c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 25617c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 25628fc7923fSDana Myers } else 25637c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 2564ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 2565db063408Sdmick " length 0x%x", 2566ebf3afa8Sdmick bus, dev, func, offset, len); 25677c478bd9Sstevel@tonic-gate } 25687c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 25697c478bd9Sstevel@tonic-gate nreg++, nasgn++; 25707c478bd9Sstevel@tonic-gate } 25717c478bd9Sstevel@tonic-gate } 25727c478bd9Sstevel@tonic-gate switch (header) { 25737c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 25747c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 25757c478bd9Sstevel@tonic-gate break; 25767c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 25777c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 25787c478bd9Sstevel@tonic-gate break; 25797c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 25807c478bd9Sstevel@tonic-gate goto done; 25817c478bd9Sstevel@tonic-gate } 25827c478bd9Sstevel@tonic-gate 25837c478bd9Sstevel@tonic-gate /* 25847c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 25857c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 25867c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 25877c478bd9Sstevel@tonic-gate */ 25887c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 25897c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 25907c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 25917c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 259270025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 259370025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 259470025d76Sjohnny else 259570025d76Sjohnny value = 0; 25967c478bd9Sstevel@tonic-gate 25977c478bd9Sstevel@tonic-gate if (value != 0) { 25987c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 25997c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 26007c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 26017c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 26027c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 26037c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 26047c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 26057c478bd9Sstevel@tonic-gate nreg++, nasgn++; 260699ed6083Sszhou /* take it out of the memory resource */ 26078fc7923fSDana Myers if (base != NULL) { 26082f283da5SDan Mick (void) memlist_remove(mem_avail, base, len); 26092f283da5SDan Mick memlist_insert(mem_used, base, len); 26102f283da5SDan Mick pci_bus_res[bus].mem_size += len; 26118fc7923fSDana Myers } 26127c478bd9Sstevel@tonic-gate } 26137c478bd9Sstevel@tonic-gate 26147c478bd9Sstevel@tonic-gate /* 26158fc7923fSDana Myers * Account for "legacy" (alias) video adapter resources 26167c478bd9Sstevel@tonic-gate */ 26177c478bd9Sstevel@tonic-gate 26187c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 26197c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 26207c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 26217c478bd9Sstevel@tonic-gate 26227c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 26237c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26247c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26257c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 26267c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 26277c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26282f283da5SDan Mick (void) memlist_remove(io_avail, 0x3b0, 0xc); 26292f283da5SDan Mick memlist_insert(io_used, 0x3b0, 0xc); 26302f283da5SDan Mick pci_bus_res[bus].io_size += 0xc; 26317c478bd9Sstevel@tonic-gate 26327c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 26337c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26347c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26357c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 26367c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 26377c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26382f283da5SDan Mick (void) memlist_remove(io_avail, 0x3c0, 0x20); 26392f283da5SDan Mick memlist_insert(io_used, 0x3c0, 0x20); 26402f283da5SDan Mick pci_bus_res[bus].io_size += 0x20; 26417c478bd9Sstevel@tonic-gate 26427c478bd9Sstevel@tonic-gate /* Video memory */ 26437c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26443e98767bSMax zhen (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 26457c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 26467c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 26477c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 26487c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 26497c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26508fc7923fSDana Myers /* remove from MEM and PMEM space */ 26512f283da5SDan Mick (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 26522f283da5SDan Mick (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 26532f283da5SDan Mick memlist_insert(mem_used, 0xa0000, 0x20000); 26542f283da5SDan Mick pci_bus_res[bus].mem_size += 0x20000; 26557c478bd9Sstevel@tonic-gate } 26567c478bd9Sstevel@tonic-gate 26577c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 26587c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 26599896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 26609896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 26617c478bd9Sstevel@tonic-gate 26627c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 26637c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26647c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26657c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 26667c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 26677c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26682f283da5SDan Mick (void) memlist_remove(io_avail, 0x2e8, 0x1); 26692f283da5SDan Mick memlist_insert(io_used, 0x2e8, 0x1); 26702f283da5SDan Mick pci_bus_res[bus].io_size += 0x1; 26717c478bd9Sstevel@tonic-gate 26727c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 26737c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26747c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26757c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 26767c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 26777c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26782f283da5SDan Mick (void) memlist_remove(io_avail, 0x2ea, 0x6); 26792f283da5SDan Mick memlist_insert(io_used, 0x2ea, 0x6); 26802f283da5SDan Mick pci_bus_res[bus].io_size += 0x6; 26817c478bd9Sstevel@tonic-gate } 26827c478bd9Sstevel@tonic-gate 26837c478bd9Sstevel@tonic-gate done: 26847c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 26857c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 26867c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 26877c478bd9Sstevel@tonic-gate "assigned-addresses", 26887c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2689c8711d4dSgs 26907c478bd9Sstevel@tonic-gate return (reprogram); 26917c478bd9Sstevel@tonic-gate } 26927c478bd9Sstevel@tonic-gate 26937c478bd9Sstevel@tonic-gate static void 269470025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 269549fbdd30SErwin T Tsaur int pciex, ushort_t is_pci_bridge) 26967c478bd9Sstevel@tonic-gate { 269770025d76Sjohnny char *dev_type; 26987c478bd9Sstevel@tonic-gate int i; 26997c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 27007c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 27017c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 270205f867c3Sgs uchar_t progclass; 270305f867c3Sgs 2704f55ce205Sszhou ASSERT(secbus <= subbus); 27057c478bd9Sstevel@tonic-gate 270605f867c3Sgs /* 270705f867c3Sgs * Check if it's a subtractive PPB. 270805f867c3Sgs */ 270905f867c3Sgs progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 271005f867c3Sgs if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 271105f867c3Sgs pci_bus_res[secbus].subtractive = B_TRUE; 271205f867c3Sgs 2713f55ce205Sszhou /* 2714f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 2715f55ce205Sszhou * such mistakes here 2716f55ce205Sszhou */ 2717*47310cedSDana Myers if (subbus > pci_bios_maxbus) { 2718*47310cedSDana Myers pci_bios_maxbus = subbus; 2719f55ce205Sszhou alloc_res_array(); 2720f55ce205Sszhou } 2721f55ce205Sszhou 2722f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 27237c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 27247c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 27257c478bd9Sstevel@tonic-gate 272649fbdd30SErwin T Tsaur dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 272770025d76Sjohnny 27287c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 27297c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 273053273e82Ssethg /* 273153273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 273253273e82Ssethg * for peer busses because there is no other way of determining its 273353273e82Ssethg * subordinate bus number). 273453273e82Ssethg */ 27357c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 27367c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 273753273e82Ssethg /* 273853273e82Ssethg * Loop through subordinate busses, initializing their parent bus 273953273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 274053273e82Ssethg * fields may very well be further refined later, as child bridges 274153273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 274253273e82Ssethg * are not peer busses by changing their par_bus fields to anything 274353273e82Ssethg * other than -1.) 274453273e82Ssethg */ 27457c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 27467c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 27477c478bd9Sstevel@tonic-gate 27487c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 274970025d76Sjohnny "device_type", dev_type); 27507c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 27517c478bd9Sstevel@tonic-gate "#address-cells", 3); 27527c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 27537c478bd9Sstevel@tonic-gate "#size-cells", 2); 27547c478bd9Sstevel@tonic-gate 27557c478bd9Sstevel@tonic-gate /* 27562f283da5SDan Mick * Collect bridge window specifications, and use them to populate 27572f283da5SDan Mick * the "avail" resources for the bus. Not all of those resources will 27582f283da5SDan Mick * end up being available; this is done top-down, and so the initial 27592f283da5SDan Mick * collection of windows populates the 'ranges' property for the 27602f283da5SDan Mick * bus node. Later, as children are found, resources are removed from 27612f283da5SDan Mick * the 'avail' list, so that it becomes the freelist for 27622f283da5SDan Mick * this point in the tree. ranges may be set again after bridge 27632f283da5SDan Mick * reprogramming in fix_ppb_res(), in which case it's set from 27642f283da5SDan Mick * used + avail. 27652f283da5SDan Mick * 27667c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 27677c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 27687c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 27697c478bd9Sstevel@tonic-gate * prefetchable memory. 27707c478bd9Sstevel@tonic-gate */ 27719896aa55Sjveta 27729896aa55Sjveta /* 27739896aa55Sjveta * io range 277405f867c3Sgs * We determine i/o windows that are left unconfigured by BIOS 27759896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 27769896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 27779896aa55Sjveta * later passes by setting the base > limit 27789896aa55Sjveta */ 27799896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 27809896aa55Sjveta if (val & PCI_COMM_IO) { 27819896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 27829896aa55Sjveta io_range[0] = ((val & 0xf0) << 8); 27839896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 27849896aa55Sjveta io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 27859896aa55Sjveta } else { 27869896aa55Sjveta io_range[0] = 0x9fff; 27879896aa55Sjveta io_range[1] = 0x1000; 27889896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 27899896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 27909896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 27919896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 27929896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 27939896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 27949896aa55Sjveta } 27959896aa55Sjveta 27967c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 27972f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 27987c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 27997c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 28002f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 280105f867c3Sgs (uint64_t)io_range[0], 280205f867c3Sgs (uint64_t)(io_range[1] - io_range[0] + 1)); 28032f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28042f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28057c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 28067c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 28077c478bd9Sstevel@tonic-gate } 28087c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 28097c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 28102269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 28112269adc8Sszhou if ((val & 0xf) == 1 && 28122269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 28132269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 28142269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 28152269adc8Sszhou } 28167c478bd9Sstevel@tonic-gate } 28177c478bd9Sstevel@tonic-gate 28187c478bd9Sstevel@tonic-gate /* mem range */ 28197c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 28207c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 28217c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 28227c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 28237c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 28242f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 28257c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 28267c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28272f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 282805f867c3Sgs (uint64_t)mem_range[0], 282905f867c3Sgs (uint64_t)(mem_range[1] - mem_range[0] + 1)); 283086ce93f0SGuoli Shu /* remove from parent resource list */ 28312f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 28328fc7923fSDana Myers (uint64_t)mem_range[0], 28338fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28342f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 28358fc7923fSDana Myers (uint64_t)mem_range[0], 28368fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28377c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 28387c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 28397c478bd9Sstevel@tonic-gate } 28407c478bd9Sstevel@tonic-gate 28417c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 28427c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 28437c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 28447c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 28457c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 28467c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 28472f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].pmem_avail, 28487c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 28497c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28502f283da5SDan Mick memlist_insert(&pci_bus_res[bus].pmem_used, 285105f867c3Sgs (uint64_t)pmem_range[0], 285205f867c3Sgs (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 285386ce93f0SGuoli Shu /* remove from parent resource list */ 28542f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 28558fc7923fSDana Myers (uint64_t)pmem_range[0], 28568fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28572f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 28588fc7923fSDana Myers (uint64_t)pmem_range[0], 28598fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28607c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 28617c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 28622269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 28632269adc8Sszhou if ((val & 0xf) == 1 && 28642269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 28652269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 28662269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 28672269adc8Sszhou } 28687c478bd9Sstevel@tonic-gate } 28697c478bd9Sstevel@tonic-gate 28702f283da5SDan Mick /* 28712f283da5SDan Mick * Add VGA legacy resources to the bridge's pci_bus_res if it 28722f283da5SDan Mick * has VGA_ENABLE set. Note that we put them in 'avail', 28732f283da5SDan Mick * because that's used to populate the ranges prop; they'll be 28742f283da5SDan Mick * removed from there by the VGA device once it's found. Also, 28752f283da5SDan Mick * remove them from the parent's available list and note them as 28762f283da5SDan Mick * used in the parent. 28772f283da5SDan Mick */ 28782f283da5SDan Mick 28792f283da5SDan Mick if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 28802f283da5SDan Mick PCI_BCNF_BCNTRL_VGA_ENABLE) { 28812f283da5SDan Mick 28822f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 28832f283da5SDan Mick 28842f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 28852f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28862f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28872f283da5SDan Mick 0x3b0, 0xc); 28882f283da5SDan Mick } 28892f283da5SDan Mick 28902f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 28912f283da5SDan Mick 28922f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 28932f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28942f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28952f283da5SDan Mick 0x3c0, 0x20); 28962f283da5SDan Mick } 28972f283da5SDan Mick 28982f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 28992f283da5SDan Mick 0x20000); 29002f283da5SDan Mick 29012f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 29022f283da5SDan Mick if (pci_bus_res[bus].mem_avail != NULL) { 29032f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 29042f283da5SDan Mick 0xa0000, 0x20000); 29052f283da5SDan Mick } 29062f283da5SDan Mick } 29077c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 29088fc7923fSDana Myers add_ranges_prop(secbus, 1); 29097c478bd9Sstevel@tonic-gate } 29107c478bd9Sstevel@tonic-gate 291109f67678Sanish extern const struct pci_class_strings_s class_pci[]; 291209f67678Sanish extern int class_pci_items; 29137c478bd9Sstevel@tonic-gate 29147c478bd9Sstevel@tonic-gate static void 29157c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 29167c478bd9Sstevel@tonic-gate { 29177c478bd9Sstevel@tonic-gate const char *desc; 29187c478bd9Sstevel@tonic-gate int i; 29197c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 29207c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 29217c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 29227c478bd9Sstevel@tonic-gate 29237c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 29247c478bd9Sstevel@tonic-gate desc = "IDE controller"; 29257c478bd9Sstevel@tonic-gate } else { 29267c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 29277c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 29287c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 29297c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 293009f67678Sanish desc = class_pci[i].actual_desc; 29317c478bd9Sstevel@tonic-gate break; 29327c478bd9Sstevel@tonic-gate } 29337c478bd9Sstevel@tonic-gate } 293409f67678Sanish if (i == class_pci_items) 29357c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 29367c478bd9Sstevel@tonic-gate } 29377c478bd9Sstevel@tonic-gate 29387c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 29397c478bd9Sstevel@tonic-gate (char *)desc); 29407c478bd9Sstevel@tonic-gate } 29417c478bd9Sstevel@tonic-gate 29427c478bd9Sstevel@tonic-gate static void 29437c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 29447c478bd9Sstevel@tonic-gate { 29457c478bd9Sstevel@tonic-gate int bus_range[2]; 29467c478bd9Sstevel@tonic-gate 29477c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 29487c478bd9Sstevel@tonic-gate return; 29497c478bd9Sstevel@tonic-gate bus_range[0] = bus; 29507c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 29517c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 29527c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 29537c478bd9Sstevel@tonic-gate } 29547c478bd9Sstevel@tonic-gate 2955b1f176e8Sjg /* 2956b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 2957b1f176e8Sjg */ 2958b1f176e8Sjg static void 2959b1f176e8Sjg add_bus_slot_names_prop(int bus) 2960b1f176e8Sjg { 2961b1f176e8Sjg char slotprop[256]; 2962b1f176e8Sjg int len; 2963b1f176e8Sjg 2964d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 2965d57b3b3dSprasad /* simply return if the property is already defined */ 2966d57b3b3dSprasad if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2967d57b3b3dSprasad DDI_PROP_DONTPASS, "slot-names")) 2968d57b3b3dSprasad return; 2969d57b3b3dSprasad } 2970d57b3b3dSprasad 2971b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2972b1f176e8Sjg if (len > 0) { 297353273e82Ssethg /* 297453273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 297553273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 297653273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 297753273e82Ssethg * subordinate to any PCI-PCI bridge). 297853273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 297953273e82Ssethg * will remove it later. 298053273e82Ssethg */ 298153273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 298253273e82Ssethg pci_bus_res[bus].dip == NULL) { 298353273e82Ssethg 2984b1f176e8Sjg create_root_bus_dip(bus); 298553273e82Ssethg } 298653273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 298753273e82Ssethg ASSERT((len % sizeof (int)) == 0); 298853273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 298953273e82Ssethg pci_bus_res[bus].dip, "slot-names", 299053273e82Ssethg (int *)slotprop, len / sizeof (int)); 299153273e82Ssethg } else { 299253273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 299353273e82Ssethg "IRQ routing table; Not adding slot-names " 299453273e82Ssethg "property for incorrect bus %d", bus); 299553273e82Ssethg } 2996b1f176e8Sjg } 2997b1f176e8Sjg } 2998b1f176e8Sjg 29998fc7923fSDana Myers /* 30008fc7923fSDana Myers * Handle both PCI root and PCI-PCI bridge range properties; 30018fc7923fSDana Myers * non-zero 'ppb' argument select PCI-PCI bridges versus root. 30028fc7923fSDana Myers */ 30038fc7923fSDana Myers static void 30048fc7923fSDana Myers memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 30057c478bd9Sstevel@tonic-gate { 30068fc7923fSDana Myers ppb_ranges_t *ppb_rp = *rp; 30078fc7923fSDana Myers pci_ranges_t *pci_rp = *rp; 30088fc7923fSDana Myers 30098fc7923fSDana Myers while (entry != NULL) { 30108fc7923fSDana Myers if (ppb) { 30118fc7923fSDana Myers ppb_rp->child_high = ppb_rp->parent_high = type; 30128fc7923fSDana Myers ppb_rp->child_mid = ppb_rp->parent_mid = 30138fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 30148fc7923fSDana Myers ppb_rp->child_low = ppb_rp->parent_low = 30158fc7923fSDana Myers (uint32_t)entry->address; 30168fc7923fSDana Myers ppb_rp->size_high = 30178fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 30188fc7923fSDana Myers ppb_rp->size_low = (uint32_t)entry->size; 30198fc7923fSDana Myers *rp = ++ppb_rp; 30208fc7923fSDana Myers } else { 30218fc7923fSDana Myers pci_rp->child_high = type; 30228fc7923fSDana Myers pci_rp->child_mid = pci_rp->parent_high = 30238fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 30248fc7923fSDana Myers pci_rp->child_low = pci_rp->parent_low = 30258fc7923fSDana Myers (uint32_t)entry->address; 30268fc7923fSDana Myers pci_rp->size_high = 30278fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 30288fc7923fSDana Myers pci_rp->size_low = (uint32_t)entry->size; 30298fc7923fSDana Myers *rp = ++pci_rp; 30308fc7923fSDana Myers } 30318fc7923fSDana Myers entry = entry->next; 30328fc7923fSDana Myers } 30338fc7923fSDana Myers } 30347c478bd9Sstevel@tonic-gate 30358fc7923fSDana Myers static void 30368fc7923fSDana Myers add_ranges_prop(int bus, int ppb) 30378fc7923fSDana Myers { 30388fc7923fSDana Myers int total, alloc_size; 30398fc7923fSDana Myers void *rp, *next_rp; 30402f283da5SDan Mick struct memlist *iolist, *memlist, *pmemlist; 30418fc7923fSDana Myers 3042ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3043ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3044ec0c94e7SDana Myers return; 3045ec0c94e7SDana Myers 30462f283da5SDan Mick iolist = memlist = pmemlist = (struct memlist *)NULL; 30472f283da5SDan Mick 30482f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 30492f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, &iolist); 30502f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 30512f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 30522f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 30532f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 30542f283da5SDan Mick 30552f283da5SDan Mick total = memlist_count(iolist); 30562f283da5SDan Mick total += memlist_count(memlist); 30572f283da5SDan Mick total += memlist_count(pmemlist); 30588fc7923fSDana Myers 30598fc7923fSDana Myers /* no property is created if no ranges are present */ 30608fc7923fSDana Myers if (total == 0) 30618fc7923fSDana Myers return; 30628fc7923fSDana Myers 30638fc7923fSDana Myers alloc_size = total * 30648fc7923fSDana Myers (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 30658fc7923fSDana Myers 30668fc7923fSDana Myers next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 30678fc7923fSDana Myers 30682f283da5SDan Mick memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 30692f283da5SDan Mick memlist_to_ranges(&next_rp, memlist, 30708fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 30712f283da5SDan Mick memlist_to_ranges(&next_rp, pmemlist, 30728fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 30738fc7923fSDana Myers 30748fc7923fSDana Myers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 30758fc7923fSDana Myers "ranges", (int *)rp, alloc_size / sizeof (int)); 30768fc7923fSDana Myers 30778fc7923fSDana Myers kmem_free(rp, alloc_size); 30782f283da5SDan Mick memlist_free_all(&iolist); 30792f283da5SDan Mick memlist_free_all(&memlist); 30802f283da5SDan Mick memlist_free_all(&pmemlist); 30817c478bd9Sstevel@tonic-gate } 30827c478bd9Sstevel@tonic-gate 30837c478bd9Sstevel@tonic-gate static void 30848fc7923fSDana Myers memlist_remove_list(struct memlist **list, struct memlist *remove_list) 30857c478bd9Sstevel@tonic-gate { 30868fc7923fSDana Myers while (list && *list && remove_list) { 30878fc7923fSDana Myers (void) memlist_remove(list, remove_list->address, 30888fc7923fSDana Myers remove_list->size); 30898fc7923fSDana Myers remove_list = remove_list->next; 30908fc7923fSDana Myers } 30917c478bd9Sstevel@tonic-gate } 30927c478bd9Sstevel@tonic-gate 30937c478bd9Sstevel@tonic-gate static int 30947c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 30957c478bd9Sstevel@tonic-gate { 30967c478bd9Sstevel@tonic-gate int i = 0; 30977c478bd9Sstevel@tonic-gate 30987c478bd9Sstevel@tonic-gate while (list) { 30997c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 31007c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 31017c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 31027c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 31037c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 31047c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 31057c478bd9Sstevel@tonic-gate 31067c478bd9Sstevel@tonic-gate list = list->next; 31077c478bd9Sstevel@tonic-gate sp++, i++; 31087c478bd9Sstevel@tonic-gate } 31097c478bd9Sstevel@tonic-gate return (i); 31107c478bd9Sstevel@tonic-gate } 31117c478bd9Sstevel@tonic-gate 31127c478bd9Sstevel@tonic-gate static void 31137c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 31147c478bd9Sstevel@tonic-gate { 31157c478bd9Sstevel@tonic-gate int i, count; 31167c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 31177c478bd9Sstevel@tonic-gate 3118ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3119ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3120ec0c94e7SDana Myers return; 3121ec0c94e7SDana Myers 31222f283da5SDan Mick count = memlist_count(pci_bus_res[bus].io_avail) + 31232f283da5SDan Mick memlist_count(pci_bus_res[bus].mem_avail) + 31242f283da5SDan Mick memlist_count(pci_bus_res[bus].pmem_avail); 31257c478bd9Sstevel@tonic-gate 31267c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 31277c478bd9Sstevel@tonic-gate return; 31287c478bd9Sstevel@tonic-gate 31297c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 31302f283da5SDan Mick i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 31317c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 31322f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 31337c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 31342f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 31357c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 31367c478bd9Sstevel@tonic-gate ASSERT(i == count); 31377c478bd9Sstevel@tonic-gate 31387c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 31397c478bd9Sstevel@tonic-gate "available", (int *)sp, 31407c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 31417c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 31427c478bd9Sstevel@tonic-gate } 3143f55ce205Sszhou 3144f55ce205Sszhou static void 3145f55ce205Sszhou alloc_res_array(void) 3146f55ce205Sszhou { 3147f55ce205Sszhou static int array_max = 0; 3148f55ce205Sszhou int old_max; 3149f55ce205Sszhou void *old_res; 3150f55ce205Sszhou 3151*47310cedSDana Myers if (array_max > pci_bios_maxbus + 1) 3152f55ce205Sszhou return; /* array is big enough */ 3153f55ce205Sszhou 3154f55ce205Sszhou old_max = array_max; 3155f55ce205Sszhou old_res = pci_bus_res; 3156f55ce205Sszhou 3157f55ce205Sszhou if (array_max == 0) 3158f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 3159f55ce205Sszhou 3160*47310cedSDana Myers while (array_max < pci_bios_maxbus + 1) 3161f55ce205Sszhou array_max <<= 1; 3162f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3163f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 3164f55ce205Sszhou 3165f55ce205Sszhou if (old_res) { /* copy content and free old array */ 3166f55ce205Sszhou bcopy(old_res, pci_bus_res, 3167f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 3168f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 3169f55ce205Sszhou } 3170f55ce205Sszhou } 3171c8589f13Ssethg 3172c8589f13Ssethg static void 3173c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3174c8589f13Ssethg ushort_t deviceid) 3175c8589f13Ssethg { 3176c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 3177c8589f13Ssethg static int numioapics = 0; 3178c8589f13Ssethg dev_info_t *ioapic_node; 3179c8589f13Ssethg uint64_t physaddr; 3180c8589f13Ssethg uint32_t lobase, hibase = 0; 3181c8589f13Ssethg 3182c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3183c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3184c8589f13Ssethg 3185c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3186c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3187c8589f13Ssethg return; 3188c8589f13Ssethg 3189c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3190c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3191c8589f13Ssethg 3192c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 3193c8589f13Ssethg 3194c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 3195c8589f13Ssethg 3196c8589f13Ssethg /* 3197c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 3198c8589f13Ssethg */ 3199c8589f13Ssethg if (ioapicsnode == NULL) { 3200c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3201c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3202c8589f13Ssethg return; 3203c8589f13Ssethg } 3204c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 3205c8589f13Ssethg } 3206c8589f13Ssethg 3207c8589f13Ssethg /* 3208c8589f13Ssethg * Create a child node for this IOAPIC 3209c8589f13Ssethg */ 3210c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3211c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 3212c8589f13Ssethg if (ioapic_node == NULL) { 3213c8589f13Ssethg return; 3214c8589f13Ssethg } 3215c8589f13Ssethg 3216c8589f13Ssethg /* Vendor and Device ID */ 3217c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3218c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 3219c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3220c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 3221c8589f13Ssethg 3222c8589f13Ssethg /* device_type */ 3223c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3224c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 3225c8589f13Ssethg 3226c8589f13Ssethg /* reg */ 3227c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3228c8589f13Ssethg "reg", physaddr); 3229c8589f13Ssethg } 3230d57b3b3dSprasad 3231d57b3b3dSprasad /* 3232d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 3233d57b3b3dSprasad * information obtained from Slot Capabilities register. 3234d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 3235d57b3b3dSprasad * information in the PCI IRQ table. 3236d57b3b3dSprasad */ 3237d57b3b3dSprasad static void 3238d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3239d57b3b3dSprasad { 3240d57b3b3dSprasad char slotprop[256]; 3241d57b3b3dSprasad int len; 3242d57b3b3dSprasad 3243d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 3244d57b3b3dSprasad 3245d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 3246d57b3b3dSprasad *(uint32_t *)slotprop = 1; 3247d57b3b3dSprasad len = 4; 3248d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3249d57b3b3dSprasad slot_num); 3250d57b3b3dSprasad len += strlen(slotprop + len) + 1; 3251d57b3b3dSprasad len += len % 4; 3252d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3253d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 3254d57b3b3dSprasad } 3255