17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22ec0c94e7SDana Myers * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/stat.h> 28ffa17327SGuoli Shu #include <sys/sysmacros.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 307c478bd9Sstevel@tonic-gate #include <sys/pci.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 337c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 347c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3570025d76Sjohnny #include <io/pci/mps_table.h> 36c88420b3Sdmick #include <sys/pci_cfgspace.h> 37c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 38c88420b3Sdmick #include <sys/psw.h> 3909f67678Sanish #include "../../../../common/pci/pci_strings.h" 40c8589f13Ssethg #include <sys/apic.h> 418a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 425af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h> 4325145214Smyers #include <sys/acpi/acpi.h> 4425145214Smyers #include <sys/acpica.h> 4586c1f4dcSVikram Hegde #include <sys/intel_iommu.h> 4694f1124eSVikram Hegde #include <sys/iommulib.h> 477c478bd9Sstevel@tonic-gate 487c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 497c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 507c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 517c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 527c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 537c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 547c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 577c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 587c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 59bd87be88Ssethg #define CONFIG_FIX 3 6070025d76Sjohnny #define COMPAT_BUFSIZE 512 617c478bd9Sstevel@tonic-gate 6205f867c3Sgs #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 6305f867c3Sgs #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 64ffa17327SGuoli Shu /* round down to nearest power of two */ 65ffa17327SGuoli Shu #define P2LE(align) \ 66ffa17327SGuoli Shu { \ 67ffa17327SGuoli Shu int i = 0; \ 68ffa17327SGuoli Shu while (align >>= 1) \ 69ffa17327SGuoli Shu i ++; \ 70ffa17327SGuoli Shu align = 1 << i; \ 71ffa17327SGuoli Shu } \ 7205f867c3Sgs 73*2f283da5SDan Mick /* for is_vga and list_is_vga_only */ 74*2f283da5SDan Mick 75*2f283da5SDan Mick enum io_mem { 76*2f283da5SDan Mick IO, 77*2f283da5SDan Mick MEM 78*2f283da5SDan Mick }; 79*2f283da5SDan Mick 80bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 81bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 82bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 83bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 84bd87be88Ssethg 85bd87be88Ssethg struct pci_fixundo { 86bd87be88Ssethg uint8_t bus; 87bd87be88Ssethg uint8_t dev; 88bd87be88Ssethg uint8_t fn; 89bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 90bd87be88Ssethg struct pci_fixundo *next; 91bd87be88Ssethg }; 92bd87be88Ssethg 9305f867c3Sgs struct pci_devfunc { 9405f867c3Sgs struct pci_devfunc *next; 9505f867c3Sgs dev_info_t *dip; 9605f867c3Sgs uchar_t dev; 9705f867c3Sgs uchar_t func; 9805f867c3Sgs boolean_t reprogram; /* this device needs to be reprogrammed */ 9905f867c3Sgs }; 10005f867c3Sgs 10178323854SJudy Chen extern int pseudo_isa; 1027c478bd9Sstevel@tonic-gate extern int pci_bios_nbus; 1037c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 1047c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 1057c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 106bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 10705f867c3Sgs static int num_root_bus = 0; /* count of root buses */ 1088fc7923fSDana Myers extern volatile int acpi_resource_discovery; 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate /* 1117c478bd9Sstevel@tonic-gate * Module prototypes 1127c478bd9Sstevel@tonic-gate */ 1137c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 1147c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 11505f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 1167c478bd9Sstevel@tonic-gate ushort_t, int); 1177c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 11870025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 1197c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 12049fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 12149fbdd30SErwin T Tsaur ushort_t); 1227c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 1237c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 124b1f176e8Sjg static void add_bus_slot_names_prop(int); 1258fc7923fSDana Myers static void add_ranges_prop(int, int); 1267c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 12749fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 12805f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t); 129f55ce205Sszhou static void alloc_res_array(); 130c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 131c8589f13Ssethg ushort_t deviceid); 132d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1338fc7923fSDana Myers static void populate_bus_res(uchar_t bus); 1348fc7923fSDana Myers static void memlist_remove_list(struct memlist **list, 1358fc7923fSDana Myers struct memlist *remove_list); 1367c478bd9Sstevel@tonic-gate 13775bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 13875bcd456Sjg 139ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 14025145214Smyers int pci_bus_always_renumber = 0; 14125145214Smyers 1421d6b7b34SJudy Chen /* 1431d6b7b34SJudy Chen * used to register ISA resource usage which must not be made 1441d6b7b34SJudy Chen * "available" from other PCI node' resource maps 1451d6b7b34SJudy Chen */ 1461d6b7b34SJudy Chen static struct { 147*2f283da5SDan Mick struct memlist *io_used; 148*2f283da5SDan Mick struct memlist *mem_used; 1491d6b7b34SJudy Chen } isa_res; 1501d6b7b34SJudy Chen 1517c478bd9Sstevel@tonic-gate /* 1527c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 1537c478bd9Sstevel@tonic-gate */ 1547c478bd9Sstevel@tonic-gate void 1557c478bd9Sstevel@tonic-gate pci_setup_tree() 1567c478bd9Sstevel@tonic-gate { 15705043691Sjames north - Sun Microsystems - Austin United States uint_t i, root_bus_addr = 0; 1587c478bd9Sstevel@tonic-gate 159f55ce205Sszhou alloc_res_array(); 1607c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 1617c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 1627c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 1637c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 1647c478bd9Sstevel@tonic-gate } 1657c478bd9Sstevel@tonic-gate 1667c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 1677c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 1687c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 1697c478bd9Sstevel@tonic-gate 1707c478bd9Sstevel@tonic-gate /* 1717c478bd9Sstevel@tonic-gate * Now enumerate peer busses 1727c478bd9Sstevel@tonic-gate * 1737c478bd9Sstevel@tonic-gate * We loop till pci_bios_nbus. On most systems, there is 1747c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 1757c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 1767c478bd9Sstevel@tonic-gate * 1777c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 1787c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 1797c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 1807c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 1817c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 1827c478bd9Sstevel@tonic-gate * device below. 1837c478bd9Sstevel@tonic-gate */ 1847c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_bios_nbus; i++) { 1857c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 1867c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 1877c478bd9Sstevel@tonic-gate } 1887c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 189b1f176e8Sjg 190b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 191b1f176e8Sjg add_bus_slot_names_prop(i); 1927c478bd9Sstevel@tonic-gate } 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate } 1957c478bd9Sstevel@tonic-gate 19625145214Smyers /* 19725145214Smyers * >0 = present, 0 = not present, <0 = error 19825145214Smyers */ 19925145214Smyers static int 20025145214Smyers pci_bbn_present(int bus) 20125145214Smyers { 20225145214Smyers ACPI_HANDLE hdl; 20325145214Smyers int rv; 20425145214Smyers 20525145214Smyers /* no dip means no _BBN */ 20625145214Smyers if (pci_bus_res[bus].dip == NULL) 20725145214Smyers return (0); 20825145214Smyers 209db2bae30SDana Myers rv = -1; /* default return value in case of error below */ 210db2bae30SDana Myers if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 211db2bae30SDana Myers switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 212db2bae30SDana Myers case AE_OK: 213db2bae30SDana Myers rv = 1; 214db2bae30SDana Myers break; 215db2bae30SDana Myers case AE_NOT_FOUND: 216db2bae30SDana Myers rv = 0; 217db2bae30SDana Myers break; 218db2bae30SDana Myers default: 219db2bae30SDana Myers break; 220db2bae30SDana Myers } 221db2bae30SDana Myers } 22225145214Smyers 223db2bae30SDana Myers return (rv); 22425145214Smyers } 22525145214Smyers 22625145214Smyers /* 22725145214Smyers * Return non-zero if any PCI bus in the system has an associated 22825145214Smyers * _BBN object, 0 otherwise. 22925145214Smyers */ 23025145214Smyers static int 23125145214Smyers pci_roots_have_bbn(void) 23225145214Smyers { 23325145214Smyers int i; 23425145214Smyers 23525145214Smyers /* 23625145214Smyers * Scan the PCI busses and look for at least 1 _BBN 23725145214Smyers */ 23825145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 23925145214Smyers /* skip non-root (peer) PCI busses */ 24025145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 24125145214Smyers continue; 24225145214Smyers 24325145214Smyers if (pci_bbn_present(i) > 0) 24425145214Smyers return (1); 24525145214Smyers } 24625145214Smyers return (0); 24725145214Smyers 24825145214Smyers } 24925145214Smyers 25025145214Smyers /* 25125145214Smyers * return non-zero if the machine is one on which we renumber 25225145214Smyers * the internal pci unit-addresses 25325145214Smyers */ 25425145214Smyers static int 25525145214Smyers pci_bus_renumber() 25625145214Smyers { 257ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 25825145214Smyers 259ee8c1d4aSdm if (pci_bus_always_renumber) 26025145214Smyers return (1); 261ee8c1d4aSdm 262ee8c1d4aSdm /* get the FADT */ 263db2bae30SDana Myers if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 264db2bae30SDana Myers AE_OK) 26525145214Smyers return (0); 26625145214Smyers 267ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 268ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 269ee8c1d4aSdm return (0); 270ee8c1d4aSdm else 271ee8c1d4aSdm return (1); 27225145214Smyers } 27325145214Smyers 27425145214Smyers /* 27525145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 27625145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 27725145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 27825145214Smyers * _BBN object associated with each peer bus; use the presence 27925145214Smyers * of this object to remove gaps in the numbering of the peer 28025145214Smyers * PCI bus unit-addresses - only peer busses with an associated 28125145214Smyers * _BBN are counted. 28225145214Smyers */ 28325145214Smyers static void 28425145214Smyers pci_renumber_root_busses(void) 28525145214Smyers { 28625145214Smyers int pci_regs[] = {0, 0, 0}; 28725145214Smyers int i, root_addr = 0; 28825145214Smyers 289ee8c1d4aSdm /* 290ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 291ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 292ee8c1d4aSdm * issue of upgrade changing physical device paths 293ee8c1d4aSdm */ 29425145214Smyers if (!pci_bus_renumber()) 29525145214Smyers return; 29625145214Smyers 29725145214Smyers /* 29825145214Smyers * If we find no _BBN objects at all, we either don't need 29925145214Smyers * to do anything or can't do anything anyway 30025145214Smyers */ 30125145214Smyers if (!pci_roots_have_bbn()) 30225145214Smyers return; 30325145214Smyers 30425145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 30525145214Smyers /* skip non-root (peer) PCI busses */ 30625145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 30725145214Smyers continue; 30825145214Smyers 30925145214Smyers if (pci_bbn_present(i) < 1) { 31025145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 31125145214Smyers continue; 31225145214Smyers } 31325145214Smyers 31425145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 31525145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 31625145214Smyers /* update reg property for node */ 31725145214Smyers pci_bus_res[i].root_addr = root_addr; 31825145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 31925145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 32025145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 32125145214Smyers } 32225145214Smyers root_addr++; 32325145214Smyers } 32425145214Smyers } 32525145214Smyers 32678323854SJudy Chen void 3271d6b7b34SJudy Chen pci_register_isa_resources(int type, uint32_t base, uint32_t size) 328aaba6dfeSmyers { 3291d6b7b34SJudy Chen (void) memlist_insert( 330*2f283da5SDan Mick (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 3311d6b7b34SJudy Chen base, size); 332aaba6dfeSmyers } 333aaba6dfeSmyers 3345af4ae46Sjveta /* 33505f867c3Sgs * Remove the resources which are already used by devices under a subtractive 33605f867c3Sgs * bridge from the bus's resources lists, because they're not available, and 33705f867c3Sgs * shouldn't be allocated to other buses. This is necessary because tracking 33805f867c3Sgs * resources for subtractive bridges is not complete. (Subtractive bridges only 33905f867c3Sgs * track some of their claimed resources, not "the rest of the address space" as 34005f867c3Sgs * they should, so that allocation to peer non-subtractive PPBs is easier. We 34105f867c3Sgs * need a fully-capable global resource allocator). 3425af4ae46Sjveta */ 34305f867c3Sgs static void 34405f867c3Sgs remove_subtractive_res() 3455af4ae46Sjveta { 34605f867c3Sgs int i, j; 34705f867c3Sgs struct memlist *list; 3485af4ae46Sjveta 34905f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) { 35005f867c3Sgs if (pci_bus_res[i].subtractive) { 35105f867c3Sgs /* remove used io ports */ 352*2f283da5SDan Mick list = pci_bus_res[i].io_used; 35305f867c3Sgs while (list) { 3548fc7923fSDana Myers for (j = 0; j <= pci_bios_nbus; j++) 3558fc7923fSDana Myers (void) memlist_remove( 356*2f283da5SDan Mick &pci_bus_res[j].io_avail, 3578fc7923fSDana Myers list->address, list->size); 35805f867c3Sgs list = list->next; 35905f867c3Sgs } 36005f867c3Sgs /* remove used mem resource */ 361*2f283da5SDan Mick list = pci_bus_res[i].mem_used; 36205f867c3Sgs while (list) { 36305f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 3648fc7923fSDana Myers (void) memlist_remove( 365*2f283da5SDan Mick &pci_bus_res[j].mem_avail, 3668fc7923fSDana Myers list->address, list->size); 3678fc7923fSDana Myers (void) memlist_remove( 368*2f283da5SDan Mick &pci_bus_res[j].pmem_avail, 3698fc7923fSDana Myers list->address, list->size); 37005f867c3Sgs } 37105f867c3Sgs list = list->next; 37205f867c3Sgs } 37305f867c3Sgs /* remove used prefetchable mem resource */ 374*2f283da5SDan Mick list = pci_bus_res[i].pmem_used; 37505f867c3Sgs while (list) { 37605f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 3778fc7923fSDana Myers (void) memlist_remove( 378*2f283da5SDan Mick &pci_bus_res[j].pmem_avail, 3798fc7923fSDana Myers list->address, list->size); 3808fc7923fSDana Myers (void) memlist_remove( 381*2f283da5SDan Mick &pci_bus_res[j].mem_avail, 3828fc7923fSDana Myers list->address, list->size); 38305f867c3Sgs } 38405f867c3Sgs list = list->next; 38505f867c3Sgs } 3865af4ae46Sjveta } 38705f867c3Sgs } 38805f867c3Sgs } 38905f867c3Sgs 3908fc7923fSDana Myers /* 391*2f283da5SDan Mick * Set up (or complete the setup of) the bus_avail resource list 3928fc7923fSDana Myers */ 39305f867c3Sgs static void 39405f867c3Sgs setup_bus_res(int bus) 39505f867c3Sgs { 39605f867c3Sgs uchar_t par_bus; 39705f867c3Sgs 39805f867c3Sgs if (pci_bus_res[bus].dip == NULL) /* unused bus */ 39905f867c3Sgs return; 40005f867c3Sgs 4018fc7923fSDana Myers /* 402*2f283da5SDan Mick * Set up bus_avail if not already filled in by populate_bus_res() 4038fc7923fSDana Myers */ 404*2f283da5SDan Mick if (pci_bus_res[bus].bus_avail == NULL) { 4058fc7923fSDana Myers ASSERT(pci_bus_res[bus].sub_bus >= bus); 406*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].bus_avail, bus, 4078fc7923fSDana Myers pci_bus_res[bus].sub_bus - bus + 1); 40805f867c3Sgs } 4095af4ae46Sjveta 410*2f283da5SDan Mick ASSERT(pci_bus_res[bus].bus_avail != NULL); 4118fc7923fSDana Myers 41205f867c3Sgs /* 41305f867c3Sgs * Remove resources from parent bus node if this is not a 41405f867c3Sgs * root bus. 41505f867c3Sgs */ 41605f867c3Sgs par_bus = pci_bus_res[bus].par_bus; 41705f867c3Sgs if (par_bus != (uchar_t)-1) { 418*2f283da5SDan Mick ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 419*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 420*2f283da5SDan Mick pci_bus_res[bus].bus_avail); 42105f867c3Sgs } 4228fc7923fSDana Myers 423*2f283da5SDan Mick /* remove self from bus_avail */; 424*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 4255af4ae46Sjveta } 4265af4ae46Sjveta 42705f867c3Sgs static uint64_t 42805f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 4295af4ae46Sjveta { 43005f867c3Sgs uint64_t addr = 0; 43105f867c3Sgs uchar_t res_bus; 4325af4ae46Sjveta 43305f867c3Sgs /* 4348fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 4358fc7923fSDana Myers * ACPI resource discovery was not successfully done. 43605f867c3Sgs */ 43705f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 4388fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 4395af4ae46Sjveta return (0); 4405af4ae46Sjveta 44105f867c3Sgs res_bus = parbus; 44205f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 443*2f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) 44405f867c3Sgs break; 44505f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 44605f867c3Sgs if (res_bus == (uchar_t)-1) 44705f867c3Sgs break; /* root bus already */ 44805f867c3Sgs } 4495af4ae46Sjveta 450*2f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 451*2f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].io_avail, 45205f867c3Sgs size, align); 45305f867c3Sgs if (addr) { 454*2f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].io_used, 45505f867c3Sgs addr, size); 4568fc7923fSDana Myers 45705f867c3Sgs /* free the old resource */ 458*2f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_avail); 459*2f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_used); 4608fc7923fSDana Myers 46105f867c3Sgs /* add the new resource */ 462*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 46305f867c3Sgs } 4645af4ae46Sjveta } 4655af4ae46Sjveta 46605f867c3Sgs return (addr); 46705f867c3Sgs } 46805f867c3Sgs 46905f867c3Sgs static uint64_t 47005f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 47105f867c3Sgs { 47205f867c3Sgs uint64_t addr = 0; 47305f867c3Sgs uchar_t res_bus; 4745af4ae46Sjveta 4755af4ae46Sjveta /* 4768fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 4778fc7923fSDana Myers * ACPI resource discovery was not successfully done. 4785af4ae46Sjveta */ 47905f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 4808fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 4815af4ae46Sjveta return (0); 4825af4ae46Sjveta 48305f867c3Sgs res_bus = parbus; 48405f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 485*2f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) 48605f867c3Sgs break; 48705f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 48805f867c3Sgs if (res_bus == (uchar_t)-1) 48905f867c3Sgs break; /* root bus already */ 49005f867c3Sgs } 49105f867c3Sgs 492*2f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) { 493*2f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 49405f867c3Sgs size, align); 49505f867c3Sgs if (addr) { 496*2f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].mem_used, 49705f867c3Sgs addr, size); 498*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 4998fc7923fSDana Myers addr, size); 5008fc7923fSDana Myers 50105f867c3Sgs /* free the old resource */ 502*2f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_avail); 503*2f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_used); 5048fc7923fSDana Myers 50505f867c3Sgs /* add the new resource */ 506*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 50705f867c3Sgs } 50805f867c3Sgs } 50905f867c3Sgs 51005f867c3Sgs return (addr); 5115af4ae46Sjveta } 5125af4ae46Sjveta 51349fbdd30SErwin T Tsaur /* 51449fbdd30SErwin T Tsaur * given a cap_id, return its cap_id location in config space 51549fbdd30SErwin T Tsaur */ 51649fbdd30SErwin T Tsaur static int 51749fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 51849fbdd30SErwin T Tsaur { 51949fbdd30SErwin T Tsaur uint8_t curcap, cap_id_loc; 52049fbdd30SErwin T Tsaur uint16_t status; 52149fbdd30SErwin T Tsaur int location = -1; 52249fbdd30SErwin T Tsaur 52349fbdd30SErwin T Tsaur /* 52449fbdd30SErwin T Tsaur * Need to check the Status register for ECP support first. 52549fbdd30SErwin T Tsaur * Also please note that for type 1 devices, the 52649fbdd30SErwin T Tsaur * offset could change. Should support type 1 next. 52749fbdd30SErwin T Tsaur */ 52849fbdd30SErwin T Tsaur status = pci_getw(bus, dev, func, PCI_CONF_STAT); 52949fbdd30SErwin T Tsaur if (!(status & PCI_STAT_CAP)) { 53049fbdd30SErwin T Tsaur return (-1); 53149fbdd30SErwin T Tsaur } 53249fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 53349fbdd30SErwin T Tsaur 53449fbdd30SErwin T Tsaur /* Walk the list of capabilities */ 53549fbdd30SErwin T Tsaur while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 53649fbdd30SErwin T Tsaur curcap = pci_getb(bus, dev, func, cap_id_loc); 53749fbdd30SErwin T Tsaur 53849fbdd30SErwin T Tsaur if (curcap == cap_id) { 53949fbdd30SErwin T Tsaur location = cap_id_loc; 54049fbdd30SErwin T Tsaur break; 54149fbdd30SErwin T Tsaur } 54249fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 54349fbdd30SErwin T Tsaur } 54449fbdd30SErwin T Tsaur return (location); 54549fbdd30SErwin T Tsaur } 54649fbdd30SErwin T Tsaur 547*2f283da5SDan Mick /* 548*2f283da5SDan Mick * Does this resource element live in the legacy VGA range? 549*2f283da5SDan Mick */ 550*2f283da5SDan Mick 551*2f283da5SDan Mick int 552*2f283da5SDan Mick is_vga(struct memlist *elem, enum io_mem io) 553*2f283da5SDan Mick { 554*2f283da5SDan Mick 555*2f283da5SDan Mick if (io == IO) { 556*2f283da5SDan Mick if ((elem->address == 0x3b0 && elem->size == 0xc) || 557*2f283da5SDan Mick (elem->address == 0x3c0 && elem->size == 0x20)) 558*2f283da5SDan Mick return (1); 559*2f283da5SDan Mick } else { 560*2f283da5SDan Mick if (elem->address == 0xa0000 && elem->size == 0x20000) 561*2f283da5SDan Mick return (1); 562*2f283da5SDan Mick } 563*2f283da5SDan Mick return (0); 564*2f283da5SDan Mick } 565*2f283da5SDan Mick 566*2f283da5SDan Mick /* 567*2f283da5SDan Mick * Does this entire resource list consist only of legacy VGA resources? 568*2f283da5SDan Mick */ 569*2f283da5SDan Mick 570*2f283da5SDan Mick int 571*2f283da5SDan Mick list_is_vga_only(struct memlist *l, enum io_mem io) 572*2f283da5SDan Mick { 573*2f283da5SDan Mick do { 574*2f283da5SDan Mick if (!is_vga(l, io)) 575*2f283da5SDan Mick return (0); 576*2f283da5SDan Mick } while ((l = l->next) != NULL); 577*2f283da5SDan Mick return (1); 578*2f283da5SDan Mick } 579*2f283da5SDan Mick 5809896aa55Sjveta /* 58105f867c3Sgs * Assign valid resources to unconfigured pci(e) bridges. We are trying 58205f867c3Sgs * to reprogram the bridge when its 58305f867c3Sgs * i) SECBUS == SUBBUS || 58405f867c3Sgs * ii) IOBASE > IOLIM || 58505f867c3Sgs * iii) MEMBASE > MEMLIM 58605f867c3Sgs * This must be done after one full pass through the PCI tree to collect 58705f867c3Sgs * all BIOS-configured resources, so that we know what resources are 58805f867c3Sgs * free and available to assign to the unconfigured PPBs. 5899896aa55Sjveta */ 5909896aa55Sjveta static void 59105f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 5929896aa55Sjveta { 5939896aa55Sjveta uchar_t bus, dev, func; 59405f867c3Sgs uchar_t parbus, subbus; 59505f867c3Sgs uint_t io_base, io_limit, mem_base, mem_limit; 596ffa17327SGuoli Shu uint_t io_size, mem_size, io_align, mem_align; 59705f867c3Sgs uint64_t addr = 0; 5985af4ae46Sjveta int *regp = NULL; 5999896aa55Sjveta uint_t reglen; 6005af4ae46Sjveta int rv, cap_ptr, physhi; 6019896aa55Sjveta dev_info_t *dip; 60205f867c3Sgs uint16_t cmd_reg; 60305f867c3Sgs struct memlist *list; 60405f867c3Sgs 60505f867c3Sgs /* skip root (peer) PCI busses */ 60605f867c3Sgs if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 60705f867c3Sgs return; 60805f867c3Sgs 60905f867c3Sgs /* skip subtractive PPB when prog_sub is not TRUE */ 61005f867c3Sgs if (pci_bus_res[secbus].subtractive && !prog_sub) 61105f867c3Sgs return; 6129896aa55Sjveta 6139896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 6145af4ae46Sjveta dip = pci_bus_res[secbus].dip; 6159896aa55Sjveta if (dip == NULL) 6169896aa55Sjveta return; 6179896aa55Sjveta 6189896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 6199896aa55Sjveta "reg", ®p, ®len); 620*2f283da5SDan Mick if (rv != DDI_PROP_SUCCESS || reglen == 0) 621*2f283da5SDan Mick return; 6225af4ae46Sjveta physhi = regp[0]; 6235af4ae46Sjveta ddi_prop_free(regp); 6249896aa55Sjveta 6255af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 6265af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 6275af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 6289896aa55Sjveta 6299896aa55Sjveta /* 63005f867c3Sgs * If pcie bridge, check to see if link is enabled 6319896aa55Sjveta */ 63249fbdd30SErwin T Tsaur cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 63349fbdd30SErwin T Tsaur if (cap_ptr != -1) { 63405f867c3Sgs cmd_reg = pci_getw(bus, dev, func, 63505f867c3Sgs (uint16_t)cap_ptr + PCIE_LINKCTL); 63605f867c3Sgs if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 63705f867c3Sgs dcmn_err(CE_NOTE, 63805f867c3Sgs "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 63905f867c3Sgs bus, dev, func); 64005f867c3Sgs return; 64105f867c3Sgs } 64205f867c3Sgs } 6439896aa55Sjveta 64405f867c3Sgs subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 64505f867c3Sgs parbus = pci_bus_res[secbus].par_bus; 64605f867c3Sgs ASSERT(parbus == bus); 647707a5600Sgs cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 6489896aa55Sjveta 6495af4ae46Sjveta /* 65005f867c3Sgs * If we have a Cardbus bridge, but no bus space 6515af4ae46Sjveta */ 65205f867c3Sgs if (pci_bus_res[secbus].num_cbb != 0 && 653*2f283da5SDan Mick pci_bus_res[secbus].bus_avail == NULL) { 65405f867c3Sgs uchar_t range; 6555af4ae46Sjveta 65605f867c3Sgs /* normally there are 2 buses under a cardbus bridge */ 65705f867c3Sgs range = pci_bus_res[secbus].num_cbb * 2; 65805f867c3Sgs 65905f867c3Sgs /* 66005f867c3Sgs * Try to find and allocate a bus-range starting at subbus+1 66105f867c3Sgs * from the parent of the PPB. 66205f867c3Sgs */ 66305f867c3Sgs for (; range != 0; range--) { 66405f867c3Sgs if (memlist_find_with_startaddr( 665*2f283da5SDan Mick &pci_bus_res[parbus].bus_avail, 66605f867c3Sgs subbus + 1, range, 1) != NULL) 66705f867c3Sgs break; /* find bus range resource at parent */ 66805f867c3Sgs } 66905f867c3Sgs if (range != 0) { 670*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].bus_avail, 67105f867c3Sgs subbus + 1, range); 67205f867c3Sgs subbus = subbus + range; 67305f867c3Sgs pci_bus_res[secbus].sub_bus = subbus; 67405f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 67505f867c3Sgs add_bus_range_prop(secbus); 67605f867c3Sgs 67705f867c3Sgs cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 67805f867c3Sgs "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 67905f867c3Sgs secbus, subbus); 68005f867c3Sgs } 68105f867c3Sgs } 68205f867c3Sgs 68305f867c3Sgs /* 684ffa17327SGuoli Shu * Calculate required IO size and alignment 685ffa17327SGuoli Shu * If bus io_size is zero, we are going to assign 512 bytes per bus, 686ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 687ffa17327SGuoli Shu * bus io_size. The size needs to be 4K aligned. 688ffa17327SGuoli Shu * 689ffa17327SGuoli Shu * We calculate alignment as the largest power of two less than the 690ffa17327SGuoli Shu * the sum of all children's IO size requirements, because this will 691ffa17327SGuoli Shu * align to the size of the largest child request within that size 692ffa17327SGuoli Shu * (which is always a power of two). 69305f867c3Sgs */ 69405f867c3Sgs io_size = (subbus - secbus + 1) * 0x200; 695ffa17327SGuoli Shu if (io_size < pci_bus_res[secbus].io_size) 696ffa17327SGuoli Shu io_size = pci_bus_res[secbus].io_size; 697ffa17327SGuoli Shu io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 698ffa17327SGuoli Shu io_align = io_size; 699ffa17327SGuoli Shu P2LE(io_align); 700ffa17327SGuoli Shu 7015af4ae46Sjveta /* 702ffa17327SGuoli Shu * Calculate required MEM size and alignment 703ffa17327SGuoli Shu * If bus mem_size is zero, we are going to assign 1M bytes per bus, 704ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 705ffa17327SGuoli Shu * bus mem_size. The size needs to be 1M aligned. 706ffa17327SGuoli Shu * 707ffa17327SGuoli Shu * For the alignment, refer to the I/O comment above. 7085af4ae46Sjveta */ 70905f867c3Sgs mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 710ffa17327SGuoli Shu if (mem_size < pci_bus_res[secbus].mem_size) { 711ffa17327SGuoli Shu mem_size = pci_bus_res[secbus].mem_size; 712ffa17327SGuoli Shu mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 713ffa17327SGuoli Shu } 714ffa17327SGuoli Shu mem_align = mem_size; 715ffa17327SGuoli Shu P2LE(mem_align); 71605f867c3Sgs 71705f867c3Sgs /* Subtractive bridge */ 71805f867c3Sgs if (pci_bus_res[secbus].subtractive && prog_sub) { 71905f867c3Sgs /* 72005f867c3Sgs * We program an arbitrary amount of I/O and memory resource 72105f867c3Sgs * for the subtractive bridge so that child dynamic-resource- 72205f867c3Sgs * allocating devices (such as Cardbus bridges) have a chance 72305f867c3Sgs * of success. Until we have full-tree resource rebalancing, 72405f867c3Sgs * dynamic resource allocation (thru busra) only looks at the 72505f867c3Sgs * parent bridge, so all PPBs must have some allocatable 72605f867c3Sgs * resource. For non-subtractive bridges, the resources come 72705f867c3Sgs * from the base/limit register "windows", but subtractive 72805f867c3Sgs * bridges often don't program those (since they don't need to). 72905f867c3Sgs * If we put all the remaining resources on the subtractive 73005f867c3Sgs * bridge, then peer non-subtractive bridges can't allocate 73105f867c3Sgs * more space (even though this is probably most correct). 73205f867c3Sgs * If we put the resources only on the parent, then allocations 73305f867c3Sgs * from children of subtractive bridges will fail without 73405f867c3Sgs * special-case code for bypassing the subtractive bridge. 73505f867c3Sgs * This solution is the middle-ground temporary solution until 73605f867c3Sgs * we have fully-capable resource allocation. 73705f867c3Sgs */ 73805f867c3Sgs 73905f867c3Sgs /* 74005f867c3Sgs * Add an arbitrary I/O resource to the subtractive PPB 74105f867c3Sgs */ 742*2f283da5SDan Mick if (pci_bus_res[secbus].io_avail == NULL) { 74305f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 744ffa17327SGuoli Shu io_align); 74505f867c3Sgs if (addr) { 7468fc7923fSDana Myers add_ranges_prop(secbus, 1); 74705f867c3Sgs pci_bus_res[secbus].io_reprogram = 74805f867c3Sgs pci_bus_res[parbus].io_reprogram; 74905f867c3Sgs 75005f867c3Sgs cmn_err(CE_NOTE, "!add io-range on subtractive" 75105f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 75205f867c3Sgs bus, dev, func, (uint32_t)addr, 75305f867c3Sgs (uint32_t)addr + io_size - 1); 75405f867c3Sgs } 75505f867c3Sgs } 75605f867c3Sgs /* 75705f867c3Sgs * Add an arbitrary memory resource to the subtractive PPB 75805f867c3Sgs */ 759*2f283da5SDan Mick if (pci_bus_res[secbus].mem_avail == NULL) { 76005f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 761ffa17327SGuoli Shu mem_align); 76205f867c3Sgs if (addr) { 7638fc7923fSDana Myers add_ranges_prop(secbus, 1); 76405f867c3Sgs pci_bus_res[secbus].mem_reprogram = 76505f867c3Sgs pci_bus_res[parbus].mem_reprogram; 76605f867c3Sgs 76705f867c3Sgs cmn_err(CE_NOTE, "!add mem-range on " 76805f867c3Sgs "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 76905f867c3Sgs bus, dev, func, (uint32_t)addr, 77005f867c3Sgs (uint32_t)addr + mem_size - 1); 77105f867c3Sgs } 77205f867c3Sgs } 77305f867c3Sgs 77405f867c3Sgs goto cmd_enable; 7755af4ae46Sjveta } 77605f867c3Sgs 77705f867c3Sgs /* 778707a5600Sgs * Check to see if we need to reprogram I/O space, either because the 779707a5600Sgs * parent bus needed reprogramming and so do we, or because I/O space is 780707a5600Sgs * disabled in base/limit or command register. 78105f867c3Sgs */ 78205f867c3Sgs io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 78305f867c3Sgs io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 78405f867c3Sgs io_base = (io_base & 0xf0) << 8; 78505f867c3Sgs io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 78605f867c3Sgs 787*2f283da5SDan Mick /* Form list of all resources passed (avail + used) */ 788*2f283da5SDan Mick list = memlist_dup(pci_bus_res[secbus].io_avail); 789*2f283da5SDan Mick memlist_merge(&pci_bus_res[secbus].io_used, &list); 790*2f283da5SDan Mick 791*2f283da5SDan Mick if ((pci_bus_res[parbus].io_reprogram || 792*2f283da5SDan Mick (io_base > io_limit) || 793*2f283da5SDan Mick (!(cmd_reg & PCI_COMM_IO))) && 794*2f283da5SDan Mick !list_is_vga_only(list, IO)) { 795*2f283da5SDan Mick if (pci_bus_res[secbus].io_used) { 796*2f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].io_used, 797*2f283da5SDan Mick &pci_bus_res[secbus].io_avail); 79805f867c3Sgs } 799*2f283da5SDan Mick if (pci_bus_res[secbus].io_avail && 80005f867c3Sgs (!pci_bus_res[parbus].io_reprogram) && 80105f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 80205f867c3Sgs /* rechoose old io ports info */ 803*2f283da5SDan Mick list = pci_bus_res[secbus].io_avail; 804*2f283da5SDan Mick io_base = 0; 805*2f283da5SDan Mick do { 806*2f283da5SDan Mick if (is_vga(list, IO)) 807*2f283da5SDan Mick continue; 808*2f283da5SDan Mick if (!io_base) { 809*2f283da5SDan Mick io_base = (uint_t)list->address; 81005f867c3Sgs io_limit = (uint_t) 811*2f283da5SDan Mick list->address + list->size - 1; 812*2f283da5SDan Mick io_base = 813*2f283da5SDan Mick P2ALIGN(io_base, PPB_IO_ALIGNMENT); 814*2f283da5SDan Mick } else { 815*2f283da5SDan Mick if (list->address + list->size > 816*2f283da5SDan Mick io_limit) { 817*2f283da5SDan Mick io_limit = (uint_t) 818*2f283da5SDan Mick (list->address + 819*2f283da5SDan Mick list->size - 1); 820*2f283da5SDan Mick } 821*2f283da5SDan Mick } 822*2f283da5SDan Mick } while ((list = list->next) != NULL); 82305f867c3Sgs /* 4K aligned */ 824*2f283da5SDan Mick io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 825*2f283da5SDan Mick io_size = io_limit - io_base + 1; 82605f867c3Sgs ASSERT(io_base <= io_limit); 827*2f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].io_avail); 828*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 82905f867c3Sgs io_base, io_size); 830*2f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].io_used, 83105f867c3Sgs io_base, io_size); 832*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].io_avail, 8338fc7923fSDana Myers io_base, io_size); 83405f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 83505f867c3Sgs } else { 83605f867c3Sgs /* get new io ports from parent bus */ 83705f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 838ffa17327SGuoli Shu io_align); 83905f867c3Sgs if (addr) { 84005f867c3Sgs io_base = addr; 84105f867c3Sgs io_limit = addr + io_size - 1; 84205f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 84305f867c3Sgs } 84405f867c3Sgs } 84505f867c3Sgs if (pci_bus_res[secbus].io_reprogram) { 84605f867c3Sgs /* reprogram PPB regs */ 84705f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 84805f867c3Sgs (uchar_t)((io_base>>8) & 0xf0)); 84905f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 85005f867c3Sgs (uchar_t)((io_limit>>8) & 0xf0)); 85105f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 85205f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 8538fc7923fSDana Myers add_ranges_prop(secbus, 1); 85405f867c3Sgs 85505f867c3Sgs cmn_err(CE_NOTE, "!reprogram io-range on" 85605f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 85705f867c3Sgs bus, dev, func, io_base, io_limit); 85805f867c3Sgs } 8599896aa55Sjveta } 8609896aa55Sjveta 8615af4ae46Sjveta /* 862707a5600Sgs * Check memory space as we did I/O space. 8635af4ae46Sjveta */ 86405f867c3Sgs mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 86505f867c3Sgs mem_base = (mem_base & 0xfff0) << 16; 86605f867c3Sgs mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 867707a5600Sgs mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 868707a5600Sgs 869*2f283da5SDan Mick list = memlist_dup(pci_bus_res[secbus].mem_avail); 870*2f283da5SDan Mick memlist_merge(&pci_bus_res[secbus].mem_used, &list); 871*2f283da5SDan Mick 872*2f283da5SDan Mick if ((pci_bus_res[parbus].mem_reprogram || 873*2f283da5SDan Mick (mem_base > mem_limit) || 874*2f283da5SDan Mick (!(cmd_reg & PCI_COMM_MAE))) && 875*2f283da5SDan Mick !list_is_vga_only(list, MEM)) { 876*2f283da5SDan Mick if (pci_bus_res[secbus].mem_used) { 877*2f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].mem_used, 878*2f283da5SDan Mick &pci_bus_res[secbus].mem_avail); 87905f867c3Sgs } 880*2f283da5SDan Mick if (pci_bus_res[secbus].mem_avail && 88105f867c3Sgs (!pci_bus_res[parbus].mem_reprogram) && 88205f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 88305f867c3Sgs /* rechoose old mem resource */ 884*2f283da5SDan Mick list = pci_bus_res[secbus].mem_avail; 885*2f283da5SDan Mick mem_base = 0; 886*2f283da5SDan Mick do { 887*2f283da5SDan Mick if (is_vga(list, MEM)) 888*2f283da5SDan Mick continue; 889*2f283da5SDan Mick if (mem_base == 0) { 890*2f283da5SDan Mick mem_base = (uint_t)list->address; 891*2f283da5SDan Mick mem_base = P2ALIGN(mem_base, 892*2f283da5SDan Mick PPB_MEM_ALIGNMENT); 89305f867c3Sgs mem_limit = (uint_t) 894*2f283da5SDan Mick (list->address + list->size - 1); 895*2f283da5SDan Mick } else { 896*2f283da5SDan Mick if ((list->address + list->size) > 897*2f283da5SDan Mick mem_limit) { 898*2f283da5SDan Mick mem_limit = (uint_t) 899*2f283da5SDan Mick (list->address + 900*2f283da5SDan Mick list->size - 1); 901*2f283da5SDan Mick } 902*2f283da5SDan Mick } 903*2f283da5SDan Mick } while ((list = list->next) != NULL); 904*2f283da5SDan Mick mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 905*2f283da5SDan Mick mem_size = mem_limit + 1 - mem_base; 90605f867c3Sgs ASSERT(mem_base <= mem_limit); 907*2f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].mem_avail); 908*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 90905f867c3Sgs mem_base, mem_size); 910*2f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].mem_used, 91105f867c3Sgs mem_base, mem_size); 912*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 9138fc7923fSDana Myers mem_base, mem_size); 91405f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 91505f867c3Sgs } else { 91605f867c3Sgs /* get new mem resource from parent bus */ 91705f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 918ffa17327SGuoli Shu mem_align); 91905f867c3Sgs if (addr) { 92005f867c3Sgs mem_base = addr; 92105f867c3Sgs mem_limit = addr + mem_size - 1; 92205f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 92305f867c3Sgs } 92405f867c3Sgs } 92505f867c3Sgs 92605f867c3Sgs if (pci_bus_res[secbus].mem_reprogram) { 92702c2c4edSGuoli Shu /* reprogram PPB MEM regs */ 92805f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 92905f867c3Sgs (uint16_t)((mem_base>>16) & 0xfff0)); 93005f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 93105f867c3Sgs (uint16_t)((mem_limit>>16) & 0xfff0)); 93202c2c4edSGuoli Shu /* 93302c2c4edSGuoli Shu * Disable PMEM window by setting base > limit. 93402c2c4edSGuoli Shu * We currently don't reprogram the PMEM like we've 93502c2c4edSGuoli Shu * done for I/O and MEM. (Devices that support prefetch 93602c2c4edSGuoli Shu * can use non-prefetch MEM.) Anyway, if the MEM access 93702c2c4edSGuoli Shu * bit is initially disabled by BIOS, we disable the 93802c2c4edSGuoli Shu * PMEM window manually by setting PMEM base > PMEM 93902c2c4edSGuoli Shu * limit here, in case there are incorrect values in 94002c2c4edSGuoli Shu * them from BIOS, so that we won't get in trouble once 94102c2c4edSGuoli Shu * the MEM access bit is enabled at the end of this 94202c2c4edSGuoli Shu * function. 94302c2c4edSGuoli Shu */ 94402c2c4edSGuoli Shu if (!(cmd_reg & PCI_COMM_MAE)) { 94502c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 94602c2c4edSGuoli Shu 0xfff0); 94702c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 94802c2c4edSGuoli Shu 0x0); 94902c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 95002c2c4edSGuoli Shu 0xffffffff); 95102c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 95202c2c4edSGuoli Shu 0x0); 95302c2c4edSGuoli Shu } 95402c2c4edSGuoli Shu 9558fc7923fSDana Myers add_ranges_prop(secbus, 1); 95605f867c3Sgs 95705f867c3Sgs cmn_err(CE_NOTE, "!reprogram mem-range on" 95805f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 95905f867c3Sgs bus, dev, func, mem_base, mem_limit); 96005f867c3Sgs } 96105f867c3Sgs } 96205f867c3Sgs 96305f867c3Sgs cmd_enable: 964*2f283da5SDan Mick if (pci_bus_res[secbus].io_avail) 96505f867c3Sgs cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 966*2f283da5SDan Mick if (pci_bus_res[secbus].mem_avail) 96705f867c3Sgs cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 96805f867c3Sgs pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 9699896aa55Sjveta } 9709896aa55Sjveta 9717c478bd9Sstevel@tonic-gate void 9727c478bd9Sstevel@tonic-gate pci_reprogram(void) 9737c478bd9Sstevel@tonic-gate { 9747c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 9757c478bd9Sstevel@tonic-gate char *onoff; 9768fc7923fSDana Myers int bus; 9777c478bd9Sstevel@tonic-gate 97825145214Smyers /* 97925145214Smyers * Excise phantom roots if possible 98025145214Smyers */ 98125145214Smyers pci_renumber_root_busses(); 98225145214Smyers 9838fc7923fSDana Myers /* 9848fc7923fSDana Myers * Do root-bus resource discovery 9858fc7923fSDana Myers */ 9868fc7923fSDana Myers for (bus = 0; bus <= pci_bios_nbus; bus++) { 9878fc7923fSDana Myers /* skip non-root (peer) PCI busses */ 9888fc7923fSDana Myers if (pci_bus_res[bus].par_bus != (uchar_t)-1) 9898fc7923fSDana Myers continue; 9908fc7923fSDana Myers 9918fc7923fSDana Myers /* 9928fc7923fSDana Myers * 1. find resources associated with this root bus 9938fc7923fSDana Myers */ 9948fc7923fSDana Myers populate_bus_res(bus); 9958fc7923fSDana Myers 9968fc7923fSDana Myers 9978fc7923fSDana Myers /* 9981d6b7b34SJudy Chen * 2. Remove used PCI and ISA resources from bus resource map 9998fc7923fSDana Myers */ 10008fc7923fSDana Myers 1001*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 1002*2f283da5SDan Mick pci_bus_res[bus].io_used); 1003*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 1004*2f283da5SDan Mick pci_bus_res[bus].mem_used); 1005*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1006*2f283da5SDan Mick pci_bus_res[bus].pmem_used); 1007*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 1008*2f283da5SDan Mick pci_bus_res[bus].pmem_used); 1009*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 1010*2f283da5SDan Mick pci_bus_res[bus].mem_used); 10111d6b7b34SJudy Chen 1012*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 1013*2f283da5SDan Mick isa_res.io_used); 1014*2f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 1015*2f283da5SDan Mick isa_res.mem_used); 10168fc7923fSDana Myers } 10178fc7923fSDana Myers 1018*2f283da5SDan Mick memlist_free_all(&isa_res.io_used); 1019*2f283da5SDan Mick memlist_free_all(&isa_res.mem_used); 10208fc7923fSDana Myers 1021fc396574Srw /* add bus-range property for root/peer bus nodes */ 1022fc396574Srw for (i = 0; i <= pci_bios_nbus; i++) { 10238fc7923fSDana Myers /* create bus-range property on root/peer buses */ 10248fc7923fSDana Myers if (pci_bus_res[i].par_bus == (uchar_t)-1) 1025fc396574Srw add_bus_range_prop(i); 10268fc7923fSDana Myers 102705f867c3Sgs /* setup bus range resource on each bus */ 102805f867c3Sgs setup_bus_res(i); 1029fc396574Srw } 1030fc396574Srw 10317c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 10327c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 10337c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 10347c478bd9Sstevel@tonic-gate pci_reconfig = 0; 10357c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 10367c478bd9Sstevel@tonic-gate } 10377c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 10387c478bd9Sstevel@tonic-gate } 10397c478bd9Sstevel@tonic-gate 104005f867c3Sgs remove_subtractive_res(); 104105f867c3Sgs 104205f867c3Sgs /* reprogram the non-subtractive PPB */ 104305f867c3Sgs if (pci_reconfig) 104405f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) 104505f867c3Sgs fix_ppb_res(i, B_FALSE); 1046aaba6dfeSmyers 10477c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 104805f867c3Sgs /* configure devices not configured by BIOS */ 10499896aa55Sjveta if (pci_reconfig) { 105005f867c3Sgs /* 105105f867c3Sgs * Reprogram the subtractive PPB. At this time, all its 105205f867c3Sgs * siblings should have got their resources already. 105305f867c3Sgs */ 105405f867c3Sgs if (pci_bus_res[i].subtractive) 105505f867c3Sgs fix_ppb_res(i, B_TRUE); 10567c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 10579896aa55Sjveta } 10588fc7923fSDana Myers } 10598fc7923fSDana Myers 10608fc7923fSDana Myers /* All dev programmed, so we can create available prop */ 10618fc7923fSDana Myers for (i = 0; i <= pci_bios_nbus; i++) 10627c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 10638fc7923fSDana Myers } 10648fc7923fSDana Myers 10658fc7923fSDana Myers /* 10668fc7923fSDana Myers * populate bus resources 10678fc7923fSDana Myers */ 10688fc7923fSDana Myers static void 10698fc7923fSDana Myers populate_bus_res(uchar_t bus) 10708fc7923fSDana Myers { 10718fc7923fSDana Myers 10728fc7923fSDana Myers /* scan BIOS structures */ 1073*2f283da5SDan Mick pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 1074*2f283da5SDan Mick pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 1075*2f283da5SDan Mick pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 1076*2f283da5SDan Mick pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 10778fc7923fSDana Myers 10786b57bdc9SDana Myers /* 10796b57bdc9SDana Myers * attempt to initialize sub_bus from the largest range-end 1080*2f283da5SDan Mick * in the bus_avail list 10816b57bdc9SDana Myers */ 1082*2f283da5SDan Mick if (pci_bus_res[bus].bus_avail != NULL) { 10836b57bdc9SDana Myers struct memlist *entry; 10846b57bdc9SDana Myers int current; 10856b57bdc9SDana Myers 1086*2f283da5SDan Mick entry = pci_bus_res[bus].bus_avail; 10876b57bdc9SDana Myers while (entry != NULL) { 10886b57bdc9SDana Myers current = entry->address + entry->size - 1; 10896b57bdc9SDana Myers if (current > pci_bus_res[bus].sub_bus) 10906b57bdc9SDana Myers pci_bus_res[bus].sub_bus = current; 10916b57bdc9SDana Myers entry = entry->next; 10926b57bdc9SDana Myers } 10936b57bdc9SDana Myers } 10946b57bdc9SDana Myers 10958fc7923fSDana Myers if (bus == 0) { 10968fc7923fSDana Myers /* 10978fc7923fSDana Myers * Special treatment of bus 0: 10988fc7923fSDana Myers * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 10998fc7923fSDana Myers * pcimem from boot and make I/O space the entire range 11006b57bdc9SDana Myers * starting at 0x100. 11018fc7923fSDana Myers */ 1102*2f283da5SDan Mick if (pci_bus_res[0].mem_avail == NULL) 1103*2f283da5SDan Mick pci_bus_res[0].mem_avail = 11048fc7923fSDana Myers memlist_dup(bootops->boot_mem->pcimem); 11058fc7923fSDana Myers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 1106*2f283da5SDan Mick if (pci_bus_res[0].io_avail == NULL) 1107*2f283da5SDan Mick memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 11087c478bd9Sstevel@tonic-gate } 11098fc7923fSDana Myers 11108fc7923fSDana Myers /* 11118fc7923fSDana Myers * Create 'ranges' property here before any resources are 11128fc7923fSDana Myers * removed from the resource lists 11138fc7923fSDana Myers */ 11148fc7923fSDana Myers add_ranges_prop(bus, 0); 11157c478bd9Sstevel@tonic-gate } 11167c478bd9Sstevel@tonic-gate 11178fc7923fSDana Myers 11187c478bd9Sstevel@tonic-gate /* 11197c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 11207c478bd9Sstevel@tonic-gate */ 11217c478bd9Sstevel@tonic-gate static void 11227c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 11237c478bd9Sstevel@tonic-gate { 11247c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 11257c478bd9Sstevel@tonic-gate dev_info_t *dip; 11267c478bd9Sstevel@tonic-gate 11277c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 11287c478bd9Sstevel@tonic-gate 112905f867c3Sgs num_root_bus++; 11307c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1131fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 11327c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 11337c478bd9Sstevel@tonic-gate "#address-cells", 3); 11347c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 11357c478bd9Sstevel@tonic-gate "#size-cells", 2); 11367c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 11377c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 11387c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 11397c478bd9Sstevel@tonic-gate 114070025d76Sjohnny /* 114170025d76Sjohnny * If system has PCIe bus, then create different properties 114270025d76Sjohnny */ 114370025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 114470025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 114570025d76Sjohnny "device_type", "pci"); 114670025d76Sjohnny 11477c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 11487c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 11497c478bd9Sstevel@tonic-gate } 11507c478bd9Sstevel@tonic-gate 11517c478bd9Sstevel@tonic-gate /* 11527c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 11537c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 11547c478bd9Sstevel@tonic-gate * to hold the already configured device details. 11557c478bd9Sstevel@tonic-gate */ 11567c478bd9Sstevel@tonic-gate void 11577c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 11587c478bd9Sstevel@tonic-gate { 11597c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 11607c478bd9Sstevel@tonic-gate ushort_t venid; 116105f867c3Sgs struct pci_devfunc *devlist = NULL, *entry; 11627c478bd9Sstevel@tonic-gate 11637c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 11647c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1165bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 1166bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 11677c478bd9Sstevel@tonic-gate } else 11687c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 11697c478bd9Sstevel@tonic-gate 11708fc7923fSDana Myers if (config_op == CONFIG_NEW) { 11718fc7923fSDana Myers devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 11728fc7923fSDana Myers while (devlist) { 11738fc7923fSDana Myers entry = devlist; 11748fc7923fSDana Myers devlist = entry->next; 11758fc7923fSDana Myers if (entry->reprogram || 11768fc7923fSDana Myers pci_bus_res[bus].io_reprogram || 11778fc7923fSDana Myers pci_bus_res[bus].mem_reprogram) { 11788fc7923fSDana Myers /* reprogram device(s) */ 11798fc7923fSDana Myers (void) add_reg_props(entry->dip, bus, 11808fc7923fSDana Myers entry->dev, entry->func, CONFIG_NEW, 0); 11818fc7923fSDana Myers } 11828fc7923fSDana Myers kmem_free(entry, sizeof (*entry)); 11838fc7923fSDana Myers } 11848fc7923fSDana Myers pci_bus_res[bus].privdata = NULL; 11858fc7923fSDana Myers return; 11868fc7923fSDana Myers } 11878fc7923fSDana Myers 11887c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 11897c478bd9Sstevel@tonic-gate nfunc = 1; 11907c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 11917c478bd9Sstevel@tonic-gate 11927c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 11937c478bd9Sstevel@tonic-gate dev, func); 11947c478bd9Sstevel@tonic-gate 11957c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1196bd87be88Ssethg 11977c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 11987c478bd9Sstevel@tonic-gate /* no function at this address */ 11997c478bd9Sstevel@tonic-gate continue; 12007c478bd9Sstevel@tonic-gate } 12017c478bd9Sstevel@tonic-gate 12027c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 12037c478bd9Sstevel@tonic-gate if (header == 0xff) { 12047c478bd9Sstevel@tonic-gate continue; /* illegal value */ 12057c478bd9Sstevel@tonic-gate } 12067c478bd9Sstevel@tonic-gate 12077c478bd9Sstevel@tonic-gate /* 12087c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 12097c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 12107c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 12117c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 12127c478bd9Sstevel@tonic-gate */ 12137c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 12147c478bd9Sstevel@tonic-gate nfunc = 8; 12157c478bd9Sstevel@tonic-gate } 121646e9e839Smyers 121705f867c3Sgs if (config_op == CONFIG_FIX || 121805f867c3Sgs config_op == CONFIG_INFO) { 1219ebf3afa8Sdmick /* 1220ebf3afa8Sdmick * Create the node, unconditionally, on the 1221ebf3afa8Sdmick * first pass only. It may still need 1222ebf3afa8Sdmick * resource assignment, which will be 1223ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 1224ebf3afa8Sdmick */ 122505f867c3Sgs process_devfunc(bus, dev, func, header, 1226ebf3afa8Sdmick venid, config_op); 1227db063408Sdmick 12287c478bd9Sstevel@tonic-gate } 12297c478bd9Sstevel@tonic-gate } 12307c478bd9Sstevel@tonic-gate } 12317c478bd9Sstevel@tonic-gate 12328fc7923fSDana Myers /* percolate bus used resources up through parents to root */ 12338fc7923fSDana Myers if (config_op == CONFIG_INFO) { 12348fc7923fSDana Myers int par_bus; 12358fc7923fSDana Myers 12368fc7923fSDana Myers par_bus = pci_bus_res[bus].par_bus; 12378fc7923fSDana Myers while (par_bus != (uchar_t)-1) { 1238ffa17327SGuoli Shu pci_bus_res[par_bus].io_size += 1239ffa17327SGuoli Shu pci_bus_res[bus].io_size; 1240ffa17327SGuoli Shu pci_bus_res[par_bus].mem_size += 1241ffa17327SGuoli Shu pci_bus_res[bus].mem_size; 12428fc7923fSDana Myers 1243*2f283da5SDan Mick if (pci_bus_res[bus].io_used) 1244*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, 1245*2f283da5SDan Mick &pci_bus_res[par_bus].io_used); 12468fc7923fSDana Myers 1247*2f283da5SDan Mick if (pci_bus_res[bus].mem_used) 1248*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, 1249*2f283da5SDan Mick &pci_bus_res[par_bus].mem_used); 12508fc7923fSDana Myers 1251*2f283da5SDan Mick if (pci_bus_res[bus].pmem_used) 1252*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, 1253*2f283da5SDan Mick &pci_bus_res[par_bus].pmem_used); 12548fc7923fSDana Myers 1255*2f283da5SDan Mick bus = par_bus; 12568fc7923fSDana Myers par_bus = pci_bus_res[par_bus].par_bus; 12577c478bd9Sstevel@tonic-gate } 12587c478bd9Sstevel@tonic-gate } 12597c478bd9Sstevel@tonic-gate } 12607c478bd9Sstevel@tonic-gate 12617c478bd9Sstevel@tonic-gate static int 12627c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 12637c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 12647c478bd9Sstevel@tonic-gate { 12657c478bd9Sstevel@tonic-gate static int prop_exist = -1; 12667c478bd9Sstevel@tonic-gate static char *pciide_str; 12677c478bd9Sstevel@tonic-gate char compat[32]; 12687c478bd9Sstevel@tonic-gate 12697c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 12707c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 12717c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 12727c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 12737c478bd9Sstevel@tonic-gate } 12747c478bd9Sstevel@tonic-gate 12757c478bd9Sstevel@tonic-gate if (!prop_exist) 12767c478bd9Sstevel@tonic-gate return (0); 12777c478bd9Sstevel@tonic-gate 12787c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 12797c478bd9Sstevel@tonic-gate if (subvenid) { 12807c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 12817c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 12827c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12837c478bd9Sstevel@tonic-gate return (1); 12847c478bd9Sstevel@tonic-gate 12857c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 12867c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 12877c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12887c478bd9Sstevel@tonic-gate return (1); 12897c478bd9Sstevel@tonic-gate 12907c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 12917c478bd9Sstevel@tonic-gate subvenid, subdevid); 12927c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12937c478bd9Sstevel@tonic-gate return (1); 12947c478bd9Sstevel@tonic-gate } 12957c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 12967c478bd9Sstevel@tonic-gate venid, devid, revid); 12977c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 12987c478bd9Sstevel@tonic-gate return (1); 12997c478bd9Sstevel@tonic-gate 13007c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 13017c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 13027c478bd9Sstevel@tonic-gate return (1); 13037c478bd9Sstevel@tonic-gate 13047c478bd9Sstevel@tonic-gate return (0); 13057c478bd9Sstevel@tonic-gate } 13067c478bd9Sstevel@tonic-gate 13077c478bd9Sstevel@tonic-gate static int 13087c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 13097c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 13107c478bd9Sstevel@tonic-gate { 13117c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 13127c478bd9Sstevel@tonic-gate ushort_t venid; 13137c478bd9Sstevel@tonic-gate ushort_t devid; 13147c478bd9Sstevel@tonic-gate } *entry; 13157c478bd9Sstevel@tonic-gate 1316334edc48Sml /* XXX SATA and other devices: need a way to add dynamically */ 13177c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 13187c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 13197c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 13207c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 1321d01a0451Stt {0x1095, 0x680}, /* Sil0680 */ 1322334edc48Sml {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 13237c478bd9Sstevel@tonic-gate {0, 0} 13247c478bd9Sstevel@tonic-gate }; 13257c478bd9Sstevel@tonic-gate 13267c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 13277c478bd9Sstevel@tonic-gate return (0); 13287c478bd9Sstevel@tonic-gate 13297c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 13307c478bd9Sstevel@tonic-gate return (1); 13317c478bd9Sstevel@tonic-gate } 13327c478bd9Sstevel@tonic-gate 1333d01a0451Stt if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1334d01a0451Stt return (1); 1335d01a0451Stt 13367c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 13377c478bd9Sstevel@tonic-gate return (0); 13387c478bd9Sstevel@tonic-gate } 13397c478bd9Sstevel@tonic-gate 13407c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 13417c478bd9Sstevel@tonic-gate while (entry->venid) { 13427c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 13437c478bd9Sstevel@tonic-gate return (1); 13447c478bd9Sstevel@tonic-gate entry++; 13457c478bd9Sstevel@tonic-gate } 1346d01a0451Stt return (0); 13477c478bd9Sstevel@tonic-gate } 13487c478bd9Sstevel@tonic-gate 13497c478bd9Sstevel@tonic-gate static int 13507c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 13517c478bd9Sstevel@tonic-gate { 13527c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 13537c478bd9Sstevel@tonic-gate 0x000100, 13547c478bd9Sstevel@tonic-gate 0x030000, 13557c478bd9Sstevel@tonic-gate 0x030001 13567c478bd9Sstevel@tonic-gate }; 13577c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 13587c478bd9Sstevel@tonic-gate 13597c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 13607c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 13617c478bd9Sstevel@tonic-gate return (1); 13627c478bd9Sstevel@tonic-gate } 13637c478bd9Sstevel@tonic-gate return (0); 13647c478bd9Sstevel@tonic-gate } 13657c478bd9Sstevel@tonic-gate 1366bd87be88Ssethg static void 1367bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1368bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 1369bd87be88Ssethg { 1370bd87be88Ssethg struct pci_fixundo *newundo; 1371bd87be88Ssethg 1372bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1373bd87be88Ssethg 1374bd87be88Ssethg /* 1375bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 1376bd87be88Ssethg * bit back on at a later time. 1377bd87be88Ssethg */ 1378bd87be88Ssethg newundo->bus = bus; 1379bd87be88Ssethg newundo->dev = dev; 1380bd87be88Ssethg newundo->fn = fn; 1381bd87be88Ssethg newundo->undofn = undofn; 1382bd87be88Ssethg newundo->next = undolist; 1383bd87be88Ssethg 1384bd87be88Ssethg /* add to the undo list in LIFO order */ 1385bd87be88Ssethg undolist = newundo; 1386bd87be88Ssethg } 1387bd87be88Ssethg 1388bd87be88Ssethg void 1389bd87be88Ssethg add_pci_fixes(void) 1390bd87be88Ssethg { 1391bd87be88Ssethg int i; 1392bd87be88Ssethg 1393bd87be88Ssethg for (i = 0; i <= pci_bios_nbus; i++) { 1394bd87be88Ssethg /* 1395bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 1396bd87be88Ssethg * This must be done before the main enumeration loop because 1397bd87be88Ssethg * some fixes must be applied to devices normally encountered 1398bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 1399bd87be88Ssethg * applied before scanning device 6, applying fixes in the 1400bd87be88Ssethg * normal enumeration loop would obviously be too late). 1401bd87be88Ssethg */ 1402bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 1403bd87be88Ssethg } 1404bd87be88Ssethg } 1405bd87be88Ssethg 1406bd87be88Ssethg void 1407bd87be88Ssethg undo_pci_fixes(void) 1408bd87be88Ssethg { 1409bd87be88Ssethg struct pci_fixundo *nextundo; 1410bd87be88Ssethg uint8_t bus, dev, fn; 1411bd87be88Ssethg 1412bd87be88Ssethg /* 1413bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 1414bd87be88Ssethg * fixes may require selective undo. 1415bd87be88Ssethg */ 1416bd87be88Ssethg while (undolist != NULL) { 1417bd87be88Ssethg 1418bd87be88Ssethg bus = undolist->bus; 1419bd87be88Ssethg dev = undolist->dev; 1420bd87be88Ssethg fn = undolist->fn; 1421bd87be88Ssethg 1422bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 1423bd87be88Ssethg 1424bd87be88Ssethg nextundo = undolist->next; 1425bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 1426bd87be88Ssethg undolist = nextundo; 1427bd87be88Ssethg } 1428bd87be88Ssethg } 1429bd87be88Ssethg 1430bd87be88Ssethg static void 1431bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1432bd87be88Ssethg { 1433bd87be88Ssethg uint8_t val8; 1434bd87be88Ssethg 1435bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1436bd87be88Ssethg /* 1437bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 1438bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 1439bd87be88Ssethg */ 1440bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 1441bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1442bd87be88Ssethg } 1443bd87be88Ssethg 1444bd87be88Ssethg static void 1445bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1446bd87be88Ssethg { 1447bd87be88Ssethg uint8_t val8; 1448bd87be88Ssethg 1449bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1450bd87be88Ssethg 1451bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 1452bd87be88Ssethg return; 1453bd87be88Ssethg 1454bd87be88Ssethg /* 1455bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 1456bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 1457bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 1458bd87be88Ssethg */ 1459bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 1460bd87be88Ssethg 1461bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1462bd87be88Ssethg 1463bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1464bd87be88Ssethg } 1465bd87be88Ssethg 1466c8711d4dSgs static void 1467c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1468c8711d4dSgs { 1469c8711d4dSgs uint16_t status; 1470c8711d4dSgs uint8_t header; 1471c8711d4dSgs uint8_t cap_ptr; 1472c8711d4dSgs uint8_t cap_id; 1473c8711d4dSgs uint16_t pmcsr; 1474c8711d4dSgs 1475c8711d4dSgs status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1476c8711d4dSgs if (!(status & PCI_STAT_CAP)) 1477c8711d4dSgs return; /* No capabilities list */ 1478c8711d4dSgs 1479c8711d4dSgs header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1480c8711d4dSgs if (header == PCI_HEADER_CARDBUS) 1481fb66942fSCasper H.S. Dik cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1482c8711d4dSgs else 1483c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1484c8711d4dSgs /* 1485c8711d4dSgs * Walk the capabilities list searching for a PM entry. 1486c8711d4dSgs */ 1487c8711d4dSgs while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1488c8711d4dSgs cap_ptr &= PCI_CAP_PTR_MASK; 1489c8711d4dSgs cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1490c8711d4dSgs if (cap_id == PCI_CAP_ID_PM) { 1491c8711d4dSgs pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1492c8711d4dSgs pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1493c8711d4dSgs pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1494c8711d4dSgs pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1495c8711d4dSgs break; 1496c8711d4dSgs } 1497c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1498c8711d4dSgs } 1499c8711d4dSgs 1500c8711d4dSgs } 1501c8711d4dSgs 150278323854SJudy Chen #define is_isa(bc, sc) \ 150378323854SJudy Chen (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 150478323854SJudy Chen 150505f867c3Sgs static void 1506bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 15077c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 15087c478bd9Sstevel@tonic-gate { 15097c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 15107c478bd9Sstevel@tonic-gate dev_info_t *dip; 1511c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 15127c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 151370025d76Sjohnny ushort_t slot_num; 15147c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 15158d483882Smlf int reprogram = 0, pciide = 0; 15167c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 151770025d76Sjohnny int pciex = 0; 151870025d76Sjohnny ushort_t is_pci_bridge = 0; 151905f867c3Sgs struct pci_devfunc *devlist = NULL, *entry = NULL; 152086c1f4dcSVikram Hegde iommu_private_t *private; 152194f1124eSVikram Hegde gfx_entry_t *gfxp; 15227c478bd9Sstevel@tonic-gate 15237c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 15247c478bd9Sstevel@tonic-gate 15257c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 15267c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 15277c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 15287c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 15297c478bd9Sstevel@tonic-gate break; 15307c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 15317c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 15327c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 153305f867c3Sgs /* Record the # of cardbus bridges found on the bus */ 153405f867c3Sgs if (config_op == CONFIG_INFO) 153505f867c3Sgs pci_bus_res[bus].num_cbb++; 15367c478bd9Sstevel@tonic-gate break; 15377c478bd9Sstevel@tonic-gate default: 15387c478bd9Sstevel@tonic-gate subvenid = 0; 15397c478bd9Sstevel@tonic-gate subdevid = 0; 15407c478bd9Sstevel@tonic-gate break; 15417c478bd9Sstevel@tonic-gate } 15427c478bd9Sstevel@tonic-gate 1543bd87be88Ssethg if (config_op == CONFIG_FIX) { 1544bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1545bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 1546bd87be88Ssethg } 154705f867c3Sgs return; 1548bd87be88Ssethg } 1549bd87be88Ssethg 15507c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 15517c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 15527c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 15537c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 15547c478bd9Sstevel@tonic-gate 15557c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 15567c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 15577c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1558c8589f13Ssethg progcl = classcode & 0xff; 15597c478bd9Sstevel@tonic-gate 15608d483882Smlf 15618d483882Smlf if (is_display(classcode)) 15627c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 156378323854SJudy Chen else if (!pseudo_isa && is_isa(basecl, subcl)) 156478323854SJudy Chen (void) snprintf(nodename, sizeof (nodename), "isa"); 15657c478bd9Sstevel@tonic-gate else if (subvenid != 0) 15667c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 15677c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 15687c478bd9Sstevel@tonic-gate else 15697c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 15707c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 15717c478bd9Sstevel@tonic-gate 15727c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 15738fc7923fSDana Myers if (pci_bus_res[bus].dip == NULL) 15747c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 15757c478bd9Sstevel@tonic-gate 15767c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 15777c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 15787c478bd9Sstevel@tonic-gate 157900d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 158000d0963fSdilpreet &is_pci_bridge) == B_TRUE) 158100d0963fSdilpreet pciex = 1; 158200d0963fSdilpreet 15837c478bd9Sstevel@tonic-gate /* add properties */ 15847c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 15857c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 15867c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 15877c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 15887c478bd9Sstevel@tonic-gate "class-code", classcode); 15897c478bd9Sstevel@tonic-gate if (func == 0) 15907c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 15917c478bd9Sstevel@tonic-gate else 15927c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 15937c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 15947c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 15957c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 15967c478bd9Sstevel@tonic-gate 1597ebf3afa8Sdmick /* add device_type for display nodes */ 1598ebf3afa8Sdmick if (is_display(classcode)) { 1599ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1600ebf3afa8Sdmick "device_type", "display"); 1601ebf3afa8Sdmick } 16027c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 16037c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 16047c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 16057c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 16067c478bd9Sstevel@tonic-gate 16077c478bd9Sstevel@tonic-gate if (subvenid != 0) { 16087c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16097c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 16107c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16117c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 16127c478bd9Sstevel@tonic-gate } 161370025d76Sjohnny if (!pciex) 161470025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 161570025d76Sjohnny "min-grant", mingrant); 161670025d76Sjohnny if (!pciex) 161770025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 161870025d76Sjohnny "max-latency", maxlatency); 16197c478bd9Sstevel@tonic-gate } 16207c478bd9Sstevel@tonic-gate 16217c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 16227c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 16237c478bd9Sstevel@tonic-gate if (intr != 0) 16247c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16257c478bd9Sstevel@tonic-gate "interrupts", intr); 16267c478bd9Sstevel@tonic-gate 16277c478bd9Sstevel@tonic-gate /* 16287c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 16297c478bd9Sstevel@tonic-gate */ 16307c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 16317c478bd9Sstevel@tonic-gate 16327c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 16337c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 163470025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 16357c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 16367c478bd9Sstevel@tonic-gate "fast-back-to-back"); 163770025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 16387c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 16397c478bd9Sstevel@tonic-gate "66mhz-capable"); 16407c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 16417c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 16427c478bd9Sstevel@tonic-gate "udf-supported"); 1643d57b3b3dSprasad if (pciex && slot_num) { 164470025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 164570025d76Sjohnny "physical-slot#", slot_num); 1646d57b3b3dSprasad if (!is_pci_bridge) 1647d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 1648d57b3b3dSprasad } 16497c478bd9Sstevel@tonic-gate 16507c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 16517c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 16527c478bd9Sstevel@tonic-gate 1653c8711d4dSgs /* Set the device PM state to D0 */ 1654c8711d4dSgs set_devpm_d0(bus, dev, func); 1655c8711d4dSgs 165670025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 165749fbdd30SErwin T Tsaur add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 165805f867c3Sgs else { 165905f867c3Sgs /* 166005f867c3Sgs * Record the non-PPB devices on the bus for possible 166105f867c3Sgs * reprogramming at 2nd bus enumeration. 166205f867c3Sgs * Note: PPB reprogramming is done in fix_ppb_res() 166305f867c3Sgs */ 166405f867c3Sgs devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 166505f867c3Sgs entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 166605f867c3Sgs entry->dip = dip; 166705f867c3Sgs entry->dev = dev; 166805f867c3Sgs entry->func = func; 166905f867c3Sgs entry->next = devlist; 167005f867c3Sgs pci_bus_res[bus].privdata = entry; 167105f867c3Sgs } 167270025d76Sjohnny 1673c8589f13Ssethg if (config_op == CONFIG_INFO && 1674c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1675c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 1676c8589f13Ssethg } 1677c8589f13Ssethg 167870025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 167970025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 168070025d76Sjohnny (func == 0)) 16818a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 168270025d76Sjohnny 168370025d76Sjohnny if (pciex && is_pci_bridge) 168470025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 168570025d76Sjohnny (char *)"PCIe-PCI bridge"); 168670025d76Sjohnny else 168770025d76Sjohnny add_model_prop(dip, classcode); 16887c478bd9Sstevel@tonic-gate 16897c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 169070025d76Sjohnny revid, classcode, pciex); 16918d483882Smlf 16928d483882Smlf /* 16938d483882Smlf * See if this device is a controller that advertises 16948d483882Smlf * itself to be a standard ATA task file controller, or one that 16958d483882Smlf * has been hard coded. 16968d483882Smlf * 16978d483882Smlf * If it is, check if any other higher precedence driver listed in 16988d483882Smlf * driver_aliases will claim the node by calling 16998d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 17008d483882Smlf * create a pci-ide node or any other special handling. 17018d483882Smlf * 17028d483882Smlf * If another driver does not bind, set the node name to pci-ide 17038d483882Smlf * and then let the special pci-ide handling for registers and 17048d483882Smlf * child pci-ide nodes proceed below. 17058d483882Smlf */ 17068d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 17078d483882Smlf subvenid, subdevid) == 1) { 17088d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 17098d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 17108d483882Smlf pciide = 1; 17118d483882Smlf } 17128d483882Smlf } 17138d483882Smlf 17147c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 17157c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 17167c478bd9Sstevel@tonic-gate 17177c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 17187c478bd9Sstevel@tonic-gate if (pciide) { 17197c478bd9Sstevel@tonic-gate dev_info_t *cdip; 17207c478bd9Sstevel@tonic-gate 17217c478bd9Sstevel@tonic-gate /* 17227c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 17237c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 17247c478bd9Sstevel@tonic-gate */ 17257c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 17267c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 17277c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 17287c478bd9Sstevel@tonic-gate "#address-cells", 1); 17297c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 17307c478bd9Sstevel@tonic-gate "#size-cells", 0); 17317c478bd9Sstevel@tonic-gate 17327c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 17337c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1734fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 17357c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 17367c478bd9Sstevel@tonic-gate "reg", 0); 17377c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 17387c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 1739fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 17407c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 17417c478bd9Sstevel@tonic-gate "reg", 1); 17427c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 17437c478bd9Sstevel@tonic-gate 17447c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 17457c478bd9Sstevel@tonic-gate } 17467c478bd9Sstevel@tonic-gate 174786c1f4dcSVikram Hegde /* allocate and set up iommu private */ 174886c1f4dcSVikram Hegde private = kmem_alloc(sizeof (iommu_private_t), KM_SLEEP); 174986c1f4dcSVikram Hegde private->idp_seg = 0; 175086c1f4dcSVikram Hegde private->idp_bus = bus; 175186c1f4dcSVikram Hegde private->idp_devfn = (dev << 3) | func; 175286c1f4dcSVikram Hegde private->idp_sec = 0; 175386c1f4dcSVikram Hegde private->idp_sub = 0; 175486c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_NONE; 175586c1f4dcSVikram Hegde /* record the bridge */ 175686c1f4dcSVikram Hegde private->idp_is_bridge = ((basecl == PCI_CLASS_BRIDGE) && 175786c1f4dcSVikram Hegde (subcl == PCI_BRIDGE_PCI)); 175886c1f4dcSVikram Hegde if (private->idp_is_bridge) { 175986c1f4dcSVikram Hegde private->idp_sec = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 176086c1f4dcSVikram Hegde private->idp_sub = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 176186c1f4dcSVikram Hegde if (pciex && is_pci_bridge) 176286c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCIE_PCI; 176386c1f4dcSVikram Hegde else if (pciex) 176486c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCIE_PCIE; 176586c1f4dcSVikram Hegde else 176686c1f4dcSVikram Hegde private->idp_bbp_type = IOMMU_PPB_PCI_PCI; 176786c1f4dcSVikram Hegde } 176886c1f4dcSVikram Hegde /* record the special devices */ 176986c1f4dcSVikram Hegde private->idp_is_display = (is_display(classcode) ? B_TRUE : B_FALSE); 177086c1f4dcSVikram Hegde private->idp_is_lpc = ((basecl == PCI_CLASS_BRIDGE) && 177186c1f4dcSVikram Hegde (subcl == PCI_BRIDGE_ISA)); 177294f1124eSVikram Hegde private->idp_intel_domain = NULL; 177386c1f4dcSVikram Hegde /* hook the private to dip */ 177486c1f4dcSVikram Hegde DEVI(dip)->devi_iommu_private = private; 177586c1f4dcSVikram Hegde 177694f1124eSVikram Hegde if (private->idp_is_display == B_TRUE) { 177794f1124eSVikram Hegde gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 177894f1124eSVikram Hegde gfxp->g_dip = dip; 177994f1124eSVikram Hegde gfxp->g_prev = NULL; 178094f1124eSVikram Hegde gfxp->g_next = gfx_devinfo_list; 178194f1124eSVikram Hegde gfx_devinfo_list = gfxp; 178294f1124eSVikram Hegde if (gfxp->g_next) 178394f1124eSVikram Hegde gfxp->g_next->g_prev = gfxp; 178494f1124eSVikram Hegde } 178594f1124eSVikram Hegde 178678323854SJudy Chen /* special handling for isa */ 178778323854SJudy Chen if (!pseudo_isa && is_isa(basecl, subcl)) { 178878323854SJudy Chen /* add device_type */ 178978323854SJudy Chen (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 179078323854SJudy Chen "device_type", "isa"); 179178323854SJudy Chen } 179278323854SJudy Chen 179305f867c3Sgs if (reprogram && (entry != NULL)) 179405f867c3Sgs entry->reprogram = B_TRUE; 17957c478bd9Sstevel@tonic-gate } 17967c478bd9Sstevel@tonic-gate 1797c2de8625SScott Carter, SD IOSW /* 1798c2de8625SScott Carter, SD IOSW * Some vendors do not use unique subsystem IDs in their products, which 1799c2de8625SScott Carter, SD IOSW * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 1800c2de8625SScott Carter, SD IOSW * Allow for these compatible forms to be excluded on a per-device basis. 1801c2de8625SScott Carter, SD IOSW */ 1802c2de8625SScott Carter, SD IOSW /*ARGSUSED*/ 1803c2de8625SScott Carter, SD IOSW static boolean_t 1804c2de8625SScott Carter, SD IOSW subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 1805c2de8625SScott Carter, SD IOSW ushort_t subdevid, uchar_t revid, uint_t classcode) 1806c2de8625SScott Carter, SD IOSW { 1807c2de8625SScott Carter, SD IOSW /* Nvidia display adapters */ 1808c2de8625SScott Carter, SD IOSW if ((venid == 0x10de) && (is_display(classcode))) 1809c2de8625SScott Carter, SD IOSW return (B_TRUE); 1810c2de8625SScott Carter, SD IOSW 1811c2de8625SScott Carter, SD IOSW return (B_FALSE); 1812c2de8625SScott Carter, SD IOSW } 1813c2de8625SScott Carter, SD IOSW 18147c478bd9Sstevel@tonic-gate /* 18157c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 18167c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 181770025d76Sjohnny * (Also used for PCI-Express devices). 18187c478bd9Sstevel@tonic-gate * 18197c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 18207c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 18217c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 18227c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 18237c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 18247c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 18257c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 18267c478bd9Sstevel@tonic-gate * 18277c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 18287c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 18297c478bd9Sstevel@tonic-gate * 183070025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 183170025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 183270025d76Sjohnny * 18337c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 18347c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 18357c478bd9Sstevel@tonic-gate */ 18367c478bd9Sstevel@tonic-gate void 18377c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 183870025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 183970025d76Sjohnny int pciex) 18407c478bd9Sstevel@tonic-gate { 184170025d76Sjohnny int i = 0; 184270025d76Sjohnny int size = COMPAT_BUFSIZE; 184370025d76Sjohnny char *compat[13]; 18447c478bd9Sstevel@tonic-gate char *buf, *curr; 18457c478bd9Sstevel@tonic-gate 18467c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 18477c478bd9Sstevel@tonic-gate 184870025d76Sjohnny if (pciex) { 184970025d76Sjohnny if (subvenid) { 185070025d76Sjohnny compat[i++] = curr; /* form 0 */ 185170025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 185270025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 185370025d76Sjohnny size -= strlen(curr) + 1; 185470025d76Sjohnny curr += strlen(curr) + 1; 185570025d76Sjohnny 185670025d76Sjohnny compat[i++] = curr; /* form 1 */ 185770025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 185870025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 185970025d76Sjohnny size -= strlen(curr) + 1; 186070025d76Sjohnny curr += strlen(curr) + 1; 186170025d76Sjohnny 186270025d76Sjohnny } 186370025d76Sjohnny compat[i++] = curr; /* form 3 */ 186470025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 186570025d76Sjohnny vendorid, deviceid, revid); 186670025d76Sjohnny size -= strlen(curr) + 1; 186770025d76Sjohnny curr += strlen(curr) + 1; 186870025d76Sjohnny 186970025d76Sjohnny compat[i++] = curr; /* form 4 */ 187070025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 187170025d76Sjohnny size -= strlen(curr) + 1; 187270025d76Sjohnny curr += strlen(curr) + 1; 187370025d76Sjohnny 187470025d76Sjohnny compat[i++] = curr; /* form 5 */ 187570025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 187670025d76Sjohnny size -= strlen(curr) + 1; 187770025d76Sjohnny curr += strlen(curr) + 1; 187870025d76Sjohnny 187970025d76Sjohnny compat[i++] = curr; /* form 6 */ 188070025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 188170025d76Sjohnny (classcode >> 8)); 188270025d76Sjohnny size -= strlen(curr) + 1; 188370025d76Sjohnny curr += strlen(curr) + 1; 188470025d76Sjohnny } 188570025d76Sjohnny 18867c478bd9Sstevel@tonic-gate if (subvenid) { 18877c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 18887c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 18897c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 18907c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18917c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18927c478bd9Sstevel@tonic-gate 18937c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 18947c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 18957c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 18967c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 18977c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 18987c478bd9Sstevel@tonic-gate 1899c2de8625SScott Carter, SD IOSW if (subsys_compat_exclude(vendorid, deviceid, subvenid, 1900c2de8625SScott Carter, SD IOSW subdevid, revid, classcode) == B_FALSE) { 1901c2de8625SScott Carter, SD IOSW compat[i++] = curr; /* form 2 */ 1902c2de8625SScott Carter, SD IOSW (void) snprintf(curr, size, "pci%x,%x", subvenid, 1903c2de8625SScott Carter, SD IOSW subdevid); 1904c2de8625SScott Carter, SD IOSW size -= strlen(curr) + 1; 1905c2de8625SScott Carter, SD IOSW curr += strlen(curr) + 1; 1906c2de8625SScott Carter, SD IOSW } 19077c478bd9Sstevel@tonic-gate } 19087c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 19097c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 19107c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 19117c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 19127c478bd9Sstevel@tonic-gate 19137c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 19147c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 19157c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 19167c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 19177c478bd9Sstevel@tonic-gate 19187c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 19197c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 19207c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 19217c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 19227c478bd9Sstevel@tonic-gate 19237c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 19247c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 192570025d76Sjohnny size -= strlen(curr) + 1; 192670025d76Sjohnny curr += strlen(curr) + 1; 19277c478bd9Sstevel@tonic-gate 19287c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 19297c478bd9Sstevel@tonic-gate "compatible", compat, i); 19307c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 19317c478bd9Sstevel@tonic-gate } 19327c478bd9Sstevel@tonic-gate 19337c478bd9Sstevel@tonic-gate /* 19347c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 19357c478bd9Sstevel@tonic-gate * 19367c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 19377c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 19387c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 19397c478bd9Sstevel@tonic-gate * mode BAR or not. 19407c478bd9Sstevel@tonic-gate */ 19417c478bd9Sstevel@tonic-gate /* 19427c478bd9Sstevel@tonic-gate * config info for pci-ide devices 19437c478bd9Sstevel@tonic-gate */ 19447c478bd9Sstevel@tonic-gate static struct { 19457c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 19467c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 19477c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 19487c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 19497c478bd9Sstevel@tonic-gate } pciide_bar[] = { 19507c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 19517c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 19527c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 19537c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 19547c478bd9Sstevel@tonic-gate }; 19557c478bd9Sstevel@tonic-gate 19567c478bd9Sstevel@tonic-gate static int 19577c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 19587c478bd9Sstevel@tonic-gate { 19597c478bd9Sstevel@tonic-gate int hard_decode = 0; 19607c478bd9Sstevel@tonic-gate 19617c478bd9Sstevel@tonic-gate /* 19627c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 19637c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 19647c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 19657c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 19667c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 19677c478bd9Sstevel@tonic-gate */ 19687c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 19697c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 19707c478bd9Sstevel@tonic-gate 19717c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 19727c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 19737c478bd9Sstevel@tonic-gate } else { 19747c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 19757c478bd9Sstevel@tonic-gate hard_decode = 1; 19767c478bd9Sstevel@tonic-gate } 19777c478bd9Sstevel@tonic-gate } 19787c478bd9Sstevel@tonic-gate 19797c478bd9Sstevel@tonic-gate /* 19807c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 19817c478bd9Sstevel@tonic-gate */ 19827c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 19837c478bd9Sstevel@tonic-gate *basep = 0; 19847c478bd9Sstevel@tonic-gate *lenp = 0; 19857c478bd9Sstevel@tonic-gate hard_decode = 0; 19867c478bd9Sstevel@tonic-gate } 19877c478bd9Sstevel@tonic-gate 19887c478bd9Sstevel@tonic-gate return (hard_decode); 19897c478bd9Sstevel@tonic-gate } 19907c478bd9Sstevel@tonic-gate 19917c478bd9Sstevel@tonic-gate 19927c478bd9Sstevel@tonic-gate /* 19937c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 19947c478bd9Sstevel@tonic-gate */ 19957c478bd9Sstevel@tonic-gate static int 19967c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 19977c478bd9Sstevel@tonic-gate int config_op, int pciide) 19987c478bd9Sstevel@tonic-gate { 19997c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 20007c478bd9Sstevel@tonic-gate ushort_t bar_sz; 20017c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 20027c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 20037c478bd9Sstevel@tonic-gate ushort_t offset, end; 20047c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 20057c478bd9Sstevel@tonic-gate uint_t phys_hi; 2006*2f283da5SDan Mick struct memlist **io_avail, **io_used; 2007*2f283da5SDan Mick struct memlist **mem_avail, **mem_used; 2008*2f283da5SDan Mick struct memlist **pmem_avail, **pmem_used; 200905f867c3Sgs uchar_t res_bus; 20107c478bd9Sstevel@tonic-gate 20117c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 20127c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 2013c8711d4dSgs int nreg, nasgn; 20147c478bd9Sstevel@tonic-gate 2015*2f283da5SDan Mick io_avail = &pci_bus_res[bus].io_avail; 2016*2f283da5SDan Mick io_used = &pci_bus_res[bus].io_used; 2017*2f283da5SDan Mick mem_avail = &pci_bus_res[bus].mem_avail; 2018*2f283da5SDan Mick mem_used = &pci_bus_res[bus].mem_used; 2019*2f283da5SDan Mick pmem_avail = &pci_bus_res[bus].pmem_avail; 2020*2f283da5SDan Mick pmem_used = &pci_bus_res[bus].pmem_used; 20217c478bd9Sstevel@tonic-gate 20227c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 20237c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 20247c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 20257c478bd9Sstevel@tonic-gate nasgn = 0; 20267c478bd9Sstevel@tonic-gate 20277c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 20287c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 20297c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 20307c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 20317c478bd9Sstevel@tonic-gate 20327c478bd9Sstevel@tonic-gate switch (header) { 20337c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 20347c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 20357c478bd9Sstevel@tonic-gate break; 20367c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 20377c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 20387c478bd9Sstevel@tonic-gate break; 20397c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 20407c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 2041ffa17327SGuoli Shu reprogram = 1; 20427c478bd9Sstevel@tonic-gate break; 20437c478bd9Sstevel@tonic-gate default: 20447c478bd9Sstevel@tonic-gate max_basereg = 0; 20457c478bd9Sstevel@tonic-gate break; 20467c478bd9Sstevel@tonic-gate } 20477c478bd9Sstevel@tonic-gate 20487c478bd9Sstevel@tonic-gate /* 20497c478bd9Sstevel@tonic-gate * Create the register property by saving the current 20508d34f104Smyers * value of the base register. Write 0xffffffff to the 20518d34f104Smyers * base register. Read the value back to determine the 20528d34f104Smyers * required size of the address space. Restore the base 20538d34f104Smyers * register contents. 20548d34f104Smyers * 20558d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 20568d34f104Smyers * since no driver is yet attached to this device, and disabling 20578d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 20588d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 20598d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 20608d34f104Smyers * Spec V1.2). 20617c478bd9Sstevel@tonic-gate */ 20627c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 20637c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 20647c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 20657c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 20667c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 20677c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 20687c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 20697c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 20707c478bd9Sstevel@tonic-gate 20717c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 20727c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 20733e98767bSMax zhen int hard_decode = 0; 20743e98767bSMax zhen 20757c478bd9Sstevel@tonic-gate /* i/o space */ 20767c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 20777c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 20787c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 20797c478bd9Sstevel@tonic-gate 20807c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 20817c478bd9Sstevel@tonic-gate if (pciide) { 2082f088817aSyt if (subclass != PCI_MASS_IDE) 20837c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 20847c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 20857c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 20867c478bd9Sstevel@tonic-gate &base, &len); 20877c478bd9Sstevel@tonic-gate } else if (value == 0) { 20887c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 20897c478bd9Sstevel@tonic-gate continue; 20907c478bd9Sstevel@tonic-gate } 20917c478bd9Sstevel@tonic-gate 20923e98767bSMax zhen regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 20933e98767bSMax zhen (hard_decode ? PCI_RELOCAT_B : offset); 20943e98767bSMax zhen regs[nreg].pci_phys_low = hard_decode ? 20953e98767bSMax zhen base & PCI_BASE_IO_ADDR_M : 0; 20963e98767bSMax zhen assigned[nasgn].pci_phys_hi = 20973e98767bSMax zhen PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 20987c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 20997c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 21007c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 21017c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 210205f867c3Sgs /* 210305f867c3Sgs * A device under a subtractive PPB can allocate 210405f867c3Sgs * resources from its parent bus if there is no resource 210505f867c3Sgs * available on its own bus. 210605f867c3Sgs */ 2107*2f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 210805f867c3Sgs res_bus = bus; 210905f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 211005f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 211105f867c3Sgs if (res_bus == (uchar_t)-1) 211205f867c3Sgs break; /* root bus already */ 2113*2f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 2114*2f283da5SDan Mick io_avail = &pci_bus_res 2115*2f283da5SDan Mick [res_bus].io_avail; 211605f867c3Sgs break; 211705f867c3Sgs } 211805f867c3Sgs } 211905f867c3Sgs } 21207c478bd9Sstevel@tonic-gate 21217c478bd9Sstevel@tonic-gate /* 21227c478bd9Sstevel@tonic-gate * first pass - gather what's there 21237c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 21247c478bd9Sstevel@tonic-gate * config - allocate regions 21257c478bd9Sstevel@tonic-gate */ 21267c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 21277c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 212805f867c3Sgs if (base != 0) { 2129*2f283da5SDan Mick (void) memlist_remove(io_avail, base, 21308fc7923fSDana Myers len); 2131*2f283da5SDan Mick memlist_insert(io_used, base, len); 2132ffa17327SGuoli Shu } else { 21337c478bd9Sstevel@tonic-gate reprogram = 1; 2134ffa17327SGuoli Shu } 2135ffa17327SGuoli Shu pci_bus_res[bus].io_size += len; 2136*2f283da5SDan Mick } else if ((*io_avail && base == 0) || 213705f867c3Sgs pci_bus_res[bus].io_reprogram) { 2138*2f283da5SDan Mick base = (uint_t)memlist_find(io_avail, len, len); 21397c478bd9Sstevel@tonic-gate if (base != 0) { 2140*2f283da5SDan Mick memlist_insert(io_used, base, len); 21417c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 21427c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 21437c478bd9Sstevel@tonic-gate base | type); 21447c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 21457c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 21467c478bd9Sstevel@tonic-gate } 21477c478bd9Sstevel@tonic-gate if (base == 0) { 21487c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 2149db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 2150db063408Sdmick " length 0x%x", 2151ebf3afa8Sdmick bus, dev, func, offset, len); 2152c8711d4dSgs } 21537c478bd9Sstevel@tonic-gate } 21547c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 21557c478bd9Sstevel@tonic-gate nreg++, nasgn++; 21567c478bd9Sstevel@tonic-gate 21577c478bd9Sstevel@tonic-gate } else { 21587c478bd9Sstevel@tonic-gate /* memory space */ 21597c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 21607c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 21617c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 21627c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 21637c478bd9Sstevel@tonic-gate } else { 21647c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 21657c478bd9Sstevel@tonic-gate base_hi = 0; 21667c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 21677c478bd9Sstevel@tonic-gate } 21687c478bd9Sstevel@tonic-gate 21697c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 21707c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 21717c478bd9Sstevel@tonic-gate 21728fc7923fSDana Myers if (value == 0) 21737c478bd9Sstevel@tonic-gate continue; 21748fc7923fSDana Myers 21757c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 21767c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 21777c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 21787c478bd9Sstevel@tonic-gate 21797c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 21808fc7923fSDana Myers if (base & PCI_BASE_PREF_M) 21817c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 21828fc7923fSDana Myers 218305f867c3Sgs /* 218405f867c3Sgs * A device under a subtractive PPB can allocate 218505f867c3Sgs * resources from its parent bus if there is no resource 218605f867c3Sgs * available on its own bus. 218705f867c3Sgs */ 2188*2f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 218905f867c3Sgs res_bus = bus; 219005f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 219105f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 219205f867c3Sgs if (res_bus == (uchar_t)-1) 219305f867c3Sgs break; /* root bus already */ 2194*2f283da5SDan Mick mem_avail = 2195*2f283da5SDan Mick &pci_bus_res[res_bus].mem_avail; 2196*2f283da5SDan Mick pmem_avail = 2197*2f283da5SDan Mick &pci_bus_res [res_bus].pmem_avail; 21988fc7923fSDana Myers /* 21998fc7923fSDana Myers * Break out as long as at least 2200*2f283da5SDan Mick * mem_avail is available 22018fc7923fSDana Myers */ 2202*2f283da5SDan Mick if ((*pmem_avail && 22038fc7923fSDana Myers (phys_hi & PCI_PREFETCH_B)) || 2204*2f283da5SDan Mick *mem_avail) 220505f867c3Sgs break; 220605f867c3Sgs } 220705f867c3Sgs } 220805f867c3Sgs 22097c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 22107c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 22117c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 22127c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 22137c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 22147c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 22157c478bd9Sstevel@tonic-gate 22167c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 22177c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 22188fc7923fSDana Myers if (base != NULL) { 22198fc7923fSDana Myers /* remove from PMEM and MEM space */ 2220*2f283da5SDan Mick (void) memlist_remove(mem_avail, 22218fc7923fSDana Myers base, len); 2222*2f283da5SDan Mick (void) memlist_remove(pmem_avail, 22238fc7923fSDana Myers base, len); 22248fc7923fSDana Myers /* only note as used in correct map */ 22258fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) 2226*2f283da5SDan Mick memlist_insert(pmem_used, 222705f867c3Sgs base, len); 22288fc7923fSDana Myers else 2229*2f283da5SDan Mick memlist_insert(mem_used, 223086ce93f0SGuoli Shu base, len); 2231ffa17327SGuoli Shu } else { 22327c478bd9Sstevel@tonic-gate reprogram = 1; 2233ffa17327SGuoli Shu } 2234ffa17327SGuoli Shu pci_bus_res[bus].mem_size += len; 2235*2f283da5SDan Mick } else if ((*mem_avail && base == NULL) || 223605f867c3Sgs pci_bus_res[bus].mem_reprogram) { 22378fc7923fSDana Myers /* 22388fc7923fSDana Myers * When desired, attempt a prefetchable 22398fc7923fSDana Myers * allocation first 22408fc7923fSDana Myers */ 22418fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) { 2242*2f283da5SDan Mick base = (uint_t)memlist_find(pmem_avail, 22438fc7923fSDana Myers len, len); 22448fc7923fSDana Myers if (base != NULL) { 2245*2f283da5SDan Mick memlist_insert(pmem_used, 22468fc7923fSDana Myers base, len); 2247*2f283da5SDan Mick (void) memlist_remove(mem_avail, 224886ce93f0SGuoli Shu base, len); 22498fc7923fSDana Myers } 22508fc7923fSDana Myers } 22518fc7923fSDana Myers /* 22528fc7923fSDana Myers * If prefetchable allocation was not 22538fc7923fSDana Myers * desired, or failed, attempt ordinary 22548fc7923fSDana Myers * memory allocation 22558fc7923fSDana Myers */ 22568fc7923fSDana Myers if (base == NULL) { 2257*2f283da5SDan Mick base = (uint_t)memlist_find(mem_avail, 22588fc7923fSDana Myers len, len); 22598fc7923fSDana Myers if (base != NULL) { 2260*2f283da5SDan Mick memlist_insert(mem_used, 226186ce93f0SGuoli Shu base, len); 2262*2f283da5SDan Mick (void) memlist_remove( 2263*2f283da5SDan Mick pmem_avail, base, len); 226486ce93f0SGuoli Shu } 22658fc7923fSDana Myers } 22668fc7923fSDana Myers if (base != NULL) { 22677c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 22687c478bd9Sstevel@tonic-gate base | type); 22697c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 22707c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 22718fc7923fSDana Myers } else 22727c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 2273ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 2274db063408Sdmick " length 0x%x", 2275ebf3afa8Sdmick bus, dev, func, offset, len); 22767c478bd9Sstevel@tonic-gate } 22777c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 22787c478bd9Sstevel@tonic-gate nreg++, nasgn++; 22797c478bd9Sstevel@tonic-gate } 22807c478bd9Sstevel@tonic-gate } 22817c478bd9Sstevel@tonic-gate switch (header) { 22827c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 22837c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 22847c478bd9Sstevel@tonic-gate break; 22857c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 22867c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 22877c478bd9Sstevel@tonic-gate break; 22887c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 22897c478bd9Sstevel@tonic-gate goto done; 22907c478bd9Sstevel@tonic-gate } 22917c478bd9Sstevel@tonic-gate 22927c478bd9Sstevel@tonic-gate /* 22937c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 22947c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 22957c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 22967c478bd9Sstevel@tonic-gate */ 22977c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 22987c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 22997c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 23007c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 230170025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 230270025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 230370025d76Sjohnny else 230470025d76Sjohnny value = 0; 23057c478bd9Sstevel@tonic-gate 23067c478bd9Sstevel@tonic-gate if (value != 0) { 23077c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 23087c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 23097c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 23107c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 23117c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 23127c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 23137c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 23147c478bd9Sstevel@tonic-gate nreg++, nasgn++; 231599ed6083Sszhou /* take it out of the memory resource */ 23168fc7923fSDana Myers if (base != NULL) { 2317*2f283da5SDan Mick (void) memlist_remove(mem_avail, base, len); 2318*2f283da5SDan Mick memlist_insert(mem_used, base, len); 2319*2f283da5SDan Mick pci_bus_res[bus].mem_size += len; 23208fc7923fSDana Myers } 23217c478bd9Sstevel@tonic-gate } 23227c478bd9Sstevel@tonic-gate 23237c478bd9Sstevel@tonic-gate /* 23248fc7923fSDana Myers * Account for "legacy" (alias) video adapter resources 23257c478bd9Sstevel@tonic-gate */ 23267c478bd9Sstevel@tonic-gate 23277c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 23287c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 23297c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 23307c478bd9Sstevel@tonic-gate 23317c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 23327c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23337c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23347c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 23357c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 23367c478bd9Sstevel@tonic-gate nreg++, nasgn++; 2337*2f283da5SDan Mick (void) memlist_remove(io_avail, 0x3b0, 0xc); 2338*2f283da5SDan Mick memlist_insert(io_used, 0x3b0, 0xc); 2339*2f283da5SDan Mick pci_bus_res[bus].io_size += 0xc; 23407c478bd9Sstevel@tonic-gate 23417c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 23427c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23437c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23447c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 23457c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 23467c478bd9Sstevel@tonic-gate nreg++, nasgn++; 2347*2f283da5SDan Mick (void) memlist_remove(io_avail, 0x3c0, 0x20); 2348*2f283da5SDan Mick memlist_insert(io_used, 0x3c0, 0x20); 2349*2f283da5SDan Mick pci_bus_res[bus].io_size += 0x20; 23507c478bd9Sstevel@tonic-gate 23517c478bd9Sstevel@tonic-gate /* Video memory */ 23527c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23533e98767bSMax zhen (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 23547c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 23557c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 23567c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 23577c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 23587c478bd9Sstevel@tonic-gate nreg++, nasgn++; 23598fc7923fSDana Myers /* remove from MEM and PMEM space */ 2360*2f283da5SDan Mick (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 2361*2f283da5SDan Mick (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 2362*2f283da5SDan Mick memlist_insert(mem_used, 0xa0000, 0x20000); 2363*2f283da5SDan Mick pci_bus_res[bus].mem_size += 0x20000; 23647c478bd9Sstevel@tonic-gate } 23657c478bd9Sstevel@tonic-gate 23667c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 23677c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 23689896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 23699896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 23707c478bd9Sstevel@tonic-gate 23717c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 23727c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23737c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23747c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 23757c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 23767c478bd9Sstevel@tonic-gate nreg++, nasgn++; 2377*2f283da5SDan Mick (void) memlist_remove(io_avail, 0x2e8, 0x1); 2378*2f283da5SDan Mick memlist_insert(io_used, 0x2e8, 0x1); 2379*2f283da5SDan Mick pci_bus_res[bus].io_size += 0x1; 23807c478bd9Sstevel@tonic-gate 23817c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 23827c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 23837c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 23847c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 23857c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 23867c478bd9Sstevel@tonic-gate nreg++, nasgn++; 2387*2f283da5SDan Mick (void) memlist_remove(io_avail, 0x2ea, 0x6); 2388*2f283da5SDan Mick memlist_insert(io_used, 0x2ea, 0x6); 2389*2f283da5SDan Mick pci_bus_res[bus].io_size += 0x6; 23907c478bd9Sstevel@tonic-gate } 23917c478bd9Sstevel@tonic-gate 23927c478bd9Sstevel@tonic-gate done: 23937c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 23947c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 23957c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 23967c478bd9Sstevel@tonic-gate "assigned-addresses", 23977c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2398c8711d4dSgs 23997c478bd9Sstevel@tonic-gate return (reprogram); 24007c478bd9Sstevel@tonic-gate } 24017c478bd9Sstevel@tonic-gate 24027c478bd9Sstevel@tonic-gate static void 240370025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 240449fbdd30SErwin T Tsaur int pciex, ushort_t is_pci_bridge) 24057c478bd9Sstevel@tonic-gate { 240670025d76Sjohnny char *dev_type; 24077c478bd9Sstevel@tonic-gate int i; 24087c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 24097c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 24107c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 241105f867c3Sgs uchar_t progclass; 241205f867c3Sgs 2413f55ce205Sszhou ASSERT(secbus <= subbus); 24147c478bd9Sstevel@tonic-gate 241505f867c3Sgs /* 241605f867c3Sgs * Check if it's a subtractive PPB. 241705f867c3Sgs */ 241805f867c3Sgs progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 241905f867c3Sgs if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 242005f867c3Sgs pci_bus_res[secbus].subtractive = B_TRUE; 242105f867c3Sgs 2422f55ce205Sszhou /* 2423f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 2424f55ce205Sszhou * such mistakes here 2425f55ce205Sszhou */ 2426f55ce205Sszhou if (subbus > pci_bios_nbus) { 2427f55ce205Sszhou pci_bios_nbus = subbus; 2428f55ce205Sszhou alloc_res_array(); 2429f55ce205Sszhou } 2430f55ce205Sszhou 2431f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 24327c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 24337c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 24347c478bd9Sstevel@tonic-gate 243549fbdd30SErwin T Tsaur dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 243670025d76Sjohnny 24377c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 24387c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 243953273e82Ssethg /* 244053273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 244153273e82Ssethg * for peer busses because there is no other way of determining its 244253273e82Ssethg * subordinate bus number). 244353273e82Ssethg */ 24447c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 24457c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 244653273e82Ssethg /* 244753273e82Ssethg * Loop through subordinate busses, initializing their parent bus 244853273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 244953273e82Ssethg * fields may very well be further refined later, as child bridges 245053273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 245153273e82Ssethg * are not peer busses by changing their par_bus fields to anything 245253273e82Ssethg * other than -1.) 245353273e82Ssethg */ 24547c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 24557c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 24567c478bd9Sstevel@tonic-gate 24577c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 245870025d76Sjohnny "device_type", dev_type); 24597c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 24607c478bd9Sstevel@tonic-gate "#address-cells", 3); 24617c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 24627c478bd9Sstevel@tonic-gate "#size-cells", 2); 24637c478bd9Sstevel@tonic-gate 24647c478bd9Sstevel@tonic-gate /* 2465*2f283da5SDan Mick * Collect bridge window specifications, and use them to populate 2466*2f283da5SDan Mick * the "avail" resources for the bus. Not all of those resources will 2467*2f283da5SDan Mick * end up being available; this is done top-down, and so the initial 2468*2f283da5SDan Mick * collection of windows populates the 'ranges' property for the 2469*2f283da5SDan Mick * bus node. Later, as children are found, resources are removed from 2470*2f283da5SDan Mick * the 'avail' list, so that it becomes the freelist for 2471*2f283da5SDan Mick * this point in the tree. ranges may be set again after bridge 2472*2f283da5SDan Mick * reprogramming in fix_ppb_res(), in which case it's set from 2473*2f283da5SDan Mick * used + avail. 2474*2f283da5SDan Mick * 24757c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 24767c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 24777c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 24787c478bd9Sstevel@tonic-gate * prefetchable memory. 24797c478bd9Sstevel@tonic-gate */ 24809896aa55Sjveta 24819896aa55Sjveta /* 24829896aa55Sjveta * io range 248305f867c3Sgs * We determine i/o windows that are left unconfigured by BIOS 24849896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 24859896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 24869896aa55Sjveta * later passes by setting the base > limit 24879896aa55Sjveta */ 24889896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 24899896aa55Sjveta if (val & PCI_COMM_IO) { 24909896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 24919896aa55Sjveta io_range[0] = ((val & 0xf0) << 8); 24929896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 24939896aa55Sjveta io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 24949896aa55Sjveta } else { 24959896aa55Sjveta io_range[0] = 0x9fff; 24969896aa55Sjveta io_range[1] = 0x1000; 24979896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 24989896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 24999896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 25009896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 25019896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 25029896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 25039896aa55Sjveta } 25049896aa55Sjveta 25057c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 2506*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 25077c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 25087c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 2509*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 251005f867c3Sgs (uint64_t)io_range[0], 251105f867c3Sgs (uint64_t)(io_range[1] - io_range[0] + 1)); 2512*2f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 2513*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 25147c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 25157c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 25167c478bd9Sstevel@tonic-gate } 25177c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 25187c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 25192269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 25202269adc8Sszhou if ((val & 0xf) == 1 && 25212269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 25222269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 25232269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 25242269adc8Sszhou } 25257c478bd9Sstevel@tonic-gate } 25267c478bd9Sstevel@tonic-gate 25277c478bd9Sstevel@tonic-gate /* mem range */ 25287c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 25297c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 25307c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 25317c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 25327c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 2533*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 25347c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 25357c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2536*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 253705f867c3Sgs (uint64_t)mem_range[0], 253805f867c3Sgs (uint64_t)(mem_range[1] - mem_range[0] + 1)); 253986ce93f0SGuoli Shu /* remove from parent resource list */ 2540*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 25418fc7923fSDana Myers (uint64_t)mem_range[0], 25428fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 2543*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 25448fc7923fSDana Myers (uint64_t)mem_range[0], 25458fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 25467c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 25477c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 25487c478bd9Sstevel@tonic-gate } 25497c478bd9Sstevel@tonic-gate 25507c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 25517c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 25527c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 25537c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 25547c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 25557c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 2556*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].pmem_avail, 25577c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 25587c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2559*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].pmem_used, 256005f867c3Sgs (uint64_t)pmem_range[0], 256105f867c3Sgs (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 256286ce93f0SGuoli Shu /* remove from parent resource list */ 2563*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 25648fc7923fSDana Myers (uint64_t)pmem_range[0], 25658fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 2566*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 25678fc7923fSDana Myers (uint64_t)pmem_range[0], 25688fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 25697c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 25707c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 25712269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 25722269adc8Sszhou if ((val & 0xf) == 1 && 25732269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 25742269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 25752269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 25762269adc8Sszhou } 25777c478bd9Sstevel@tonic-gate } 25787c478bd9Sstevel@tonic-gate 2579*2f283da5SDan Mick /* 2580*2f283da5SDan Mick * Add VGA legacy resources to the bridge's pci_bus_res if it 2581*2f283da5SDan Mick * has VGA_ENABLE set. Note that we put them in 'avail', 2582*2f283da5SDan Mick * because that's used to populate the ranges prop; they'll be 2583*2f283da5SDan Mick * removed from there by the VGA device once it's found. Also, 2584*2f283da5SDan Mick * remove them from the parent's available list and note them as 2585*2f283da5SDan Mick * used in the parent. 2586*2f283da5SDan Mick */ 2587*2f283da5SDan Mick 2588*2f283da5SDan Mick if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 2589*2f283da5SDan Mick PCI_BCNF_BCNTRL_VGA_ENABLE) { 2590*2f283da5SDan Mick 2591*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 2592*2f283da5SDan Mick 2593*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 2594*2f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 2595*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 2596*2f283da5SDan Mick 0x3b0, 0xc); 2597*2f283da5SDan Mick } 2598*2f283da5SDan Mick 2599*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 2600*2f283da5SDan Mick 2601*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 2602*2f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 2603*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 2604*2f283da5SDan Mick 0x3c0, 0x20); 2605*2f283da5SDan Mick } 2606*2f283da5SDan Mick 2607*2f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 2608*2f283da5SDan Mick 0x20000); 2609*2f283da5SDan Mick 2610*2f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 2611*2f283da5SDan Mick if (pci_bus_res[bus].mem_avail != NULL) { 2612*2f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 2613*2f283da5SDan Mick 0xa0000, 0x20000); 2614*2f283da5SDan Mick } 2615*2f283da5SDan Mick } 26167c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 26178fc7923fSDana Myers add_ranges_prop(secbus, 1); 26187c478bd9Sstevel@tonic-gate } 26197c478bd9Sstevel@tonic-gate 262009f67678Sanish extern const struct pci_class_strings_s class_pci[]; 262109f67678Sanish extern int class_pci_items; 26227c478bd9Sstevel@tonic-gate 26237c478bd9Sstevel@tonic-gate static void 26247c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 26257c478bd9Sstevel@tonic-gate { 26267c478bd9Sstevel@tonic-gate const char *desc; 26277c478bd9Sstevel@tonic-gate int i; 26287c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 26297c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 26307c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 26317c478bd9Sstevel@tonic-gate 26327c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 26337c478bd9Sstevel@tonic-gate desc = "IDE controller"; 26347c478bd9Sstevel@tonic-gate } else { 26357c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 26367c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 26377c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 26387c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 263909f67678Sanish desc = class_pci[i].actual_desc; 26407c478bd9Sstevel@tonic-gate break; 26417c478bd9Sstevel@tonic-gate } 26427c478bd9Sstevel@tonic-gate } 264309f67678Sanish if (i == class_pci_items) 26447c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 26457c478bd9Sstevel@tonic-gate } 26467c478bd9Sstevel@tonic-gate 26477c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 26487c478bd9Sstevel@tonic-gate (char *)desc); 26497c478bd9Sstevel@tonic-gate } 26507c478bd9Sstevel@tonic-gate 26517c478bd9Sstevel@tonic-gate static void 26527c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 26537c478bd9Sstevel@tonic-gate { 26547c478bd9Sstevel@tonic-gate int bus_range[2]; 26557c478bd9Sstevel@tonic-gate 26567c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 26577c478bd9Sstevel@tonic-gate return; 26587c478bd9Sstevel@tonic-gate bus_range[0] = bus; 26597c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 26607c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 26617c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 26627c478bd9Sstevel@tonic-gate } 26637c478bd9Sstevel@tonic-gate 2664b1f176e8Sjg /* 2665b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 2666b1f176e8Sjg */ 2667b1f176e8Sjg static void 2668b1f176e8Sjg add_bus_slot_names_prop(int bus) 2669b1f176e8Sjg { 2670b1f176e8Sjg char slotprop[256]; 2671b1f176e8Sjg int len; 2672b1f176e8Sjg 2673d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 2674d57b3b3dSprasad /* simply return if the property is already defined */ 2675d57b3b3dSprasad if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2676d57b3b3dSprasad DDI_PROP_DONTPASS, "slot-names")) 2677d57b3b3dSprasad return; 2678d57b3b3dSprasad } 2679d57b3b3dSprasad 2680b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2681b1f176e8Sjg if (len > 0) { 268253273e82Ssethg /* 268353273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 268453273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 268553273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 268653273e82Ssethg * subordinate to any PCI-PCI bridge). 268753273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 268853273e82Ssethg * will remove it later. 268953273e82Ssethg */ 269053273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 269153273e82Ssethg pci_bus_res[bus].dip == NULL) { 269253273e82Ssethg 2693b1f176e8Sjg create_root_bus_dip(bus); 269453273e82Ssethg } 269553273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 269653273e82Ssethg ASSERT((len % sizeof (int)) == 0); 269753273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 269853273e82Ssethg pci_bus_res[bus].dip, "slot-names", 269953273e82Ssethg (int *)slotprop, len / sizeof (int)); 270053273e82Ssethg } else { 270153273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 270253273e82Ssethg "IRQ routing table; Not adding slot-names " 270353273e82Ssethg "property for incorrect bus %d", bus); 270453273e82Ssethg } 2705b1f176e8Sjg } 2706b1f176e8Sjg } 2707b1f176e8Sjg 27088fc7923fSDana Myers /* 27098fc7923fSDana Myers * Handle both PCI root and PCI-PCI bridge range properties; 27108fc7923fSDana Myers * non-zero 'ppb' argument select PCI-PCI bridges versus root. 27118fc7923fSDana Myers */ 27128fc7923fSDana Myers static void 27138fc7923fSDana Myers memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 27147c478bd9Sstevel@tonic-gate { 27158fc7923fSDana Myers ppb_ranges_t *ppb_rp = *rp; 27168fc7923fSDana Myers pci_ranges_t *pci_rp = *rp; 27178fc7923fSDana Myers 27188fc7923fSDana Myers while (entry != NULL) { 27198fc7923fSDana Myers if (ppb) { 27208fc7923fSDana Myers ppb_rp->child_high = ppb_rp->parent_high = type; 27218fc7923fSDana Myers ppb_rp->child_mid = ppb_rp->parent_mid = 27228fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 27238fc7923fSDana Myers ppb_rp->child_low = ppb_rp->parent_low = 27248fc7923fSDana Myers (uint32_t)entry->address; 27258fc7923fSDana Myers ppb_rp->size_high = 27268fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 27278fc7923fSDana Myers ppb_rp->size_low = (uint32_t)entry->size; 27288fc7923fSDana Myers *rp = ++ppb_rp; 27298fc7923fSDana Myers } else { 27308fc7923fSDana Myers pci_rp->child_high = type; 27318fc7923fSDana Myers pci_rp->child_mid = pci_rp->parent_high = 27328fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 27338fc7923fSDana Myers pci_rp->child_low = pci_rp->parent_low = 27348fc7923fSDana Myers (uint32_t)entry->address; 27358fc7923fSDana Myers pci_rp->size_high = 27368fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 27378fc7923fSDana Myers pci_rp->size_low = (uint32_t)entry->size; 27388fc7923fSDana Myers *rp = ++pci_rp; 27398fc7923fSDana Myers } 27408fc7923fSDana Myers entry = entry->next; 27418fc7923fSDana Myers } 27428fc7923fSDana Myers } 27437c478bd9Sstevel@tonic-gate 27448fc7923fSDana Myers static void 27458fc7923fSDana Myers add_ranges_prop(int bus, int ppb) 27468fc7923fSDana Myers { 27478fc7923fSDana Myers int total, alloc_size; 27488fc7923fSDana Myers void *rp, *next_rp; 2749*2f283da5SDan Mick struct memlist *iolist, *memlist, *pmemlist; 27508fc7923fSDana Myers 2751ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 2752ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 2753ec0c94e7SDana Myers return; 2754ec0c94e7SDana Myers 2755*2f283da5SDan Mick iolist = memlist = pmemlist = (struct memlist *)NULL; 2756*2f283da5SDan Mick 2757*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 2758*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, &iolist); 2759*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 2760*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 2761*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 2762*2f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 2763*2f283da5SDan Mick 2764*2f283da5SDan Mick total = memlist_count(iolist); 2765*2f283da5SDan Mick total += memlist_count(memlist); 2766*2f283da5SDan Mick total += memlist_count(pmemlist); 27678fc7923fSDana Myers 27688fc7923fSDana Myers /* no property is created if no ranges are present */ 27698fc7923fSDana Myers if (total == 0) 27708fc7923fSDana Myers return; 27718fc7923fSDana Myers 27728fc7923fSDana Myers alloc_size = total * 27738fc7923fSDana Myers (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 27748fc7923fSDana Myers 27758fc7923fSDana Myers next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 27768fc7923fSDana Myers 2777*2f283da5SDan Mick memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 2778*2f283da5SDan Mick memlist_to_ranges(&next_rp, memlist, 27798fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 2780*2f283da5SDan Mick memlist_to_ranges(&next_rp, pmemlist, 27818fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 27828fc7923fSDana Myers 27838fc7923fSDana Myers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 27848fc7923fSDana Myers "ranges", (int *)rp, alloc_size / sizeof (int)); 27858fc7923fSDana Myers 27868fc7923fSDana Myers kmem_free(rp, alloc_size); 2787*2f283da5SDan Mick memlist_free_all(&iolist); 2788*2f283da5SDan Mick memlist_free_all(&memlist); 2789*2f283da5SDan Mick memlist_free_all(&pmemlist); 27907c478bd9Sstevel@tonic-gate } 27917c478bd9Sstevel@tonic-gate 27927c478bd9Sstevel@tonic-gate static void 27938fc7923fSDana Myers memlist_remove_list(struct memlist **list, struct memlist *remove_list) 27947c478bd9Sstevel@tonic-gate { 27958fc7923fSDana Myers while (list && *list && remove_list) { 27968fc7923fSDana Myers (void) memlist_remove(list, remove_list->address, 27978fc7923fSDana Myers remove_list->size); 27988fc7923fSDana Myers remove_list = remove_list->next; 27998fc7923fSDana Myers } 28007c478bd9Sstevel@tonic-gate } 28017c478bd9Sstevel@tonic-gate 28027c478bd9Sstevel@tonic-gate static int 28037c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 28047c478bd9Sstevel@tonic-gate { 28057c478bd9Sstevel@tonic-gate int i = 0; 28067c478bd9Sstevel@tonic-gate 28077c478bd9Sstevel@tonic-gate while (list) { 28087c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 28097c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 28107c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 28117c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 28127c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 28137c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 28147c478bd9Sstevel@tonic-gate 28157c478bd9Sstevel@tonic-gate list = list->next; 28167c478bd9Sstevel@tonic-gate sp++, i++; 28177c478bd9Sstevel@tonic-gate } 28187c478bd9Sstevel@tonic-gate return (i); 28197c478bd9Sstevel@tonic-gate } 28207c478bd9Sstevel@tonic-gate 28217c478bd9Sstevel@tonic-gate static void 28227c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 28237c478bd9Sstevel@tonic-gate { 28247c478bd9Sstevel@tonic-gate int i, count; 28257c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 28267c478bd9Sstevel@tonic-gate 2827ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 2828ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 2829ec0c94e7SDana Myers return; 2830ec0c94e7SDana Myers 2831*2f283da5SDan Mick count = memlist_count(pci_bus_res[bus].io_avail) + 2832*2f283da5SDan Mick memlist_count(pci_bus_res[bus].mem_avail) + 2833*2f283da5SDan Mick memlist_count(pci_bus_res[bus].pmem_avail); 28347c478bd9Sstevel@tonic-gate 28357c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 28367c478bd9Sstevel@tonic-gate return; 28377c478bd9Sstevel@tonic-gate 28387c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 2839*2f283da5SDan Mick i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 28407c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 2841*2f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 28427c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 2843*2f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 28447c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 28457c478bd9Sstevel@tonic-gate ASSERT(i == count); 28467c478bd9Sstevel@tonic-gate 28477c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 28487c478bd9Sstevel@tonic-gate "available", (int *)sp, 28497c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 28507c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 28517c478bd9Sstevel@tonic-gate } 2852f55ce205Sszhou 2853f55ce205Sszhou static void 2854f55ce205Sszhou alloc_res_array(void) 2855f55ce205Sszhou { 2856f55ce205Sszhou static int array_max = 0; 2857f55ce205Sszhou int old_max; 2858f55ce205Sszhou void *old_res; 2859f55ce205Sszhou 2860f55ce205Sszhou if (array_max > pci_bios_nbus + 1) 2861f55ce205Sszhou return; /* array is big enough */ 2862f55ce205Sszhou 2863f55ce205Sszhou old_max = array_max; 2864f55ce205Sszhou old_res = pci_bus_res; 2865f55ce205Sszhou 2866f55ce205Sszhou if (array_max == 0) 2867f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 2868f55ce205Sszhou 2869f55ce205Sszhou while (array_max < pci_bios_nbus + 1) 2870f55ce205Sszhou array_max <<= 1; 2871f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 2872f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 2873f55ce205Sszhou 2874f55ce205Sszhou if (old_res) { /* copy content and free old array */ 2875f55ce205Sszhou bcopy(old_res, pci_bus_res, 2876f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 2877f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 2878f55ce205Sszhou } 2879f55ce205Sszhou } 2880c8589f13Ssethg 2881c8589f13Ssethg static void 2882c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 2883c8589f13Ssethg ushort_t deviceid) 2884c8589f13Ssethg { 2885c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 2886c8589f13Ssethg static int numioapics = 0; 2887c8589f13Ssethg dev_info_t *ioapic_node; 2888c8589f13Ssethg uint64_t physaddr; 2889c8589f13Ssethg uint32_t lobase, hibase = 0; 2890c8589f13Ssethg 2891c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 2892c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 2893c8589f13Ssethg 2894c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 2895c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 2896c8589f13Ssethg return; 2897c8589f13Ssethg 2898c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 2899c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 2900c8589f13Ssethg 2901c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 2902c8589f13Ssethg 2903c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 2904c8589f13Ssethg 2905c8589f13Ssethg /* 2906c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 2907c8589f13Ssethg */ 2908c8589f13Ssethg if (ioapicsnode == NULL) { 2909c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 2910c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 2911c8589f13Ssethg return; 2912c8589f13Ssethg } 2913c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 2914c8589f13Ssethg } 2915c8589f13Ssethg 2916c8589f13Ssethg /* 2917c8589f13Ssethg * Create a child node for this IOAPIC 2918c8589f13Ssethg */ 2919c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 2920c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 2921c8589f13Ssethg if (ioapic_node == NULL) { 2922c8589f13Ssethg return; 2923c8589f13Ssethg } 2924c8589f13Ssethg 2925c8589f13Ssethg /* Vendor and Device ID */ 2926c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2927c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 2928c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 2929c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 2930c8589f13Ssethg 2931c8589f13Ssethg /* device_type */ 2932c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 2933c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 2934c8589f13Ssethg 2935c8589f13Ssethg /* reg */ 2936c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 2937c8589f13Ssethg "reg", physaddr); 2938c8589f13Ssethg } 2939d57b3b3dSprasad 2940d57b3b3dSprasad /* 2941d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 2942d57b3b3dSprasad * information obtained from Slot Capabilities register. 2943d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 2944d57b3b3dSprasad * information in the PCI IRQ table. 2945d57b3b3dSprasad */ 2946d57b3b3dSprasad static void 2947d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 2948d57b3b3dSprasad { 2949d57b3b3dSprasad char slotprop[256]; 2950d57b3b3dSprasad int len; 2951d57b3b3dSprasad 2952d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 2953d57b3b3dSprasad 2954d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 2955d57b3b3dSprasad *(uint32_t *)slotprop = 1; 2956d57b3b3dSprasad len = 4; 2957d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 2958d57b3b3dSprasad slot_num); 2959d57b3b3dSprasad len += strlen(slotprop + len) + 1; 2960d57b3b3dSprasad len += len % 4; 2961d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 2962d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 2963d57b3b3dSprasad } 2964