17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 575bcd456Sjg * Common Development and Distribution License (the "License"). 675bcd456Sjg * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22ec0c94e7SDana Myers * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/stat.h> 28ffa17327SGuoli Shu #include <sys/sysmacros.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 307c478bd9Sstevel@tonic-gate #include <sys/pci.h> 317c478bd9Sstevel@tonic-gate #include <sys/pci_impl.h> 327c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 337c478bd9Sstevel@tonic-gate #include <sys/memlist.h> 347c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 3570025d76Sjohnny #include <io/pci/mps_table.h> 36c88420b3Sdmick #include <sys/pci_cfgspace.h> 37c88420b3Sdmick #include <sys/pci_cfgspace_impl.h> 38c88420b3Sdmick #include <sys/psw.h> 3909f67678Sanish #include "../../../../common/pci/pci_strings.h" 40c8589f13Ssethg #include <sys/apic.h> 418a5a0d1eSanish #include <io/pciex/pcie_nvidia.h> 425af4ae46Sjveta #include <io/hotplug/pciehpc/pciehpc_acpi.h> 4325145214Smyers #include <sys/acpi/acpi.h> 4425145214Smyers #include <sys/acpica.h> 4586c1f4dcSVikram Hegde #include <sys/intel_iommu.h> 4694f1124eSVikram Hegde #include <sys/iommulib.h> 47*00dfdf4aSDana Myers #include <sys/devcache.h> 487c478bd9Sstevel@tonic-gate 497c478bd9Sstevel@tonic-gate #define pci_getb (*pci_getb_func) 507c478bd9Sstevel@tonic-gate #define pci_getw (*pci_getw_func) 517c478bd9Sstevel@tonic-gate #define pci_getl (*pci_getl_func) 527c478bd9Sstevel@tonic-gate #define pci_putb (*pci_putb_func) 537c478bd9Sstevel@tonic-gate #define pci_putw (*pci_putw_func) 547c478bd9Sstevel@tonic-gate #define pci_putl (*pci_putl_func) 557c478bd9Sstevel@tonic-gate #define dcmn_err if (pci_boot_debug) cmn_err 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate #define CONFIG_INFO 0 587c478bd9Sstevel@tonic-gate #define CONFIG_UPDATE 1 597c478bd9Sstevel@tonic-gate #define CONFIG_NEW 2 60bd87be88Ssethg #define CONFIG_FIX 3 6170025d76Sjohnny #define COMPAT_BUFSIZE 512 627c478bd9Sstevel@tonic-gate 6305f867c3Sgs #define PPB_IO_ALIGNMENT 0x1000 /* 4K aligned */ 6405f867c3Sgs #define PPB_MEM_ALIGNMENT 0x100000 /* 1M aligned */ 65ffa17327SGuoli Shu /* round down to nearest power of two */ 66ffa17327SGuoli Shu #define P2LE(align) \ 67ffa17327SGuoli Shu { \ 68ffa17327SGuoli Shu int i = 0; \ 69ffa17327SGuoli Shu while (align >>= 1) \ 70ffa17327SGuoli Shu i ++; \ 71ffa17327SGuoli Shu align = 1 << i; \ 72ffa17327SGuoli Shu } \ 7305f867c3Sgs 742f283da5SDan Mick /* for is_vga and list_is_vga_only */ 752f283da5SDan Mick 762f283da5SDan Mick enum io_mem { 772f283da5SDan Mick IO, 782f283da5SDan Mick MEM 792f283da5SDan Mick }; 802f283da5SDan Mick 81bd87be88Ssethg /* See AMD-8111 Datasheet Rev 3.03, Page 149: */ 82bd87be88Ssethg #define LPC_IO_CONTROL_REG_1 0x40 83bd87be88Ssethg #define AMD8111_ENABLENMI (uint8_t)0x80 84bd87be88Ssethg #define DEVID_AMD8111_LPC 0x7468 85bd87be88Ssethg 86bd87be88Ssethg struct pci_fixundo { 87bd87be88Ssethg uint8_t bus; 88bd87be88Ssethg uint8_t dev; 89bd87be88Ssethg uint8_t fn; 90bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t); 91bd87be88Ssethg struct pci_fixundo *next; 92bd87be88Ssethg }; 93bd87be88Ssethg 9405f867c3Sgs struct pci_devfunc { 9505f867c3Sgs struct pci_devfunc *next; 9605f867c3Sgs dev_info_t *dip; 9705f867c3Sgs uchar_t dev; 9805f867c3Sgs uchar_t func; 9905f867c3Sgs boolean_t reprogram; /* this device needs to be reprogrammed */ 10005f867c3Sgs }; 10105f867c3Sgs 10278323854SJudy Chen extern int pseudo_isa; 1037c478bd9Sstevel@tonic-gate extern int pci_bios_nbus; 1047c478bd9Sstevel@tonic-gate static uchar_t max_dev_pci = 32; /* PCI standard */ 1057c478bd9Sstevel@tonic-gate int pci_boot_debug = 0; 1067c478bd9Sstevel@tonic-gate extern struct memlist *find_bus_res(int, int); 107bd87be88Ssethg static struct pci_fixundo *undolist = NULL; 10805f867c3Sgs static int num_root_bus = 0; /* count of root buses */ 1098fc7923fSDana Myers extern volatile int acpi_resource_discovery; 1107c478bd9Sstevel@tonic-gate 1117c478bd9Sstevel@tonic-gate /* 1127c478bd9Sstevel@tonic-gate * Module prototypes 1137c478bd9Sstevel@tonic-gate */ 1147c478bd9Sstevel@tonic-gate static void enumerate_bus_devs(uchar_t bus, int config_op); 1157c478bd9Sstevel@tonic-gate static void create_root_bus_dip(uchar_t bus); 11605f867c3Sgs static void process_devfunc(uchar_t, uchar_t, uchar_t, uchar_t, 1177c478bd9Sstevel@tonic-gate ushort_t, int); 1187c478bd9Sstevel@tonic-gate static void add_compatible(dev_info_t *, ushort_t, ushort_t, 11970025d76Sjohnny ushort_t, ushort_t, uchar_t, uint_t, int); 1207c478bd9Sstevel@tonic-gate static int add_reg_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, int); 12149fbdd30SErwin T Tsaur static void add_ppb_props(dev_info_t *, uchar_t, uchar_t, uchar_t, int, 12249fbdd30SErwin T Tsaur ushort_t); 1237c478bd9Sstevel@tonic-gate static void add_model_prop(dev_info_t *, uint_t); 1247c478bd9Sstevel@tonic-gate static void add_bus_range_prop(int); 125b1f176e8Sjg static void add_bus_slot_names_prop(int); 1268fc7923fSDana Myers static void add_ranges_prop(int, int); 1277c478bd9Sstevel@tonic-gate static void add_bus_available_prop(int); 12849fbdd30SErwin T Tsaur static int get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id); 12905f867c3Sgs static void fix_ppb_res(uchar_t, boolean_t); 130f55ce205Sszhou static void alloc_res_array(); 131c8589f13Ssethg static void create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 132c8589f13Ssethg ushort_t deviceid); 133d57b3b3dSprasad static void pciex_slot_names_prop(dev_info_t *, ushort_t); 1348fc7923fSDana Myers static void populate_bus_res(uchar_t bus); 1358fc7923fSDana Myers static void memlist_remove_list(struct memlist **list, 1368fc7923fSDana Myers struct memlist *remove_list); 1377c478bd9Sstevel@tonic-gate 138*00dfdf4aSDana Myers static void pci_scan_bbn(void); 139*00dfdf4aSDana Myers static int pci_unitaddr_cache_valid(void); 140*00dfdf4aSDana Myers static int pci_bus_unitaddr(int); 141*00dfdf4aSDana Myers static void pci_unitaddr_cache_create(void); 142*00dfdf4aSDana Myers 143*00dfdf4aSDana Myers static int pci_cache_unpack_nvlist(nvf_handle_t, nvlist_t *, char *); 144*00dfdf4aSDana Myers static int pci_cache_pack_nvlist(nvf_handle_t, nvlist_t **); 145*00dfdf4aSDana Myers static void pci_cache_free_list(nvf_handle_t); 146*00dfdf4aSDana Myers 14775bcd456Sjg extern int pci_slot_names_prop(int, char *, int); 14875bcd456Sjg 149ee8c1d4aSdm /* set non-zero to force PCI peer-bus renumbering */ 15025145214Smyers int pci_bus_always_renumber = 0; 15125145214Smyers 1521d6b7b34SJudy Chen /* 1531d6b7b34SJudy Chen * used to register ISA resource usage which must not be made 1541d6b7b34SJudy Chen * "available" from other PCI node' resource maps 1551d6b7b34SJudy Chen */ 1561d6b7b34SJudy Chen static struct { 1572f283da5SDan Mick struct memlist *io_used; 1582f283da5SDan Mick struct memlist *mem_used; 1591d6b7b34SJudy Chen } isa_res; 1601d6b7b34SJudy Chen 161*00dfdf4aSDana Myers /* 162*00dfdf4aSDana Myers * PCI unit-address cache management 163*00dfdf4aSDana Myers */ 164*00dfdf4aSDana Myers static nvf_ops_t pci_unitaddr_cache_ops = { 165*00dfdf4aSDana Myers "/etc/devices/pci_unitaddr_persistent", /* path to cache */ 166*00dfdf4aSDana Myers pci_cache_unpack_nvlist, /* read in nvlist form */ 167*00dfdf4aSDana Myers pci_cache_pack_nvlist, /* convert to nvlist form */ 168*00dfdf4aSDana Myers pci_cache_free_list, /* free data list */ 169*00dfdf4aSDana Myers NULL /* write complete callback */ 170*00dfdf4aSDana Myers }; 171*00dfdf4aSDana Myers 172*00dfdf4aSDana Myers typedef struct { 173*00dfdf4aSDana Myers list_node_t pua_nodes; 174*00dfdf4aSDana Myers int pua_index; 175*00dfdf4aSDana Myers int pua_addr; 176*00dfdf4aSDana Myers } pua_node_t; 177*00dfdf4aSDana Myers 178*00dfdf4aSDana Myers nvf_handle_t puafd_handle; 179*00dfdf4aSDana Myers int pua_cache_valid = 0; 180*00dfdf4aSDana Myers 181*00dfdf4aSDana Myers 182*00dfdf4aSDana Myers /*ARGSUSED*/ 183*00dfdf4aSDana Myers static ACPI_STATUS 184*00dfdf4aSDana Myers pci_process_acpi_device(ACPI_HANDLE hdl, UINT32 level, void *ctx, void **rv) 185*00dfdf4aSDana Myers { 186*00dfdf4aSDana Myers ACPI_BUFFER rb; 187*00dfdf4aSDana Myers ACPI_OBJECT ro; 188*00dfdf4aSDana Myers ACPI_DEVICE_INFO *adi; 189*00dfdf4aSDana Myers 190*00dfdf4aSDana Myers /* 191*00dfdf4aSDana Myers * Use AcpiGetObjectInfo() to find the device _HID 192*00dfdf4aSDana Myers * If not a PCI root-bus, ignore this device and continue 193*00dfdf4aSDana Myers * the walk 194*00dfdf4aSDana Myers */ 195*00dfdf4aSDana Myers 196*00dfdf4aSDana Myers rb.Length = ACPI_ALLOCATE_BUFFER; 197*00dfdf4aSDana Myers if (ACPI_FAILURE(AcpiGetObjectInfo(hdl, &rb))) 198*00dfdf4aSDana Myers return (AE_OK); 199*00dfdf4aSDana Myers 200*00dfdf4aSDana Myers adi = rb.Pointer; 201*00dfdf4aSDana Myers if (!(adi->Valid & ACPI_VALID_HID)) { 202*00dfdf4aSDana Myers AcpiOsFree(adi); 203*00dfdf4aSDana Myers return (AE_OK); 204*00dfdf4aSDana Myers } 205*00dfdf4aSDana Myers 206*00dfdf4aSDana Myers if (strncmp(adi->HardwareId.Value, PCI_ROOT_HID_STRING, 207*00dfdf4aSDana Myers sizeof (PCI_ROOT_HID_STRING)) && 208*00dfdf4aSDana Myers strncmp(adi->HardwareId.Value, PCI_EXPRESS_ROOT_HID_STRING, 209*00dfdf4aSDana Myers sizeof (PCI_EXPRESS_ROOT_HID_STRING))) { 210*00dfdf4aSDana Myers AcpiOsFree(adi); 211*00dfdf4aSDana Myers return (AE_OK); 212*00dfdf4aSDana Myers } 213*00dfdf4aSDana Myers 214*00dfdf4aSDana Myers AcpiOsFree(adi); 215*00dfdf4aSDana Myers 216*00dfdf4aSDana Myers /* 217*00dfdf4aSDana Myers * XXX: ancient Big Bear broken _BBN will result in two 218*00dfdf4aSDana Myers * bus 0 _BBNs being found, so we need to handle duplicate 219*00dfdf4aSDana Myers * bus 0 gracefully. However, broken _BBN does not 220*00dfdf4aSDana Myers * hide a childless root-bridge so no need to work-around it 221*00dfdf4aSDana Myers * here 222*00dfdf4aSDana Myers */ 223*00dfdf4aSDana Myers rb.Pointer = &ro; 224*00dfdf4aSDana Myers rb.Length = sizeof (ro); 225*00dfdf4aSDana Myers if (ACPI_SUCCESS(AcpiEvaluateObjectTyped(hdl, "_BBN", 226*00dfdf4aSDana Myers NULL, &rb, ACPI_TYPE_INTEGER))) { 227*00dfdf4aSDana Myers /* PCI with _BBN, process it, go no deeper */ 228*00dfdf4aSDana Myers if (pci_bus_res[ro.Integer.Value].par_bus == (uchar_t)-1 && 229*00dfdf4aSDana Myers pci_bus_res[ro.Integer.Value].dip == NULL) 230*00dfdf4aSDana Myers create_root_bus_dip((uchar_t)ro.Integer.Value); 231*00dfdf4aSDana Myers return (AE_CTRL_DEPTH); 232*00dfdf4aSDana Myers } 233*00dfdf4aSDana Myers 234*00dfdf4aSDana Myers /* PCI and no _BBN, continue walk */ 235*00dfdf4aSDana Myers return (AE_OK); 236*00dfdf4aSDana Myers } 237*00dfdf4aSDana Myers 238*00dfdf4aSDana Myers /* 239*00dfdf4aSDana Myers * Scan the ACPI namespace for all top-level instances of _BBN 240*00dfdf4aSDana Myers * in order to discover childless root-bridges (which enumeration 241*00dfdf4aSDana Myers * may not find; root-bridges are inferred by the existence of 242*00dfdf4aSDana Myers * children). This scan should find all root-bridges that have 243*00dfdf4aSDana Myers * been enumerated, and any childless root-bridges not enumerated. 244*00dfdf4aSDana Myers * Root-bridge for bus 0 may not have a _BBN object. 245*00dfdf4aSDana Myers */ 246*00dfdf4aSDana Myers static void 247*00dfdf4aSDana Myers pci_scan_bbn() 248*00dfdf4aSDana Myers { 249*00dfdf4aSDana Myers void *rv; 250*00dfdf4aSDana Myers 251*00dfdf4aSDana Myers (void) AcpiGetDevices(NULL, pci_process_acpi_device, NULL, &rv); 252*00dfdf4aSDana Myers } 253*00dfdf4aSDana Myers 254*00dfdf4aSDana Myers static void 255*00dfdf4aSDana Myers pci_unitaddr_cache_init(void) 256*00dfdf4aSDana Myers { 257*00dfdf4aSDana Myers 258*00dfdf4aSDana Myers puafd_handle = nvf_register_file(&pci_unitaddr_cache_ops); 259*00dfdf4aSDana Myers ASSERT(puafd_handle); 260*00dfdf4aSDana Myers 261*00dfdf4aSDana Myers list_create(nvf_list(puafd_handle), sizeof (pua_node_t), 262*00dfdf4aSDana Myers offsetof(pua_node_t, pua_nodes)); 263*00dfdf4aSDana Myers 264*00dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 265*00dfdf4aSDana Myers (void) nvf_read_file(puafd_handle); 266*00dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 267*00dfdf4aSDana Myers } 268*00dfdf4aSDana Myers 269*00dfdf4aSDana Myers /* 270*00dfdf4aSDana Myers * Format of /etc/devices/pci_unitaddr_persistent: 271*00dfdf4aSDana Myers * 272*00dfdf4aSDana Myers * The persistent record of unit-address assignments contains 273*00dfdf4aSDana Myers * a list of name/value pairs, where name is a string representation 274*00dfdf4aSDana Myers * of the "index value" of the PCI root-bus and the value is 275*00dfdf4aSDana Myers * the assigned unit-address. 276*00dfdf4aSDana Myers * 277*00dfdf4aSDana Myers * The "index value" is simply the zero-based index of the PCI 278*00dfdf4aSDana Myers * root-buses ordered by physical bus number; first PCI bus is 0, 279*00dfdf4aSDana Myers * second is 1, and so on. 280*00dfdf4aSDana Myers */ 281*00dfdf4aSDana Myers 282*00dfdf4aSDana Myers static int 283*00dfdf4aSDana Myers pci_cache_unpack_nvlist(nvf_handle_t hdl, nvlist_t *nvl, char *name) 284*00dfdf4aSDana Myers { 285*00dfdf4aSDana Myers long index; 286*00dfdf4aSDana Myers int32_t value; 287*00dfdf4aSDana Myers nvpair_t *np; 288*00dfdf4aSDana Myers pua_node_t *node; 289*00dfdf4aSDana Myers 290*00dfdf4aSDana Myers np = NULL; 291*00dfdf4aSDana Myers while ((np = nvlist_next_nvpair(nvl, np)) != NULL) { 292*00dfdf4aSDana Myers /* name of nvpair is index value */ 293*00dfdf4aSDana Myers if (ddi_strtol(nvpair_name(np), NULL, 10, &index) != 0) 294*00dfdf4aSDana Myers continue; 295*00dfdf4aSDana Myers 296*00dfdf4aSDana Myers if (nvpair_value_int32(np, &value) != 0) 297*00dfdf4aSDana Myers continue; 298*00dfdf4aSDana Myers 299*00dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 300*00dfdf4aSDana Myers node->pua_index = index; 301*00dfdf4aSDana Myers node->pua_addr = value; 302*00dfdf4aSDana Myers list_insert_tail(nvf_list(hdl), node); 303*00dfdf4aSDana Myers } 304*00dfdf4aSDana Myers 305*00dfdf4aSDana Myers pua_cache_valid = 1; 306*00dfdf4aSDana Myers return (DDI_SUCCESS); 307*00dfdf4aSDana Myers } 308*00dfdf4aSDana Myers 309*00dfdf4aSDana Myers static int 310*00dfdf4aSDana Myers pci_cache_pack_nvlist(nvf_handle_t hdl, nvlist_t **ret_nvl) 311*00dfdf4aSDana Myers { 312*00dfdf4aSDana Myers int rval; 313*00dfdf4aSDana Myers nvlist_t *nvl, *sub_nvl; 314*00dfdf4aSDana Myers list_t *listp; 315*00dfdf4aSDana Myers pua_node_t *pua; 316*00dfdf4aSDana Myers char buf[13]; 317*00dfdf4aSDana Myers 318*00dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 319*00dfdf4aSDana Myers 320*00dfdf4aSDana Myers rval = nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 321*00dfdf4aSDana Myers if (rval != DDI_SUCCESS) { 322*00dfdf4aSDana Myers nvf_error("%s: nvlist alloc error %d\n", 323*00dfdf4aSDana Myers nvf_cache_name(hdl), rval); 324*00dfdf4aSDana Myers return (DDI_FAILURE); 325*00dfdf4aSDana Myers } 326*00dfdf4aSDana Myers 327*00dfdf4aSDana Myers sub_nvl = NULL; 328*00dfdf4aSDana Myers rval = nvlist_alloc(&sub_nvl, NV_UNIQUE_NAME, KM_SLEEP); 329*00dfdf4aSDana Myers if (rval != DDI_SUCCESS) 330*00dfdf4aSDana Myers goto error; 331*00dfdf4aSDana Myers 332*00dfdf4aSDana Myers listp = nvf_list(hdl); 333*00dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 334*00dfdf4aSDana Myers pua = list_next(listp, pua)) { 335*00dfdf4aSDana Myers snprintf(buf, sizeof (buf), "%d", pua->pua_index); 336*00dfdf4aSDana Myers rval = nvlist_add_int32(sub_nvl, buf, pua->pua_addr); 337*00dfdf4aSDana Myers if (rval != DDI_SUCCESS) 338*00dfdf4aSDana Myers goto error; 339*00dfdf4aSDana Myers } 340*00dfdf4aSDana Myers 341*00dfdf4aSDana Myers rval = nvlist_add_nvlist(nvl, "table", sub_nvl); 342*00dfdf4aSDana Myers if (rval != DDI_SUCCESS) 343*00dfdf4aSDana Myers goto error; 344*00dfdf4aSDana Myers nvlist_free(sub_nvl); 345*00dfdf4aSDana Myers 346*00dfdf4aSDana Myers *ret_nvl = nvl; 347*00dfdf4aSDana Myers return (DDI_SUCCESS); 348*00dfdf4aSDana Myers 349*00dfdf4aSDana Myers error: 350*00dfdf4aSDana Myers if (sub_nvl) 351*00dfdf4aSDana Myers nvlist_free(sub_nvl); 352*00dfdf4aSDana Myers ASSERT(nvl); 353*00dfdf4aSDana Myers nvlist_free(nvl); 354*00dfdf4aSDana Myers *ret_nvl = NULL; 355*00dfdf4aSDana Myers return (DDI_FAILURE); 356*00dfdf4aSDana Myers } 357*00dfdf4aSDana Myers 358*00dfdf4aSDana Myers static void 359*00dfdf4aSDana Myers pci_cache_free_list(nvf_handle_t hdl) 360*00dfdf4aSDana Myers { 361*00dfdf4aSDana Myers list_t *listp; 362*00dfdf4aSDana Myers pua_node_t *pua; 363*00dfdf4aSDana Myers 364*00dfdf4aSDana Myers ASSERT(RW_WRITE_HELD(nvf_lock(hdl))); 365*00dfdf4aSDana Myers 366*00dfdf4aSDana Myers listp = nvf_list(hdl); 367*00dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 368*00dfdf4aSDana Myers pua = list_next(listp, pua)) { 369*00dfdf4aSDana Myers list_remove(listp, pua); 370*00dfdf4aSDana Myers kmem_free(pua, sizeof (pua_node_t)); 371*00dfdf4aSDana Myers } 372*00dfdf4aSDana Myers } 373*00dfdf4aSDana Myers 374*00dfdf4aSDana Myers 375*00dfdf4aSDana Myers static int 376*00dfdf4aSDana Myers pci_unitaddr_cache_valid(void) 377*00dfdf4aSDana Myers { 378*00dfdf4aSDana Myers 379*00dfdf4aSDana Myers /* read only, no need for rw lock */ 380*00dfdf4aSDana Myers return (pua_cache_valid); 381*00dfdf4aSDana Myers } 382*00dfdf4aSDana Myers 383*00dfdf4aSDana Myers 384*00dfdf4aSDana Myers static int 385*00dfdf4aSDana Myers pci_bus_unitaddr(int index) 386*00dfdf4aSDana Myers { 387*00dfdf4aSDana Myers pua_node_t *pua; 388*00dfdf4aSDana Myers list_t *listp; 389*00dfdf4aSDana Myers int addr; 390*00dfdf4aSDana Myers 391*00dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_READER); 392*00dfdf4aSDana Myers 393*00dfdf4aSDana Myers addr = -1; /* default return if no match */ 394*00dfdf4aSDana Myers listp = nvf_list(puafd_handle); 395*00dfdf4aSDana Myers for (pua = list_head(listp); pua != NULL; 396*00dfdf4aSDana Myers pua = list_next(listp, pua)) { 397*00dfdf4aSDana Myers if (pua->pua_index == index) { 398*00dfdf4aSDana Myers addr = pua->pua_addr; 399*00dfdf4aSDana Myers break; 400*00dfdf4aSDana Myers } 401*00dfdf4aSDana Myers } 402*00dfdf4aSDana Myers 403*00dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 404*00dfdf4aSDana Myers return (addr); 405*00dfdf4aSDana Myers } 406*00dfdf4aSDana Myers 407*00dfdf4aSDana Myers static void 408*00dfdf4aSDana Myers pci_unitaddr_cache_create(void) 409*00dfdf4aSDana Myers { 410*00dfdf4aSDana Myers int i, index; 411*00dfdf4aSDana Myers pua_node_t *node; 412*00dfdf4aSDana Myers list_t *listp; 413*00dfdf4aSDana Myers 414*00dfdf4aSDana Myers rw_enter(nvf_lock(puafd_handle), RW_WRITER); 415*00dfdf4aSDana Myers 416*00dfdf4aSDana Myers index = 0; 417*00dfdf4aSDana Myers listp = nvf_list(puafd_handle); 418*00dfdf4aSDana Myers for (i = 0; i <= pci_bios_nbus; i++) { 419*00dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 420*00dfdf4aSDana Myers if ((pci_bus_res[i].par_bus != (uchar_t)-1) || 421*00dfdf4aSDana Myers (pci_bus_res[i].dip == NULL)) 422*00dfdf4aSDana Myers continue; 423*00dfdf4aSDana Myers node = kmem_zalloc(sizeof (pua_node_t), KM_SLEEP); 424*00dfdf4aSDana Myers node->pua_index = index++; 425*00dfdf4aSDana Myers node->pua_addr = pci_bus_res[i].root_addr; 426*00dfdf4aSDana Myers list_insert_tail(listp, node); 427*00dfdf4aSDana Myers } 428*00dfdf4aSDana Myers 429*00dfdf4aSDana Myers (void) nvf_mark_dirty(puafd_handle); 430*00dfdf4aSDana Myers rw_exit(nvf_lock(puafd_handle)); 431*00dfdf4aSDana Myers nvf_wake_daemon(); 432*00dfdf4aSDana Myers } 433*00dfdf4aSDana Myers 434*00dfdf4aSDana Myers 4357c478bd9Sstevel@tonic-gate /* 4367c478bd9Sstevel@tonic-gate * Enumerate all PCI devices 4377c478bd9Sstevel@tonic-gate */ 4387c478bd9Sstevel@tonic-gate void 439*00dfdf4aSDana Myers pci_setup_tree(void) 4407c478bd9Sstevel@tonic-gate { 44105043691Sjames north - Sun Microsystems - Austin United States uint_t i, root_bus_addr = 0; 4427c478bd9Sstevel@tonic-gate 443f55ce205Sszhou alloc_res_array(); 4447c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 4457c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = (uchar_t)-1; 4467c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = (uchar_t)-1; 4477c478bd9Sstevel@tonic-gate pci_bus_res[i].sub_bus = i; 4487c478bd9Sstevel@tonic-gate } 4497c478bd9Sstevel@tonic-gate 4507c478bd9Sstevel@tonic-gate pci_bus_res[0].root_addr = root_bus_addr++; 4517c478bd9Sstevel@tonic-gate create_root_bus_dip(0); 4527c478bd9Sstevel@tonic-gate enumerate_bus_devs(0, CONFIG_INFO); 4537c478bd9Sstevel@tonic-gate 4547c478bd9Sstevel@tonic-gate /* 4557c478bd9Sstevel@tonic-gate * Now enumerate peer busses 4567c478bd9Sstevel@tonic-gate * 4577c478bd9Sstevel@tonic-gate * We loop till pci_bios_nbus. On most systems, there is 4587c478bd9Sstevel@tonic-gate * one more bus at the high end, which implements the ISA 4597c478bd9Sstevel@tonic-gate * compatibility bus. We don't care about that. 4607c478bd9Sstevel@tonic-gate * 4617c478bd9Sstevel@tonic-gate * Note: In the old (bootconf) enumeration, the peer bus 4627c478bd9Sstevel@tonic-gate * address did not use the bus number, and there were 4637c478bd9Sstevel@tonic-gate * too many peer busses created. The root_bus_addr is 4647c478bd9Sstevel@tonic-gate * used to maintain the old peer bus address assignment. 4657c478bd9Sstevel@tonic-gate * However, we stop enumerating phantom peers with no 4667c478bd9Sstevel@tonic-gate * device below. 4677c478bd9Sstevel@tonic-gate */ 4687c478bd9Sstevel@tonic-gate for (i = 1; i <= pci_bios_nbus; i++) { 4697c478bd9Sstevel@tonic-gate if (pci_bus_res[i].dip == NULL) { 4707c478bd9Sstevel@tonic-gate pci_bus_res[i].root_addr = root_bus_addr++; 4717c478bd9Sstevel@tonic-gate } 4727c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_INFO); 473b1f176e8Sjg 474b1f176e8Sjg /* add slot-names property for named pci hot-plug slots */ 475b1f176e8Sjg add_bus_slot_names_prop(i); 4767c478bd9Sstevel@tonic-gate } 4777c478bd9Sstevel@tonic-gate 4787c478bd9Sstevel@tonic-gate } 4797c478bd9Sstevel@tonic-gate 48025145214Smyers /* 48125145214Smyers * >0 = present, 0 = not present, <0 = error 48225145214Smyers */ 48325145214Smyers static int 48425145214Smyers pci_bbn_present(int bus) 48525145214Smyers { 48625145214Smyers ACPI_HANDLE hdl; 48725145214Smyers int rv; 48825145214Smyers 48925145214Smyers /* no dip means no _BBN */ 49025145214Smyers if (pci_bus_res[bus].dip == NULL) 49125145214Smyers return (0); 49225145214Smyers 493db2bae30SDana Myers rv = -1; /* default return value in case of error below */ 494db2bae30SDana Myers if (ACPI_SUCCESS(acpica_get_handle(pci_bus_res[bus].dip, &hdl))) { 495db2bae30SDana Myers switch (AcpiEvaluateObject(hdl, "_BBN", NULL, NULL)) { 496db2bae30SDana Myers case AE_OK: 497db2bae30SDana Myers rv = 1; 498db2bae30SDana Myers break; 499db2bae30SDana Myers case AE_NOT_FOUND: 500db2bae30SDana Myers rv = 0; 501db2bae30SDana Myers break; 502db2bae30SDana Myers default: 503db2bae30SDana Myers break; 504db2bae30SDana Myers } 505db2bae30SDana Myers } 50625145214Smyers 507db2bae30SDana Myers return (rv); 50825145214Smyers } 50925145214Smyers 51025145214Smyers /* 51125145214Smyers * Return non-zero if any PCI bus in the system has an associated 51225145214Smyers * _BBN object, 0 otherwise. 51325145214Smyers */ 51425145214Smyers static int 51525145214Smyers pci_roots_have_bbn(void) 51625145214Smyers { 51725145214Smyers int i; 51825145214Smyers 51925145214Smyers /* 52025145214Smyers * Scan the PCI busses and look for at least 1 _BBN 52125145214Smyers */ 52225145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 52325145214Smyers /* skip non-root (peer) PCI busses */ 52425145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 52525145214Smyers continue; 52625145214Smyers 52725145214Smyers if (pci_bbn_present(i) > 0) 52825145214Smyers return (1); 52925145214Smyers } 53025145214Smyers return (0); 53125145214Smyers 53225145214Smyers } 53325145214Smyers 53425145214Smyers /* 53525145214Smyers * return non-zero if the machine is one on which we renumber 53625145214Smyers * the internal pci unit-addresses 53725145214Smyers */ 53825145214Smyers static int 53925145214Smyers pci_bus_renumber() 54025145214Smyers { 541ee8c1d4aSdm ACPI_TABLE_HEADER *fadt; 54225145214Smyers 543ee8c1d4aSdm if (pci_bus_always_renumber) 54425145214Smyers return (1); 545ee8c1d4aSdm 546ee8c1d4aSdm /* get the FADT */ 547db2bae30SDana Myers if (AcpiGetTable(ACPI_SIG_FADT, 1, (ACPI_TABLE_HEADER **)&fadt) != 548db2bae30SDana Myers AE_OK) 54925145214Smyers return (0); 55025145214Smyers 551ee8c1d4aSdm /* compare OEM Table ID to "SUNm31" */ 552ee8c1d4aSdm if (strncmp("SUNm31", fadt->OemId, 6)) 553ee8c1d4aSdm return (0); 554ee8c1d4aSdm else 555ee8c1d4aSdm return (1); 55625145214Smyers } 55725145214Smyers 55825145214Smyers /* 55925145214Smyers * Initial enumeration of the physical PCI bus hierarchy can 56025145214Smyers * leave 'gaps' in the order of peer PCI bus unit-addresses. 56125145214Smyers * Systems with more than one peer PCI bus *must* have an ACPI 56225145214Smyers * _BBN object associated with each peer bus; use the presence 56325145214Smyers * of this object to remove gaps in the numbering of the peer 56425145214Smyers * PCI bus unit-addresses - only peer busses with an associated 56525145214Smyers * _BBN are counted. 56625145214Smyers */ 56725145214Smyers static void 56825145214Smyers pci_renumber_root_busses(void) 56925145214Smyers { 57025145214Smyers int pci_regs[] = {0, 0, 0}; 57125145214Smyers int i, root_addr = 0; 57225145214Smyers 573ee8c1d4aSdm /* 574ee8c1d4aSdm * Currently, we only enable the re-numbering on specific 575ee8c1d4aSdm * Sun machines; this is a work-around for the more complicated 576ee8c1d4aSdm * issue of upgrade changing physical device paths 577ee8c1d4aSdm */ 57825145214Smyers if (!pci_bus_renumber()) 57925145214Smyers return; 58025145214Smyers 58125145214Smyers /* 58225145214Smyers * If we find no _BBN objects at all, we either don't need 58325145214Smyers * to do anything or can't do anything anyway 58425145214Smyers */ 58525145214Smyers if (!pci_roots_have_bbn()) 58625145214Smyers return; 58725145214Smyers 58825145214Smyers for (i = 0; i <= pci_bios_nbus; i++) { 58925145214Smyers /* skip non-root (peer) PCI busses */ 59025145214Smyers if (pci_bus_res[i].par_bus != (uchar_t)-1) 59125145214Smyers continue; 59225145214Smyers 59325145214Smyers if (pci_bbn_present(i) < 1) { 59425145214Smyers pci_bus_res[i].root_addr = (uchar_t)-1; 59525145214Smyers continue; 59625145214Smyers } 59725145214Smyers 59825145214Smyers ASSERT(pci_bus_res[i].dip != NULL); 59925145214Smyers if (pci_bus_res[i].root_addr != root_addr) { 60025145214Smyers /* update reg property for node */ 60125145214Smyers pci_bus_res[i].root_addr = root_addr; 60225145214Smyers pci_regs[0] = pci_bus_res[i].root_addr; 60325145214Smyers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 60425145214Smyers pci_bus_res[i].dip, "reg", (int *)pci_regs, 3); 60525145214Smyers } 60625145214Smyers root_addr++; 60725145214Smyers } 60825145214Smyers } 60925145214Smyers 61078323854SJudy Chen void 6111d6b7b34SJudy Chen pci_register_isa_resources(int type, uint32_t base, uint32_t size) 612aaba6dfeSmyers { 6131d6b7b34SJudy Chen (void) memlist_insert( 6142f283da5SDan Mick (type == 1) ? &isa_res.io_used : &isa_res.mem_used, 6151d6b7b34SJudy Chen base, size); 616aaba6dfeSmyers } 617aaba6dfeSmyers 6185af4ae46Sjveta /* 61905f867c3Sgs * Remove the resources which are already used by devices under a subtractive 62005f867c3Sgs * bridge from the bus's resources lists, because they're not available, and 62105f867c3Sgs * shouldn't be allocated to other buses. This is necessary because tracking 62205f867c3Sgs * resources for subtractive bridges is not complete. (Subtractive bridges only 62305f867c3Sgs * track some of their claimed resources, not "the rest of the address space" as 62405f867c3Sgs * they should, so that allocation to peer non-subtractive PPBs is easier. We 62505f867c3Sgs * need a fully-capable global resource allocator). 6265af4ae46Sjveta */ 62705f867c3Sgs static void 62805f867c3Sgs remove_subtractive_res() 6295af4ae46Sjveta { 63005f867c3Sgs int i, j; 63105f867c3Sgs struct memlist *list; 6325af4ae46Sjveta 63305f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) { 63405f867c3Sgs if (pci_bus_res[i].subtractive) { 63505f867c3Sgs /* remove used io ports */ 6362f283da5SDan Mick list = pci_bus_res[i].io_used; 63705f867c3Sgs while (list) { 6388fc7923fSDana Myers for (j = 0; j <= pci_bios_nbus; j++) 6398fc7923fSDana Myers (void) memlist_remove( 6402f283da5SDan Mick &pci_bus_res[j].io_avail, 6418fc7923fSDana Myers list->address, list->size); 64205f867c3Sgs list = list->next; 64305f867c3Sgs } 64405f867c3Sgs /* remove used mem resource */ 6452f283da5SDan Mick list = pci_bus_res[i].mem_used; 64605f867c3Sgs while (list) { 64705f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 6488fc7923fSDana Myers (void) memlist_remove( 6492f283da5SDan Mick &pci_bus_res[j].mem_avail, 6508fc7923fSDana Myers list->address, list->size); 6518fc7923fSDana Myers (void) memlist_remove( 6522f283da5SDan Mick &pci_bus_res[j].pmem_avail, 6538fc7923fSDana Myers list->address, list->size); 65405f867c3Sgs } 65505f867c3Sgs list = list->next; 65605f867c3Sgs } 65705f867c3Sgs /* remove used prefetchable mem resource */ 6582f283da5SDan Mick list = pci_bus_res[i].pmem_used; 65905f867c3Sgs while (list) { 66005f867c3Sgs for (j = 0; j <= pci_bios_nbus; j++) { 6618fc7923fSDana Myers (void) memlist_remove( 6622f283da5SDan Mick &pci_bus_res[j].pmem_avail, 6638fc7923fSDana Myers list->address, list->size); 6648fc7923fSDana Myers (void) memlist_remove( 6652f283da5SDan Mick &pci_bus_res[j].mem_avail, 6668fc7923fSDana Myers list->address, list->size); 66705f867c3Sgs } 66805f867c3Sgs list = list->next; 66905f867c3Sgs } 6705af4ae46Sjveta } 67105f867c3Sgs } 67205f867c3Sgs } 67305f867c3Sgs 6748fc7923fSDana Myers /* 6752f283da5SDan Mick * Set up (or complete the setup of) the bus_avail resource list 6768fc7923fSDana Myers */ 67705f867c3Sgs static void 67805f867c3Sgs setup_bus_res(int bus) 67905f867c3Sgs { 68005f867c3Sgs uchar_t par_bus; 68105f867c3Sgs 68205f867c3Sgs if (pci_bus_res[bus].dip == NULL) /* unused bus */ 68305f867c3Sgs return; 68405f867c3Sgs 6858fc7923fSDana Myers /* 6862f283da5SDan Mick * Set up bus_avail if not already filled in by populate_bus_res() 6878fc7923fSDana Myers */ 6882f283da5SDan Mick if (pci_bus_res[bus].bus_avail == NULL) { 6898fc7923fSDana Myers ASSERT(pci_bus_res[bus].sub_bus >= bus); 6902f283da5SDan Mick memlist_insert(&pci_bus_res[bus].bus_avail, bus, 6918fc7923fSDana Myers pci_bus_res[bus].sub_bus - bus + 1); 69205f867c3Sgs } 6935af4ae46Sjveta 6942f283da5SDan Mick ASSERT(pci_bus_res[bus].bus_avail != NULL); 6958fc7923fSDana Myers 69605f867c3Sgs /* 69705f867c3Sgs * Remove resources from parent bus node if this is not a 69805f867c3Sgs * root bus. 69905f867c3Sgs */ 70005f867c3Sgs par_bus = pci_bus_res[bus].par_bus; 70105f867c3Sgs if (par_bus != (uchar_t)-1) { 7022f283da5SDan Mick ASSERT(pci_bus_res[par_bus].bus_avail != NULL); 7032f283da5SDan Mick memlist_remove_list(&pci_bus_res[par_bus].bus_avail, 7042f283da5SDan Mick pci_bus_res[bus].bus_avail); 70505f867c3Sgs } 7068fc7923fSDana Myers 7072f283da5SDan Mick /* remove self from bus_avail */; 7082f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].bus_avail, bus, 1); 7095af4ae46Sjveta } 7105af4ae46Sjveta 71105f867c3Sgs static uint64_t 71205f867c3Sgs get_parbus_io_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 7135af4ae46Sjveta { 71405f867c3Sgs uint64_t addr = 0; 71505f867c3Sgs uchar_t res_bus; 7165af4ae46Sjveta 71705f867c3Sgs /* 7188fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7198fc7923fSDana Myers * ACPI resource discovery was not successfully done. 72005f867c3Sgs */ 72105f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7228fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7235af4ae46Sjveta return (0); 7245af4ae46Sjveta 72505f867c3Sgs res_bus = parbus; 72605f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7272f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) 72805f867c3Sgs break; 72905f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 73005f867c3Sgs if (res_bus == (uchar_t)-1) 73105f867c3Sgs break; /* root bus already */ 73205f867c3Sgs } 7335af4ae46Sjveta 7342f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 7352f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].io_avail, 73605f867c3Sgs size, align); 73705f867c3Sgs if (addr) { 7382f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].io_used, 73905f867c3Sgs addr, size); 7408fc7923fSDana Myers 74105f867c3Sgs /* free the old resource */ 7422f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_avail); 7432f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].io_used); 7448fc7923fSDana Myers 74505f867c3Sgs /* add the new resource */ 7462f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_avail, addr, size); 74705f867c3Sgs } 7485af4ae46Sjveta } 7495af4ae46Sjveta 75005f867c3Sgs return (addr); 75105f867c3Sgs } 75205f867c3Sgs 75305f867c3Sgs static uint64_t 75405f867c3Sgs get_parbus_mem_res(uchar_t parbus, uchar_t bus, uint64_t size, uint64_t align) 75505f867c3Sgs { 75605f867c3Sgs uint64_t addr = 0; 75705f867c3Sgs uchar_t res_bus; 7585af4ae46Sjveta 7595af4ae46Sjveta /* 7608fc7923fSDana Myers * Skip root(peer) buses in multiple-root-bus systems when 7618fc7923fSDana Myers * ACPI resource discovery was not successfully done. 7625af4ae46Sjveta */ 76305f867c3Sgs if ((pci_bus_res[parbus].par_bus == (uchar_t)-1) && 7648fc7923fSDana Myers (num_root_bus > 1) && (acpi_resource_discovery <= 0)) 7655af4ae46Sjveta return (0); 7665af4ae46Sjveta 76705f867c3Sgs res_bus = parbus; 76805f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 7692f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) 77005f867c3Sgs break; 77105f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 77205f867c3Sgs if (res_bus == (uchar_t)-1) 77305f867c3Sgs break; /* root bus already */ 77405f867c3Sgs } 77505f867c3Sgs 7762f283da5SDan Mick if (pci_bus_res[res_bus].mem_avail) { 7772f283da5SDan Mick addr = memlist_find(&pci_bus_res[res_bus].mem_avail, 77805f867c3Sgs size, align); 77905f867c3Sgs if (addr) { 7802f283da5SDan Mick memlist_insert(&pci_bus_res[res_bus].mem_used, 78105f867c3Sgs addr, size); 7822f283da5SDan Mick (void) memlist_remove(&pci_bus_res[res_bus].pmem_avail, 7838fc7923fSDana Myers addr, size); 7848fc7923fSDana Myers 78505f867c3Sgs /* free the old resource */ 7862f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_avail); 7872f283da5SDan Mick memlist_free_all(&pci_bus_res[bus].mem_used); 7888fc7923fSDana Myers 78905f867c3Sgs /* add the new resource */ 7902f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_avail, addr, size); 79105f867c3Sgs } 79205f867c3Sgs } 79305f867c3Sgs 79405f867c3Sgs return (addr); 7955af4ae46Sjveta } 7965af4ae46Sjveta 79749fbdd30SErwin T Tsaur /* 79849fbdd30SErwin T Tsaur * given a cap_id, return its cap_id location in config space 79949fbdd30SErwin T Tsaur */ 80049fbdd30SErwin T Tsaur static int 80149fbdd30SErwin T Tsaur get_pci_cap(uchar_t bus, uchar_t dev, uchar_t func, uint8_t cap_id) 80249fbdd30SErwin T Tsaur { 80349fbdd30SErwin T Tsaur uint8_t curcap, cap_id_loc; 80449fbdd30SErwin T Tsaur uint16_t status; 80549fbdd30SErwin T Tsaur int location = -1; 80649fbdd30SErwin T Tsaur 80749fbdd30SErwin T Tsaur /* 80849fbdd30SErwin T Tsaur * Need to check the Status register for ECP support first. 80949fbdd30SErwin T Tsaur * Also please note that for type 1 devices, the 81049fbdd30SErwin T Tsaur * offset could change. Should support type 1 next. 81149fbdd30SErwin T Tsaur */ 81249fbdd30SErwin T Tsaur status = pci_getw(bus, dev, func, PCI_CONF_STAT); 81349fbdd30SErwin T Tsaur if (!(status & PCI_STAT_CAP)) { 81449fbdd30SErwin T Tsaur return (-1); 81549fbdd30SErwin T Tsaur } 81649fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 81749fbdd30SErwin T Tsaur 81849fbdd30SErwin T Tsaur /* Walk the list of capabilities */ 81949fbdd30SErwin T Tsaur while (cap_id_loc && cap_id_loc != (uint8_t)-1) { 82049fbdd30SErwin T Tsaur curcap = pci_getb(bus, dev, func, cap_id_loc); 82149fbdd30SErwin T Tsaur 82249fbdd30SErwin T Tsaur if (curcap == cap_id) { 82349fbdd30SErwin T Tsaur location = cap_id_loc; 82449fbdd30SErwin T Tsaur break; 82549fbdd30SErwin T Tsaur } 82649fbdd30SErwin T Tsaur cap_id_loc = pci_getb(bus, dev, func, cap_id_loc + 1); 82749fbdd30SErwin T Tsaur } 82849fbdd30SErwin T Tsaur return (location); 82949fbdd30SErwin T Tsaur } 83049fbdd30SErwin T Tsaur 8312f283da5SDan Mick /* 8322f283da5SDan Mick * Does this resource element live in the legacy VGA range? 8332f283da5SDan Mick */ 8342f283da5SDan Mick 8352f283da5SDan Mick int 8362f283da5SDan Mick is_vga(struct memlist *elem, enum io_mem io) 8372f283da5SDan Mick { 8382f283da5SDan Mick 8392f283da5SDan Mick if (io == IO) { 8402f283da5SDan Mick if ((elem->address == 0x3b0 && elem->size == 0xc) || 8412f283da5SDan Mick (elem->address == 0x3c0 && elem->size == 0x20)) 8422f283da5SDan Mick return (1); 8432f283da5SDan Mick } else { 8442f283da5SDan Mick if (elem->address == 0xa0000 && elem->size == 0x20000) 8452f283da5SDan Mick return (1); 8462f283da5SDan Mick } 8472f283da5SDan Mick return (0); 8482f283da5SDan Mick } 8492f283da5SDan Mick 8502f283da5SDan Mick /* 8512f283da5SDan Mick * Does this entire resource list consist only of legacy VGA resources? 8522f283da5SDan Mick */ 8532f283da5SDan Mick 8542f283da5SDan Mick int 8552f283da5SDan Mick list_is_vga_only(struct memlist *l, enum io_mem io) 8562f283da5SDan Mick { 8572f283da5SDan Mick do { 8582f283da5SDan Mick if (!is_vga(l, io)) 8592f283da5SDan Mick return (0); 8602f283da5SDan Mick } while ((l = l->next) != NULL); 8612f283da5SDan Mick return (1); 8622f283da5SDan Mick } 8632f283da5SDan Mick 8649896aa55Sjveta /* 86505f867c3Sgs * Assign valid resources to unconfigured pci(e) bridges. We are trying 86605f867c3Sgs * to reprogram the bridge when its 86705f867c3Sgs * i) SECBUS == SUBBUS || 86805f867c3Sgs * ii) IOBASE > IOLIM || 86905f867c3Sgs * iii) MEMBASE > MEMLIM 87005f867c3Sgs * This must be done after one full pass through the PCI tree to collect 87105f867c3Sgs * all BIOS-configured resources, so that we know what resources are 87205f867c3Sgs * free and available to assign to the unconfigured PPBs. 8739896aa55Sjveta */ 8749896aa55Sjveta static void 87505f867c3Sgs fix_ppb_res(uchar_t secbus, boolean_t prog_sub) 8769896aa55Sjveta { 8779896aa55Sjveta uchar_t bus, dev, func; 87805f867c3Sgs uchar_t parbus, subbus; 87905f867c3Sgs uint_t io_base, io_limit, mem_base, mem_limit; 880ffa17327SGuoli Shu uint_t io_size, mem_size, io_align, mem_align; 88105f867c3Sgs uint64_t addr = 0; 8825af4ae46Sjveta int *regp = NULL; 8839896aa55Sjveta uint_t reglen; 8845af4ae46Sjveta int rv, cap_ptr, physhi; 8859896aa55Sjveta dev_info_t *dip; 88605f867c3Sgs uint16_t cmd_reg; 88742e542bcSDan Mick struct memlist *list, *scratch_list; 88805f867c3Sgs 88905f867c3Sgs /* skip root (peer) PCI busses */ 89005f867c3Sgs if (pci_bus_res[secbus].par_bus == (uchar_t)-1) 89105f867c3Sgs return; 89205f867c3Sgs 89305f867c3Sgs /* skip subtractive PPB when prog_sub is not TRUE */ 89405f867c3Sgs if (pci_bus_res[secbus].subtractive && !prog_sub) 89505f867c3Sgs return; 8969896aa55Sjveta 8979896aa55Sjveta /* some entries may be empty due to discontiguous bus numbering */ 8985af4ae46Sjveta dip = pci_bus_res[secbus].dip; 8999896aa55Sjveta if (dip == NULL) 9009896aa55Sjveta return; 9019896aa55Sjveta 9029896aa55Sjveta rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 9039896aa55Sjveta "reg", ®p, ®len); 9042f283da5SDan Mick if (rv != DDI_PROP_SUCCESS || reglen == 0) 9052f283da5SDan Mick return; 9065af4ae46Sjveta physhi = regp[0]; 9075af4ae46Sjveta ddi_prop_free(regp); 9089896aa55Sjveta 9095af4ae46Sjveta func = (uchar_t)PCI_REG_FUNC_G(physhi); 9105af4ae46Sjveta dev = (uchar_t)PCI_REG_DEV_G(physhi); 9115af4ae46Sjveta bus = (uchar_t)PCI_REG_BUS_G(physhi); 9129896aa55Sjveta 9139896aa55Sjveta /* 91405f867c3Sgs * If pcie bridge, check to see if link is enabled 9159896aa55Sjveta */ 91649fbdd30SErwin T Tsaur cap_ptr = get_pci_cap(bus, dev, func, PCI_CAP_ID_PCI_E); 91749fbdd30SErwin T Tsaur if (cap_ptr != -1) { 91805f867c3Sgs cmd_reg = pci_getw(bus, dev, func, 91905f867c3Sgs (uint16_t)cap_ptr + PCIE_LINKCTL); 92005f867c3Sgs if (cmd_reg & PCIE_LINKCTL_LINK_DISABLE) { 92105f867c3Sgs dcmn_err(CE_NOTE, 92205f867c3Sgs "!fix_ppb_res: ppb[%x/%x/%x] link is disabled.\n", 92305f867c3Sgs bus, dev, func); 92405f867c3Sgs return; 92505f867c3Sgs } 92605f867c3Sgs } 9279896aa55Sjveta 92805f867c3Sgs subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 92905f867c3Sgs parbus = pci_bus_res[secbus].par_bus; 93005f867c3Sgs ASSERT(parbus == bus); 931707a5600Sgs cmd_reg = pci_getw(bus, dev, func, PCI_CONF_COMM); 9329896aa55Sjveta 9335af4ae46Sjveta /* 93405f867c3Sgs * If we have a Cardbus bridge, but no bus space 9355af4ae46Sjveta */ 93605f867c3Sgs if (pci_bus_res[secbus].num_cbb != 0 && 9372f283da5SDan Mick pci_bus_res[secbus].bus_avail == NULL) { 93805f867c3Sgs uchar_t range; 9395af4ae46Sjveta 94005f867c3Sgs /* normally there are 2 buses under a cardbus bridge */ 94105f867c3Sgs range = pci_bus_res[secbus].num_cbb * 2; 94205f867c3Sgs 94305f867c3Sgs /* 94405f867c3Sgs * Try to find and allocate a bus-range starting at subbus+1 94505f867c3Sgs * from the parent of the PPB. 94605f867c3Sgs */ 94705f867c3Sgs for (; range != 0; range--) { 94805f867c3Sgs if (memlist_find_with_startaddr( 9492f283da5SDan Mick &pci_bus_res[parbus].bus_avail, 95005f867c3Sgs subbus + 1, range, 1) != NULL) 95105f867c3Sgs break; /* find bus range resource at parent */ 95205f867c3Sgs } 95305f867c3Sgs if (range != 0) { 9542f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].bus_avail, 95505f867c3Sgs subbus + 1, range); 95605f867c3Sgs subbus = subbus + range; 95705f867c3Sgs pci_bus_res[secbus].sub_bus = subbus; 95805f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_SUBBUS, subbus); 95905f867c3Sgs add_bus_range_prop(secbus); 96005f867c3Sgs 96105f867c3Sgs cmn_err(CE_NOTE, "!reprogram bus-range on ppb" 96205f867c3Sgs "[%x/%x/%x]: %x ~ %x\n", bus, dev, func, 96305f867c3Sgs secbus, subbus); 96405f867c3Sgs } 96505f867c3Sgs } 96605f867c3Sgs 96705f867c3Sgs /* 968ffa17327SGuoli Shu * Calculate required IO size and alignment 969ffa17327SGuoli Shu * If bus io_size is zero, we are going to assign 512 bytes per bus, 970ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 971ffa17327SGuoli Shu * bus io_size. The size needs to be 4K aligned. 972ffa17327SGuoli Shu * 973ffa17327SGuoli Shu * We calculate alignment as the largest power of two less than the 974ffa17327SGuoli Shu * the sum of all children's IO size requirements, because this will 975ffa17327SGuoli Shu * align to the size of the largest child request within that size 976ffa17327SGuoli Shu * (which is always a power of two). 97705f867c3Sgs */ 97805f867c3Sgs io_size = (subbus - secbus + 1) * 0x200; 979ffa17327SGuoli Shu if (io_size < pci_bus_res[secbus].io_size) 980ffa17327SGuoli Shu io_size = pci_bus_res[secbus].io_size; 981ffa17327SGuoli Shu io_size = P2ROUNDUP(io_size, PPB_IO_ALIGNMENT); 982ffa17327SGuoli Shu io_align = io_size; 983ffa17327SGuoli Shu P2LE(io_align); 984ffa17327SGuoli Shu 9855af4ae46Sjveta /* 986ffa17327SGuoli Shu * Calculate required MEM size and alignment 987ffa17327SGuoli Shu * If bus mem_size is zero, we are going to assign 1M bytes per bus, 988ffa17327SGuoli Shu * otherwise, we'll choose the maximum value of such calculation and 989ffa17327SGuoli Shu * bus mem_size. The size needs to be 1M aligned. 990ffa17327SGuoli Shu * 991ffa17327SGuoli Shu * For the alignment, refer to the I/O comment above. 9925af4ae46Sjveta */ 99305f867c3Sgs mem_size = (subbus - secbus + 1) * PPB_MEM_ALIGNMENT; 994ffa17327SGuoli Shu if (mem_size < pci_bus_res[secbus].mem_size) { 995ffa17327SGuoli Shu mem_size = pci_bus_res[secbus].mem_size; 996ffa17327SGuoli Shu mem_size = P2ROUNDUP(mem_size, PPB_MEM_ALIGNMENT); 997ffa17327SGuoli Shu } 998ffa17327SGuoli Shu mem_align = mem_size; 999ffa17327SGuoli Shu P2LE(mem_align); 100005f867c3Sgs 100105f867c3Sgs /* Subtractive bridge */ 100205f867c3Sgs if (pci_bus_res[secbus].subtractive && prog_sub) { 100305f867c3Sgs /* 100405f867c3Sgs * We program an arbitrary amount of I/O and memory resource 100505f867c3Sgs * for the subtractive bridge so that child dynamic-resource- 100605f867c3Sgs * allocating devices (such as Cardbus bridges) have a chance 100705f867c3Sgs * of success. Until we have full-tree resource rebalancing, 100805f867c3Sgs * dynamic resource allocation (thru busra) only looks at the 100905f867c3Sgs * parent bridge, so all PPBs must have some allocatable 101005f867c3Sgs * resource. For non-subtractive bridges, the resources come 101105f867c3Sgs * from the base/limit register "windows", but subtractive 101205f867c3Sgs * bridges often don't program those (since they don't need to). 101305f867c3Sgs * If we put all the remaining resources on the subtractive 101405f867c3Sgs * bridge, then peer non-subtractive bridges can't allocate 101505f867c3Sgs * more space (even though this is probably most correct). 101605f867c3Sgs * If we put the resources only on the parent, then allocations 101705f867c3Sgs * from children of subtractive bridges will fail without 101805f867c3Sgs * special-case code for bypassing the subtractive bridge. 101905f867c3Sgs * This solution is the middle-ground temporary solution until 102005f867c3Sgs * we have fully-capable resource allocation. 102105f867c3Sgs */ 102205f867c3Sgs 102305f867c3Sgs /* 102405f867c3Sgs * Add an arbitrary I/O resource to the subtractive PPB 102505f867c3Sgs */ 10262f283da5SDan Mick if (pci_bus_res[secbus].io_avail == NULL) { 102705f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1028ffa17327SGuoli Shu io_align); 102905f867c3Sgs if (addr) { 10308fc7923fSDana Myers add_ranges_prop(secbus, 1); 103105f867c3Sgs pci_bus_res[secbus].io_reprogram = 103205f867c3Sgs pci_bus_res[parbus].io_reprogram; 103305f867c3Sgs 103405f867c3Sgs cmn_err(CE_NOTE, "!add io-range on subtractive" 103505f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 103605f867c3Sgs bus, dev, func, (uint32_t)addr, 103705f867c3Sgs (uint32_t)addr + io_size - 1); 103805f867c3Sgs } 103905f867c3Sgs } 104005f867c3Sgs /* 104105f867c3Sgs * Add an arbitrary memory resource to the subtractive PPB 104205f867c3Sgs */ 10432f283da5SDan Mick if (pci_bus_res[secbus].mem_avail == NULL) { 104405f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1045ffa17327SGuoli Shu mem_align); 104605f867c3Sgs if (addr) { 10478fc7923fSDana Myers add_ranges_prop(secbus, 1); 104805f867c3Sgs pci_bus_res[secbus].mem_reprogram = 104905f867c3Sgs pci_bus_res[parbus].mem_reprogram; 105005f867c3Sgs 105105f867c3Sgs cmn_err(CE_NOTE, "!add mem-range on " 105205f867c3Sgs "subtractive ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 105305f867c3Sgs bus, dev, func, (uint32_t)addr, 105405f867c3Sgs (uint32_t)addr + mem_size - 1); 105505f867c3Sgs } 105605f867c3Sgs } 105705f867c3Sgs 105805f867c3Sgs goto cmd_enable; 10595af4ae46Sjveta } 106005f867c3Sgs 106105f867c3Sgs /* 1062707a5600Sgs * Check to see if we need to reprogram I/O space, either because the 1063707a5600Sgs * parent bus needed reprogramming and so do we, or because I/O space is 1064707a5600Sgs * disabled in base/limit or command register. 106505f867c3Sgs */ 106605f867c3Sgs io_base = pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 106705f867c3Sgs io_limit = pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 106805f867c3Sgs io_base = (io_base & 0xf0) << 8; 106905f867c3Sgs io_limit = ((io_limit & 0xf0) << 8) | 0xfff; 107005f867c3Sgs 10712f283da5SDan Mick /* Form list of all resources passed (avail + used) */ 107242e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].io_avail); 107342e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].io_used, &scratch_list); 10742f283da5SDan Mick 10752f283da5SDan Mick if ((pci_bus_res[parbus].io_reprogram || 10762f283da5SDan Mick (io_base > io_limit) || 10772f283da5SDan Mick (!(cmd_reg & PCI_COMM_IO))) && 107842e542bcSDan Mick !list_is_vga_only(scratch_list, IO)) { 10792f283da5SDan Mick if (pci_bus_res[secbus].io_used) { 10802f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].io_used, 10812f283da5SDan Mick &pci_bus_res[secbus].io_avail); 108205f867c3Sgs } 10832f283da5SDan Mick if (pci_bus_res[secbus].io_avail && 108405f867c3Sgs (!pci_bus_res[parbus].io_reprogram) && 108505f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 108605f867c3Sgs /* rechoose old io ports info */ 10872f283da5SDan Mick list = pci_bus_res[secbus].io_avail; 10882f283da5SDan Mick io_base = 0; 10892f283da5SDan Mick do { 10902f283da5SDan Mick if (is_vga(list, IO)) 10912f283da5SDan Mick continue; 10922f283da5SDan Mick if (!io_base) { 10932f283da5SDan Mick io_base = (uint_t)list->address; 109405f867c3Sgs io_limit = (uint_t) 10952f283da5SDan Mick list->address + list->size - 1; 10962f283da5SDan Mick io_base = 10972f283da5SDan Mick P2ALIGN(io_base, PPB_IO_ALIGNMENT); 10982f283da5SDan Mick } else { 10992f283da5SDan Mick if (list->address + list->size > 11002f283da5SDan Mick io_limit) { 11012f283da5SDan Mick io_limit = (uint_t) 11022f283da5SDan Mick (list->address + 11032f283da5SDan Mick list->size - 1); 11042f283da5SDan Mick } 11052f283da5SDan Mick } 11062f283da5SDan Mick } while ((list = list->next) != NULL); 110705f867c3Sgs /* 4K aligned */ 11082f283da5SDan Mick io_limit = P2ROUNDUP(io_limit, PPB_IO_ALIGNMENT) - 1; 11092f283da5SDan Mick io_size = io_limit - io_base + 1; 111005f867c3Sgs ASSERT(io_base <= io_limit); 11112f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].io_avail); 11122f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 111305f867c3Sgs io_base, io_size); 11142f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].io_used, 111505f867c3Sgs io_base, io_size); 11162f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].io_avail, 11178fc7923fSDana Myers io_base, io_size); 111805f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 111905f867c3Sgs } else { 112005f867c3Sgs /* get new io ports from parent bus */ 112105f867c3Sgs addr = get_parbus_io_res(parbus, secbus, io_size, 1122ffa17327SGuoli Shu io_align); 112305f867c3Sgs if (addr) { 112405f867c3Sgs io_base = addr; 112505f867c3Sgs io_limit = addr + io_size - 1; 112605f867c3Sgs pci_bus_res[secbus].io_reprogram = B_TRUE; 112705f867c3Sgs } 112805f867c3Sgs } 112905f867c3Sgs if (pci_bus_res[secbus].io_reprogram) { 113005f867c3Sgs /* reprogram PPB regs */ 113105f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 113205f867c3Sgs (uchar_t)((io_base>>8) & 0xf0)); 113305f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 113405f867c3Sgs (uchar_t)((io_limit>>8) & 0xf0)); 113505f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 113605f867c3Sgs pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 11378fc7923fSDana Myers add_ranges_prop(secbus, 1); 113805f867c3Sgs 113905f867c3Sgs cmn_err(CE_NOTE, "!reprogram io-range on" 114005f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 114105f867c3Sgs bus, dev, func, io_base, io_limit); 114205f867c3Sgs } 11439896aa55Sjveta } 114442e542bcSDan Mick memlist_free_all(&scratch_list); 11459896aa55Sjveta 11465af4ae46Sjveta /* 1147707a5600Sgs * Check memory space as we did I/O space. 11485af4ae46Sjveta */ 114905f867c3Sgs mem_base = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 115005f867c3Sgs mem_base = (mem_base & 0xfff0) << 16; 115105f867c3Sgs mem_limit = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 1152707a5600Sgs mem_limit = ((mem_limit & 0xfff0) << 16) | 0xfffff; 1153707a5600Sgs 115442e542bcSDan Mick scratch_list = memlist_dup(pci_bus_res[secbus].mem_avail); 115542e542bcSDan Mick memlist_merge(&pci_bus_res[secbus].mem_used, &scratch_list); 11562f283da5SDan Mick 11572f283da5SDan Mick if ((pci_bus_res[parbus].mem_reprogram || 11582f283da5SDan Mick (mem_base > mem_limit) || 11592f283da5SDan Mick (!(cmd_reg & PCI_COMM_MAE))) && 116042e542bcSDan Mick !list_is_vga_only(scratch_list, MEM)) { 11612f283da5SDan Mick if (pci_bus_res[secbus].mem_used) { 11622f283da5SDan Mick memlist_subsume(&pci_bus_res[secbus].mem_used, 11632f283da5SDan Mick &pci_bus_res[secbus].mem_avail); 116405f867c3Sgs } 11652f283da5SDan Mick if (pci_bus_res[secbus].mem_avail && 116605f867c3Sgs (!pci_bus_res[parbus].mem_reprogram) && 116705f867c3Sgs (!pci_bus_res[parbus].subtractive)) { 116805f867c3Sgs /* rechoose old mem resource */ 11692f283da5SDan Mick list = pci_bus_res[secbus].mem_avail; 11702f283da5SDan Mick mem_base = 0; 11712f283da5SDan Mick do { 11722f283da5SDan Mick if (is_vga(list, MEM)) 11732f283da5SDan Mick continue; 11742f283da5SDan Mick if (mem_base == 0) { 11752f283da5SDan Mick mem_base = (uint_t)list->address; 11762f283da5SDan Mick mem_base = P2ALIGN(mem_base, 11772f283da5SDan Mick PPB_MEM_ALIGNMENT); 117805f867c3Sgs mem_limit = (uint_t) 11792f283da5SDan Mick (list->address + list->size - 1); 11802f283da5SDan Mick } else { 11812f283da5SDan Mick if ((list->address + list->size) > 11822f283da5SDan Mick mem_limit) { 11832f283da5SDan Mick mem_limit = (uint_t) 11842f283da5SDan Mick (list->address + 11852f283da5SDan Mick list->size - 1); 11862f283da5SDan Mick } 11872f283da5SDan Mick } 11882f283da5SDan Mick } while ((list = list->next) != NULL); 11892f283da5SDan Mick mem_limit = P2ROUNDUP(mem_limit, PPB_MEM_ALIGNMENT) - 1; 11902f283da5SDan Mick mem_size = mem_limit + 1 - mem_base; 119105f867c3Sgs ASSERT(mem_base <= mem_limit); 11922f283da5SDan Mick memlist_free_all(&pci_bus_res[secbus].mem_avail); 11932f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 119405f867c3Sgs mem_base, mem_size); 11952f283da5SDan Mick memlist_insert(&pci_bus_res[parbus].mem_used, 119605f867c3Sgs mem_base, mem_size); 11972f283da5SDan Mick (void) memlist_remove(&pci_bus_res[parbus].mem_avail, 11988fc7923fSDana Myers mem_base, mem_size); 119905f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 120005f867c3Sgs } else { 120105f867c3Sgs /* get new mem resource from parent bus */ 120205f867c3Sgs addr = get_parbus_mem_res(parbus, secbus, mem_size, 1203ffa17327SGuoli Shu mem_align); 120405f867c3Sgs if (addr) { 120505f867c3Sgs mem_base = addr; 120605f867c3Sgs mem_limit = addr + mem_size - 1; 120705f867c3Sgs pci_bus_res[secbus].mem_reprogram = B_TRUE; 120805f867c3Sgs } 120905f867c3Sgs } 121005f867c3Sgs 121105f867c3Sgs if (pci_bus_res[secbus].mem_reprogram) { 121202c2c4edSGuoli Shu /* reprogram PPB MEM regs */ 121305f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_BASE, 121405f867c3Sgs (uint16_t)((mem_base>>16) & 0xfff0)); 121505f867c3Sgs pci_putw(bus, dev, func, PCI_BCNF_MEM_LIMIT, 121605f867c3Sgs (uint16_t)((mem_limit>>16) & 0xfff0)); 121702c2c4edSGuoli Shu /* 121802c2c4edSGuoli Shu * Disable PMEM window by setting base > limit. 121902c2c4edSGuoli Shu * We currently don't reprogram the PMEM like we've 122002c2c4edSGuoli Shu * done for I/O and MEM. (Devices that support prefetch 122102c2c4edSGuoli Shu * can use non-prefetch MEM.) Anyway, if the MEM access 122202c2c4edSGuoli Shu * bit is initially disabled by BIOS, we disable the 122302c2c4edSGuoli Shu * PMEM window manually by setting PMEM base > PMEM 122402c2c4edSGuoli Shu * limit here, in case there are incorrect values in 122502c2c4edSGuoli Shu * them from BIOS, so that we won't get in trouble once 122602c2c4edSGuoli Shu * the MEM access bit is enabled at the end of this 122702c2c4edSGuoli Shu * function. 122802c2c4edSGuoli Shu */ 122902c2c4edSGuoli Shu if (!(cmd_reg & PCI_COMM_MAE)) { 123002c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_BASE_LOW, 123102c2c4edSGuoli Shu 0xfff0); 123202c2c4edSGuoli Shu pci_putw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW, 123302c2c4edSGuoli Shu 0x0); 123402c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH, 123502c2c4edSGuoli Shu 0xffffffff); 123602c2c4edSGuoli Shu pci_putl(bus, dev, func, PCI_BCNF_PF_LIMIT_HIGH, 123702c2c4edSGuoli Shu 0x0); 123802c2c4edSGuoli Shu } 123902c2c4edSGuoli Shu 12408fc7923fSDana Myers add_ranges_prop(secbus, 1); 124105f867c3Sgs 124205f867c3Sgs cmn_err(CE_NOTE, "!reprogram mem-range on" 124305f867c3Sgs " ppb[%x/%x/%x]: 0x%x ~ 0x%x\n", 124405f867c3Sgs bus, dev, func, mem_base, mem_limit); 124505f867c3Sgs } 124605f867c3Sgs } 124742e542bcSDan Mick memlist_free_all(&scratch_list); 124805f867c3Sgs 124905f867c3Sgs cmd_enable: 12502f283da5SDan Mick if (pci_bus_res[secbus].io_avail) 125105f867c3Sgs cmd_reg |= PCI_COMM_IO | PCI_COMM_ME; 12522f283da5SDan Mick if (pci_bus_res[secbus].mem_avail) 125305f867c3Sgs cmd_reg |= PCI_COMM_MAE | PCI_COMM_ME; 125405f867c3Sgs pci_putw(bus, dev, func, PCI_CONF_COMM, cmd_reg); 12559896aa55Sjveta } 12569896aa55Sjveta 12577c478bd9Sstevel@tonic-gate void 12587c478bd9Sstevel@tonic-gate pci_reprogram(void) 12597c478bd9Sstevel@tonic-gate { 12607c478bd9Sstevel@tonic-gate int i, pci_reconfig = 1; 12617c478bd9Sstevel@tonic-gate char *onoff; 12628fc7923fSDana Myers int bus; 12637c478bd9Sstevel@tonic-gate 126425145214Smyers /* 1265*00dfdf4aSDana Myers * Scan ACPI namespace for _BBN objects, make sure that 1266*00dfdf4aSDana Myers * childless root-bridges appear in devinfo tree 126725145214Smyers */ 1268*00dfdf4aSDana Myers pci_scan_bbn(); 1269*00dfdf4aSDana Myers pci_unitaddr_cache_init(); 1270*00dfdf4aSDana Myers 1271*00dfdf4aSDana Myers /* 1272*00dfdf4aSDana Myers * Fix-up unit-address assignments if cache is available 1273*00dfdf4aSDana Myers */ 1274*00dfdf4aSDana Myers if (pci_unitaddr_cache_valid()) { 1275*00dfdf4aSDana Myers int pci_regs[] = {0, 0, 0}; 1276*00dfdf4aSDana Myers int new_addr; 1277*00dfdf4aSDana Myers int index = 0; 1278*00dfdf4aSDana Myers 1279*00dfdf4aSDana Myers for (bus = 0; bus <= pci_bios_nbus; bus++) { 1280*00dfdf4aSDana Myers /* skip non-root (peer) PCI busses */ 1281*00dfdf4aSDana Myers if ((pci_bus_res[bus].par_bus != (uchar_t)-1) || 1282*00dfdf4aSDana Myers (pci_bus_res[bus].dip == NULL)) 1283*00dfdf4aSDana Myers continue; 1284*00dfdf4aSDana Myers 1285*00dfdf4aSDana Myers new_addr = pci_bus_unitaddr(index); 1286*00dfdf4aSDana Myers if (pci_bus_res[bus].root_addr != new_addr) { 1287*00dfdf4aSDana Myers /* update reg property for node */ 1288*00dfdf4aSDana Myers pci_regs[0] = pci_bus_res[bus].root_addr = 1289*00dfdf4aSDana Myers new_addr; 1290*00dfdf4aSDana Myers (void) ndi_prop_update_int_array( 1291*00dfdf4aSDana Myers DDI_DEV_T_NONE, pci_bus_res[bus].dip, 1292*00dfdf4aSDana Myers "reg", (int *)pci_regs, 3); 1293*00dfdf4aSDana Myers } 1294*00dfdf4aSDana Myers index++; 1295*00dfdf4aSDana Myers } 1296*00dfdf4aSDana Myers } else { 1297*00dfdf4aSDana Myers /* perform legacy processing */ 1298*00dfdf4aSDana Myers pci_renumber_root_busses(); 1299*00dfdf4aSDana Myers pci_unitaddr_cache_create(); 1300*00dfdf4aSDana Myers } 130125145214Smyers 13028fc7923fSDana Myers /* 13038fc7923fSDana Myers * Do root-bus resource discovery 13048fc7923fSDana Myers */ 13058fc7923fSDana Myers for (bus = 0; bus <= pci_bios_nbus; bus++) { 13068fc7923fSDana Myers /* skip non-root (peer) PCI busses */ 13078fc7923fSDana Myers if (pci_bus_res[bus].par_bus != (uchar_t)-1) 13088fc7923fSDana Myers continue; 13098fc7923fSDana Myers 13108fc7923fSDana Myers /* 13118fc7923fSDana Myers * 1. find resources associated with this root bus 13128fc7923fSDana Myers */ 13138fc7923fSDana Myers populate_bus_res(bus); 13148fc7923fSDana Myers 13158fc7923fSDana Myers 13168fc7923fSDana Myers /* 13171d6b7b34SJudy Chen * 2. Remove used PCI and ISA resources from bus resource map 13188fc7923fSDana Myers */ 13198fc7923fSDana Myers 13202f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13212f283da5SDan Mick pci_bus_res[bus].io_used); 13222f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13232f283da5SDan Mick pci_bus_res[bus].mem_used); 13242f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13252f283da5SDan Mick pci_bus_res[bus].pmem_used); 13262f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13272f283da5SDan Mick pci_bus_res[bus].pmem_used); 13282f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].pmem_avail, 13292f283da5SDan Mick pci_bus_res[bus].mem_used); 13301d6b7b34SJudy Chen 13312f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].io_avail, 13322f283da5SDan Mick isa_res.io_used); 13332f283da5SDan Mick memlist_remove_list(&pci_bus_res[bus].mem_avail, 13342f283da5SDan Mick isa_res.mem_used); 13358fc7923fSDana Myers } 13368fc7923fSDana Myers 13372f283da5SDan Mick memlist_free_all(&isa_res.io_used); 13382f283da5SDan Mick memlist_free_all(&isa_res.mem_used); 13398fc7923fSDana Myers 1340fc396574Srw /* add bus-range property for root/peer bus nodes */ 1341fc396574Srw for (i = 0; i <= pci_bios_nbus; i++) { 13428fc7923fSDana Myers /* create bus-range property on root/peer buses */ 13438fc7923fSDana Myers if (pci_bus_res[i].par_bus == (uchar_t)-1) 1344fc396574Srw add_bus_range_prop(i); 13458fc7923fSDana Myers 134605f867c3Sgs /* setup bus range resource on each bus */ 134705f867c3Sgs setup_bus_res(i); 1348fc396574Srw } 1349fc396574Srw 13507c478bd9Sstevel@tonic-gate if (ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 13517c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "pci-reprog", &onoff) == DDI_SUCCESS) { 13527c478bd9Sstevel@tonic-gate if (strcmp(onoff, "off") == 0) { 13537c478bd9Sstevel@tonic-gate pci_reconfig = 0; 13547c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "pci device reprogramming disabled"); 13557c478bd9Sstevel@tonic-gate } 13567c478bd9Sstevel@tonic-gate ddi_prop_free(onoff); 13577c478bd9Sstevel@tonic-gate } 13587c478bd9Sstevel@tonic-gate 135905f867c3Sgs remove_subtractive_res(); 136005f867c3Sgs 136105f867c3Sgs /* reprogram the non-subtractive PPB */ 136205f867c3Sgs if (pci_reconfig) 136305f867c3Sgs for (i = 0; i <= pci_bios_nbus; i++) 136405f867c3Sgs fix_ppb_res(i, B_FALSE); 1365aaba6dfeSmyers 13667c478bd9Sstevel@tonic-gate for (i = 0; i <= pci_bios_nbus; i++) { 136705f867c3Sgs /* configure devices not configured by BIOS */ 13689896aa55Sjveta if (pci_reconfig) { 136905f867c3Sgs /* 137005f867c3Sgs * Reprogram the subtractive PPB. At this time, all its 137105f867c3Sgs * siblings should have got their resources already. 137205f867c3Sgs */ 137305f867c3Sgs if (pci_bus_res[i].subtractive) 137405f867c3Sgs fix_ppb_res(i, B_TRUE); 13757c478bd9Sstevel@tonic-gate enumerate_bus_devs(i, CONFIG_NEW); 13769896aa55Sjveta } 13778fc7923fSDana Myers } 13788fc7923fSDana Myers 13798fc7923fSDana Myers /* All dev programmed, so we can create available prop */ 13808fc7923fSDana Myers for (i = 0; i <= pci_bios_nbus; i++) 13817c478bd9Sstevel@tonic-gate add_bus_available_prop(i); 13828fc7923fSDana Myers } 13838fc7923fSDana Myers 13848fc7923fSDana Myers /* 13858fc7923fSDana Myers * populate bus resources 13868fc7923fSDana Myers */ 13878fc7923fSDana Myers static void 13888fc7923fSDana Myers populate_bus_res(uchar_t bus) 13898fc7923fSDana Myers { 13908fc7923fSDana Myers 13918fc7923fSDana Myers /* scan BIOS structures */ 13922f283da5SDan Mick pci_bus_res[bus].pmem_avail = find_bus_res(bus, PREFETCH_TYPE); 13932f283da5SDan Mick pci_bus_res[bus].mem_avail = find_bus_res(bus, MEM_TYPE); 13942f283da5SDan Mick pci_bus_res[bus].io_avail = find_bus_res(bus, IO_TYPE); 13952f283da5SDan Mick pci_bus_res[bus].bus_avail = find_bus_res(bus, BUSRANGE_TYPE); 13968fc7923fSDana Myers 13976b57bdc9SDana Myers /* 13986b57bdc9SDana Myers * attempt to initialize sub_bus from the largest range-end 13992f283da5SDan Mick * in the bus_avail list 14006b57bdc9SDana Myers */ 14012f283da5SDan Mick if (pci_bus_res[bus].bus_avail != NULL) { 14026b57bdc9SDana Myers struct memlist *entry; 14036b57bdc9SDana Myers int current; 14046b57bdc9SDana Myers 14052f283da5SDan Mick entry = pci_bus_res[bus].bus_avail; 14066b57bdc9SDana Myers while (entry != NULL) { 14076b57bdc9SDana Myers current = entry->address + entry->size - 1; 14086b57bdc9SDana Myers if (current > pci_bus_res[bus].sub_bus) 14096b57bdc9SDana Myers pci_bus_res[bus].sub_bus = current; 14106b57bdc9SDana Myers entry = entry->next; 14116b57bdc9SDana Myers } 14126b57bdc9SDana Myers } 14136b57bdc9SDana Myers 14148fc7923fSDana Myers if (bus == 0) { 14158fc7923fSDana Myers /* 14168fc7923fSDana Myers * Special treatment of bus 0: 14178fc7923fSDana Myers * If no IO/MEM resource from ACPI/MPSPEC/HRT, copy 14188fc7923fSDana Myers * pcimem from boot and make I/O space the entire range 14196b57bdc9SDana Myers * starting at 0x100. 14208fc7923fSDana Myers */ 14212f283da5SDan Mick if (pci_bus_res[0].mem_avail == NULL) 14222f283da5SDan Mick pci_bus_res[0].mem_avail = 14238fc7923fSDana Myers memlist_dup(bootops->boot_mem->pcimem); 14248fc7923fSDana Myers /* Exclude 0x00 to 0xff of the I/O space, used by all PCs */ 14252f283da5SDan Mick if (pci_bus_res[0].io_avail == NULL) 14262f283da5SDan Mick memlist_insert(&pci_bus_res[0].io_avail, 0x100, 0xffff); 14277c478bd9Sstevel@tonic-gate } 14288fc7923fSDana Myers 14298fc7923fSDana Myers /* 14308fc7923fSDana Myers * Create 'ranges' property here before any resources are 14318fc7923fSDana Myers * removed from the resource lists 14328fc7923fSDana Myers */ 14338fc7923fSDana Myers add_ranges_prop(bus, 0); 14347c478bd9Sstevel@tonic-gate } 14357c478bd9Sstevel@tonic-gate 14368fc7923fSDana Myers 14377c478bd9Sstevel@tonic-gate /* 14387c478bd9Sstevel@tonic-gate * Create top-level bus dips, i.e. /pci@0,0, /pci@1,0... 14397c478bd9Sstevel@tonic-gate */ 14407c478bd9Sstevel@tonic-gate static void 14417c478bd9Sstevel@tonic-gate create_root_bus_dip(uchar_t bus) 14427c478bd9Sstevel@tonic-gate { 14437c478bd9Sstevel@tonic-gate int pci_regs[] = {0, 0, 0}; 14447c478bd9Sstevel@tonic-gate dev_info_t *dip; 14457c478bd9Sstevel@tonic-gate 14467c478bd9Sstevel@tonic-gate ASSERT(pci_bus_res[bus].par_bus == (uchar_t)-1); 14477c478bd9Sstevel@tonic-gate 144805f867c3Sgs num_root_bus++; 14497c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(ddi_root_node(), "pci", 1450fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &dip); 14517c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14527c478bd9Sstevel@tonic-gate "#address-cells", 3); 14537c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 14547c478bd9Sstevel@tonic-gate "#size-cells", 2); 14557c478bd9Sstevel@tonic-gate pci_regs[0] = pci_bus_res[bus].root_addr; 14567c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 14577c478bd9Sstevel@tonic-gate "reg", (int *)pci_regs, 3); 14587c478bd9Sstevel@tonic-gate 145970025d76Sjohnny /* 146070025d76Sjohnny * If system has PCIe bus, then create different properties 146170025d76Sjohnny */ 146270025d76Sjohnny if (create_pcie_root_bus(bus, dip) == B_FALSE) 146370025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 146470025d76Sjohnny "device_type", "pci"); 146570025d76Sjohnny 14667c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 14677c478bd9Sstevel@tonic-gate pci_bus_res[bus].dip = dip; 14687c478bd9Sstevel@tonic-gate } 14697c478bd9Sstevel@tonic-gate 14707c478bd9Sstevel@tonic-gate /* 14717c478bd9Sstevel@tonic-gate * For any fixed configuration (often compatability) pci devices 14727c478bd9Sstevel@tonic-gate * and those with their own expansion rom, create device nodes 14737c478bd9Sstevel@tonic-gate * to hold the already configured device details. 14747c478bd9Sstevel@tonic-gate */ 14757c478bd9Sstevel@tonic-gate void 14767c478bd9Sstevel@tonic-gate enumerate_bus_devs(uchar_t bus, int config_op) 14777c478bd9Sstevel@tonic-gate { 14787c478bd9Sstevel@tonic-gate uchar_t dev, func, nfunc, header; 14797c478bd9Sstevel@tonic-gate ushort_t venid; 148005f867c3Sgs struct pci_devfunc *devlist = NULL, *entry; 14817c478bd9Sstevel@tonic-gate 14827c478bd9Sstevel@tonic-gate if (config_op == CONFIG_NEW) { 14837c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "configuring pci bus 0x%x", bus); 1484bd87be88Ssethg } else if (config_op == CONFIG_FIX) { 1485bd87be88Ssethg dcmn_err(CE_NOTE, "fixing devices on pci bus 0x%x", bus); 14867c478bd9Sstevel@tonic-gate } else 14877c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "enumerating pci bus 0x%x", bus); 14887c478bd9Sstevel@tonic-gate 14898fc7923fSDana Myers if (config_op == CONFIG_NEW) { 14908fc7923fSDana Myers devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 14918fc7923fSDana Myers while (devlist) { 14928fc7923fSDana Myers entry = devlist; 14938fc7923fSDana Myers devlist = entry->next; 14948fc7923fSDana Myers if (entry->reprogram || 14958fc7923fSDana Myers pci_bus_res[bus].io_reprogram || 14968fc7923fSDana Myers pci_bus_res[bus].mem_reprogram) { 14978fc7923fSDana Myers /* reprogram device(s) */ 14988fc7923fSDana Myers (void) add_reg_props(entry->dip, bus, 14998fc7923fSDana Myers entry->dev, entry->func, CONFIG_NEW, 0); 15008fc7923fSDana Myers } 15018fc7923fSDana Myers kmem_free(entry, sizeof (*entry)); 15028fc7923fSDana Myers } 15038fc7923fSDana Myers pci_bus_res[bus].privdata = NULL; 15048fc7923fSDana Myers return; 15058fc7923fSDana Myers } 15068fc7923fSDana Myers 15077c478bd9Sstevel@tonic-gate for (dev = 0; dev < max_dev_pci; dev++) { 15087c478bd9Sstevel@tonic-gate nfunc = 1; 15097c478bd9Sstevel@tonic-gate for (func = 0; func < nfunc; func++) { 15107c478bd9Sstevel@tonic-gate 15117c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "probing dev 0x%x, func 0x%x", 15127c478bd9Sstevel@tonic-gate dev, func); 15137c478bd9Sstevel@tonic-gate 15147c478bd9Sstevel@tonic-gate venid = pci_getw(bus, dev, func, PCI_CONF_VENID); 1515bd87be88Ssethg 15167c478bd9Sstevel@tonic-gate if ((venid == 0xffff) || (venid == 0)) { 15177c478bd9Sstevel@tonic-gate /* no function at this address */ 15187c478bd9Sstevel@tonic-gate continue; 15197c478bd9Sstevel@tonic-gate } 15207c478bd9Sstevel@tonic-gate 15217c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER); 15227c478bd9Sstevel@tonic-gate if (header == 0xff) { 15237c478bd9Sstevel@tonic-gate continue; /* illegal value */ 15247c478bd9Sstevel@tonic-gate } 15257c478bd9Sstevel@tonic-gate 15267c478bd9Sstevel@tonic-gate /* 15277c478bd9Sstevel@tonic-gate * according to some mail from Microsoft posted 15287c478bd9Sstevel@tonic-gate * to the pci-drivers alias, their only requirement 15297c478bd9Sstevel@tonic-gate * for a multifunction device is for the 1st 15307c478bd9Sstevel@tonic-gate * function to have to PCI_HEADER_MULTI bit set. 15317c478bd9Sstevel@tonic-gate */ 15327c478bd9Sstevel@tonic-gate if ((func == 0) && (header & PCI_HEADER_MULTI)) { 15337c478bd9Sstevel@tonic-gate nfunc = 8; 15347c478bd9Sstevel@tonic-gate } 153546e9e839Smyers 153605f867c3Sgs if (config_op == CONFIG_FIX || 153705f867c3Sgs config_op == CONFIG_INFO) { 1538ebf3afa8Sdmick /* 1539ebf3afa8Sdmick * Create the node, unconditionally, on the 1540ebf3afa8Sdmick * first pass only. It may still need 1541ebf3afa8Sdmick * resource assignment, which will be 1542ebf3afa8Sdmick * done on the second, CONFIG_NEW, pass. 1543ebf3afa8Sdmick */ 154405f867c3Sgs process_devfunc(bus, dev, func, header, 1545ebf3afa8Sdmick venid, config_op); 1546db063408Sdmick 15477c478bd9Sstevel@tonic-gate } 15487c478bd9Sstevel@tonic-gate } 15497c478bd9Sstevel@tonic-gate } 15507c478bd9Sstevel@tonic-gate 15518fc7923fSDana Myers /* percolate bus used resources up through parents to root */ 15528fc7923fSDana Myers if (config_op == CONFIG_INFO) { 15538fc7923fSDana Myers int par_bus; 15548fc7923fSDana Myers 15558fc7923fSDana Myers par_bus = pci_bus_res[bus].par_bus; 15568fc7923fSDana Myers while (par_bus != (uchar_t)-1) { 1557ffa17327SGuoli Shu pci_bus_res[par_bus].io_size += 1558ffa17327SGuoli Shu pci_bus_res[bus].io_size; 1559ffa17327SGuoli Shu pci_bus_res[par_bus].mem_size += 1560ffa17327SGuoli Shu pci_bus_res[bus].mem_size; 15618fc7923fSDana Myers 15622f283da5SDan Mick if (pci_bus_res[bus].io_used) 15632f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, 15642f283da5SDan Mick &pci_bus_res[par_bus].io_used); 15658fc7923fSDana Myers 15662f283da5SDan Mick if (pci_bus_res[bus].mem_used) 15672f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, 15682f283da5SDan Mick &pci_bus_res[par_bus].mem_used); 15698fc7923fSDana Myers 15702f283da5SDan Mick if (pci_bus_res[bus].pmem_used) 15712f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, 15722f283da5SDan Mick &pci_bus_res[par_bus].pmem_used); 15738fc7923fSDana Myers 15742f283da5SDan Mick bus = par_bus; 15758fc7923fSDana Myers par_bus = pci_bus_res[par_bus].par_bus; 15767c478bd9Sstevel@tonic-gate } 15777c478bd9Sstevel@tonic-gate } 15787c478bd9Sstevel@tonic-gate } 15797c478bd9Sstevel@tonic-gate 15807c478bd9Sstevel@tonic-gate static int 15817c478bd9Sstevel@tonic-gate check_pciide_prop(uchar_t revid, ushort_t venid, ushort_t devid, 15827c478bd9Sstevel@tonic-gate ushort_t subvenid, ushort_t subdevid) 15837c478bd9Sstevel@tonic-gate { 15847c478bd9Sstevel@tonic-gate static int prop_exist = -1; 15857c478bd9Sstevel@tonic-gate static char *pciide_str; 15867c478bd9Sstevel@tonic-gate char compat[32]; 15877c478bd9Sstevel@tonic-gate 15887c478bd9Sstevel@tonic-gate if (prop_exist == -1) { 15897c478bd9Sstevel@tonic-gate prop_exist = (ddi_prop_lookup_string(DDI_DEV_T_ANY, 15907c478bd9Sstevel@tonic-gate ddi_root_node(), DDI_PROP_DONTPASS, "pci-ide", 15917c478bd9Sstevel@tonic-gate &pciide_str) == DDI_SUCCESS); 15927c478bd9Sstevel@tonic-gate } 15937c478bd9Sstevel@tonic-gate 15947c478bd9Sstevel@tonic-gate if (!prop_exist) 15957c478bd9Sstevel@tonic-gate return (0); 15967c478bd9Sstevel@tonic-gate 15977c478bd9Sstevel@tonic-gate /* compare property value against various forms of compatible */ 15987c478bd9Sstevel@tonic-gate if (subvenid) { 15997c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x.%x", 16007c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid, revid); 16017c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16027c478bd9Sstevel@tonic-gate return (1); 16037c478bd9Sstevel@tonic-gate 16047c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x.%x", 16057c478bd9Sstevel@tonic-gate venid, devid, subvenid, subdevid); 16067c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16077c478bd9Sstevel@tonic-gate return (1); 16087c478bd9Sstevel@tonic-gate 16097c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", 16107c478bd9Sstevel@tonic-gate subvenid, subdevid); 16117c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16127c478bd9Sstevel@tonic-gate return (1); 16137c478bd9Sstevel@tonic-gate } 16147c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x.%x", 16157c478bd9Sstevel@tonic-gate venid, devid, revid); 16167c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16177c478bd9Sstevel@tonic-gate return (1); 16187c478bd9Sstevel@tonic-gate 16197c478bd9Sstevel@tonic-gate (void) snprintf(compat, sizeof (compat), "pci%x,%x", venid, devid); 16207c478bd9Sstevel@tonic-gate if (strcmp(pciide_str, compat) == 0) 16217c478bd9Sstevel@tonic-gate return (1); 16227c478bd9Sstevel@tonic-gate 16237c478bd9Sstevel@tonic-gate return (0); 16247c478bd9Sstevel@tonic-gate } 16257c478bd9Sstevel@tonic-gate 16267c478bd9Sstevel@tonic-gate static int 16277c478bd9Sstevel@tonic-gate is_pciide(uchar_t basecl, uchar_t subcl, uchar_t revid, 16287c478bd9Sstevel@tonic-gate ushort_t venid, ushort_t devid, ushort_t subvenid, ushort_t subdevid) 16297c478bd9Sstevel@tonic-gate { 16307c478bd9Sstevel@tonic-gate struct ide_table { /* table for PCI_MASS_OTHER */ 16317c478bd9Sstevel@tonic-gate ushort_t venid; 16327c478bd9Sstevel@tonic-gate ushort_t devid; 16337c478bd9Sstevel@tonic-gate } *entry; 16347c478bd9Sstevel@tonic-gate 1635334edc48Sml /* XXX SATA and other devices: need a way to add dynamically */ 16367c478bd9Sstevel@tonic-gate static struct ide_table ide_other[] = { 16377c478bd9Sstevel@tonic-gate {0x1095, 0x3112}, 16387c478bd9Sstevel@tonic-gate {0x1095, 0x3114}, 16397c478bd9Sstevel@tonic-gate {0x1095, 0x3512}, 1640d01a0451Stt {0x1095, 0x680}, /* Sil0680 */ 1641334edc48Sml {0x1283, 0x8211}, /* ITE 8211F is subcl PCI_MASS_OTHER */ 16427c478bd9Sstevel@tonic-gate {0, 0} 16437c478bd9Sstevel@tonic-gate }; 16447c478bd9Sstevel@tonic-gate 16457c478bd9Sstevel@tonic-gate if (basecl != PCI_CLASS_MASS) 16467c478bd9Sstevel@tonic-gate return (0); 16477c478bd9Sstevel@tonic-gate 16487c478bd9Sstevel@tonic-gate if (subcl == PCI_MASS_IDE) { 16497c478bd9Sstevel@tonic-gate return (1); 16507c478bd9Sstevel@tonic-gate } 16517c478bd9Sstevel@tonic-gate 1652d01a0451Stt if (check_pciide_prop(revid, venid, devid, subvenid, subdevid)) 1653d01a0451Stt return (1); 1654d01a0451Stt 16557c478bd9Sstevel@tonic-gate if (subcl != PCI_MASS_OTHER && subcl != PCI_MASS_SATA) { 16567c478bd9Sstevel@tonic-gate return (0); 16577c478bd9Sstevel@tonic-gate } 16587c478bd9Sstevel@tonic-gate 16597c478bd9Sstevel@tonic-gate entry = &ide_other[0]; 16607c478bd9Sstevel@tonic-gate while (entry->venid) { 16617c478bd9Sstevel@tonic-gate if (entry->venid == venid && entry->devid == devid) 16627c478bd9Sstevel@tonic-gate return (1); 16637c478bd9Sstevel@tonic-gate entry++; 16647c478bd9Sstevel@tonic-gate } 1665d01a0451Stt return (0); 16667c478bd9Sstevel@tonic-gate } 16677c478bd9Sstevel@tonic-gate 16687c478bd9Sstevel@tonic-gate static int 16697c478bd9Sstevel@tonic-gate is_display(uint_t classcode) 16707c478bd9Sstevel@tonic-gate { 16717c478bd9Sstevel@tonic-gate static uint_t disp_classes[] = { 16727c478bd9Sstevel@tonic-gate 0x000100, 16737c478bd9Sstevel@tonic-gate 0x030000, 16747c478bd9Sstevel@tonic-gate 0x030001 16757c478bd9Sstevel@tonic-gate }; 16767c478bd9Sstevel@tonic-gate int i, nclasses = sizeof (disp_classes) / sizeof (uint_t); 16777c478bd9Sstevel@tonic-gate 16787c478bd9Sstevel@tonic-gate for (i = 0; i < nclasses; i++) { 16797c478bd9Sstevel@tonic-gate if (classcode == disp_classes[i]) 16807c478bd9Sstevel@tonic-gate return (1); 16817c478bd9Sstevel@tonic-gate } 16827c478bd9Sstevel@tonic-gate return (0); 16837c478bd9Sstevel@tonic-gate } 16847c478bd9Sstevel@tonic-gate 1685bd87be88Ssethg static void 1686bd87be88Ssethg add_undofix_entry(uint8_t bus, uint8_t dev, uint8_t fn, 1687bd87be88Ssethg void (*undofn)(uint8_t, uint8_t, uint8_t)) 1688bd87be88Ssethg { 1689bd87be88Ssethg struct pci_fixundo *newundo; 1690bd87be88Ssethg 1691bd87be88Ssethg newundo = kmem_alloc(sizeof (struct pci_fixundo), KM_SLEEP); 1692bd87be88Ssethg 1693bd87be88Ssethg /* 1694bd87be88Ssethg * Adding an item to this list means that we must turn its NMIENABLE 1695bd87be88Ssethg * bit back on at a later time. 1696bd87be88Ssethg */ 1697bd87be88Ssethg newundo->bus = bus; 1698bd87be88Ssethg newundo->dev = dev; 1699bd87be88Ssethg newundo->fn = fn; 1700bd87be88Ssethg newundo->undofn = undofn; 1701bd87be88Ssethg newundo->next = undolist; 1702bd87be88Ssethg 1703bd87be88Ssethg /* add to the undo list in LIFO order */ 1704bd87be88Ssethg undolist = newundo; 1705bd87be88Ssethg } 1706bd87be88Ssethg 1707bd87be88Ssethg void 1708bd87be88Ssethg add_pci_fixes(void) 1709bd87be88Ssethg { 1710bd87be88Ssethg int i; 1711bd87be88Ssethg 1712bd87be88Ssethg for (i = 0; i <= pci_bios_nbus; i++) { 1713bd87be88Ssethg /* 1714bd87be88Ssethg * For each bus, apply needed fixes to the appropriate devices. 1715bd87be88Ssethg * This must be done before the main enumeration loop because 1716bd87be88Ssethg * some fixes must be applied to devices normally encountered 1717bd87be88Ssethg * later in the pci scan (e.g. if a fix to device 7 must be 1718bd87be88Ssethg * applied before scanning device 6, applying fixes in the 1719bd87be88Ssethg * normal enumeration loop would obviously be too late). 1720bd87be88Ssethg */ 1721bd87be88Ssethg enumerate_bus_devs(i, CONFIG_FIX); 1722bd87be88Ssethg } 1723bd87be88Ssethg } 1724bd87be88Ssethg 1725bd87be88Ssethg void 1726bd87be88Ssethg undo_pci_fixes(void) 1727bd87be88Ssethg { 1728bd87be88Ssethg struct pci_fixundo *nextundo; 1729bd87be88Ssethg uint8_t bus, dev, fn; 1730bd87be88Ssethg 1731bd87be88Ssethg /* 1732bd87be88Ssethg * All fixes in the undo list are performed unconditionally. Future 1733bd87be88Ssethg * fixes may require selective undo. 1734bd87be88Ssethg */ 1735bd87be88Ssethg while (undolist != NULL) { 1736bd87be88Ssethg 1737bd87be88Ssethg bus = undolist->bus; 1738bd87be88Ssethg dev = undolist->dev; 1739bd87be88Ssethg fn = undolist->fn; 1740bd87be88Ssethg 1741bd87be88Ssethg (*(undolist->undofn))(bus, dev, fn); 1742bd87be88Ssethg 1743bd87be88Ssethg nextundo = undolist->next; 1744bd87be88Ssethg kmem_free(undolist, sizeof (struct pci_fixundo)); 1745bd87be88Ssethg undolist = nextundo; 1746bd87be88Ssethg } 1747bd87be88Ssethg } 1748bd87be88Ssethg 1749bd87be88Ssethg static void 1750bd87be88Ssethg undo_amd8111_pci_fix(uint8_t bus, uint8_t dev, uint8_t fn) 1751bd87be88Ssethg { 1752bd87be88Ssethg uint8_t val8; 1753bd87be88Ssethg 1754bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1755bd87be88Ssethg /* 1756bd87be88Ssethg * The NMIONERR bit is turned back on to allow the SMM BIOS 1757bd87be88Ssethg * to handle more critical PCI errors (e.g. PERR#). 1758bd87be88Ssethg */ 1759bd87be88Ssethg val8 |= AMD8111_ENABLENMI; 1760bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1761bd87be88Ssethg } 1762bd87be88Ssethg 1763bd87be88Ssethg static void 1764bd87be88Ssethg pci_fix_amd8111(uint8_t bus, uint8_t dev, uint8_t fn) 1765bd87be88Ssethg { 1766bd87be88Ssethg uint8_t val8; 1767bd87be88Ssethg 1768bd87be88Ssethg val8 = pci_getb(bus, dev, fn, LPC_IO_CONTROL_REG_1); 1769bd87be88Ssethg 1770bd87be88Ssethg if ((val8 & AMD8111_ENABLENMI) == 0) 1771bd87be88Ssethg return; 1772bd87be88Ssethg 1773bd87be88Ssethg /* 1774bd87be88Ssethg * We reset NMIONERR in the LPC because master-abort on the PCI 1775bd87be88Ssethg * bridge side of the 8111 will cause NMI, which might cause SMI, 1776bd87be88Ssethg * which sometimes prevents all devices from being enumerated. 1777bd87be88Ssethg */ 1778bd87be88Ssethg val8 &= ~AMD8111_ENABLENMI; 1779bd87be88Ssethg 1780bd87be88Ssethg pci_putb(bus, dev, fn, LPC_IO_CONTROL_REG_1, val8); 1781bd87be88Ssethg 1782bd87be88Ssethg add_undofix_entry(bus, dev, fn, undo_amd8111_pci_fix); 1783bd87be88Ssethg } 1784bd87be88Ssethg 1785c8711d4dSgs static void 1786c8711d4dSgs set_devpm_d0(uchar_t bus, uchar_t dev, uchar_t func) 1787c8711d4dSgs { 1788c8711d4dSgs uint16_t status; 1789c8711d4dSgs uint8_t header; 1790c8711d4dSgs uint8_t cap_ptr; 1791c8711d4dSgs uint8_t cap_id; 1792c8711d4dSgs uint16_t pmcsr; 1793c8711d4dSgs 1794c8711d4dSgs status = pci_getw(bus, dev, func, PCI_CONF_STAT); 1795c8711d4dSgs if (!(status & PCI_STAT_CAP)) 1796c8711d4dSgs return; /* No capabilities list */ 1797c8711d4dSgs 1798c8711d4dSgs header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 1799c8711d4dSgs if (header == PCI_HEADER_CARDBUS) 1800fb66942fSCasper H.S. Dik cap_ptr = pci_getb(bus, dev, func, PCI_CBUS_CAP_PTR); 1801c8711d4dSgs else 1802c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, PCI_CONF_CAP_PTR); 1803c8711d4dSgs /* 1804c8711d4dSgs * Walk the capabilities list searching for a PM entry. 1805c8711d4dSgs */ 1806c8711d4dSgs while (cap_ptr != PCI_CAP_NEXT_PTR_NULL && cap_ptr >= PCI_CAP_PTR_OFF) { 1807c8711d4dSgs cap_ptr &= PCI_CAP_PTR_MASK; 1808c8711d4dSgs cap_id = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_ID); 1809c8711d4dSgs if (cap_id == PCI_CAP_ID_PM) { 1810c8711d4dSgs pmcsr = pci_getw(bus, dev, func, cap_ptr + PCI_PMCSR); 1811c8711d4dSgs pmcsr &= ~(PCI_PMCSR_STATE_MASK); 1812c8711d4dSgs pmcsr |= PCI_PMCSR_D0; /* D0 state */ 1813c8711d4dSgs pci_putw(bus, dev, func, cap_ptr + PCI_PMCSR, pmcsr); 1814c8711d4dSgs break; 1815c8711d4dSgs } 1816c8711d4dSgs cap_ptr = pci_getb(bus, dev, func, cap_ptr + PCI_CAP_NEXT_PTR); 1817c8711d4dSgs } 1818c8711d4dSgs 1819c8711d4dSgs } 1820c8711d4dSgs 182178323854SJudy Chen #define is_isa(bc, sc) \ 182278323854SJudy Chen (((bc) == PCI_CLASS_BRIDGE) && ((sc) == PCI_BRIDGE_ISA)) 182378323854SJudy Chen 182405f867c3Sgs static void 1825bd87be88Ssethg process_devfunc(uchar_t bus, uchar_t dev, uchar_t func, uchar_t header, 18267c478bd9Sstevel@tonic-gate ushort_t vendorid, int config_op) 18277c478bd9Sstevel@tonic-gate { 18287c478bd9Sstevel@tonic-gate char nodename[32], unitaddr[5]; 18297c478bd9Sstevel@tonic-gate dev_info_t *dip; 1830c8589f13Ssethg uchar_t basecl, subcl, progcl, intr, revid; 18317c478bd9Sstevel@tonic-gate ushort_t subvenid, subdevid, status; 183270025d76Sjohnny ushort_t slot_num; 18337c478bd9Sstevel@tonic-gate uint_t classcode, revclass; 18348d483882Smlf int reprogram = 0, pciide = 0; 18357c478bd9Sstevel@tonic-gate int power[2] = {1, 1}; 183670025d76Sjohnny int pciex = 0; 183770025d76Sjohnny ushort_t is_pci_bridge = 0; 183805f867c3Sgs struct pci_devfunc *devlist = NULL, *entry = NULL; 183994f1124eSVikram Hegde gfx_entry_t *gfxp; 18407c478bd9Sstevel@tonic-gate 18417c478bd9Sstevel@tonic-gate ushort_t deviceid = pci_getw(bus, dev, func, PCI_CONF_DEVID); 18427c478bd9Sstevel@tonic-gate 18437c478bd9Sstevel@tonic-gate switch (header & PCI_HEADER_TYPE_M) { 18447c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 18457c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CONF_SUBVENID); 18467c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CONF_SUBSYSID); 18477c478bd9Sstevel@tonic-gate break; 18487c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 18497c478bd9Sstevel@tonic-gate subvenid = pci_getw(bus, dev, func, PCI_CBUS_SUBVENID); 18507c478bd9Sstevel@tonic-gate subdevid = pci_getw(bus, dev, func, PCI_CBUS_SUBSYSID); 185105f867c3Sgs /* Record the # of cardbus bridges found on the bus */ 185205f867c3Sgs if (config_op == CONFIG_INFO) 185305f867c3Sgs pci_bus_res[bus].num_cbb++; 18547c478bd9Sstevel@tonic-gate break; 18557c478bd9Sstevel@tonic-gate default: 18567c478bd9Sstevel@tonic-gate subvenid = 0; 18577c478bd9Sstevel@tonic-gate subdevid = 0; 18587c478bd9Sstevel@tonic-gate break; 18597c478bd9Sstevel@tonic-gate } 18607c478bd9Sstevel@tonic-gate 1861bd87be88Ssethg if (config_op == CONFIG_FIX) { 1862bd87be88Ssethg if (vendorid == VENID_AMD && deviceid == DEVID_AMD8111_LPC) { 1863bd87be88Ssethg pci_fix_amd8111(bus, dev, func); 1864bd87be88Ssethg } 186505f867c3Sgs return; 1866bd87be88Ssethg } 1867bd87be88Ssethg 18687c478bd9Sstevel@tonic-gate /* XXX should be use generic names? derive from class? */ 18697c478bd9Sstevel@tonic-gate revclass = pci_getl(bus, dev, func, PCI_CONF_REVID); 18707c478bd9Sstevel@tonic-gate classcode = revclass >> 8; 18717c478bd9Sstevel@tonic-gate revid = revclass & 0xff; 18727c478bd9Sstevel@tonic-gate 18737c478bd9Sstevel@tonic-gate /* figure out if this is pci-ide */ 18747c478bd9Sstevel@tonic-gate basecl = classcode >> 16; 18757c478bd9Sstevel@tonic-gate subcl = (classcode >> 8) & 0xff; 1876c8589f13Ssethg progcl = classcode & 0xff; 18777c478bd9Sstevel@tonic-gate 18788d483882Smlf 18798d483882Smlf if (is_display(classcode)) 18807c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), "display"); 188178323854SJudy Chen else if (!pseudo_isa && is_isa(basecl, subcl)) 188278323854SJudy Chen (void) snprintf(nodename, sizeof (nodename), "isa"); 18837c478bd9Sstevel@tonic-gate else if (subvenid != 0) 18847c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 18857c478bd9Sstevel@tonic-gate "pci%x,%x", subvenid, subdevid); 18867c478bd9Sstevel@tonic-gate else 18877c478bd9Sstevel@tonic-gate (void) snprintf(nodename, sizeof (nodename), 18887c478bd9Sstevel@tonic-gate "pci%x,%x", vendorid, deviceid); 18897c478bd9Sstevel@tonic-gate 18907c478bd9Sstevel@tonic-gate /* make sure parent bus dip has been created */ 18918fc7923fSDana Myers if (pci_bus_res[bus].dip == NULL) 18927c478bd9Sstevel@tonic-gate create_root_bus_dip(bus); 18937c478bd9Sstevel@tonic-gate 18947c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(pci_bus_res[bus].dip, nodename, 18957c478bd9Sstevel@tonic-gate DEVI_SID_NODEID, &dip); 18967c478bd9Sstevel@tonic-gate 189700d0963fSdilpreet if (check_if_device_is_pciex(dip, bus, dev, func, &slot_num, 189800d0963fSdilpreet &is_pci_bridge) == B_TRUE) 189900d0963fSdilpreet pciex = 1; 190000d0963fSdilpreet 19017c478bd9Sstevel@tonic-gate /* add properties */ 19027c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", deviceid); 19037c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", vendorid); 19047c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, "revision-id", revid); 19057c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19067c478bd9Sstevel@tonic-gate "class-code", classcode); 19077c478bd9Sstevel@tonic-gate if (func == 0) 19087c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), "%x", dev); 19097c478bd9Sstevel@tonic-gate else 19107c478bd9Sstevel@tonic-gate (void) snprintf(unitaddr, sizeof (unitaddr), 19117c478bd9Sstevel@tonic-gate "%x,%x", dev, func); 19127c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 19137c478bd9Sstevel@tonic-gate "unit-address", unitaddr); 19147c478bd9Sstevel@tonic-gate 1915ebf3afa8Sdmick /* add device_type for display nodes */ 1916ebf3afa8Sdmick if (is_display(classcode)) { 1917ebf3afa8Sdmick (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 1918ebf3afa8Sdmick "device_type", "display"); 1919ebf3afa8Sdmick } 19207c478bd9Sstevel@tonic-gate /* add special stuff for header type */ 19217c478bd9Sstevel@tonic-gate if ((header & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 19227c478bd9Sstevel@tonic-gate uchar_t mingrant = pci_getb(bus, dev, func, PCI_CONF_MIN_G); 19237c478bd9Sstevel@tonic-gate uchar_t maxlatency = pci_getb(bus, dev, func, PCI_CONF_MAX_L); 19247c478bd9Sstevel@tonic-gate 19257c478bd9Sstevel@tonic-gate if (subvenid != 0) { 19267c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19277c478bd9Sstevel@tonic-gate "subsystem-id", subdevid); 19287c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19297c478bd9Sstevel@tonic-gate "subsystem-vendor-id", subvenid); 19307c478bd9Sstevel@tonic-gate } 193170025d76Sjohnny if (!pciex) 193270025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 193370025d76Sjohnny "min-grant", mingrant); 193470025d76Sjohnny if (!pciex) 193570025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 193670025d76Sjohnny "max-latency", maxlatency); 19377c478bd9Sstevel@tonic-gate } 19387c478bd9Sstevel@tonic-gate 19397c478bd9Sstevel@tonic-gate /* interrupt, record if not 0 */ 19407c478bd9Sstevel@tonic-gate intr = pci_getb(bus, dev, func, PCI_CONF_IPIN); 19417c478bd9Sstevel@tonic-gate if (intr != 0) 19427c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19437c478bd9Sstevel@tonic-gate "interrupts", intr); 19447c478bd9Sstevel@tonic-gate 19457c478bd9Sstevel@tonic-gate /* 19467c478bd9Sstevel@tonic-gate * Add support for 133 mhz pci eventually 19477c478bd9Sstevel@tonic-gate */ 19487c478bd9Sstevel@tonic-gate status = pci_getw(bus, dev, func, PCI_CONF_STAT); 19497c478bd9Sstevel@tonic-gate 19507c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 19517c478bd9Sstevel@tonic-gate "devsel-speed", (status & PCI_STAT_DEVSELT) >> 9); 195270025d76Sjohnny if (!pciex && (status & PCI_STAT_FBBC)) 19537c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19547c478bd9Sstevel@tonic-gate "fast-back-to-back"); 195570025d76Sjohnny if (!pciex && (status & PCI_STAT_66MHZ)) 19567c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19577c478bd9Sstevel@tonic-gate "66mhz-capable"); 19587c478bd9Sstevel@tonic-gate if (status & PCI_STAT_UDF) 19597c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 19607c478bd9Sstevel@tonic-gate "udf-supported"); 1961d57b3b3dSprasad if (pciex && slot_num) { 196270025d76Sjohnny (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 196370025d76Sjohnny "physical-slot#", slot_num); 1964d57b3b3dSprasad if (!is_pci_bridge) 1965d57b3b3dSprasad pciex_slot_names_prop(dip, slot_num); 1966d57b3b3dSprasad } 19677c478bd9Sstevel@tonic-gate 19687c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 19697c478bd9Sstevel@tonic-gate "power-consumption", power, 2); 19707c478bd9Sstevel@tonic-gate 1971c8711d4dSgs /* Set the device PM state to D0 */ 1972c8711d4dSgs set_devpm_d0(bus, dev, func); 1973c8711d4dSgs 197470025d76Sjohnny if ((basecl == PCI_CLASS_BRIDGE) && (subcl == PCI_BRIDGE_PCI)) 197549fbdd30SErwin T Tsaur add_ppb_props(dip, bus, dev, func, pciex, is_pci_bridge); 197605f867c3Sgs else { 197705f867c3Sgs /* 197805f867c3Sgs * Record the non-PPB devices on the bus for possible 197905f867c3Sgs * reprogramming at 2nd bus enumeration. 198005f867c3Sgs * Note: PPB reprogramming is done in fix_ppb_res() 198105f867c3Sgs */ 198205f867c3Sgs devlist = (struct pci_devfunc *)pci_bus_res[bus].privdata; 198305f867c3Sgs entry = kmem_zalloc(sizeof (*entry), KM_SLEEP); 198405f867c3Sgs entry->dip = dip; 198505f867c3Sgs entry->dev = dev; 198605f867c3Sgs entry->func = func; 198705f867c3Sgs entry->next = devlist; 198805f867c3Sgs pci_bus_res[bus].privdata = entry; 198905f867c3Sgs } 199070025d76Sjohnny 1991c8589f13Ssethg if (config_op == CONFIG_INFO && 1992c8589f13Ssethg IS_CLASS_IOAPIC(basecl, subcl, progcl)) { 1993c8589f13Ssethg create_ioapic_node(bus, dev, func, vendorid, deviceid); 1994c8589f13Ssethg } 1995c8589f13Ssethg 199670025d76Sjohnny /* check for ck8-04 based PCI ISA bridge only */ 199770025d76Sjohnny if (NVIDIA_IS_LPC_BRIDGE(vendorid, deviceid) && (dev == 1) && 199870025d76Sjohnny (func == 0)) 19998a5a0d1eSanish add_nvidia_isa_bridge_props(dip, bus, dev, func); 200070025d76Sjohnny 200170025d76Sjohnny if (pciex && is_pci_bridge) 200270025d76Sjohnny (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 200370025d76Sjohnny (char *)"PCIe-PCI bridge"); 200470025d76Sjohnny else 200570025d76Sjohnny add_model_prop(dip, classcode); 20067c478bd9Sstevel@tonic-gate 20077c478bd9Sstevel@tonic-gate add_compatible(dip, subvenid, subdevid, vendorid, deviceid, 200870025d76Sjohnny revid, classcode, pciex); 20098d483882Smlf 20108d483882Smlf /* 20118d483882Smlf * See if this device is a controller that advertises 20128d483882Smlf * itself to be a standard ATA task file controller, or one that 20138d483882Smlf * has been hard coded. 20148d483882Smlf * 20158d483882Smlf * If it is, check if any other higher precedence driver listed in 20168d483882Smlf * driver_aliases will claim the node by calling 20178d483882Smlf * ddi_compatibile_driver_major. If so, clear pciide and do not 20188d483882Smlf * create a pci-ide node or any other special handling. 20198d483882Smlf * 20208d483882Smlf * If another driver does not bind, set the node name to pci-ide 20218d483882Smlf * and then let the special pci-ide handling for registers and 20228d483882Smlf * child pci-ide nodes proceed below. 20238d483882Smlf */ 20248d483882Smlf if (is_pciide(basecl, subcl, revid, vendorid, deviceid, 20258d483882Smlf subvenid, subdevid) == 1) { 20268d483882Smlf if (ddi_compatible_driver_major(dip, NULL) == (major_t)-1) { 20278d483882Smlf (void) ndi_devi_set_nodename(dip, "pci-ide", 0); 20288d483882Smlf pciide = 1; 20298d483882Smlf } 20308d483882Smlf } 20318d483882Smlf 20327c478bd9Sstevel@tonic-gate reprogram = add_reg_props(dip, bus, dev, func, config_op, pciide); 20337c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(dip, 0); 20347c478bd9Sstevel@tonic-gate 20357c478bd9Sstevel@tonic-gate /* special handling for pci-ide */ 20367c478bd9Sstevel@tonic-gate if (pciide) { 20377c478bd9Sstevel@tonic-gate dev_info_t *cdip; 20387c478bd9Sstevel@tonic-gate 20397c478bd9Sstevel@tonic-gate /* 20407c478bd9Sstevel@tonic-gate * Create properties specified by P1275 Working Group 20417c478bd9Sstevel@tonic-gate * Proposal #414 Version 1 20427c478bd9Sstevel@tonic-gate */ 20437c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 20447c478bd9Sstevel@tonic-gate "device_type", "pci-ide"); 20457c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20467c478bd9Sstevel@tonic-gate "#address-cells", 1); 20477c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 20487c478bd9Sstevel@tonic-gate "#size-cells", 0); 20497c478bd9Sstevel@tonic-gate 20507c478bd9Sstevel@tonic-gate /* allocate two child nodes */ 20517c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2052fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 20537c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 20547c478bd9Sstevel@tonic-gate "reg", 0); 20557c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 20567c478bd9Sstevel@tonic-gate ndi_devi_alloc_sleep(dip, "ide", 2057fa9e4066Sahrens (pnode_t)DEVI_SID_NODEID, &cdip); 20587c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 20597c478bd9Sstevel@tonic-gate "reg", 1); 20607c478bd9Sstevel@tonic-gate (void) ndi_devi_bind_driver(cdip, 0); 20617c478bd9Sstevel@tonic-gate 20627c478bd9Sstevel@tonic-gate reprogram = 0; /* don't reprogram pci-ide bridge */ 20637c478bd9Sstevel@tonic-gate } 20647c478bd9Sstevel@tonic-gate 20657e301000SVikram Hegde if (is_display(classcode)) { 206694f1124eSVikram Hegde gfxp = kmem_zalloc(sizeof (*gfxp), KM_SLEEP); 206794f1124eSVikram Hegde gfxp->g_dip = dip; 206894f1124eSVikram Hegde gfxp->g_prev = NULL; 206994f1124eSVikram Hegde gfxp->g_next = gfx_devinfo_list; 207094f1124eSVikram Hegde gfx_devinfo_list = gfxp; 207194f1124eSVikram Hegde if (gfxp->g_next) 207294f1124eSVikram Hegde gfxp->g_next->g_prev = gfxp; 207394f1124eSVikram Hegde } 207494f1124eSVikram Hegde 207578323854SJudy Chen /* special handling for isa */ 207678323854SJudy Chen if (!pseudo_isa && is_isa(basecl, subcl)) { 207778323854SJudy Chen /* add device_type */ 207878323854SJudy Chen (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 207978323854SJudy Chen "device_type", "isa"); 208078323854SJudy Chen } 208178323854SJudy Chen 208205f867c3Sgs if (reprogram && (entry != NULL)) 208305f867c3Sgs entry->reprogram = B_TRUE; 20847e301000SVikram Hegde 20857c478bd9Sstevel@tonic-gate } 20867c478bd9Sstevel@tonic-gate 2087c2de8625SScott Carter, SD IOSW /* 2088c2de8625SScott Carter, SD IOSW * Some vendors do not use unique subsystem IDs in their products, which 2089c2de8625SScott Carter, SD IOSW * makes the use of form 2 compatible names (pciSSSS,ssss) inappropriate. 2090c2de8625SScott Carter, SD IOSW * Allow for these compatible forms to be excluded on a per-device basis. 2091c2de8625SScott Carter, SD IOSW */ 2092c2de8625SScott Carter, SD IOSW /*ARGSUSED*/ 2093c2de8625SScott Carter, SD IOSW static boolean_t 2094c2de8625SScott Carter, SD IOSW subsys_compat_exclude(ushort_t venid, ushort_t devid, ushort_t subvenid, 2095c2de8625SScott Carter, SD IOSW ushort_t subdevid, uchar_t revid, uint_t classcode) 2096c2de8625SScott Carter, SD IOSW { 2097c2de8625SScott Carter, SD IOSW /* Nvidia display adapters */ 2098c2de8625SScott Carter, SD IOSW if ((venid == 0x10de) && (is_display(classcode))) 2099c2de8625SScott Carter, SD IOSW return (B_TRUE); 2100c2de8625SScott Carter, SD IOSW 2101c2de8625SScott Carter, SD IOSW return (B_FALSE); 2102c2de8625SScott Carter, SD IOSW } 2103c2de8625SScott Carter, SD IOSW 21047c478bd9Sstevel@tonic-gate /* 21057c478bd9Sstevel@tonic-gate * Set the compatible property to a value compliant with 21067c478bd9Sstevel@tonic-gate * rev 2.1 of the IEEE1275 PCI binding. 210770025d76Sjohnny * (Also used for PCI-Express devices). 21087c478bd9Sstevel@tonic-gate * 21097c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss.RR (0) 21107c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.SSSS.ssss (1) 21117c478bd9Sstevel@tonic-gate * pciSSSS,ssss (2) 21127c478bd9Sstevel@tonic-gate * pciVVVV,DDDD.RR (3) 21137c478bd9Sstevel@tonic-gate * pciVVVV,DDDD (4) 21147c478bd9Sstevel@tonic-gate * pciclass,CCSSPP (5) 21157c478bd9Sstevel@tonic-gate * pciclass,CCSS (6) 21167c478bd9Sstevel@tonic-gate * 21177c478bd9Sstevel@tonic-gate * The Subsystem (SSSS) forms are not inserted if 21187c478bd9Sstevel@tonic-gate * subsystem-vendor-id is 0. 21197c478bd9Sstevel@tonic-gate * 212070025d76Sjohnny * NOTE: For PCI-Express devices "pci" is replaced with "pciex" in 0-6 above 212170025d76Sjohnny * property 2 is not created as per "1275 bindings for PCI Express Interconnect" 212270025d76Sjohnny * 21237c478bd9Sstevel@tonic-gate * Set with setprop and \x00 between each 21247c478bd9Sstevel@tonic-gate * to generate the encoded string array form. 21257c478bd9Sstevel@tonic-gate */ 21267c478bd9Sstevel@tonic-gate void 21277c478bd9Sstevel@tonic-gate add_compatible(dev_info_t *dip, ushort_t subvenid, ushort_t subdevid, 212870025d76Sjohnny ushort_t vendorid, ushort_t deviceid, uchar_t revid, uint_t classcode, 212970025d76Sjohnny int pciex) 21307c478bd9Sstevel@tonic-gate { 213170025d76Sjohnny int i = 0; 213270025d76Sjohnny int size = COMPAT_BUFSIZE; 213370025d76Sjohnny char *compat[13]; 21347c478bd9Sstevel@tonic-gate char *buf, *curr; 21357c478bd9Sstevel@tonic-gate 21367c478bd9Sstevel@tonic-gate curr = buf = kmem_alloc(size, KM_SLEEP); 21377c478bd9Sstevel@tonic-gate 213870025d76Sjohnny if (pciex) { 213970025d76Sjohnny if (subvenid) { 214070025d76Sjohnny compat[i++] = curr; /* form 0 */ 214170025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x.%x", 214270025d76Sjohnny vendorid, deviceid, subvenid, subdevid, revid); 214370025d76Sjohnny size -= strlen(curr) + 1; 214470025d76Sjohnny curr += strlen(curr) + 1; 214570025d76Sjohnny 214670025d76Sjohnny compat[i++] = curr; /* form 1 */ 214770025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x.%x", 214870025d76Sjohnny vendorid, deviceid, subvenid, subdevid); 214970025d76Sjohnny size -= strlen(curr) + 1; 215070025d76Sjohnny curr += strlen(curr) + 1; 215170025d76Sjohnny 215270025d76Sjohnny } 215370025d76Sjohnny compat[i++] = curr; /* form 3 */ 215470025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x.%x", 215570025d76Sjohnny vendorid, deviceid, revid); 215670025d76Sjohnny size -= strlen(curr) + 1; 215770025d76Sjohnny curr += strlen(curr) + 1; 215870025d76Sjohnny 215970025d76Sjohnny compat[i++] = curr; /* form 4 */ 216070025d76Sjohnny (void) snprintf(curr, size, "pciex%x,%x", vendorid, deviceid); 216170025d76Sjohnny size -= strlen(curr) + 1; 216270025d76Sjohnny curr += strlen(curr) + 1; 216370025d76Sjohnny 216470025d76Sjohnny compat[i++] = curr; /* form 5 */ 216570025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%06x", classcode); 216670025d76Sjohnny size -= strlen(curr) + 1; 216770025d76Sjohnny curr += strlen(curr) + 1; 216870025d76Sjohnny 216970025d76Sjohnny compat[i++] = curr; /* form 6 */ 217070025d76Sjohnny (void) snprintf(curr, size, "pciexclass,%04x", 217170025d76Sjohnny (classcode >> 8)); 217270025d76Sjohnny size -= strlen(curr) + 1; 217370025d76Sjohnny curr += strlen(curr) + 1; 217470025d76Sjohnny } 217570025d76Sjohnny 21767c478bd9Sstevel@tonic-gate if (subvenid) { 21777c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 0 */ 21787c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x.%x", 21797c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid, revid); 21807c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 21817c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 21827c478bd9Sstevel@tonic-gate 21837c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 1 */ 21847c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x.%x", 21857c478bd9Sstevel@tonic-gate vendorid, deviceid, subvenid, subdevid); 21867c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 21877c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 21887c478bd9Sstevel@tonic-gate 2189c2de8625SScott Carter, SD IOSW if (subsys_compat_exclude(vendorid, deviceid, subvenid, 2190c2de8625SScott Carter, SD IOSW subdevid, revid, classcode) == B_FALSE) { 2191c2de8625SScott Carter, SD IOSW compat[i++] = curr; /* form 2 */ 2192c2de8625SScott Carter, SD IOSW (void) snprintf(curr, size, "pci%x,%x", subvenid, 2193c2de8625SScott Carter, SD IOSW subdevid); 2194c2de8625SScott Carter, SD IOSW size -= strlen(curr) + 1; 2195c2de8625SScott Carter, SD IOSW curr += strlen(curr) + 1; 2196c2de8625SScott Carter, SD IOSW } 21977c478bd9Sstevel@tonic-gate } 21987c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 3 */ 21997c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x.%x", vendorid, deviceid, revid); 22007c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22017c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22027c478bd9Sstevel@tonic-gate 22037c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 4 */ 22047c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pci%x,%x", vendorid, deviceid); 22057c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22067c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22077c478bd9Sstevel@tonic-gate 22087c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 5 */ 22097c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%06x", classcode); 22107c478bd9Sstevel@tonic-gate size -= strlen(curr) + 1; 22117c478bd9Sstevel@tonic-gate curr += strlen(curr) + 1; 22127c478bd9Sstevel@tonic-gate 22137c478bd9Sstevel@tonic-gate compat[i++] = curr; /* form 6 */ 22147c478bd9Sstevel@tonic-gate (void) snprintf(curr, size, "pciclass,%04x", (classcode >> 8)); 221570025d76Sjohnny size -= strlen(curr) + 1; 221670025d76Sjohnny curr += strlen(curr) + 1; 22177c478bd9Sstevel@tonic-gate 22187c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 22197c478bd9Sstevel@tonic-gate "compatible", compat, i); 22207c478bd9Sstevel@tonic-gate kmem_free(buf, COMPAT_BUFSIZE); 22217c478bd9Sstevel@tonic-gate } 22227c478bd9Sstevel@tonic-gate 22237c478bd9Sstevel@tonic-gate /* 22247c478bd9Sstevel@tonic-gate * Adjust the reg properties for a dual channel PCI-IDE device. 22257c478bd9Sstevel@tonic-gate * 22267c478bd9Sstevel@tonic-gate * NOTE: don't do anything that changes the order of the hard-decodes 22277c478bd9Sstevel@tonic-gate * and programmed BARs. The kernel driver depends on these values 22287c478bd9Sstevel@tonic-gate * being in this order regardless of whether they're for a 'native' 22297c478bd9Sstevel@tonic-gate * mode BAR or not. 22307c478bd9Sstevel@tonic-gate */ 22317c478bd9Sstevel@tonic-gate /* 22327c478bd9Sstevel@tonic-gate * config info for pci-ide devices 22337c478bd9Sstevel@tonic-gate */ 22347c478bd9Sstevel@tonic-gate static struct { 22357c478bd9Sstevel@tonic-gate uchar_t native_mask; /* 0 == 'compatibility' mode, 1 == native */ 22367c478bd9Sstevel@tonic-gate uchar_t bar_offset; /* offset for alt status register */ 22377c478bd9Sstevel@tonic-gate ushort_t addr; /* compatibility mode base address */ 22387c478bd9Sstevel@tonic-gate ushort_t length; /* number of ports for this BAR */ 22397c478bd9Sstevel@tonic-gate } pciide_bar[] = { 22407c478bd9Sstevel@tonic-gate { 0x01, 0, 0x1f0, 8 }, /* primary lower BAR */ 22417c478bd9Sstevel@tonic-gate { 0x01, 2, 0x3f6, 1 }, /* primary upper BAR */ 22427c478bd9Sstevel@tonic-gate { 0x04, 0, 0x170, 8 }, /* secondary lower BAR */ 22437c478bd9Sstevel@tonic-gate { 0x04, 2, 0x376, 1 } /* secondary upper BAR */ 22447c478bd9Sstevel@tonic-gate }; 22457c478bd9Sstevel@tonic-gate 22467c478bd9Sstevel@tonic-gate static int 22477c478bd9Sstevel@tonic-gate pciIdeAdjustBAR(uchar_t progcl, int index, uint_t *basep, uint_t *lenp) 22487c478bd9Sstevel@tonic-gate { 22497c478bd9Sstevel@tonic-gate int hard_decode = 0; 22507c478bd9Sstevel@tonic-gate 22517c478bd9Sstevel@tonic-gate /* 22527c478bd9Sstevel@tonic-gate * Adjust the base and len for the BARs of the PCI-IDE 22537c478bd9Sstevel@tonic-gate * device's primary and secondary controllers. The first 22547c478bd9Sstevel@tonic-gate * two BARs are for the primary controller and the next 22557c478bd9Sstevel@tonic-gate * two BARs are for the secondary controller. The fifth 22567c478bd9Sstevel@tonic-gate * and sixth bars are never adjusted. 22577c478bd9Sstevel@tonic-gate */ 22587c478bd9Sstevel@tonic-gate if (index >= 0 && index <= 3) { 22597c478bd9Sstevel@tonic-gate *lenp = pciide_bar[index].length; 22607c478bd9Sstevel@tonic-gate 22617c478bd9Sstevel@tonic-gate if (progcl & pciide_bar[index].native_mask) { 22627c478bd9Sstevel@tonic-gate *basep += pciide_bar[index].bar_offset; 22637c478bd9Sstevel@tonic-gate } else { 22647c478bd9Sstevel@tonic-gate *basep = pciide_bar[index].addr; 22657c478bd9Sstevel@tonic-gate hard_decode = 1; 22667c478bd9Sstevel@tonic-gate } 22677c478bd9Sstevel@tonic-gate } 22687c478bd9Sstevel@tonic-gate 22697c478bd9Sstevel@tonic-gate /* 22707c478bd9Sstevel@tonic-gate * if either base or len is zero make certain both are zero 22717c478bd9Sstevel@tonic-gate */ 22727c478bd9Sstevel@tonic-gate if (*basep == 0 || *lenp == 0) { 22737c478bd9Sstevel@tonic-gate *basep = 0; 22747c478bd9Sstevel@tonic-gate *lenp = 0; 22757c478bd9Sstevel@tonic-gate hard_decode = 0; 22767c478bd9Sstevel@tonic-gate } 22777c478bd9Sstevel@tonic-gate 22787c478bd9Sstevel@tonic-gate return (hard_decode); 22797c478bd9Sstevel@tonic-gate } 22807c478bd9Sstevel@tonic-gate 22817c478bd9Sstevel@tonic-gate 22827c478bd9Sstevel@tonic-gate /* 22837c478bd9Sstevel@tonic-gate * Add the "reg" and "assigned-addresses" property 22847c478bd9Sstevel@tonic-gate */ 22857c478bd9Sstevel@tonic-gate static int 22867c478bd9Sstevel@tonic-gate add_reg_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 22877c478bd9Sstevel@tonic-gate int config_op, int pciide) 22887c478bd9Sstevel@tonic-gate { 22897c478bd9Sstevel@tonic-gate uchar_t baseclass, subclass, progclass, header; 22907c478bd9Sstevel@tonic-gate ushort_t bar_sz; 22917c478bd9Sstevel@tonic-gate uint_t value = 0, len, devloc; 22927c478bd9Sstevel@tonic-gate uint_t base, base_hi, type; 22937c478bd9Sstevel@tonic-gate ushort_t offset, end; 22947c478bd9Sstevel@tonic-gate int max_basereg, j, reprogram = 0; 22957c478bd9Sstevel@tonic-gate uint_t phys_hi; 22962f283da5SDan Mick struct memlist **io_avail, **io_used; 22972f283da5SDan Mick struct memlist **mem_avail, **mem_used; 22982f283da5SDan Mick struct memlist **pmem_avail, **pmem_used; 229905f867c3Sgs uchar_t res_bus; 23007c478bd9Sstevel@tonic-gate 23017c478bd9Sstevel@tonic-gate pci_regspec_t regs[16] = {{0}}; 23027c478bd9Sstevel@tonic-gate pci_regspec_t assigned[15] = {{0}}; 2303c8711d4dSgs int nreg, nasgn; 23047c478bd9Sstevel@tonic-gate 23052f283da5SDan Mick io_avail = &pci_bus_res[bus].io_avail; 23062f283da5SDan Mick io_used = &pci_bus_res[bus].io_used; 23072f283da5SDan Mick mem_avail = &pci_bus_res[bus].mem_avail; 23082f283da5SDan Mick mem_used = &pci_bus_res[bus].mem_used; 23092f283da5SDan Mick pmem_avail = &pci_bus_res[bus].pmem_avail; 23102f283da5SDan Mick pmem_used = &pci_bus_res[bus].pmem_used; 23117c478bd9Sstevel@tonic-gate 23127c478bd9Sstevel@tonic-gate devloc = (uint_t)bus << 16 | (uint_t)dev << 11 | (uint_t)func << 8; 23137c478bd9Sstevel@tonic-gate regs[0].pci_phys_hi = devloc; 23147c478bd9Sstevel@tonic-gate nreg = 1; /* rest of regs[0] is all zero */ 23157c478bd9Sstevel@tonic-gate nasgn = 0; 23167c478bd9Sstevel@tonic-gate 23177c478bd9Sstevel@tonic-gate baseclass = pci_getb(bus, dev, func, PCI_CONF_BASCLASS); 23187c478bd9Sstevel@tonic-gate subclass = pci_getb(bus, dev, func, PCI_CONF_SUBCLASS); 23197c478bd9Sstevel@tonic-gate progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 23207c478bd9Sstevel@tonic-gate header = pci_getb(bus, dev, func, PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 23217c478bd9Sstevel@tonic-gate 23227c478bd9Sstevel@tonic-gate switch (header) { 23237c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 23247c478bd9Sstevel@tonic-gate max_basereg = PCI_BASE_NUM; 23257c478bd9Sstevel@tonic-gate break; 23267c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 23277c478bd9Sstevel@tonic-gate max_basereg = PCI_BCNF_BASE_NUM; 23287c478bd9Sstevel@tonic-gate break; 23297c478bd9Sstevel@tonic-gate case PCI_HEADER_CARDBUS: 23307c478bd9Sstevel@tonic-gate max_basereg = PCI_CBUS_BASE_NUM; 2331ffa17327SGuoli Shu reprogram = 1; 23327c478bd9Sstevel@tonic-gate break; 23337c478bd9Sstevel@tonic-gate default: 23347c478bd9Sstevel@tonic-gate max_basereg = 0; 23357c478bd9Sstevel@tonic-gate break; 23367c478bd9Sstevel@tonic-gate } 23377c478bd9Sstevel@tonic-gate 23387c478bd9Sstevel@tonic-gate /* 23397c478bd9Sstevel@tonic-gate * Create the register property by saving the current 23408d34f104Smyers * value of the base register. Write 0xffffffff to the 23418d34f104Smyers * base register. Read the value back to determine the 23428d34f104Smyers * required size of the address space. Restore the base 23438d34f104Smyers * register contents. 23448d34f104Smyers * 23458d34f104Smyers * Do not disable I/O and memory access; this isn't necessary 23468d34f104Smyers * since no driver is yet attached to this device, and disabling 23478d34f104Smyers * I/O and memory access has the side-effect of disabling PCI-PCI 23488d34f104Smyers * bridge mappings, which makes the bridge transparent to secondary- 23498d34f104Smyers * bus activity (see sections 4.1-4.3 of the PCI-PCI Bridge 23508d34f104Smyers * Spec V1.2). 23517c478bd9Sstevel@tonic-gate */ 23527c478bd9Sstevel@tonic-gate end = PCI_CONF_BASE0 + max_basereg * sizeof (uint_t); 23537c478bd9Sstevel@tonic-gate for (j = 0, offset = PCI_CONF_BASE0; offset < end; 23547c478bd9Sstevel@tonic-gate j++, offset += bar_sz) { 23557c478bd9Sstevel@tonic-gate /* determine the size of the address space */ 23567c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 23577c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 0xffffffff); 23587c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 23597c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 23607c478bd9Sstevel@tonic-gate 23617c478bd9Sstevel@tonic-gate /* construct phys hi,med.lo, size hi, lo */ 23627c478bd9Sstevel@tonic-gate if ((pciide && j < 4) || (base & PCI_BASE_SPACE_IO)) { 23633e98767bSMax zhen int hard_decode = 0; 23643e98767bSMax zhen 23657c478bd9Sstevel@tonic-gate /* i/o space */ 23667c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 23677c478bd9Sstevel@tonic-gate value &= PCI_BASE_IO_ADDR_M; 23687c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 23697c478bd9Sstevel@tonic-gate 23707c478bd9Sstevel@tonic-gate /* XXX Adjust first 4 IDE registers */ 23717c478bd9Sstevel@tonic-gate if (pciide) { 2372f088817aSyt if (subclass != PCI_MASS_IDE) 23737c478bd9Sstevel@tonic-gate progclass = (PCI_IDE_IF_NATIVE_PRI | 23747c478bd9Sstevel@tonic-gate PCI_IDE_IF_NATIVE_SEC); 23757c478bd9Sstevel@tonic-gate hard_decode = pciIdeAdjustBAR(progclass, j, 23767c478bd9Sstevel@tonic-gate &base, &len); 23777c478bd9Sstevel@tonic-gate } else if (value == 0) { 23787c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 23797c478bd9Sstevel@tonic-gate continue; 23807c478bd9Sstevel@tonic-gate } 23817c478bd9Sstevel@tonic-gate 23823e98767bSMax zhen regs[nreg].pci_phys_hi = PCI_ADDR_IO | devloc | 23833e98767bSMax zhen (hard_decode ? PCI_RELOCAT_B : offset); 23843e98767bSMax zhen regs[nreg].pci_phys_low = hard_decode ? 23853e98767bSMax zhen base & PCI_BASE_IO_ADDR_M : 0; 23863e98767bSMax zhen assigned[nasgn].pci_phys_hi = 23873e98767bSMax zhen PCI_RELOCAT_B | regs[nreg].pci_phys_hi; 23887c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 23897c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 23907c478bd9Sstevel@tonic-gate type = base & (~PCI_BASE_IO_ADDR_M); 23917c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 239205f867c3Sgs /* 239305f867c3Sgs * A device under a subtractive PPB can allocate 239405f867c3Sgs * resources from its parent bus if there is no resource 239505f867c3Sgs * available on its own bus. 239605f867c3Sgs */ 23972f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*io_avail == NULL)) { 239805f867c3Sgs res_bus = bus; 239905f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 240005f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 240105f867c3Sgs if (res_bus == (uchar_t)-1) 240205f867c3Sgs break; /* root bus already */ 24032f283da5SDan Mick if (pci_bus_res[res_bus].io_avail) { 24042f283da5SDan Mick io_avail = &pci_bus_res 24052f283da5SDan Mick [res_bus].io_avail; 240605f867c3Sgs break; 240705f867c3Sgs } 240805f867c3Sgs } 240905f867c3Sgs } 24107c478bd9Sstevel@tonic-gate 24117c478bd9Sstevel@tonic-gate /* 24127c478bd9Sstevel@tonic-gate * first pass - gather what's there 24137c478bd9Sstevel@tonic-gate * update/second pass - adjust/allocate regions 24147c478bd9Sstevel@tonic-gate * config - allocate regions 24157c478bd9Sstevel@tonic-gate */ 24167c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { /* first pass */ 24177c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 241805f867c3Sgs if (base != 0) { 24192f283da5SDan Mick (void) memlist_remove(io_avail, base, 24208fc7923fSDana Myers len); 24212f283da5SDan Mick memlist_insert(io_used, base, len); 2422ffa17327SGuoli Shu } else { 24237c478bd9Sstevel@tonic-gate reprogram = 1; 2424ffa17327SGuoli Shu } 2425ffa17327SGuoli Shu pci_bus_res[bus].io_size += len; 24262f283da5SDan Mick } else if ((*io_avail && base == 0) || 242705f867c3Sgs pci_bus_res[bus].io_reprogram) { 24282f283da5SDan Mick base = (uint_t)memlist_find(io_avail, len, len); 24297c478bd9Sstevel@tonic-gate if (base != 0) { 24302f283da5SDan Mick memlist_insert(io_used, base, len); 24317c478bd9Sstevel@tonic-gate /* XXX need to worry about 64-bit? */ 24327c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 24337c478bd9Sstevel@tonic-gate base | type); 24347c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 24357c478bd9Sstevel@tonic-gate base &= PCI_BASE_IO_ADDR_M; 24367c478bd9Sstevel@tonic-gate } 24377c478bd9Sstevel@tonic-gate if (base == 0) { 24387c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program" 2439db063408Sdmick " IO space [%d/%d/%d] BAR@0x%x" 2440db063408Sdmick " length 0x%x", 2441ebf3afa8Sdmick bus, dev, func, offset, len); 2442c8711d4dSgs } 24437c478bd9Sstevel@tonic-gate } 24447c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 24457c478bd9Sstevel@tonic-gate nreg++, nasgn++; 24467c478bd9Sstevel@tonic-gate 24477c478bd9Sstevel@tonic-gate } else { 24487c478bd9Sstevel@tonic-gate /* memory space */ 24497c478bd9Sstevel@tonic-gate if ((base & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) { 24507c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_64; 24517c478bd9Sstevel@tonic-gate base_hi = pci_getl(bus, dev, func, offset + 4); 24527c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM64; 24537c478bd9Sstevel@tonic-gate } else { 24547c478bd9Sstevel@tonic-gate bar_sz = PCI_BAR_SZ_32; 24557c478bd9Sstevel@tonic-gate base_hi = 0; 24567c478bd9Sstevel@tonic-gate phys_hi = PCI_ADDR_MEM32; 24577c478bd9Sstevel@tonic-gate } 24587c478bd9Sstevel@tonic-gate 24597c478bd9Sstevel@tonic-gate /* skip base regs with size of 0 */ 24607c478bd9Sstevel@tonic-gate value &= PCI_BASE_M_ADDR_M; 24617c478bd9Sstevel@tonic-gate 24628fc7923fSDana Myers if (value == 0) 24637c478bd9Sstevel@tonic-gate continue; 24648fc7923fSDana Myers 24657c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 24667c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 24677c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = len; 24687c478bd9Sstevel@tonic-gate 24697c478bd9Sstevel@tonic-gate phys_hi |= (devloc | offset); 24708fc7923fSDana Myers if (base & PCI_BASE_PREF_M) 24717c478bd9Sstevel@tonic-gate phys_hi |= PCI_PREFETCH_B; 24728fc7923fSDana Myers 247305f867c3Sgs /* 247405f867c3Sgs * A device under a subtractive PPB can allocate 247505f867c3Sgs * resources from its parent bus if there is no resource 247605f867c3Sgs * available on its own bus. 247705f867c3Sgs */ 24782f283da5SDan Mick if ((config_op == CONFIG_NEW) && (*mem_avail == NULL)) { 247905f867c3Sgs res_bus = bus; 248005f867c3Sgs while (pci_bus_res[res_bus].subtractive) { 248105f867c3Sgs res_bus = pci_bus_res[res_bus].par_bus; 248205f867c3Sgs if (res_bus == (uchar_t)-1) 248305f867c3Sgs break; /* root bus already */ 24842f283da5SDan Mick mem_avail = 24852f283da5SDan Mick &pci_bus_res[res_bus].mem_avail; 24862f283da5SDan Mick pmem_avail = 24872f283da5SDan Mick &pci_bus_res [res_bus].pmem_avail; 24888fc7923fSDana Myers /* 24898fc7923fSDana Myers * Break out as long as at least 24902f283da5SDan Mick * mem_avail is available 24918fc7923fSDana Myers */ 24922f283da5SDan Mick if ((*pmem_avail && 24938fc7923fSDana Myers (phys_hi & PCI_PREFETCH_B)) || 24942f283da5SDan Mick *mem_avail) 249505f867c3Sgs break; 249605f867c3Sgs } 249705f867c3Sgs } 249805f867c3Sgs 24997c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = 25007c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = phys_hi; 25017c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi |= PCI_RELOCAT_B; 25027c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_mid = base_hi; 25037c478bd9Sstevel@tonic-gate type = base & ~PCI_BASE_M_ADDR_M; 25047c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 25057c478bd9Sstevel@tonic-gate 25067c478bd9Sstevel@tonic-gate if (config_op == CONFIG_INFO) { 25077c478bd9Sstevel@tonic-gate /* take out of the resource map of the bus */ 25088fc7923fSDana Myers if (base != NULL) { 25098fc7923fSDana Myers /* remove from PMEM and MEM space */ 25102f283da5SDan Mick (void) memlist_remove(mem_avail, 25118fc7923fSDana Myers base, len); 25122f283da5SDan Mick (void) memlist_remove(pmem_avail, 25138fc7923fSDana Myers base, len); 25148fc7923fSDana Myers /* only note as used in correct map */ 25158fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) 25162f283da5SDan Mick memlist_insert(pmem_used, 251705f867c3Sgs base, len); 25188fc7923fSDana Myers else 25192f283da5SDan Mick memlist_insert(mem_used, 252086ce93f0SGuoli Shu base, len); 2521ffa17327SGuoli Shu } else { 25227c478bd9Sstevel@tonic-gate reprogram = 1; 2523ffa17327SGuoli Shu } 2524ffa17327SGuoli Shu pci_bus_res[bus].mem_size += len; 25252f283da5SDan Mick } else if ((*mem_avail && base == NULL) || 252605f867c3Sgs pci_bus_res[bus].mem_reprogram) { 25278fc7923fSDana Myers /* 25288fc7923fSDana Myers * When desired, attempt a prefetchable 25298fc7923fSDana Myers * allocation first 25308fc7923fSDana Myers */ 25318fc7923fSDana Myers if (phys_hi & PCI_PREFETCH_B) { 25322f283da5SDan Mick base = (uint_t)memlist_find(pmem_avail, 25338fc7923fSDana Myers len, len); 25348fc7923fSDana Myers if (base != NULL) { 25352f283da5SDan Mick memlist_insert(pmem_used, 25368fc7923fSDana Myers base, len); 25372f283da5SDan Mick (void) memlist_remove(mem_avail, 253886ce93f0SGuoli Shu base, len); 25398fc7923fSDana Myers } 25408fc7923fSDana Myers } 25418fc7923fSDana Myers /* 25428fc7923fSDana Myers * If prefetchable allocation was not 25438fc7923fSDana Myers * desired, or failed, attempt ordinary 25448fc7923fSDana Myers * memory allocation 25458fc7923fSDana Myers */ 25468fc7923fSDana Myers if (base == NULL) { 25472f283da5SDan Mick base = (uint_t)memlist_find(mem_avail, 25488fc7923fSDana Myers len, len); 25498fc7923fSDana Myers if (base != NULL) { 25502f283da5SDan Mick memlist_insert(mem_used, 255186ce93f0SGuoli Shu base, len); 25522f283da5SDan Mick (void) memlist_remove( 25532f283da5SDan Mick pmem_avail, base, len); 255486ce93f0SGuoli Shu } 25558fc7923fSDana Myers } 25568fc7923fSDana Myers if (base != NULL) { 25577c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, 25587c478bd9Sstevel@tonic-gate base | type); 25597c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 25607c478bd9Sstevel@tonic-gate base &= PCI_BASE_M_ADDR_M; 25618fc7923fSDana Myers } else 25627c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "failed to program " 2563ebf3afa8Sdmick "mem space [%d/%d/%d] BAR@0x%x" 2564db063408Sdmick " length 0x%x", 2565ebf3afa8Sdmick bus, dev, func, offset, len); 25667c478bd9Sstevel@tonic-gate } 25677c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 25687c478bd9Sstevel@tonic-gate nreg++, nasgn++; 25697c478bd9Sstevel@tonic-gate } 25707c478bd9Sstevel@tonic-gate } 25717c478bd9Sstevel@tonic-gate switch (header) { 25727c478bd9Sstevel@tonic-gate case PCI_HEADER_ZERO: 25737c478bd9Sstevel@tonic-gate offset = PCI_CONF_ROM; 25747c478bd9Sstevel@tonic-gate break; 25757c478bd9Sstevel@tonic-gate case PCI_HEADER_PPB: 25767c478bd9Sstevel@tonic-gate offset = PCI_BCNF_ROM; 25777c478bd9Sstevel@tonic-gate break; 25787c478bd9Sstevel@tonic-gate default: /* including PCI_HEADER_CARDBUS */ 25797c478bd9Sstevel@tonic-gate goto done; 25807c478bd9Sstevel@tonic-gate } 25817c478bd9Sstevel@tonic-gate 25827c478bd9Sstevel@tonic-gate /* 25837c478bd9Sstevel@tonic-gate * Add the expansion rom memory space 25847c478bd9Sstevel@tonic-gate * Determine the size of the ROM base reg; don't write reserved bits 25857c478bd9Sstevel@tonic-gate * ROM isn't in the PCI memory space. 25867c478bd9Sstevel@tonic-gate */ 25877c478bd9Sstevel@tonic-gate base = pci_getl(bus, dev, func, offset); 25887c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, PCI_BASE_ROM_ADDR_M); 25897c478bd9Sstevel@tonic-gate value = pci_getl(bus, dev, func, offset); 25907c478bd9Sstevel@tonic-gate pci_putl(bus, dev, func, offset, base); 259170025d76Sjohnny if (value & PCI_BASE_ROM_ENABLE) 259270025d76Sjohnny value &= PCI_BASE_ROM_ADDR_M; 259370025d76Sjohnny else 259470025d76Sjohnny value = 0; 25957c478bd9Sstevel@tonic-gate 25967c478bd9Sstevel@tonic-gate if (value != 0) { 25977c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = (PCI_ADDR_MEM32 | devloc) + offset; 25987c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_hi = (PCI_RELOCAT_B | 25997c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | devloc) + offset; 26007c478bd9Sstevel@tonic-gate base &= PCI_BASE_ROM_ADDR_M; 26017c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = base; 26027c478bd9Sstevel@tonic-gate len = ((value ^ (value-1)) + 1) >> 1; 26037c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = len; 26047c478bd9Sstevel@tonic-gate nreg++, nasgn++; 260599ed6083Sszhou /* take it out of the memory resource */ 26068fc7923fSDana Myers if (base != NULL) { 26072f283da5SDan Mick (void) memlist_remove(mem_avail, base, len); 26082f283da5SDan Mick memlist_insert(mem_used, base, len); 26092f283da5SDan Mick pci_bus_res[bus].mem_size += len; 26108fc7923fSDana Myers } 26117c478bd9Sstevel@tonic-gate } 26127c478bd9Sstevel@tonic-gate 26137c478bd9Sstevel@tonic-gate /* 26148fc7923fSDana Myers * Account for "legacy" (alias) video adapter resources 26157c478bd9Sstevel@tonic-gate */ 26167c478bd9Sstevel@tonic-gate 26177c478bd9Sstevel@tonic-gate /* add the three hard-decode, aliased address spaces for VGA */ 26187c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY && subclass == PCI_DISPLAY_VGA) || 26197c478bd9Sstevel@tonic-gate (baseclass == PCI_CLASS_NONE && subclass == PCI_NONE_VGA)) { 26207c478bd9Sstevel@tonic-gate 26217c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3b0-0x3bb */ 26227c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26237c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26247c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3b0; 26257c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0xc; 26267c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26272f283da5SDan Mick (void) memlist_remove(io_avail, 0x3b0, 0xc); 26282f283da5SDan Mick memlist_insert(io_used, 0x3b0, 0xc); 26292f283da5SDan Mick pci_bus_res[bus].io_size += 0xc; 26307c478bd9Sstevel@tonic-gate 26317c478bd9Sstevel@tonic-gate /* VGA hard decode 0x3c0-0x3df */ 26327c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26337c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26347c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x3c0; 26357c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x20; 26367c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26372f283da5SDan Mick (void) memlist_remove(io_avail, 0x3c0, 0x20); 26382f283da5SDan Mick memlist_insert(io_used, 0x3c0, 0x20); 26392f283da5SDan Mick pci_bus_res[bus].io_size += 0x20; 26407c478bd9Sstevel@tonic-gate 26417c478bd9Sstevel@tonic-gate /* Video memory */ 26427c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26433e98767bSMax zhen (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_MEM32 | devloc); 26447c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = 26457c478bd9Sstevel@tonic-gate assigned[nasgn].pci_phys_low = 0xa0000; 26467c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = 26477c478bd9Sstevel@tonic-gate assigned[nasgn].pci_size_low = 0x20000; 26487c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26498fc7923fSDana Myers /* remove from MEM and PMEM space */ 26502f283da5SDan Mick (void) memlist_remove(mem_avail, 0xa0000, 0x20000); 26512f283da5SDan Mick (void) memlist_remove(pmem_avail, 0xa0000, 0x20000); 26522f283da5SDan Mick memlist_insert(mem_used, 0xa0000, 0x20000); 26532f283da5SDan Mick pci_bus_res[bus].mem_size += 0x20000; 26547c478bd9Sstevel@tonic-gate } 26557c478bd9Sstevel@tonic-gate 26567c478bd9Sstevel@tonic-gate /* add the hard-decode, aliased address spaces for 8514 */ 26577c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_DISPLAY) && 26589896aa55Sjveta (subclass == PCI_DISPLAY_VGA) && 26599896aa55Sjveta (progclass & PCI_DISPLAY_IF_8514)) { 26607c478bd9Sstevel@tonic-gate 26617c478bd9Sstevel@tonic-gate /* hard decode 0x2e8 */ 26627c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26637c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26647c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2e8; 26657c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x1; 26667c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26672f283da5SDan Mick (void) memlist_remove(io_avail, 0x2e8, 0x1); 26682f283da5SDan Mick memlist_insert(io_used, 0x2e8, 0x1); 26692f283da5SDan Mick pci_bus_res[bus].io_size += 0x1; 26707c478bd9Sstevel@tonic-gate 26717c478bd9Sstevel@tonic-gate /* hard decode 0x2ea-0x2ef */ 26727c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_hi = assigned[nasgn].pci_phys_hi = 26737c478bd9Sstevel@tonic-gate (PCI_RELOCAT_B | PCI_ALIAS_B | PCI_ADDR_IO | devloc); 26747c478bd9Sstevel@tonic-gate regs[nreg].pci_phys_low = assigned[nasgn].pci_phys_low = 0x2ea; 26757c478bd9Sstevel@tonic-gate regs[nreg].pci_size_low = assigned[nasgn].pci_size_low = 0x6; 26767c478bd9Sstevel@tonic-gate nreg++, nasgn++; 26772f283da5SDan Mick (void) memlist_remove(io_avail, 0x2ea, 0x6); 26782f283da5SDan Mick memlist_insert(io_used, 0x2ea, 0x6); 26792f283da5SDan Mick pci_bus_res[bus].io_size += 0x6; 26807c478bd9Sstevel@tonic-gate } 26817c478bd9Sstevel@tonic-gate 26827c478bd9Sstevel@tonic-gate done: 26837c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 26847c478bd9Sstevel@tonic-gate (int *)regs, nreg * sizeof (pci_regspec_t) / sizeof (int)); 26857c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 26867c478bd9Sstevel@tonic-gate "assigned-addresses", 26877c478bd9Sstevel@tonic-gate (int *)assigned, nasgn * sizeof (pci_regspec_t) / sizeof (int)); 2688c8711d4dSgs 26897c478bd9Sstevel@tonic-gate return (reprogram); 26907c478bd9Sstevel@tonic-gate } 26917c478bd9Sstevel@tonic-gate 26927c478bd9Sstevel@tonic-gate static void 269370025d76Sjohnny add_ppb_props(dev_info_t *dip, uchar_t bus, uchar_t dev, uchar_t func, 269449fbdd30SErwin T Tsaur int pciex, ushort_t is_pci_bridge) 26957c478bd9Sstevel@tonic-gate { 269670025d76Sjohnny char *dev_type; 26977c478bd9Sstevel@tonic-gate int i; 26987c478bd9Sstevel@tonic-gate uint_t val, io_range[2], mem_range[2], pmem_range[2]; 26997c478bd9Sstevel@tonic-gate uchar_t secbus = pci_getb(bus, dev, func, PCI_BCNF_SECBUS); 27007c478bd9Sstevel@tonic-gate uchar_t subbus = pci_getb(bus, dev, func, PCI_BCNF_SUBBUS); 270105f867c3Sgs uchar_t progclass; 270205f867c3Sgs 2703f55ce205Sszhou ASSERT(secbus <= subbus); 27047c478bd9Sstevel@tonic-gate 270505f867c3Sgs /* 270605f867c3Sgs * Check if it's a subtractive PPB. 270705f867c3Sgs */ 270805f867c3Sgs progclass = pci_getb(bus, dev, func, PCI_CONF_PROGCLASS); 270905f867c3Sgs if (progclass == PCI_BRIDGE_PCI_IF_SUBDECODE) 271005f867c3Sgs pci_bus_res[secbus].subtractive = B_TRUE; 271105f867c3Sgs 2712f55ce205Sszhou /* 2713f55ce205Sszhou * Some BIOSes lie about max pci busses, we allow for 2714f55ce205Sszhou * such mistakes here 2715f55ce205Sszhou */ 2716f55ce205Sszhou if (subbus > pci_bios_nbus) { 2717f55ce205Sszhou pci_bios_nbus = subbus; 2718f55ce205Sszhou alloc_res_array(); 2719f55ce205Sszhou } 2720f55ce205Sszhou 2721f55ce205Sszhou ASSERT(pci_bus_res[secbus].dip == NULL); 27227c478bd9Sstevel@tonic-gate pci_bus_res[secbus].dip = dip; 27237c478bd9Sstevel@tonic-gate pci_bus_res[secbus].par_bus = bus; 27247c478bd9Sstevel@tonic-gate 272549fbdd30SErwin T Tsaur dev_type = (pciex && !is_pci_bridge) ? "pciex" : "pci"; 272670025d76Sjohnny 27277c478bd9Sstevel@tonic-gate /* setup bus number hierarchy */ 27287c478bd9Sstevel@tonic-gate pci_bus_res[secbus].sub_bus = subbus; 272953273e82Ssethg /* 273053273e82Ssethg * Keep track of the largest subordinate bus number (this is essential 273153273e82Ssethg * for peer busses because there is no other way of determining its 273253273e82Ssethg * subordinate bus number). 273353273e82Ssethg */ 27347c478bd9Sstevel@tonic-gate if (subbus > pci_bus_res[bus].sub_bus) 27357c478bd9Sstevel@tonic-gate pci_bus_res[bus].sub_bus = subbus; 273653273e82Ssethg /* 273753273e82Ssethg * Loop through subordinate busses, initializing their parent bus 273853273e82Ssethg * field to this bridge's parent. The subordinate busses' parent 273953273e82Ssethg * fields may very well be further refined later, as child bridges 274053273e82Ssethg * are enumerated. (The value is to note that the subordinate busses 274153273e82Ssethg * are not peer busses by changing their par_bus fields to anything 274253273e82Ssethg * other than -1.) 274353273e82Ssethg */ 27447c478bd9Sstevel@tonic-gate for (i = secbus + 1; i <= subbus; i++) 27457c478bd9Sstevel@tonic-gate pci_bus_res[i].par_bus = bus; 27467c478bd9Sstevel@tonic-gate 27477c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 274870025d76Sjohnny "device_type", dev_type); 27497c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 27507c478bd9Sstevel@tonic-gate "#address-cells", 3); 27517c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 27527c478bd9Sstevel@tonic-gate "#size-cells", 2); 27537c478bd9Sstevel@tonic-gate 27547c478bd9Sstevel@tonic-gate /* 27552f283da5SDan Mick * Collect bridge window specifications, and use them to populate 27562f283da5SDan Mick * the "avail" resources for the bus. Not all of those resources will 27572f283da5SDan Mick * end up being available; this is done top-down, and so the initial 27582f283da5SDan Mick * collection of windows populates the 'ranges' property for the 27592f283da5SDan Mick * bus node. Later, as children are found, resources are removed from 27602f283da5SDan Mick * the 'avail' list, so that it becomes the freelist for 27612f283da5SDan Mick * this point in the tree. ranges may be set again after bridge 27622f283da5SDan Mick * reprogramming in fix_ppb_res(), in which case it's set from 27632f283da5SDan Mick * used + avail. 27642f283da5SDan Mick * 27657c478bd9Sstevel@tonic-gate * According to PPB spec, the base register should be programmed 27667c478bd9Sstevel@tonic-gate * with a value bigger than the limit register when there are 27677c478bd9Sstevel@tonic-gate * no resources available. This applies to io, memory, and 27687c478bd9Sstevel@tonic-gate * prefetchable memory. 27697c478bd9Sstevel@tonic-gate */ 27709896aa55Sjveta 27719896aa55Sjveta /* 27729896aa55Sjveta * io range 277305f867c3Sgs * We determine i/o windows that are left unconfigured by BIOS 27749896aa55Sjveta * through its i/o enable bit as Microsoft recommends OEMs to do. 27759896aa55Sjveta * If it is unset, we disable i/o and mark it for reconfiguration in 27769896aa55Sjveta * later passes by setting the base > limit 27779896aa55Sjveta */ 27789896aa55Sjveta val = (uint_t)pci_getw(bus, dev, func, PCI_CONF_COMM); 27799896aa55Sjveta if (val & PCI_COMM_IO) { 27809896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_BASE_LOW); 27819896aa55Sjveta io_range[0] = ((val & 0xf0) << 8); 27829896aa55Sjveta val = (uint_t)pci_getb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW); 27839896aa55Sjveta io_range[1] = ((val & 0xf0) << 8) | 0xFFF; 27849896aa55Sjveta } else { 27859896aa55Sjveta io_range[0] = 0x9fff; 27869896aa55Sjveta io_range[1] = 0x1000; 27879896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_BASE_LOW, 27889896aa55Sjveta (uint8_t)((io_range[0] >> 8) & 0xf0)); 27899896aa55Sjveta pci_putb(bus, dev, func, PCI_BCNF_IO_LIMIT_LOW, 27909896aa55Sjveta (uint8_t)((io_range[1] >> 8) & 0xf0)); 27919896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_BASE_HI, 0); 27929896aa55Sjveta pci_putw(bus, dev, func, PCI_BCNF_IO_LIMIT_HI, 0); 27939896aa55Sjveta } 27949896aa55Sjveta 27957c478bd9Sstevel@tonic-gate if (io_range[0] != 0 && io_range[0] < io_range[1]) { 27962f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 27977c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 27987c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 27992f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 280005f867c3Sgs (uint64_t)io_range[0], 280105f867c3Sgs (uint64_t)(io_range[1] - io_range[0] + 1)); 28022f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28032f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28047c478bd9Sstevel@tonic-gate (uint64_t)io_range[0], 28057c478bd9Sstevel@tonic-gate (uint64_t)(io_range[1] - io_range[0] + 1)); 28067c478bd9Sstevel@tonic-gate } 28077c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d io-range: 0x%x-%x", 28087c478bd9Sstevel@tonic-gate secbus, io_range[0], io_range[1]); 28092269adc8Sszhou /* if 32-bit supported, make sure upper bits are not set */ 28102269adc8Sszhou if ((val & 0xf) == 1 && 28112269adc8Sszhou pci_getw(bus, dev, func, PCI_BCNF_IO_BASE_HI)) { 28122269adc8Sszhou cmn_err(CE_NOTE, "unsupported 32-bit IO address on" 28132269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 28142269adc8Sszhou } 28157c478bd9Sstevel@tonic-gate } 28167c478bd9Sstevel@tonic-gate 28177c478bd9Sstevel@tonic-gate /* mem range */ 28187c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_BASE); 28197c478bd9Sstevel@tonic-gate mem_range[0] = ((val & 0xFFF0) << 16); 28207c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_MEM_LIMIT); 28217c478bd9Sstevel@tonic-gate mem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 28227c478bd9Sstevel@tonic-gate if (mem_range[0] != 0 && mem_range[0] < mem_range[1]) { 28232f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 28247c478bd9Sstevel@tonic-gate (uint64_t)mem_range[0], 28257c478bd9Sstevel@tonic-gate (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28262f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 282705f867c3Sgs (uint64_t)mem_range[0], 282805f867c3Sgs (uint64_t)(mem_range[1] - mem_range[0] + 1)); 282986ce93f0SGuoli Shu /* remove from parent resource list */ 28302f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 28318fc7923fSDana Myers (uint64_t)mem_range[0], 28328fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28332f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 28348fc7923fSDana Myers (uint64_t)mem_range[0], 28358fc7923fSDana Myers (uint64_t)(mem_range[1] - mem_range[0] + 1)); 28367c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d mem-range: 0x%x-%x", 28377c478bd9Sstevel@tonic-gate secbus, mem_range[0], mem_range[1]); 28387c478bd9Sstevel@tonic-gate } 28397c478bd9Sstevel@tonic-gate 28407c478bd9Sstevel@tonic-gate /* prefetchable memory range */ 28417c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_BASE_LOW); 28427c478bd9Sstevel@tonic-gate pmem_range[0] = ((val & 0xFFF0) << 16); 28437c478bd9Sstevel@tonic-gate val = (uint_t)pci_getw(bus, dev, func, PCI_BCNF_PF_LIMIT_LOW); 28447c478bd9Sstevel@tonic-gate pmem_range[1] = ((val & 0xFFF0) << 16) | 0xFFFFF; 28457c478bd9Sstevel@tonic-gate if (pmem_range[0] != 0 && pmem_range[0] < pmem_range[1]) { 28462f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].pmem_avail, 28477c478bd9Sstevel@tonic-gate (uint64_t)pmem_range[0], 28487c478bd9Sstevel@tonic-gate (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28492f283da5SDan Mick memlist_insert(&pci_bus_res[bus].pmem_used, 285005f867c3Sgs (uint64_t)pmem_range[0], 285105f867c3Sgs (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 285286ce93f0SGuoli Shu /* remove from parent resource list */ 28532f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].pmem_avail, 28548fc7923fSDana Myers (uint64_t)pmem_range[0], 28558fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28562f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 28578fc7923fSDana Myers (uint64_t)pmem_range[0], 28588fc7923fSDana Myers (uint64_t)(pmem_range[1] - pmem_range[0] + 1)); 28597c478bd9Sstevel@tonic-gate dcmn_err(CE_NOTE, "bus %d pmem-range: 0x%x-%x", 28607c478bd9Sstevel@tonic-gate secbus, pmem_range[0], pmem_range[1]); 28612269adc8Sszhou /* if 64-bit supported, make sure upper bits are not set */ 28622269adc8Sszhou if ((val & 0xf) == 1 && 28632269adc8Sszhou pci_getl(bus, dev, func, PCI_BCNF_PF_BASE_HIGH)) { 28642269adc8Sszhou cmn_err(CE_NOTE, "unsupported 64-bit prefetch memory on" 28652269adc8Sszhou " pci-pci bridge [%d/%d/%d]", bus, dev, func); 28662269adc8Sszhou } 28677c478bd9Sstevel@tonic-gate } 28687c478bd9Sstevel@tonic-gate 28692f283da5SDan Mick /* 28702f283da5SDan Mick * Add VGA legacy resources to the bridge's pci_bus_res if it 28712f283da5SDan Mick * has VGA_ENABLE set. Note that we put them in 'avail', 28722f283da5SDan Mick * because that's used to populate the ranges prop; they'll be 28732f283da5SDan Mick * removed from there by the VGA device once it's found. Also, 28742f283da5SDan Mick * remove them from the parent's available list and note them as 28752f283da5SDan Mick * used in the parent. 28762f283da5SDan Mick */ 28772f283da5SDan Mick 28782f283da5SDan Mick if (pci_getw(bus, dev, func, PCI_BCNF_BCNTRL) & 28792f283da5SDan Mick PCI_BCNF_BCNTRL_VGA_ENABLE) { 28802f283da5SDan Mick 28812f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3b0, 0xc); 28822f283da5SDan Mick 28832f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3b0, 0xc); 28842f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28852f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28862f283da5SDan Mick 0x3b0, 0xc); 28872f283da5SDan Mick } 28882f283da5SDan Mick 28892f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].io_avail, 0x3c0, 0x20); 28902f283da5SDan Mick 28912f283da5SDan Mick memlist_insert(&pci_bus_res[bus].io_used, 0x3c0, 0x20); 28922f283da5SDan Mick if (pci_bus_res[bus].io_avail != NULL) { 28932f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].io_avail, 28942f283da5SDan Mick 0x3c0, 0x20); 28952f283da5SDan Mick } 28962f283da5SDan Mick 28972f283da5SDan Mick memlist_insert(&pci_bus_res[secbus].mem_avail, 0xa0000, 28982f283da5SDan Mick 0x20000); 28992f283da5SDan Mick 29002f283da5SDan Mick memlist_insert(&pci_bus_res[bus].mem_used, 0xa0000, 0x20000); 29012f283da5SDan Mick if (pci_bus_res[bus].mem_avail != NULL) { 29022f283da5SDan Mick (void) memlist_remove(&pci_bus_res[bus].mem_avail, 29032f283da5SDan Mick 0xa0000, 0x20000); 29042f283da5SDan Mick } 29052f283da5SDan Mick } 29067c478bd9Sstevel@tonic-gate add_bus_range_prop(secbus); 29078fc7923fSDana Myers add_ranges_prop(secbus, 1); 29087c478bd9Sstevel@tonic-gate } 29097c478bd9Sstevel@tonic-gate 291009f67678Sanish extern const struct pci_class_strings_s class_pci[]; 291109f67678Sanish extern int class_pci_items; 29127c478bd9Sstevel@tonic-gate 29137c478bd9Sstevel@tonic-gate static void 29147c478bd9Sstevel@tonic-gate add_model_prop(dev_info_t *dip, uint_t classcode) 29157c478bd9Sstevel@tonic-gate { 29167c478bd9Sstevel@tonic-gate const char *desc; 29177c478bd9Sstevel@tonic-gate int i; 29187c478bd9Sstevel@tonic-gate uchar_t baseclass = classcode >> 16; 29197c478bd9Sstevel@tonic-gate uchar_t subclass = (classcode >> 8) & 0xff; 29207c478bd9Sstevel@tonic-gate uchar_t progclass = classcode & 0xff; 29217c478bd9Sstevel@tonic-gate 29227c478bd9Sstevel@tonic-gate if ((baseclass == PCI_CLASS_MASS) && (subclass == PCI_MASS_IDE)) { 29237c478bd9Sstevel@tonic-gate desc = "IDE controller"; 29247c478bd9Sstevel@tonic-gate } else { 29257c478bd9Sstevel@tonic-gate for (desc = 0, i = 0; i < class_pci_items; i++) { 29267c478bd9Sstevel@tonic-gate if ((baseclass == class_pci[i].base_class) && 29277c478bd9Sstevel@tonic-gate (subclass == class_pci[i].sub_class) && 29287c478bd9Sstevel@tonic-gate (progclass == class_pci[i].prog_class)) { 292909f67678Sanish desc = class_pci[i].actual_desc; 29307c478bd9Sstevel@tonic-gate break; 29317c478bd9Sstevel@tonic-gate } 29327c478bd9Sstevel@tonic-gate } 293309f67678Sanish if (i == class_pci_items) 29347c478bd9Sstevel@tonic-gate desc = "Unknown class of pci/pnpbios device"; 29357c478bd9Sstevel@tonic-gate } 29367c478bd9Sstevel@tonic-gate 29377c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 29387c478bd9Sstevel@tonic-gate (char *)desc); 29397c478bd9Sstevel@tonic-gate } 29407c478bd9Sstevel@tonic-gate 29417c478bd9Sstevel@tonic-gate static void 29427c478bd9Sstevel@tonic-gate add_bus_range_prop(int bus) 29437c478bd9Sstevel@tonic-gate { 29447c478bd9Sstevel@tonic-gate int bus_range[2]; 29457c478bd9Sstevel@tonic-gate 29467c478bd9Sstevel@tonic-gate if (pci_bus_res[bus].dip == NULL) 29477c478bd9Sstevel@tonic-gate return; 29487c478bd9Sstevel@tonic-gate bus_range[0] = bus; 29497c478bd9Sstevel@tonic-gate bus_range[1] = pci_bus_res[bus].sub_bus; 29507c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 29517c478bd9Sstevel@tonic-gate "bus-range", (int *)bus_range, 2); 29527c478bd9Sstevel@tonic-gate } 29537c478bd9Sstevel@tonic-gate 2954b1f176e8Sjg /* 2955b1f176e8Sjg * Add slot-names property for any named pci hot-plug slots 2956b1f176e8Sjg */ 2957b1f176e8Sjg static void 2958b1f176e8Sjg add_bus_slot_names_prop(int bus) 2959b1f176e8Sjg { 2960b1f176e8Sjg char slotprop[256]; 2961b1f176e8Sjg int len; 2962b1f176e8Sjg 2963d57b3b3dSprasad if (pci_bus_res[bus].dip != NULL) { 2964d57b3b3dSprasad /* simply return if the property is already defined */ 2965d57b3b3dSprasad if (ddi_prop_exists(DDI_DEV_T_ANY, pci_bus_res[bus].dip, 2966d57b3b3dSprasad DDI_PROP_DONTPASS, "slot-names")) 2967d57b3b3dSprasad return; 2968d57b3b3dSprasad } 2969d57b3b3dSprasad 2970b1f176e8Sjg len = pci_slot_names_prop(bus, slotprop, sizeof (slotprop)); 2971b1f176e8Sjg if (len > 0) { 297253273e82Ssethg /* 297353273e82Ssethg * Only create a peer bus node if this bus may be a peer bus. 297453273e82Ssethg * It may be a peer bus if the dip is NULL and if par_bus is 297553273e82Ssethg * -1 (par_bus is -1 if this bus was not found to be 297653273e82Ssethg * subordinate to any PCI-PCI bridge). 297753273e82Ssethg * If it's not a peer bus, then the ACPI BBN-handling code 297853273e82Ssethg * will remove it later. 297953273e82Ssethg */ 298053273e82Ssethg if (pci_bus_res[bus].par_bus == (uchar_t)-1 && 298153273e82Ssethg pci_bus_res[bus].dip == NULL) { 298253273e82Ssethg 2983b1f176e8Sjg create_root_bus_dip(bus); 298453273e82Ssethg } 298553273e82Ssethg if (pci_bus_res[bus].dip != NULL) { 298653273e82Ssethg ASSERT((len % sizeof (int)) == 0); 298753273e82Ssethg (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 298853273e82Ssethg pci_bus_res[bus].dip, "slot-names", 298953273e82Ssethg (int *)slotprop, len / sizeof (int)); 299053273e82Ssethg } else { 299153273e82Ssethg cmn_err(CE_NOTE, "!BIOS BUG: Invalid bus number in PCI " 299253273e82Ssethg "IRQ routing table; Not adding slot-names " 299353273e82Ssethg "property for incorrect bus %d", bus); 299453273e82Ssethg } 2995b1f176e8Sjg } 2996b1f176e8Sjg } 2997b1f176e8Sjg 29988fc7923fSDana Myers /* 29998fc7923fSDana Myers * Handle both PCI root and PCI-PCI bridge range properties; 30008fc7923fSDana Myers * non-zero 'ppb' argument select PCI-PCI bridges versus root. 30018fc7923fSDana Myers */ 30028fc7923fSDana Myers static void 30038fc7923fSDana Myers memlist_to_ranges(void **rp, struct memlist *entry, int type, int ppb) 30047c478bd9Sstevel@tonic-gate { 30058fc7923fSDana Myers ppb_ranges_t *ppb_rp = *rp; 30068fc7923fSDana Myers pci_ranges_t *pci_rp = *rp; 30078fc7923fSDana Myers 30088fc7923fSDana Myers while (entry != NULL) { 30098fc7923fSDana Myers if (ppb) { 30108fc7923fSDana Myers ppb_rp->child_high = ppb_rp->parent_high = type; 30118fc7923fSDana Myers ppb_rp->child_mid = ppb_rp->parent_mid = 30128fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 30138fc7923fSDana Myers ppb_rp->child_low = ppb_rp->parent_low = 30148fc7923fSDana Myers (uint32_t)entry->address; 30158fc7923fSDana Myers ppb_rp->size_high = 30168fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 30178fc7923fSDana Myers ppb_rp->size_low = (uint32_t)entry->size; 30188fc7923fSDana Myers *rp = ++ppb_rp; 30198fc7923fSDana Myers } else { 30208fc7923fSDana Myers pci_rp->child_high = type; 30218fc7923fSDana Myers pci_rp->child_mid = pci_rp->parent_high = 30228fc7923fSDana Myers (uint32_t)(entry->address >> 32); /* XXX */ 30238fc7923fSDana Myers pci_rp->child_low = pci_rp->parent_low = 30248fc7923fSDana Myers (uint32_t)entry->address; 30258fc7923fSDana Myers pci_rp->size_high = 30268fc7923fSDana Myers (uint32_t)(entry->size >> 32); /* XXX */ 30278fc7923fSDana Myers pci_rp->size_low = (uint32_t)entry->size; 30288fc7923fSDana Myers *rp = ++pci_rp; 30298fc7923fSDana Myers } 30308fc7923fSDana Myers entry = entry->next; 30318fc7923fSDana Myers } 30328fc7923fSDana Myers } 30337c478bd9Sstevel@tonic-gate 30348fc7923fSDana Myers static void 30358fc7923fSDana Myers add_ranges_prop(int bus, int ppb) 30368fc7923fSDana Myers { 30378fc7923fSDana Myers int total, alloc_size; 30388fc7923fSDana Myers void *rp, *next_rp; 30392f283da5SDan Mick struct memlist *iolist, *memlist, *pmemlist; 30408fc7923fSDana Myers 3041ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3042ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3043ec0c94e7SDana Myers return; 3044ec0c94e7SDana Myers 30452f283da5SDan Mick iolist = memlist = pmemlist = (struct memlist *)NULL; 30462f283da5SDan Mick 30472f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_avail, &iolist); 30482f283da5SDan Mick memlist_merge(&pci_bus_res[bus].io_used, &iolist); 30492f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_avail, &memlist); 30502f283da5SDan Mick memlist_merge(&pci_bus_res[bus].mem_used, &memlist); 30512f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_avail, &pmemlist); 30522f283da5SDan Mick memlist_merge(&pci_bus_res[bus].pmem_used, &pmemlist); 30532f283da5SDan Mick 30542f283da5SDan Mick total = memlist_count(iolist); 30552f283da5SDan Mick total += memlist_count(memlist); 30562f283da5SDan Mick total += memlist_count(pmemlist); 30578fc7923fSDana Myers 30588fc7923fSDana Myers /* no property is created if no ranges are present */ 30598fc7923fSDana Myers if (total == 0) 30608fc7923fSDana Myers return; 30618fc7923fSDana Myers 30628fc7923fSDana Myers alloc_size = total * 30638fc7923fSDana Myers (ppb ? sizeof (ppb_ranges_t) : sizeof (pci_ranges_t)); 30648fc7923fSDana Myers 30658fc7923fSDana Myers next_rp = rp = kmem_alloc(alloc_size, KM_SLEEP); 30668fc7923fSDana Myers 30672f283da5SDan Mick memlist_to_ranges(&next_rp, iolist, PCI_ADDR_IO | PCI_REG_REL_M, ppb); 30682f283da5SDan Mick memlist_to_ranges(&next_rp, memlist, 30698fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M, ppb); 30702f283da5SDan Mick memlist_to_ranges(&next_rp, pmemlist, 30718fc7923fSDana Myers PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M, ppb); 30728fc7923fSDana Myers 30738fc7923fSDana Myers (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 30748fc7923fSDana Myers "ranges", (int *)rp, alloc_size / sizeof (int)); 30758fc7923fSDana Myers 30768fc7923fSDana Myers kmem_free(rp, alloc_size); 30772f283da5SDan Mick memlist_free_all(&iolist); 30782f283da5SDan Mick memlist_free_all(&memlist); 30792f283da5SDan Mick memlist_free_all(&pmemlist); 30807c478bd9Sstevel@tonic-gate } 30817c478bd9Sstevel@tonic-gate 30827c478bd9Sstevel@tonic-gate static void 30838fc7923fSDana Myers memlist_remove_list(struct memlist **list, struct memlist *remove_list) 30847c478bd9Sstevel@tonic-gate { 30858fc7923fSDana Myers while (list && *list && remove_list) { 30868fc7923fSDana Myers (void) memlist_remove(list, remove_list->address, 30878fc7923fSDana Myers remove_list->size); 30888fc7923fSDana Myers remove_list = remove_list->next; 30898fc7923fSDana Myers } 30907c478bd9Sstevel@tonic-gate } 30917c478bd9Sstevel@tonic-gate 30927c478bd9Sstevel@tonic-gate static int 30937c478bd9Sstevel@tonic-gate memlist_to_spec(struct pci_phys_spec *sp, struct memlist *list, int type) 30947c478bd9Sstevel@tonic-gate { 30957c478bd9Sstevel@tonic-gate int i = 0; 30967c478bd9Sstevel@tonic-gate 30977c478bd9Sstevel@tonic-gate while (list) { 30987c478bd9Sstevel@tonic-gate /* assume 32-bit addresses */ 30997c478bd9Sstevel@tonic-gate sp->pci_phys_hi = type; 31007c478bd9Sstevel@tonic-gate sp->pci_phys_mid = 0; 31017c478bd9Sstevel@tonic-gate sp->pci_phys_low = (uint32_t)list->address; 31027c478bd9Sstevel@tonic-gate sp->pci_size_hi = 0; 31037c478bd9Sstevel@tonic-gate sp->pci_size_low = (uint32_t)list->size; 31047c478bd9Sstevel@tonic-gate 31057c478bd9Sstevel@tonic-gate list = list->next; 31067c478bd9Sstevel@tonic-gate sp++, i++; 31077c478bd9Sstevel@tonic-gate } 31087c478bd9Sstevel@tonic-gate return (i); 31097c478bd9Sstevel@tonic-gate } 31107c478bd9Sstevel@tonic-gate 31117c478bd9Sstevel@tonic-gate static void 31127c478bd9Sstevel@tonic-gate add_bus_available_prop(int bus) 31137c478bd9Sstevel@tonic-gate { 31147c478bd9Sstevel@tonic-gate int i, count; 31157c478bd9Sstevel@tonic-gate struct pci_phys_spec *sp; 31167c478bd9Sstevel@tonic-gate 3117ec0c94e7SDana Myers /* no devinfo node - unused bus, return */ 3118ec0c94e7SDana Myers if (pci_bus_res[bus].dip == NULL) 3119ec0c94e7SDana Myers return; 3120ec0c94e7SDana Myers 31212f283da5SDan Mick count = memlist_count(pci_bus_res[bus].io_avail) + 31222f283da5SDan Mick memlist_count(pci_bus_res[bus].mem_avail) + 31232f283da5SDan Mick memlist_count(pci_bus_res[bus].pmem_avail); 31247c478bd9Sstevel@tonic-gate 31257c478bd9Sstevel@tonic-gate if (count == 0) /* nothing available */ 31267c478bd9Sstevel@tonic-gate return; 31277c478bd9Sstevel@tonic-gate 31287c478bd9Sstevel@tonic-gate sp = kmem_alloc(count * sizeof (*sp), KM_SLEEP); 31292f283da5SDan Mick i = memlist_to_spec(&sp[0], pci_bus_res[bus].io_avail, 31307c478bd9Sstevel@tonic-gate PCI_ADDR_IO | PCI_REG_REL_M); 31312f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].mem_avail, 31327c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M); 31332f283da5SDan Mick i += memlist_to_spec(&sp[i], pci_bus_res[bus].pmem_avail, 31347c478bd9Sstevel@tonic-gate PCI_ADDR_MEM32 | PCI_REG_REL_M | PCI_REG_PF_M); 31357c478bd9Sstevel@tonic-gate ASSERT(i == count); 31367c478bd9Sstevel@tonic-gate 31377c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, pci_bus_res[bus].dip, 31387c478bd9Sstevel@tonic-gate "available", (int *)sp, 31397c478bd9Sstevel@tonic-gate i * sizeof (struct pci_phys_spec) / sizeof (int)); 31407c478bd9Sstevel@tonic-gate kmem_free(sp, count * sizeof (*sp)); 31417c478bd9Sstevel@tonic-gate } 3142f55ce205Sszhou 3143f55ce205Sszhou static void 3144f55ce205Sszhou alloc_res_array(void) 3145f55ce205Sszhou { 3146f55ce205Sszhou static int array_max = 0; 3147f55ce205Sszhou int old_max; 3148f55ce205Sszhou void *old_res; 3149f55ce205Sszhou 3150f55ce205Sszhou if (array_max > pci_bios_nbus + 1) 3151f55ce205Sszhou return; /* array is big enough */ 3152f55ce205Sszhou 3153f55ce205Sszhou old_max = array_max; 3154f55ce205Sszhou old_res = pci_bus_res; 3155f55ce205Sszhou 3156f55ce205Sszhou if (array_max == 0) 3157f55ce205Sszhou array_max = 16; /* start with a reasonable number */ 3158f55ce205Sszhou 3159f55ce205Sszhou while (array_max < pci_bios_nbus + 1) 3160f55ce205Sszhou array_max <<= 1; 3161f55ce205Sszhou pci_bus_res = (struct pci_bus_resource *)kmem_zalloc( 3162f55ce205Sszhou array_max * sizeof (struct pci_bus_resource), KM_SLEEP); 3163f55ce205Sszhou 3164f55ce205Sszhou if (old_res) { /* copy content and free old array */ 3165f55ce205Sszhou bcopy(old_res, pci_bus_res, 3166f55ce205Sszhou old_max * sizeof (struct pci_bus_resource)); 3167f55ce205Sszhou kmem_free(old_res, old_max * sizeof (struct pci_bus_resource)); 3168f55ce205Sszhou } 3169f55ce205Sszhou } 3170c8589f13Ssethg 3171c8589f13Ssethg static void 3172c8589f13Ssethg create_ioapic_node(int bus, int dev, int fn, ushort_t vendorid, 3173c8589f13Ssethg ushort_t deviceid) 3174c8589f13Ssethg { 3175c8589f13Ssethg static dev_info_t *ioapicsnode = NULL; 3176c8589f13Ssethg static int numioapics = 0; 3177c8589f13Ssethg dev_info_t *ioapic_node; 3178c8589f13Ssethg uint64_t physaddr; 3179c8589f13Ssethg uint32_t lobase, hibase = 0; 3180c8589f13Ssethg 3181c8589f13Ssethg /* BAR 0 contains the IOAPIC's memory-mapped I/O address */ 3182c8589f13Ssethg lobase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0); 3183c8589f13Ssethg 3184c8589f13Ssethg /* We (and the rest of the world) only support memory-mapped IOAPICs */ 3185c8589f13Ssethg if ((lobase & PCI_BASE_SPACE_M) != PCI_BASE_SPACE_MEM) 3186c8589f13Ssethg return; 3187c8589f13Ssethg 3188c8589f13Ssethg if ((lobase & PCI_BASE_TYPE_M) == PCI_BASE_TYPE_ALL) 3189c8589f13Ssethg hibase = (*pci_getl_func)(bus, dev, fn, PCI_CONF_BASE0 + 4); 3190c8589f13Ssethg 3191c8589f13Ssethg lobase &= PCI_BASE_M_ADDR_M; 3192c8589f13Ssethg 3193c8589f13Ssethg physaddr = (((uint64_t)hibase) << 32) | lobase; 3194c8589f13Ssethg 3195c8589f13Ssethg /* 3196c8589f13Ssethg * Create a nexus node for all IOAPICs under the root node. 3197c8589f13Ssethg */ 3198c8589f13Ssethg if (ioapicsnode == NULL) { 3199c8589f13Ssethg if (ndi_devi_alloc(ddi_root_node(), IOAPICS_NODE_NAME, 3200c8589f13Ssethg (pnode_t)DEVI_SID_NODEID, &ioapicsnode) != NDI_SUCCESS) { 3201c8589f13Ssethg return; 3202c8589f13Ssethg } 3203c8589f13Ssethg (void) ndi_devi_online(ioapicsnode, 0); 3204c8589f13Ssethg } 3205c8589f13Ssethg 3206c8589f13Ssethg /* 3207c8589f13Ssethg * Create a child node for this IOAPIC 3208c8589f13Ssethg */ 3209c8589f13Ssethg ioapic_node = ddi_add_child(ioapicsnode, IOAPICS_CHILD_NAME, 3210c8589f13Ssethg DEVI_SID_NODEID, numioapics++); 3211c8589f13Ssethg if (ioapic_node == NULL) { 3212c8589f13Ssethg return; 3213c8589f13Ssethg } 3214c8589f13Ssethg 3215c8589f13Ssethg /* Vendor and Device ID */ 3216c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3217c8589f13Ssethg IOAPICS_PROP_VENID, vendorid); 3218c8589f13Ssethg (void) ndi_prop_update_int(DDI_DEV_T_NONE, ioapic_node, 3219c8589f13Ssethg IOAPICS_PROP_DEVID, deviceid); 3220c8589f13Ssethg 3221c8589f13Ssethg /* device_type */ 3222c8589f13Ssethg (void) ndi_prop_update_string(DDI_DEV_T_NONE, ioapic_node, 3223c8589f13Ssethg "device_type", IOAPICS_DEV_TYPE); 3224c8589f13Ssethg 3225c8589f13Ssethg /* reg */ 3226c8589f13Ssethg (void) ndi_prop_update_int64(DDI_DEV_T_NONE, ioapic_node, 3227c8589f13Ssethg "reg", physaddr); 3228c8589f13Ssethg } 3229d57b3b3dSprasad 3230d57b3b3dSprasad /* 3231d57b3b3dSprasad * NOTE: For PCIe slots, the name is generated from the slot number 3232d57b3b3dSprasad * information obtained from Slot Capabilities register. 3233d57b3b3dSprasad * For non-PCIe slots, it is generated based on the slot number 3234d57b3b3dSprasad * information in the PCI IRQ table. 3235d57b3b3dSprasad */ 3236d57b3b3dSprasad static void 3237d57b3b3dSprasad pciex_slot_names_prop(dev_info_t *dip, ushort_t slot_num) 3238d57b3b3dSprasad { 3239d57b3b3dSprasad char slotprop[256]; 3240d57b3b3dSprasad int len; 3241d57b3b3dSprasad 3242d57b3b3dSprasad bzero(slotprop, sizeof (slotprop)); 3243d57b3b3dSprasad 3244d57b3b3dSprasad /* set mask to 1 as there is only one slot (i.e dev 0) */ 3245d57b3b3dSprasad *(uint32_t *)slotprop = 1; 3246d57b3b3dSprasad len = 4; 3247d57b3b3dSprasad (void) snprintf(slotprop + len, sizeof (slotprop) - len, "pcie%d", 3248d57b3b3dSprasad slot_num); 3249d57b3b3dSprasad len += strlen(slotprop + len) + 1; 3250d57b3b3dSprasad len += len % 4; 3251d57b3b3dSprasad (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "slot-names", 3252d57b3b3dSprasad (int *)slotprop, len / sizeof (int)); 3253d57b3b3dSprasad } 3254