120c794b3Sgavinm /* 220c794b3Sgavinm * CDDL HEADER START 320c794b3Sgavinm * 420c794b3Sgavinm * The contents of this file are subject to the terms of the 520c794b3Sgavinm * Common Development and Distribution License (the "License"). 620c794b3Sgavinm * You may not use this file except in compliance with the License. 720c794b3Sgavinm * 820c794b3Sgavinm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 920c794b3Sgavinm * or http://www.opensolaris.org/os/licensing. 1020c794b3Sgavinm * See the License for the specific language governing permissions 1120c794b3Sgavinm * and limitations under the License. 1220c794b3Sgavinm * 1320c794b3Sgavinm * When distributing Covered Code, include this CDDL HEADER in each 1420c794b3Sgavinm * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1520c794b3Sgavinm * If applicable, add the following below this CDDL HEADER, with the 1620c794b3Sgavinm * fields enclosed by brackets "[]" replaced with your own identifying 1720c794b3Sgavinm * information: Portions Copyright [yyyy] [name of copyright owner] 1820c794b3Sgavinm * 1920c794b3Sgavinm * CDDL HEADER END 2020c794b3Sgavinm */ 2120c794b3Sgavinm 2220c794b3Sgavinm /* 23*85738508SVuong Nguyen * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 2420c794b3Sgavinm * Use is subject to license terms. 2520c794b3Sgavinm */ 2620c794b3Sgavinm 2720c794b3Sgavinm #ifndef _NB_LOG_H 2820c794b3Sgavinm #define _NB_LOG_H 2920c794b3Sgavinm 3020c794b3Sgavinm #ifdef __cplusplus 3120c794b3Sgavinm extern "C" { 3220c794b3Sgavinm #endif 3320c794b3Sgavinm 3420c794b3Sgavinm #include <sys/cpu_module.h> 3520c794b3Sgavinm #include "nb5000.h" 3620c794b3Sgavinm 3720c794b3Sgavinm #define NB_MAX_ERRORS 4 3820c794b3Sgavinm 3920c794b3Sgavinm /* North Bridge front side bus error registers */ 4020c794b3Sgavinm 4120c794b3Sgavinm typedef struct nb_fsb_regs { 4220c794b3Sgavinm uint8_t fsb; /* cpu slot */ 4320c794b3Sgavinm uint8_t ferr_fat_fsb; 4420c794b3Sgavinm uint8_t nerr_fat_fsb; 4520c794b3Sgavinm uint8_t ferr_nf_fsb; 4620c794b3Sgavinm uint8_t nerr_nf_fsb; 4720c794b3Sgavinm uint64_t nrecfsb_addr; 4820c794b3Sgavinm uint32_t nrecfsb; 4920c794b3Sgavinm uint32_t recfsb; 5020c794b3Sgavinm } nb_fsb_regs_t; 5120c794b3Sgavinm 5220c794b3Sgavinm /* PCI express ESI (South Bridge) error registers */ 5320c794b3Sgavinm 5420c794b3Sgavinm typedef struct nb_pex_regs { 5520c794b3Sgavinm uint8_t pex; /* pci express slot */ 5620c794b3Sgavinm uint32_t pex_fat_ferr; 5720c794b3Sgavinm uint32_t pex_fat_nerr; 5820c794b3Sgavinm uint32_t pex_nf_corr_ferr; 5920c794b3Sgavinm uint32_t pex_nf_corr_nerr; 6020c794b3Sgavinm uint32_t uncerrsev; /* uncorrectable error severity */ 6120c794b3Sgavinm uint32_t rperrsts; /* root error status */ 6220c794b3Sgavinm uint32_t rperrsid; /* error source identification */ 6320c794b3Sgavinm uint32_t uncerrsts; /* uncorrectable error status */ 6420c794b3Sgavinm uint32_t aerrcapctrl; /* advanced error capabilities and control */ 6520c794b3Sgavinm uint32_t corerrsts; /* correctable error status */ 6620c794b3Sgavinm uint16_t pexdevsts; /* pci express device status */ 6720c794b3Sgavinm } nb_pex_regs_t; 6820c794b3Sgavinm 6920c794b3Sgavinm /* North Bridge memory controller hub internal error registers */ 7020c794b3Sgavinm 7120c794b3Sgavinm typedef struct nb_int { 725f28a827Saf uint16_t ferr_fat_int; /* first fatal error */ 735f28a827Saf uint16_t ferr_nf_int; /* first non-fatal error */ 745f28a827Saf uint16_t nerr_fat_int; /* next fatal error */ 755f28a827Saf uint16_t nerr_nf_int; /* next non-fatal error */ 7620c794b3Sgavinm uint32_t nrecint; /* non recoverable error log */ 7720c794b3Sgavinm uint32_t recint; /* recoverable error log */ 7820c794b3Sgavinm uint64_t nrecsf; /* non recoverable control information */ 7920c794b3Sgavinm uint64_t recsf; /* recoverable control information */ 8020c794b3Sgavinm } nb_int_t; 8120c794b3Sgavinm 8220c794b3Sgavinm /* memory errors */ 8320c794b3Sgavinm 8420c794b3Sgavinm typedef struct nb_fat_fbd { 8520c794b3Sgavinm uint32_t ferr_fat_fbd; /* fb-dimm first fatal error */ 8620c794b3Sgavinm uint32_t nerr_fat_fbd; /* fb-dimm next fatal error */ 875f28a827Saf uint32_t nrecmema; /* non recoverable memory error log */ 8820c794b3Sgavinm uint32_t nrecmemb; /* non recoverable memory error log */ 8920c794b3Sgavinm uint32_t nrecfglog; /* non recoverable dimm configuration */ 9020c794b3Sgavinm uint32_t nrecfbda; /* non recoverable dimm log A */ 9120c794b3Sgavinm uint32_t nrecfbdb; /* non recoverable dimm log B */ 9220c794b3Sgavinm uint32_t nrecfbdc; /* non recoverable dimm log C */ 9320c794b3Sgavinm uint32_t nrecfbdd; /* non recoverable dimm log D */ 9420c794b3Sgavinm uint32_t nrecfbde; /* non recoverable dimm log E */ 955de8e333Saf uint32_t nrecfbdf; /* non recoverable dimm log F */ 9620c794b3Sgavinm uint32_t spcpc; /* spare copy control */ 9720c794b3Sgavinm uint8_t spcps; /* spare copy status */ 9820c794b3Sgavinm uint32_t uerrcnt; /* uncorrectable error count */ 9920c794b3Sgavinm uint32_t uerrcnt_last; /* saved copy of uncorrectable error count */ 10020c794b3Sgavinm uint32_t badrama; /* bad dram marker A */ 10120c794b3Sgavinm uint16_t badramb; /* bad dram marker B */ 10220c794b3Sgavinm uint32_t badcnt; /* bad dram counter */ 10320c794b3Sgavinm } nb_fat_fbd_t; 10420c794b3Sgavinm 10520c794b3Sgavinm typedef struct nb_nf_fbd { 10620c794b3Sgavinm uint32_t ferr_nf_fbd; /* fb-dimm first non-fatal error */ 10720c794b3Sgavinm uint32_t nerr_nf_fbd; /* fb-dimm next non-fatal error */ 10820c794b3Sgavinm uint32_t redmemb; /* recoverable dimm data error log */ 1095f28a827Saf uint32_t recmema; /* recoverable memory error log A */ 11020c794b3Sgavinm uint32_t recmemb; /* recoverable memory error log B */ 11120c794b3Sgavinm uint32_t recfglog; /* recoverable dimm configuration */ 11220c794b3Sgavinm uint32_t recfbda; /* recoverable dimm log A */ 11320c794b3Sgavinm uint32_t recfbdb; /* recoverable dimm log B */ 11420c794b3Sgavinm uint32_t recfbdc; /* recoverable dimm log C */ 11520c794b3Sgavinm uint32_t recfbdd; /* recoverable dimm log D */ 11620c794b3Sgavinm uint32_t recfbde; /* recoverable dimm log E */ 1175de8e333Saf uint32_t recfbdf; /* recoverable dimm log F */ 11820c794b3Sgavinm uint32_t spcpc; /* spare copy control */ 11920c794b3Sgavinm uint8_t spcps; /* spare copy status */ 1205f28a827Saf uint32_t cerrcnta; /* correctable error count A */ 1215f28a827Saf uint32_t cerrcntb; /* correctable error count B */ 1225f28a827Saf uint32_t cerrcntc; /* correctable error count C */ 1235f28a827Saf uint32_t cerrcntd; /* correctable error count D */ 1245f28a827Saf uint32_t cerrcnta_last; /* saved copy of correctable error count A */ 1255f28a827Saf uint32_t cerrcntb_last; /* saved copy of correctable error count B */ 1265f28a827Saf uint32_t cerrcntc_last; /* saved copy of correctable error count C */ 1275f28a827Saf uint32_t cerrcntd_last; /* saved copy of correctable error count D */ 12820c794b3Sgavinm uint32_t badrama; /* bad dram marker A */ 12920c794b3Sgavinm uint16_t badramb; /* bad dram marker B */ 13020c794b3Sgavinm uint32_t badcnt; /* bad dram counter */ 13120c794b3Sgavinm } nb_nf_fbd_t; 13220c794b3Sgavinm 133*85738508SVuong Nguyen typedef struct nb_nf_mem { 134*85738508SVuong Nguyen /* Memory registers */ 135*85738508SVuong Nguyen uint32_t ferr_nf_mem; /* MC first non-fatal error */ 136*85738508SVuong Nguyen uint32_t nerr_nf_mem; /* MC next non-fatal error */ 137*85738508SVuong Nguyen uint32_t nrecmema; /* non-recoverable memory error log A */ 138*85738508SVuong Nguyen uint32_t nrecmemb; /* non-recoverable memory error log B */ 139*85738508SVuong Nguyen uint32_t redmema; /* recoverable memory data error log A */ 140*85738508SVuong Nguyen uint32_t redmemb; /* recoverable memory data error log B */ 141*85738508SVuong Nguyen uint32_t recmema; /* recoverable memory error log A */ 142*85738508SVuong Nguyen uint32_t recmemb; /* recoverable memory error log B */ 143*85738508SVuong Nguyen 144*85738508SVuong Nguyen /* Spare rank */ 145*85738508SVuong Nguyen uint32_t spcpc; /* spare copy control */ 146*85738508SVuong Nguyen uint8_t spcps; /* spare copy status */ 147*85738508SVuong Nguyen 148*85738508SVuong Nguyen /* RAS */ 149*85738508SVuong Nguyen uint32_t cerrcnt; /* correctable error count A */ 150*85738508SVuong Nguyen uint32_t cerrcnt_ext; /* correctable error count B */ 151*85738508SVuong Nguyen uint32_t cerrcnt_last; /* correctable error count A */ 152*85738508SVuong Nguyen uint32_t cerrcnt_ext_last; /* correctable error count B */ 153*85738508SVuong Nguyen uint32_t badram; /* bad dram marker */ 154*85738508SVuong Nguyen uint32_t badcnt; /* bad dram counter */ 155*85738508SVuong Nguyen uint32_t validlog; /* valid log markers */ 156*85738508SVuong Nguyen } nb_nf_mem_t; 157*85738508SVuong Nguyen 15820c794b3Sgavinm typedef struct nb_dma { 15920c794b3Sgavinm uint16_t pcists; 16020c794b3Sgavinm uint16_t pexdevsts; 16120c794b3Sgavinm } nb_dma_t; 16220c794b3Sgavinm 1635f28a827Saf typedef struct nb_thr { 1645f28a827Saf uint8_t ferr_fat_thr; 1655f28a827Saf uint8_t ferr_nf_thr; 1665f28a827Saf uint8_t nerr_fat_thr; 1675f28a827Saf uint8_t nerr_nf_thr; 1685f28a827Saf uint8_t ctsts; 1695f28a827Saf uint16_t thrtsts; 1705f28a827Saf } nb_thr_t; 1715f28a827Saf 17220c794b3Sgavinm typedef struct nb_regs { 17320c794b3Sgavinm int flag; 17420c794b3Sgavinm uint32_t chipset; 17520c794b3Sgavinm uint64_t ferr; 17620c794b3Sgavinm uint32_t nerr; 17720c794b3Sgavinm union { 17820c794b3Sgavinm nb_fsb_regs_t fsb_regs; 17920c794b3Sgavinm nb_pex_regs_t pex_regs; 18020c794b3Sgavinm nb_int_t int_regs; 18120c794b3Sgavinm nb_fat_fbd_t fat_fbd_regs; 18220c794b3Sgavinm nb_nf_fbd_t nf_fbd_regs; 183*85738508SVuong Nguyen nb_nf_mem_t nf_mem_regs; 18420c794b3Sgavinm nb_dma_t dma_regs; 1855f28a827Saf nb_thr_t thr_regs; 18620c794b3Sgavinm } nb; 18720c794b3Sgavinm } nb_regs_t; 18820c794b3Sgavinm 18920c794b3Sgavinm #define NB_REG_LOG_FREE 0 19020c794b3Sgavinm #define NB_REG_LOG_FSB 1 19120c794b3Sgavinm #define NB_REG_LOG_PEX 2 19220c794b3Sgavinm #define NB_REG_LOG_INT 3 19320c794b3Sgavinm #define NB_REG_LOG_FAT_FBD 4 19420c794b3Sgavinm #define NB_REG_LOG_NF_FBD 5 19520c794b3Sgavinm #define NB_REG_LOG_DMA 6 1965f28a827Saf #define NB_REG_LOG_THR 7 197*85738508SVuong Nguyen #define NB_REG_LOG_NF_MEM 8 19820c794b3Sgavinm 19920c794b3Sgavinm typedef struct nb_logout { 20020c794b3Sgavinm uint64_t acl_timestamp; 20120c794b3Sgavinm char *type; 20220c794b3Sgavinm nb_regs_t nb_regs; 20320c794b3Sgavinm } nb_logout_t; 20420c794b3Sgavinm 20520c794b3Sgavinm typedef struct nb_mem_scatchpad { 20620c794b3Sgavinm int intel_error_list; /* error number in Chipset Error List */ 20720c794b3Sgavinm int branch; 20820c794b3Sgavinm int channel; 20920c794b3Sgavinm int rank; 21020c794b3Sgavinm int dimm; 21120c794b3Sgavinm int bank; 21220c794b3Sgavinm int cas; 21320c794b3Sgavinm int ras; 21420c794b3Sgavinm uint64_t offset; 21520c794b3Sgavinm uint64_t pa; 21620c794b3Sgavinm } nb_mem_scatchpad_t; 21720c794b3Sgavinm 21820c794b3Sgavinm typedef union nb_scatchpad { 21920c794b3Sgavinm nb_mem_scatchpad_t ms; 22020c794b3Sgavinm int intel_error_list; /* error number in Chipset Error List */ 22120c794b3Sgavinm } nb_scatchpad_t; 22220c794b3Sgavinm 22320c794b3Sgavinm typedef struct nb_dimm { 22420c794b3Sgavinm uint64_t dimm_size; 22520c794b3Sgavinm uint8_t mtr_present; 226*85738508SVuong Nguyen uint8_t start_rank; /* id of the 1st rank */ 227*85738508SVuong Nguyen uint8_t nranks; /* number of ranks */ 22820c794b3Sgavinm uint8_t nbanks; 22920c794b3Sgavinm uint8_t ncolumn; 23020c794b3Sgavinm uint8_t nrow; 23120c794b3Sgavinm uint8_t width; 23220c794b3Sgavinm uint8_t manufacture_location; 23320c794b3Sgavinm uint8_t manufacture_week; 23420c794b3Sgavinm uint8_t manufacture_year; /* years from 2000 */ 23520c794b3Sgavinm uint16_t manufacture_id; 23620c794b3Sgavinm uint32_t serial_number; 23720c794b3Sgavinm char part_number[16]; 23820c794b3Sgavinm char revision[2]; 23920c794b3Sgavinm char label[64]; 24020c794b3Sgavinm } nb_dimm_t; 24120c794b3Sgavinm 24220c794b3Sgavinm typedef struct bank_select { 24320c794b3Sgavinm uint64_t base; 24420c794b3Sgavinm uint64_t limit; 24520c794b3Sgavinm uint8_t way[2]; 24620c794b3Sgavinm } bank_select_t; 24720c794b3Sgavinm 24820c794b3Sgavinm typedef struct rank_select { 24920c794b3Sgavinm uint64_t base; 25020c794b3Sgavinm uint64_t limit; 25120c794b3Sgavinm uint32_t hole_base; 25220c794b3Sgavinm uint32_t hole_size; 25320c794b3Sgavinm uint8_t rank[4]; 25420c794b3Sgavinm uint8_t interleave; 25520c794b3Sgavinm uint8_t branch_interleave; 25620c794b3Sgavinm } rank_select_t; 25720c794b3Sgavinm 25820c794b3Sgavinm enum nb_memory_mode { NB_MEMORY_SINGLE_CHANNEL, NB_MEMORY_NORMAL, 25920c794b3Sgavinm NB_MEMORY_SPARE_RANK, NB_MEMORY_MIRROR }; 26020c794b3Sgavinm 26120c794b3Sgavinm extern int nb_5000_memory_controller; 26220c794b3Sgavinm extern int nb_number_memory_controllers; 263*85738508SVuong Nguyen extern int nb_channels_per_branch; 26420c794b3Sgavinm extern int nb_dimms_per_channel; 26520c794b3Sgavinm 26620c794b3Sgavinm extern nb_dimm_t **nb_dimms; 26720c794b3Sgavinm extern uint32_t nb_chipset; 26820c794b3Sgavinm 26920c794b3Sgavinm extern int nb_init(void); 27020c794b3Sgavinm extern int nb_dev_init(void); 27120c794b3Sgavinm extern void nb_dev_reinit(void); 27220c794b3Sgavinm extern void nb_unload(void); 27320c794b3Sgavinm extern void nb_dev_unload(void); 27420c794b3Sgavinm extern uint32_t top_of_low_memory; 2755de8e333Saf extern bank_select_t nb_banks[NB_MAX_MEM_BRANCH_SELECT]; 2765de8e333Saf extern rank_select_t nb_ranks[NB_5000_MAX_MEM_CONTROLLERS] 2775de8e333Saf [NB_MAX_MEM_RANK_SELECT]; 27820c794b3Sgavinm extern uint8_t spare_rank[NB_5000_MAX_MEM_CONTROLLERS]; 27920c794b3Sgavinm extern enum nb_memory_mode nb_mode; 280*85738508SVuong Nguyen extern int nb_rank2dimm(int, int); 28120c794b3Sgavinm 28220c794b3Sgavinm extern int inb_mc_register(cmi_hdl_t, void *, void *, void *); 28320c794b3Sgavinm extern void nb_scrubber_enable(void); 28420c794b3Sgavinm extern void nb_error_trap(cmi_hdl_t, boolean_t, boolean_t); 28520c794b3Sgavinm 28620c794b3Sgavinm extern void nb_pci_cfg_setup(dev_info_t *); 28720c794b3Sgavinm extern void nb_pci_cfg_free(void); 28820c794b3Sgavinm 28920c794b3Sgavinm extern void *ras_regs; 29020c794b3Sgavinm 29120c794b3Sgavinm extern uint8_t nb_pci_getb(int, int, int, int, int *); 29220c794b3Sgavinm extern uint16_t nb_pci_getw(int, int, int, int, int *); 29320c794b3Sgavinm extern uint32_t nb_pci_getl(int, int, int, int, int *); 29420c794b3Sgavinm extern void nb_pci_putb(int, int, int, int, uint8_t); 29520c794b3Sgavinm extern void nb_pci_putw(int, int, int, int, uint16_t); 29620c794b3Sgavinm extern void nb_pci_putl(int, int, int, int, uint32_t); 29720c794b3Sgavinm 29820c794b3Sgavinm extern void nb_fsb_mask_mc(int, uint16_t); 29920c794b3Sgavinm extern void nb_fbd_mask_mc(uint32_t); 300*85738508SVuong Nguyen extern void nb_mem_mask_mc(uint32_t); 3015f28a827Saf extern void nb_int_mask_mc(uint32_t); 3025f28a827Saf extern void nb_thr_mask_mc(uint16_t); 30320c794b3Sgavinm extern void nb_mask_mc_reset(void); 30420c794b3Sgavinm 30520c794b3Sgavinm extern int nb_mask_mc_set; 30620c794b3Sgavinm 30720c794b3Sgavinm extern errorq_t *nb_queue; 30820c794b3Sgavinm extern kmutex_t nb_mutex; 30920c794b3Sgavinm 31020c794b3Sgavinm extern void nb_drain(void *, const void *, const errorq_elem_t *); 31120c794b3Sgavinm extern void nb_used_spare_rank(int, int); 31220c794b3Sgavinm 31320c794b3Sgavinm extern uint_t nb_config_gen; 31420c794b3Sgavinm 31520c794b3Sgavinm #ifdef __cplusplus 31620c794b3Sgavinm } 31720c794b3Sgavinm #endif 31820c794b3Sgavinm 31920c794b3Sgavinm #endif /* _NB_LOG_H */ 320