1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NB_LOG_H 28 #define _NB_LOG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/cpu_module.h> 37 #include "nb5000.h" 38 39 #define NB_MAX_ERRORS 4 40 41 /* North Bridge front side bus error registers */ 42 43 typedef struct nb_fsb_regs { 44 uint8_t fsb; /* cpu slot */ 45 uint8_t ferr_fat_fsb; 46 uint8_t nerr_fat_fsb; 47 uint8_t ferr_nf_fsb; 48 uint8_t nerr_nf_fsb; 49 uint64_t nrecfsb_addr; 50 uint32_t nrecfsb; 51 uint32_t recfsb; 52 } nb_fsb_regs_t; 53 54 /* PCI express ESI (South Bridge) error registers */ 55 56 typedef struct nb_pex_regs { 57 uint8_t pex; /* pci express slot */ 58 uint32_t pex_fat_ferr; 59 uint32_t pex_fat_nerr; 60 uint32_t pex_nf_corr_ferr; 61 uint32_t pex_nf_corr_nerr; 62 uint32_t uncerrsev; /* uncorrectable error severity */ 63 uint32_t rperrsts; /* root error status */ 64 uint32_t rperrsid; /* error source identification */ 65 uint32_t uncerrsts; /* uncorrectable error status */ 66 uint32_t aerrcapctrl; /* advanced error capabilities and control */ 67 uint32_t corerrsts; /* correctable error status */ 68 uint16_t pexdevsts; /* pci express device status */ 69 } nb_pex_regs_t; 70 71 /* North Bridge memory controller hub internal error registers */ 72 73 typedef struct nb_int { 74 uint8_t ferr_fat_int; /* first fatal error */ 75 uint8_t ferr_nf_int; /* first non-fatal error */ 76 uint8_t nerr_fat_int; /* next fatal error */ 77 uint8_t nerr_nf_int; /* next non-fatal error */ 78 uint32_t nrecint; /* non recoverable error log */ 79 uint32_t recint; /* recoverable error log */ 80 uint64_t nrecsf; /* non recoverable control information */ 81 uint64_t recsf; /* recoverable control information */ 82 } nb_int_t; 83 84 /* memory errors */ 85 86 typedef struct nb_fat_fbd { 87 uint32_t ferr_fat_fbd; /* fb-dimm first fatal error */ 88 uint32_t nerr_fat_fbd; /* fb-dimm next fatal error */ 89 uint16_t nrecmema; /* non recoverable memory error log */ 90 uint32_t nrecmemb; /* non recoverable memory error log */ 91 uint32_t nrecfglog; /* non recoverable dimm configuration */ 92 uint32_t nrecfbda; /* non recoverable dimm log A */ 93 uint32_t nrecfbdb; /* non recoverable dimm log B */ 94 uint32_t nrecfbdc; /* non recoverable dimm log C */ 95 uint32_t nrecfbdd; /* non recoverable dimm log D */ 96 uint32_t nrecfbde; /* non recoverable dimm log E */ 97 uint32_t nrecfbdf; /* non recoverable dimm log F */ 98 uint32_t spcpc; /* spare copy control */ 99 uint8_t spcps; /* spare copy status */ 100 uint32_t uerrcnt; /* uncorrectable error count */ 101 uint32_t uerrcnt_last; /* saved copy of uncorrectable error count */ 102 uint32_t badrama; /* bad dram marker A */ 103 uint16_t badramb; /* bad dram marker B */ 104 uint32_t badcnt; /* bad dram counter */ 105 } nb_fat_fbd_t; 106 107 typedef struct nb_nf_fbd { 108 uint32_t ferr_nf_fbd; /* fb-dimm first non-fatal error */ 109 uint32_t nerr_nf_fbd; /* fb-dimm next non-fatal error */ 110 uint32_t redmemb; /* recoverable dimm data error log */ 111 uint16_t recmema; /* recoverable memory error log A */ 112 uint32_t recmemb; /* recoverable memory error log B */ 113 uint32_t recfglog; /* recoverable dimm configuration */ 114 uint32_t recfbda; /* recoverable dimm log A */ 115 uint32_t recfbdb; /* recoverable dimm log B */ 116 uint32_t recfbdc; /* recoverable dimm log C */ 117 uint32_t recfbdd; /* recoverable dimm log D */ 118 uint32_t recfbde; /* recoverable dimm log E */ 119 uint32_t recfbdf; /* recoverable dimm log F */ 120 uint32_t spcpc; /* spare copy control */ 121 uint8_t spcps; /* spare copy status */ 122 uint32_t cerrcnt; /* correctable error count */ 123 uint32_t cerrcnt_last; /* saved copy of correctable error count */ 124 uint32_t badrama; /* bad dram marker A */ 125 uint16_t badramb; /* bad dram marker B */ 126 uint32_t badcnt; /* bad dram counter */ 127 } nb_nf_fbd_t; 128 129 typedef struct nb_dma { 130 uint16_t pcists; 131 uint16_t pexdevsts; 132 } nb_dma_t; 133 134 typedef struct nb_regs { 135 int flag; 136 uint32_t chipset; 137 uint64_t ferr; 138 uint32_t nerr; 139 union { 140 nb_fsb_regs_t fsb_regs; 141 nb_pex_regs_t pex_regs; 142 nb_int_t int_regs; 143 nb_fat_fbd_t fat_fbd_regs; 144 nb_nf_fbd_t nf_fbd_regs; 145 nb_dma_t dma_regs; 146 } nb; 147 } nb_regs_t; 148 149 #define NB_REG_LOG_FREE 0 150 #define NB_REG_LOG_FSB 1 151 #define NB_REG_LOG_PEX 2 152 #define NB_REG_LOG_INT 3 153 #define NB_REG_LOG_FAT_FBD 4 154 #define NB_REG_LOG_NF_FBD 5 155 #define NB_REG_LOG_DMA 6 156 157 typedef struct nb_logout { 158 uint64_t acl_timestamp; 159 char *type; 160 nb_regs_t nb_regs; 161 } nb_logout_t; 162 163 typedef struct nb_mem_scatchpad { 164 int intel_error_list; /* error number in Chipset Error List */ 165 int branch; 166 int channel; 167 int rank; 168 int dimm; 169 int bank; 170 int cas; 171 int ras; 172 uint64_t offset; 173 uint64_t pa; 174 } nb_mem_scatchpad_t; 175 176 typedef union nb_scatchpad { 177 nb_mem_scatchpad_t ms; 178 int intel_error_list; /* error number in Chipset Error List */ 179 } nb_scatchpad_t; 180 181 typedef struct nb_dimm { 182 uint64_t dimm_size; 183 uint8_t mtr_present; 184 uint8_t nranks; 185 uint8_t nbanks; 186 uint8_t ncolumn; 187 uint8_t nrow; 188 uint8_t width; 189 uint8_t manufacture_location; 190 uint8_t manufacture_week; 191 uint8_t manufacture_year; /* years from 2000 */ 192 uint16_t manufacture_id; 193 uint32_t serial_number; 194 char part_number[16]; 195 char revision[2]; 196 char label[64]; 197 } nb_dimm_t; 198 199 typedef struct bank_select { 200 uint64_t base; 201 uint64_t limit; 202 uint8_t way[2]; 203 } bank_select_t; 204 205 typedef struct rank_select { 206 uint64_t base; 207 uint64_t limit; 208 uint32_t hole_base; 209 uint32_t hole_size; 210 uint8_t rank[4]; 211 uint8_t interleave; 212 uint8_t branch_interleave; 213 } rank_select_t; 214 215 enum nb_memory_mode { NB_MEMORY_SINGLE_CHANNEL, NB_MEMORY_NORMAL, 216 NB_MEMORY_SPARE_RANK, NB_MEMORY_MIRROR }; 217 218 extern int nb_5000_memory_controller; 219 extern int nb_number_memory_controllers; 220 extern int nb_dimms_per_channel; 221 222 extern nb_dimm_t **nb_dimms; 223 extern uint32_t nb_chipset; 224 225 extern int nb_init(void); 226 extern int nb_dev_init(void); 227 extern void nb_dev_reinit(void); 228 extern void nb_unload(void); 229 extern void nb_dev_unload(void); 230 extern uint32_t top_of_low_memory; 231 extern bank_select_t nb_banks[NB_MAX_MEM_BRANCH_SELECT]; 232 extern rank_select_t nb_ranks[NB_5000_MAX_MEM_CONTROLLERS] 233 [NB_MAX_MEM_RANK_SELECT]; 234 extern uint8_t spare_rank[NB_5000_MAX_MEM_CONTROLLERS]; 235 extern enum nb_memory_mode nb_mode; 236 237 extern int inb_mc_register(cmi_hdl_t, void *, void *, void *); 238 extern void nb_scrubber_enable(void); 239 extern void nb_error_trap(cmi_hdl_t, boolean_t, boolean_t); 240 241 extern void nb_pci_cfg_setup(dev_info_t *); 242 extern void nb_pci_cfg_free(void); 243 244 extern void *ras_regs; 245 246 extern uint8_t nb_pci_getb(int, int, int, int, int *); 247 extern uint16_t nb_pci_getw(int, int, int, int, int *); 248 extern uint32_t nb_pci_getl(int, int, int, int, int *); 249 extern void nb_pci_putb(int, int, int, int, uint8_t); 250 extern void nb_pci_putw(int, int, int, int, uint16_t); 251 extern void nb_pci_putl(int, int, int, int, uint32_t); 252 253 extern void nb_fsb_mask_mc(int, uint16_t); 254 extern void nb_fbd_mask_mc(uint32_t); 255 extern void nb_int_mask_mc(uint8_t); 256 extern void nb_mask_mc_reset(void); 257 258 extern int nb_mask_mc_set; 259 260 extern errorq_t *nb_queue; 261 extern kmutex_t nb_mutex; 262 263 extern void nb_drain(void *, const void *, const errorq_elem_t *); 264 extern void nb_used_spare_rank(int, int); 265 266 extern uint_t nb_config_gen; 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 #endif /* _NB_LOG_H */ 273