1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _NB_LOG_H
28 #define	_NB_LOG_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/cpu_module.h>
37 #include "nb5000.h"
38 
39 #define	NB_MAX_ERRORS	4
40 
41 /* North Bridge front side bus error registers */
42 
43 typedef struct nb_fsb_regs {
44 	uint8_t	fsb;		/* cpu slot */
45 	uint8_t ferr_fat_fsb;
46 	uint8_t nerr_fat_fsb;
47 	uint8_t ferr_nf_fsb;
48 	uint8_t nerr_nf_fsb;
49 	uint64_t nrecfsb_addr;
50 	uint32_t nrecfsb;
51 	uint32_t recfsb;
52 } nb_fsb_regs_t;
53 
54 /* PCI express ESI (South Bridge) error registers */
55 
56 typedef struct nb_pex_regs {
57 	uint8_t pex;		/* pci express slot */
58 	uint32_t pex_fat_ferr;
59 	uint32_t pex_fat_nerr;
60 	uint32_t pex_nf_corr_ferr;
61 	uint32_t pex_nf_corr_nerr;
62 	uint32_t uncerrsev;		/* uncorrectable error severity */
63 	uint32_t rperrsts;		/* root error status */
64 	uint32_t rperrsid;		/* error source identification */
65 	uint32_t uncerrsts;		/* uncorrectable error status */
66 	uint32_t aerrcapctrl;	/* advanced error capabilities and control */
67 	uint32_t corerrsts;	/* correctable error status */
68 	uint16_t pexdevsts;	/* pci express device status */
69 } nb_pex_regs_t;
70 
71 /* North Bridge memory controller hub internal error registers */
72 
73 typedef struct nb_int {
74 	uint8_t ferr_fat_int;	/* first fatal error */
75 	uint8_t ferr_nf_int;	/* first non-fatal error */
76 	uint8_t nerr_fat_int;	/* next fatal error */
77 	uint8_t nerr_nf_int;	/* next non-fatal error */
78 	uint32_t nrecint;	/* non recoverable error log */
79 	uint32_t recint;	/* recoverable error log */
80 	uint64_t nrecsf;	/* non recoverable control information */
81 	uint64_t recsf;		/* recoverable control information */
82 } nb_int_t;
83 
84 /* memory errors */
85 
86 typedef struct nb_fat_fbd {
87 	uint32_t ferr_fat_fbd;	/* fb-dimm first fatal error */
88 	uint32_t nerr_fat_fbd;	/* fb-dimm next fatal error */
89 	uint16_t nrecmema;	/* non recoverable memory error log */
90 	uint32_t nrecmemb;	/* non recoverable memory error log */
91 	uint32_t nrecfglog;	/* non recoverable dimm configuration */
92 	uint32_t nrecfbda;	/* non recoverable dimm log A */
93 	uint32_t nrecfbdb;	/* non recoverable dimm log B */
94 	uint32_t nrecfbdc;	/* non recoverable dimm log C */
95 	uint32_t nrecfbdd;	/* non recoverable dimm log D */
96 	uint32_t nrecfbde;	/* non recoverable dimm log E */
97 	uint32_t spcpc;		/* spare copy control */
98 	uint8_t spcps;		/* spare copy status */
99 	uint32_t uerrcnt;	/* uncorrectable error count */
100 	uint32_t uerrcnt_last;	/* saved copy of uncorrectable error count */
101 	uint32_t badrama;	/* bad dram marker A */
102 	uint16_t badramb;	/* bad dram marker B */
103 	uint32_t badcnt;	/* bad dram counter */
104 } nb_fat_fbd_t;
105 
106 typedef struct nb_nf_fbd {
107 	uint32_t ferr_nf_fbd;	/* fb-dimm first non-fatal error */
108 	uint32_t nerr_nf_fbd;	/* fb-dimm next non-fatal error */
109 	uint32_t redmemb;	/* recoverable dimm data error log */
110 	uint16_t recmema;	/* recoverable memory error log A */
111 	uint32_t recmemb;	/* recoverable memory error log B */
112 	uint32_t recfglog;	/* recoverable dimm configuration */
113 	uint32_t recfbda;	/* recoverable dimm log A */
114 	uint32_t recfbdb;	/* recoverable dimm log B */
115 	uint32_t recfbdc;	/* recoverable dimm log C */
116 	uint32_t recfbdd;	/* recoverable dimm log D */
117 	uint32_t recfbde;	/* recoverable dimm log E */
118 	uint32_t spcpc;		/* spare copy control */
119 	uint8_t spcps;		/* spare copy status */
120 	uint32_t cerrcnt;	/* correctable error count */
121 	uint32_t cerrcnt_last;	/* saved copy of correctable error count */
122 	uint32_t badrama;	/* bad dram marker A */
123 	uint16_t badramb;	/* bad dram marker B */
124 	uint32_t badcnt;	/* bad dram counter */
125 } nb_nf_fbd_t;
126 
127 typedef struct nb_dma {
128 	uint16_t pcists;
129 	uint16_t pexdevsts;
130 } nb_dma_t;
131 
132 typedef struct nb_regs {
133 	int flag;
134 	uint32_t chipset;
135 	uint64_t ferr;
136 	uint32_t nerr;
137 	union {
138 		nb_fsb_regs_t fsb_regs;
139 		nb_pex_regs_t pex_regs;
140 		nb_int_t int_regs;
141 		nb_fat_fbd_t fat_fbd_regs;
142 		nb_nf_fbd_t nf_fbd_regs;
143 		nb_dma_t dma_regs;
144 	} nb;
145 } nb_regs_t;
146 
147 #define	NB_REG_LOG_FREE		0
148 #define	NB_REG_LOG_FSB		1
149 #define	NB_REG_LOG_PEX		2
150 #define	NB_REG_LOG_INT		3
151 #define	NB_REG_LOG_FAT_FBD	4
152 #define	NB_REG_LOG_NF_FBD	5
153 #define	NB_REG_LOG_DMA		6
154 
155 typedef struct nb_logout {
156 	uint64_t acl_timestamp;
157 	char *type;
158 	nb_regs_t nb_regs;
159 } nb_logout_t;
160 
161 typedef struct nb_mem_scatchpad {
162 	int intel_error_list;		/* error number in Chipset Error List */
163 	int branch;
164 	int channel;
165 	int rank;
166 	int dimm;
167 	int bank;
168 	int cas;
169 	int ras;
170 	uint64_t offset;
171 	uint64_t pa;
172 } nb_mem_scatchpad_t;
173 
174 typedef union nb_scatchpad {
175 	nb_mem_scatchpad_t ms;
176 	int intel_error_list;		/* error number in Chipset Error List */
177 } nb_scatchpad_t;
178 
179 typedef struct nb_dimm {
180 	uint64_t dimm_size;
181 	uint8_t mtr_present;
182 	uint8_t nranks;
183 	uint8_t nbanks;
184 	uint8_t ncolumn;
185 	uint8_t nrow;
186 	uint8_t width;
187 	uint8_t manufacture_location;
188 	uint8_t manufacture_week;
189 	uint8_t manufacture_year;	/* years from 2000 */
190 	uint16_t manufacture_id;
191 	uint32_t serial_number;
192 	char part_number[16];
193 	char revision[2];
194 	char label[64];
195 } nb_dimm_t;
196 
197 typedef struct bank_select {
198 	uint64_t base;
199 	uint64_t limit;
200 	uint8_t	way[2];
201 } bank_select_t;
202 
203 typedef struct rank_select {
204 	uint64_t base;
205 	uint64_t limit;
206 	uint32_t hole_base;
207 	uint32_t hole_size;
208 	uint8_t	rank[4];
209 	uint8_t interleave;
210 	uint8_t branch_interleave;
211 } rank_select_t;
212 
213 enum nb_memory_mode { NB_MEMORY_SINGLE_CHANNEL, NB_MEMORY_NORMAL,
214     NB_MEMORY_SPARE_RANK, NB_MEMORY_MIRROR };
215 
216 extern int nb_5000_memory_controller;
217 extern int nb_number_memory_controllers;
218 extern int nb_dimms_per_channel;
219 
220 extern nb_dimm_t **nb_dimms;
221 extern uint32_t nb_chipset;
222 
223 extern int nb_init(void);
224 extern int nb_dev_init(void);
225 extern void nb_dev_reinit(void);
226 extern void nb_unload(void);
227 extern void nb_dev_unload(void);
228 extern uint32_t top_of_low_memory;
229 extern bank_select_t nb_banks[NB_MEM_BRANCH_SELECT];
230 extern rank_select_t nb_ranks[NB_5000_MAX_MEM_CONTROLLERS][NB_MEM_RANK_SELECT];
231 extern uint8_t spare_rank[NB_5000_MAX_MEM_CONTROLLERS];
232 extern enum nb_memory_mode nb_mode;
233 
234 extern int inb_mc_register(cmi_hdl_t, void *, void *, void *);
235 extern void nb_scrubber_enable(void);
236 extern void nb_error_trap(cmi_hdl_t, boolean_t, boolean_t);
237 
238 extern void nb_pci_cfg_setup(dev_info_t *);
239 extern void nb_pci_cfg_free(void);
240 
241 extern void *ras_regs;
242 
243 extern uint8_t nb_pci_getb(int, int, int, int, int *);
244 extern uint16_t nb_pci_getw(int, int, int, int, int *);
245 extern uint32_t nb_pci_getl(int, int, int, int, int *);
246 extern void nb_pci_putb(int, int, int, int, uint8_t);
247 extern void nb_pci_putw(int, int, int, int, uint16_t);
248 extern void nb_pci_putl(int, int, int, int, uint32_t);
249 
250 extern void nb_fsb_mask_mc(int, uint16_t);
251 extern void nb_fbd_mask_mc(uint32_t);
252 extern void nb_int_mask_mc(uint8_t);
253 extern void nb_mask_mc_reset(void);
254 
255 extern int nb_mask_mc_set;
256 
257 extern errorq_t *nb_queue;
258 extern kmutex_t nb_mutex;
259 
260 extern void nb_drain(void *, const void *, const errorq_elem_t *);
261 extern void nb_used_spare_rank(int, int);
262 
263 extern uint_t nb_config_gen;
264 
265 #ifdef __cplusplus
266 }
267 #endif
268 
269 #endif /* _NB_LOG_H */
270