1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #include <sys/types.h>
28 #include <sys/time.h>
29 #include <sys/nvpair.h>
30 #include <sys/cmn_err.h>
31 #include <sys/cred.h>
32 #include <sys/open.h>
33 #include <sys/ddi.h>
34 #include <sys/sunddi.h>
35 #include <sys/conf.h>
36 #include <sys/modctl.h>
37 #include <sys/cyclic.h>
38 #include <sys/errorq.h>
39 #include <sys/stat.h>
40 #include <sys/cpuvar.h>
41 #include <sys/mc_intel.h>
42 #include <sys/mc.h>
43 #include <sys/fm/protocol.h>
44 #include "nb_log.h"
45 #include "nb5000.h"
46 
47 char _depends_on[] = "drv/smbios";
48 
49 nvlist_t *inb_mc_nvl;
50 krwlock_t inb_mc_lock;
51 
52 char *inb_mc_snapshot;
53 uint_t nb_config_gen;
54 uint_t inb_mc_snapshotgen;
55 size_t inb_mc_snapshotsz;
56 static dev_info_t *inb_dip;
57 int nb_allow_detach = 0;
58 
59 static uint64_t
60 rank_to_base(uint8_t branch, uint8_t rank, uint8_t *interleave, uint64_t *limit,
61     uint64_t *hole_base, uint64_t *hole_size, uint8_t *wayp,
62     uint8_t *branch_interleavep)
63 {
64 	uint8_t i, j;
65 	uint64_t base = 0;
66 	uint64_t lt = 0;
67 	uint64_t h = 0;
68 	uint64_t hs = 0;
69 	uint8_t il = 1;
70 	uint8_t way = 0;
71 	uint8_t branch_interleave = 0;
72 
73 	for (i = 0; i < NB_MEM_RANK_SELECT; i++) {
74 		for (j = 0; j < NB_RANKS_IN_SELECT; j++) {
75 			if (nb_ranks[branch][i].rank[j] == rank) {
76 				base = nb_ranks[branch][i].base;
77 				lt = nb_ranks[branch][i].limit;
78 				il = nb_ranks[branch][i].interleave;
79 				h = nb_ranks[branch][i].hole_base;
80 				hs = nb_ranks[branch][i].hole_size;
81 				way = j;
82 				branch_interleave =
83 				    nb_ranks[branch][i].branch_interleave;
84 				i = NB_MEM_RANK_SELECT;
85 				break;
86 			}
87 		}
88 	}
89 	if (lt == 0) {
90 		for (i = 0; lt == 0 && i < NB_MEM_BRANCH_SELECT; i++) {
91 			if (nb_banks[i].way[branch] &&
92 			    base >= nb_banks[i].base &&
93 			    base < nb_banks[i].base + nb_banks[i].limit) {
94 				lt = nb_banks[i].limit;
95 				break;
96 			}
97 		}
98 	}
99 	*interleave = il;
100 	*limit = lt;
101 	*hole_base = h;
102 	*hole_size = hs;
103 	*wayp = way;
104 	*branch_interleavep = branch_interleave;
105 	return (base);
106 }
107 
108 void
109 inb_rank(nvlist_t *newdimm, nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
110 {
111 	nvlist_t **newrank;
112 	int i;
113 
114 	newrank = kmem_zalloc(sizeof (nvlist_t *) * nb_dimm->nranks, KM_SLEEP);
115 	for (i = 0; i < nb_dimm->nranks; i++) {
116 		uint64_t dimm_base;
117 		uint64_t limit;
118 		uint8_t interleave;
119 		uint8_t way;
120 		uint8_t branch_interleave;
121 		uint64_t hole_base;
122 		uint64_t hole_size;
123 
124 		dimm_base = rank_to_base(channel/2, dimm*2 + i, &interleave,
125 		    &limit, &hole_base, &hole_size, &way, &branch_interleave);
126 		(void) nvlist_alloc(&newrank[i], NV_UNIQUE_NAME, KM_SLEEP);
127 
128 		(void) nvlist_add_uint64(newrank[i], "dimm-rank-base",
129 		    dimm_base);
130 		if (hole_size) {
131 			(void) nvlist_add_uint64(newrank[i], "dimm-hole",
132 			    hole_base);
133 			(void) nvlist_add_uint64(newrank[i], "dimm-hole-size",
134 			    hole_size);
135 		}
136 		(void) nvlist_add_uint64(newrank[i], "dimm-rank-limit",
137 		    limit);
138 		if (interleave > 1) {
139 			(void) nvlist_add_uint32(newrank[i],
140 			    "dimm-rank-interleave", (uint32_t)interleave);
141 			(void) nvlist_add_uint32(newrank[i],
142 			    "dimm-rank-interleave-way", (uint32_t)way);
143 			if (branch_interleave) {
144 				(void) nvlist_add_uint32(newrank[i],
145 				    "dimm-rank-interleave-branch", (uint32_t)1);
146 			}
147 		}
148 	}
149 	(void) nvlist_add_nvlist_array(newdimm, MCINTEL_NVLIST_RANKS, newrank,
150 	    nb_dimm->nranks);
151 	for (i = 0; i < nb_dimm->nranks; i++)
152 		nvlist_free(newrank[i]);
153 	kmem_free(newrank, sizeof (nvlist_t *) * nb_dimm->nranks);
154 }
155 
156 nvlist_t *
157 inb_dimm(nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
158 {
159 	nvlist_t *newdimm;
160 	uint8_t t;
161 	char sbuf[65];
162 
163 	(void) nvlist_alloc(&newdimm, NV_UNIQUE_NAME, KM_SLEEP);
164 	(void) nvlist_add_uint32(newdimm, "dimm-number", dimm);
165 
166 	if (nb_dimm->dimm_size >= 1024*1024*1024) {
167 		(void) snprintf(sbuf, sizeof (sbuf), "%dG",
168 		    (int)(nb_dimm->dimm_size / (1024*1024*1024)));
169 	} else {
170 		(void) snprintf(sbuf, sizeof (sbuf), "%dM",
171 		    (int)(nb_dimm->dimm_size / (1024*1024)));
172 	}
173 	(void) nvlist_add_string(newdimm, "dimm-size", sbuf);
174 	(void) nvlist_add_uint64(newdimm, "size", nb_dimm->dimm_size);
175 	(void) nvlist_add_uint32(newdimm, "nbanks", (uint32_t)nb_dimm->nbanks);
176 	(void) nvlist_add_uint32(newdimm, "ncolumn",
177 	    (uint32_t)nb_dimm->ncolumn);
178 	(void) nvlist_add_uint32(newdimm, "nrow", (uint32_t)nb_dimm->nrow);
179 	(void) nvlist_add_uint32(newdimm, "width", (uint32_t)nb_dimm->width);
180 	(void) nvlist_add_uint32(newdimm, "ranks", (uint32_t)nb_dimm->nranks);
181 	inb_rank(newdimm, nb_dimm, channel, dimm);
182 	(void) nvlist_add_uint32(newdimm, "manufacture-id",
183 	    (uint32_t)nb_dimm->manufacture_id);
184 	(void) nvlist_add_uint32(newdimm, "manufacture-location",
185 	    (uint32_t)nb_dimm->manufacture_location);
186 	(void) nvlist_add_uint32(newdimm, "manufacture-week",
187 	    (uint32_t)nb_dimm->manufacture_week);
188 	(void) nvlist_add_uint32(newdimm, "manufacture-year",
189 	    (uint32_t)nb_dimm->manufacture_year + 2000);
190 	/* create Sun Serial number from SPD data */
191 	(void) snprintf(sbuf, sizeof (sbuf), "%04x%02x%02x%02x%08x",
192 	    (uint32_t)nb_dimm->manufacture_id & 0x7fff,
193 	    (uint32_t)nb_dimm->manufacture_location,
194 	    (uint32_t)nb_dimm->manufacture_year,
195 	    (uint32_t)nb_dimm->manufacture_week,
196 	    nb_dimm->serial_number);
197 	(void) nvlist_add_string(newdimm, FM_FMRI_HC_SERIAL_ID, sbuf);
198 	if (nb_dimm->part_number && nb_dimm->part_number[0]) {
199 		t = sizeof (nb_dimm->part_number);
200 		(void) strncpy(sbuf, nb_dimm->part_number, t);
201 		sbuf[t] = 0;
202 		(void) nvlist_add_string(newdimm, FM_FMRI_HC_PART, sbuf);
203 	}
204 	if (nb_dimm->revision && nb_dimm->revision[0]) {
205 		t = sizeof (nb_dimm->revision);
206 		(void) strncpy(sbuf, nb_dimm->revision, t);
207 		sbuf[t] = 0;
208 		(void) nvlist_add_string(newdimm, FM_FMRI_HC_REVISION, sbuf);
209 	}
210 	t = sizeof (nb_dimm->label);
211 	(void) strncpy(sbuf, nb_dimm->label, t);
212 	sbuf[t] = 0;
213 	(void) nvlist_add_string(newdimm, FM_FAULT_FRU_LABEL, sbuf);
214 	return (newdimm);
215 }
216 
217 static void
218 inb_dimmlist(nvlist_t *nvl)
219 {
220 	nvlist_t **dimmlist;
221 	nvlist_t **newchannel;
222 	int nchannels = nb_number_memory_controllers * 2;
223 	int nd;
224 	uint8_t i, j;
225 	nb_dimm_t **dimmpp;
226 	nb_dimm_t *dimmp;
227 
228 	dimmlist =  kmem_zalloc(sizeof (nvlist_t *) * nb_dimms_per_channel,
229 	    KM_SLEEP);
230 	newchannel = kmem_zalloc(sizeof (nvlist_t *) * nchannels, KM_SLEEP);
231 	dimmpp = nb_dimms;
232 	for (i = 0; i < nchannels; i++) {
233 		(void) nvlist_alloc(&newchannel[i], NV_UNIQUE_NAME, KM_SLEEP);
234 		nd = 0;
235 		for (j = 0; j < nb_dimms_per_channel; j++) {
236 			dimmp = *dimmpp;
237 			if (dimmp != NULL) {
238 				dimmlist[nd] = inb_dimm(dimmp, i, (uint32_t)j);
239 				nd++;
240 			}
241 			dimmpp++;
242 		}
243 		if (nd) {
244 			(void) nvlist_add_nvlist_array(newchannel[i],
245 			    "memory-dimms", dimmlist, nd);
246 			for (j = 0; j < nd; j++)
247 				nvlist_free(dimmlist[j]);
248 		}
249 	}
250 	(void) nvlist_add_nvlist_array(nvl, MCINTEL_NVLIST_MC, newchannel,
251 	    nchannels);
252 	for (i = 0; i < nchannels; i++)
253 		nvlist_free(newchannel[i]);
254 	kmem_free(dimmlist, sizeof (nvlist_t *) * nb_dimms_per_channel);
255 	kmem_free(newchannel, sizeof (nvlist_t *) * nchannels);
256 }
257 
258 static char *
259 inb_mc_name()
260 {
261 	char *mc;
262 
263 	switch (nb_chipset) {
264 	case INTEL_NB_7300:
265 		mc = "Intel 7300";
266 		break;
267 	case INTEL_NB_5400:
268 		mc = "Intel 5400";
269 		break;
270 	case INTEL_NB_5400A:
271 		mc = "Intel 5400A";
272 		break;
273 	case INTEL_NB_5400B:
274 		mc = "Intel 5400B";
275 		break;
276 	case INTEL_NB_5000P:
277 		mc = "Intel 5000P";
278 		break;
279 	case INTEL_NB_5000V:
280 		mc = "Intel 5000V";
281 		break;
282 	case INTEL_NB_5000X:
283 		mc = "Intel 5000X";
284 		break;
285 	case INTEL_NB_5000Z:
286 		mc = "Intel 5000Z";
287 		break;
288 	default:
289 		mc = "Intel 5000";
290 		break;
291 	}
292 	return (mc);
293 }
294 
295 static void
296 inb_create_nvl()
297 {
298 	nvlist_t *nvl;
299 
300 	(void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
301 	(void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR,
302 	    MCINTEL_NVLIST_VERS);
303 	(void) nvlist_add_string(nvl, "memory-controller", inb_mc_name());
304 	inb_dimmlist(nvl);
305 
306 	if (inb_mc_nvl)
307 		nvlist_free(inb_mc_nvl);
308 	inb_mc_nvl = nvl;
309 }
310 
311 static void
312 inb_mc_snapshot_destroy()
313 {
314 	ASSERT(RW_LOCK_HELD(&inb_mc_lock));
315 
316 	if (inb_mc_snapshot == NULL)
317 		return;
318 
319 	kmem_free(inb_mc_snapshot, inb_mc_snapshotsz);
320 	inb_mc_snapshot = NULL;
321 	inb_mc_snapshotsz = 0;
322 	inb_mc_snapshotgen++;
323 }
324 
325 static int
326 inb_mc_snapshot_update()
327 {
328 	ASSERT(RW_LOCK_HELD(&inb_mc_lock));
329 
330 	if (inb_mc_snapshot != NULL)
331 		return (0);
332 
333 	if (nvlist_pack(inb_mc_nvl, &inb_mc_snapshot, &inb_mc_snapshotsz,
334 	    NV_ENCODE_XDR, KM_SLEEP) != 0)
335 		return (-1);
336 
337 	return (0);
338 }
339 
340 /*ARGSUSED*/
341 static int
342 inb_mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
343     int *rvalp)
344 {
345 	int rc = 0;
346 	mc_snapshot_info_t mcs;
347 
348 	if (cmd != MC_IOC_SNAPSHOT_INFO && cmd != MC_IOC_SNAPSHOT)
349 		return (EINVAL);
350 
351 	rw_enter(&inb_mc_lock, RW_READER);
352 	if (inb_mc_nvl == NULL || inb_mc_snapshotgen != nb_config_gen) {
353 		if (!rw_tryupgrade(&inb_mc_lock)) {
354 			rw_exit(&inb_mc_lock);
355 			return (EAGAIN);
356 		}
357 		if (inb_mc_nvl)
358 			inb_mc_snapshot_destroy();
359 		inb_create_nvl();
360 		nb_config_gen = inb_mc_snapshotgen;
361 		(void) inb_mc_snapshot_update();
362 	}
363 	switch (cmd) {
364 	case MC_IOC_SNAPSHOT_INFO:
365 		mcs.mcs_size = (uint32_t)inb_mc_snapshotsz;
366 		mcs.mcs_gen = inb_mc_snapshotgen;
367 
368 		if (ddi_copyout(&mcs, (void *)arg, sizeof (mc_snapshot_info_t),
369 		    mode) < 0)
370 			rc = EFAULT;
371 		break;
372 	case MC_IOC_SNAPSHOT:
373 		if (ddi_copyout(inb_mc_snapshot, (void *)arg, inb_mc_snapshotsz,
374 		    mode) < 0)
375 			rc = EFAULT;
376 		break;
377 	}
378 	rw_exit(&inb_mc_lock);
379 	return (rc);
380 }
381 
382 /*ARGSUSED*/
383 static int
384 inb_mc_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
385     void **result)
386 {
387 	if ((infocmd != DDI_INFO_DEVT2DEVINFO &&
388 	    infocmd != DDI_INFO_DEVT2INSTANCE) || inb_dip == NULL) {
389 		*result = NULL;
390 		return (DDI_FAILURE);
391 	}
392 	if (infocmd == DDI_INFO_DEVT2DEVINFO)
393 		*result = inb_dip;
394 	else
395 		*result = (void *)(uintptr_t)ddi_get_instance(inb_dip);
396 	return (0);
397 }
398 
399 static int
400 inb_mc_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
401 {
402 	if (cmd == DDI_RESUME) {
403 		nb_dev_reinit();
404 		return (DDI_SUCCESS);
405 	}
406 	if (cmd != DDI_ATTACH)
407 		return (DDI_FAILURE);
408 	if (inb_dip == NULL) {
409 		inb_dip = dip;
410 		(void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
411 		    inb_mc_name());
412 		nb_pci_cfg_setup(dip);
413 		if (nb_dev_init()) {
414 			nb_pci_cfg_free();
415 			inb_dip = NULL;
416 			return (DDI_FAILURE);
417 		}
418 		if (ddi_create_minor_node(dip, "mc-intel", S_IFCHR, 0,
419 		    "ddi_mem_ctrl", 0) != DDI_SUCCESS) {
420 			cmn_err(CE_WARN, "failed to create minor node"
421 			    " for memory controller\n");
422 		}
423 		cmi_hdl_walk(inb_mc_register, NULL, NULL, NULL);
424 	}
425 
426 	return (DDI_SUCCESS);
427 }
428 
429 /*ARGSUSED*/
430 static int
431 inb_mc_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
432 {
433 	if (nb_allow_detach && cmd == DDI_DETACH && dip == inb_dip) {
434 		rw_enter(&inb_mc_lock, RW_WRITER);
435 		inb_mc_snapshot_destroy();
436 		rw_exit(&inb_mc_lock);
437 		inb_dip = NULL;
438 		return (DDI_SUCCESS);
439 	} else if (cmd == DDI_SUSPEND || cmd == DDI_PM_SUSPEND) {
440 		return (DDI_SUCCESS);
441 	} else {
442 		return (DDI_FAILURE);
443 	}
444 }
445 
446 /*ARGSUSED*/
447 static int
448 inb_mc_open(dev_t *devp, int flag, int otyp, cred_t *credp)
449 {
450 	if (otyp != OTYP_CHR)
451 		return (EINVAL);
452 
453 	rw_enter(&inb_mc_lock, RW_READER);
454 	if (getminor(*devp) >= 1) {
455 		rw_exit(&inb_mc_lock);
456 		return (EINVAL);
457 	}
458 	rw_exit(&inb_mc_lock);
459 
460 	return (0);
461 }
462 
463 /*ARGSUSED*/
464 static int
465 inb_mc_close(dev_t dev, int flag, int otyp, cred_t *credp)
466 {
467 	return (0);
468 }
469 
470 
471 static struct cb_ops inb_mc_cb_ops = {
472 	inb_mc_open,
473 	inb_mc_close,
474 	nodev,		/* not a block driver */
475 	nodev,		/* no print routine */
476 	nodev,		/* no dump routine */
477 	nodev,		/* no read routine */
478 	nodev,		/* no write routine */
479 	inb_mc_ioctl,
480 	nodev,		/* no devmap routine */
481 	nodev,		/* no mmap routine */
482 	nodev,		/* no segmap routine */
483 	nochpoll,	/* no chpoll routine */
484 	ddi_prop_op,
485 	0,		/* not a STREAMS driver */
486 	D_NEW | D_MP,	/* safe for multi-thread/multi-processor */
487 };
488 
489 static struct dev_ops inb_mc_ops = {
490 	DEVO_REV,		/* devo_rev */
491 	0,			/* devo_refcnt */
492 	inb_mc_getinfo,		/* devo_getinfo */
493 	nulldev,		/* devo_identify */
494 	nulldev,		/* devo_probe */
495 	inb_mc_attach,		/* devo_attach */
496 	inb_mc_detach,		/* devo_detach */
497 	nodev,			/* devo_reset */
498 	&inb_mc_cb_ops,		/* devo_cb_ops */
499 	NULL,			/* devo_bus_ops */
500 	NULL,			/* devo_power */
501 	ddi_quiesce_not_needed,		/* devo_quiesce */
502 };
503 
504 static struct modldrv modldrv = {
505 	&mod_driverops,
506 	"Intel 5000 Memory Controller Hub Module",
507 	&inb_mc_ops
508 };
509 
510 static struct modlinkage modlinkage = {
511 	MODREV_1,
512 	(void *)&modldrv,
513 	NULL
514 };
515 
516 int
517 _init(void)
518 {
519 	int err;
520 
521 	err = nb_init();
522 	if (err == 0 && (err = mod_install(&modlinkage)) == 0)
523 		rw_init(&inb_mc_lock, NULL, RW_DRIVER, NULL);
524 
525 	return (err);
526 }
527 
528 int
529 _info(struct modinfo *modinfop)
530 {
531 	return (mod_info(&modlinkage, modinfop));
532 }
533 
534 int
535 _fini(void)
536 {
537 	int err;
538 
539 	if ((err = mod_remove(&modlinkage)) == 0) {
540 		nb_unload();
541 		rw_destroy(&inb_mc_lock);
542 	}
543 
544 	return (err);
545 }
546