1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/time.h> 31 #include <sys/nvpair.h> 32 #include <sys/cmn_err.h> 33 #include <sys/cred.h> 34 #include <sys/open.h> 35 #include <sys/ddi.h> 36 #include <sys/sunddi.h> 37 #include <sys/conf.h> 38 #include <sys/modctl.h> 39 #include <sys/cyclic.h> 40 #include <sys/errorq.h> 41 #include <sys/stat.h> 42 #include <sys/cpuvar.h> 43 #include <sys/mc_intel.h> 44 #include <sys/mc.h> 45 #include <sys/fm/protocol.h> 46 #include "nb_log.h" 47 #include "nb5000.h" 48 49 char _depends_on[] = "drv/smbios"; 50 51 nvlist_t *inb_mc_nvl; 52 krwlock_t inb_mc_lock; 53 54 char *inb_mc_snapshot; 55 uint_t nb_config_gen; 56 uint_t inb_mc_snapshotgen; 57 size_t inb_mc_snapshotsz; 58 static dev_info_t *inb_dip; 59 int nb_allow_detach = 0; 60 61 static uint64_t 62 rank_to_base(uint8_t branch, uint8_t rank, uint8_t *interleave, uint64_t *limit, 63 uint64_t *hole_base, uint64_t *hole_size, uint8_t *wayp, 64 uint8_t *branch_interleavep) 65 { 66 uint8_t i, j; 67 uint64_t base = 0; 68 uint64_t lt = 0; 69 uint64_t h = 0; 70 uint64_t hs = 0; 71 uint8_t il = 1; 72 uint8_t way = 0; 73 uint8_t branch_interleave = 0; 74 75 for (i = 0; i < NB_MEM_RANK_SELECT; i++) { 76 for (j = 0; j < NB_RANKS_IN_SELECT; j++) { 77 if (nb_ranks[branch][i].rank[j] == rank) { 78 base = nb_ranks[branch][i].base; 79 lt = nb_ranks[branch][i].limit; 80 il = nb_ranks[branch][i].interleave; 81 h = nb_ranks[branch][i].hole_base; 82 hs = nb_ranks[branch][i].hole_size; 83 way = j; 84 branch_interleave = 85 nb_ranks[branch][i].branch_interleave; 86 i = NB_MEM_RANK_SELECT; 87 break; 88 } 89 } 90 } 91 if (lt == 0) { 92 for (i = 0; lt == 0 && i < NB_MEM_BRANCH_SELECT; i++) { 93 if (nb_banks[i].way[branch] && 94 base >= nb_banks[i].base && 95 base < nb_banks[i].base + nb_banks[i].limit) { 96 lt = nb_banks[i].limit; 97 break; 98 } 99 } 100 } 101 *interleave = il; 102 *limit = lt; 103 *hole_base = h; 104 *hole_size = hs; 105 *wayp = way; 106 *branch_interleavep = branch_interleave; 107 return (base); 108 } 109 110 void 111 inb_rank(nvlist_t *newdimm, nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm) 112 { 113 nvlist_t **newrank; 114 int i; 115 116 newrank = kmem_zalloc(sizeof (nvlist_t *) * nb_dimm->nranks, KM_SLEEP); 117 for (i = 0; i < nb_dimm->nranks; i++) { 118 uint64_t dimm_base; 119 uint64_t limit; 120 uint8_t interleave; 121 uint8_t way; 122 uint8_t branch_interleave; 123 uint64_t hole_base; 124 uint64_t hole_size; 125 126 dimm_base = rank_to_base(channel/2, dimm*2 + i, &interleave, 127 &limit, &hole_base, &hole_size, &way, &branch_interleave); 128 (void) nvlist_alloc(&newrank[i], NV_UNIQUE_NAME, KM_SLEEP); 129 130 (void) nvlist_add_uint64(newrank[i], "dimm-rank-base", 131 dimm_base); 132 if (hole_size) { 133 (void) nvlist_add_uint64(newrank[i], "dimm-hole", 134 hole_base); 135 (void) nvlist_add_uint64(newrank[i], "dimm-hole-size", 136 hole_size); 137 } 138 (void) nvlist_add_uint64(newrank[i], "dimm-rank-limit", 139 limit); 140 if (interleave > 1) { 141 (void) nvlist_add_uint32(newrank[i], 142 "dimm-rank-interleave", (uint32_t)interleave); 143 (void) nvlist_add_uint32(newrank[i], 144 "dimm-rank-interleave-way", (uint32_t)way); 145 if (branch_interleave) { 146 (void) nvlist_add_uint32(newrank[i], 147 "dimm-rank-interleave-branch", (uint32_t)1); 148 } 149 } 150 } 151 (void) nvlist_add_nvlist_array(newdimm, MCINTEL_NVLIST_RANKS, newrank, 152 nb_dimm->nranks); 153 for (i = 0; i < nb_dimm->nranks; i++) 154 nvlist_free(newrank[i]); 155 kmem_free(newrank, sizeof (nvlist_t *) * nb_dimm->nranks); 156 } 157 158 nvlist_t * 159 inb_dimm(nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm) 160 { 161 nvlist_t *newdimm; 162 uint8_t t; 163 char sbuf[65]; 164 165 (void) nvlist_alloc(&newdimm, NV_UNIQUE_NAME, KM_SLEEP); 166 (void) nvlist_add_uint32(newdimm, "dimm-number", dimm); 167 168 if (nb_dimm->dimm_size >= 1024*1024*1024) { 169 (void) snprintf(sbuf, sizeof (sbuf), "%dG", 170 (int)(nb_dimm->dimm_size / (1024*1024*1024))); 171 } else { 172 (void) snprintf(sbuf, sizeof (sbuf), "%dM", 173 (int)(nb_dimm->dimm_size / (1024*1024))); 174 } 175 (void) nvlist_add_string(newdimm, "dimm-size", sbuf); 176 (void) nvlist_add_uint64(newdimm, "size", nb_dimm->dimm_size); 177 (void) nvlist_add_uint32(newdimm, "nbanks", (uint32_t)nb_dimm->nbanks); 178 (void) nvlist_add_uint32(newdimm, "ncolumn", 179 (uint32_t)nb_dimm->ncolumn); 180 (void) nvlist_add_uint32(newdimm, "nrow", (uint32_t)nb_dimm->nrow); 181 (void) nvlist_add_uint32(newdimm, "width", (uint32_t)nb_dimm->width); 182 (void) nvlist_add_uint32(newdimm, "ranks", (uint32_t)nb_dimm->nranks); 183 inb_rank(newdimm, nb_dimm, channel, dimm); 184 (void) nvlist_add_uint32(newdimm, "manufacture-id", 185 (uint32_t)nb_dimm->manufacture_id); 186 (void) nvlist_add_uint32(newdimm, "manufacture-location", 187 (uint32_t)nb_dimm->manufacture_location); 188 (void) nvlist_add_uint32(newdimm, "manufacture-week", 189 (uint32_t)nb_dimm->manufacture_week); 190 (void) nvlist_add_uint32(newdimm, "manufacture-year", 191 (uint32_t)nb_dimm->manufacture_year + 2000); 192 /* create Sun Serial number from SPD data */ 193 (void) snprintf(sbuf, sizeof (sbuf), "%04x%02x%02x%02x%08x", 194 (uint32_t)nb_dimm->manufacture_id & 0x7fff, 195 (uint32_t)nb_dimm->manufacture_location, 196 (uint32_t)nb_dimm->manufacture_year, 197 (uint32_t)nb_dimm->manufacture_week, 198 nb_dimm->serial_number); 199 (void) nvlist_add_string(newdimm, FM_FMRI_HC_SERIAL_ID, sbuf); 200 if (nb_dimm->part_number && nb_dimm->part_number[0]) { 201 t = sizeof (nb_dimm->part_number); 202 (void) strncpy(sbuf, nb_dimm->part_number, t); 203 sbuf[t] = 0; 204 (void) nvlist_add_string(newdimm, FM_FMRI_HC_PART, sbuf); 205 } 206 if (nb_dimm->revision && nb_dimm->revision[0]) { 207 t = sizeof (nb_dimm->revision); 208 (void) strncpy(sbuf, nb_dimm->revision, t); 209 sbuf[t] = 0; 210 (void) nvlist_add_string(newdimm, FM_FMRI_HC_REVISION, sbuf); 211 } 212 t = sizeof (nb_dimm->label); 213 (void) strncpy(sbuf, nb_dimm->label, t); 214 sbuf[t] = 0; 215 (void) nvlist_add_string(newdimm, FM_FAULT_FRU_LABEL, sbuf); 216 return (newdimm); 217 } 218 219 static void 220 inb_dimmlist(nvlist_t *nvl) 221 { 222 nvlist_t **dimmlist; 223 nvlist_t **newchannel; 224 int nchannels = nb_number_memory_controllers * 2; 225 int nd; 226 uint8_t i, j; 227 nb_dimm_t **dimmpp; 228 nb_dimm_t *dimmp; 229 230 dimmlist = kmem_zalloc(sizeof (nvlist_t *) * nb_dimms_per_channel, 231 KM_SLEEP); 232 newchannel = kmem_zalloc(sizeof (nvlist_t *) * nchannels, KM_SLEEP); 233 dimmpp = nb_dimms; 234 for (i = 0; i < nchannels; i++) { 235 (void) nvlist_alloc(&newchannel[i], NV_UNIQUE_NAME, KM_SLEEP); 236 nd = 0; 237 for (j = 0; j < nb_dimms_per_channel; j++) { 238 dimmp = *dimmpp; 239 if (dimmp != NULL) { 240 dimmlist[nd] = inb_dimm(dimmp, i, (uint32_t)j); 241 nd++; 242 } 243 dimmpp++; 244 } 245 if (nd) { 246 (void) nvlist_add_nvlist_array(newchannel[i], 247 "memory-dimms", dimmlist, nd); 248 for (j = 0; j < nd; j++) 249 nvlist_free(dimmlist[j]); 250 } 251 } 252 (void) nvlist_add_nvlist_array(nvl, MCINTEL_NVLIST_MC, newchannel, 253 nchannels); 254 for (i = 0; i < nchannels; i++) 255 nvlist_free(newchannel[i]); 256 kmem_free(dimmlist, sizeof (nvlist_t *) * nb_dimms_per_channel); 257 kmem_free(newchannel, sizeof (nvlist_t *) * nchannels); 258 } 259 260 static char * 261 inb_mc_name() 262 { 263 char *mc; 264 265 switch (nb_chipset) { 266 case INTEL_NB_7300: 267 mc = "Intel 7300"; 268 break; 269 case INTEL_NB_5400: 270 mc = "Intel 5400"; 271 break; 272 case INTEL_NB_5400A: 273 mc = "Intel 5400A"; 274 break; 275 case INTEL_NB_5400B: 276 mc = "Intel 5400B"; 277 break; 278 case INTEL_NB_5000P: 279 mc = "Intel 5000P"; 280 break; 281 case INTEL_NB_5000V: 282 mc = "Intel 5000V"; 283 break; 284 case INTEL_NB_5000X: 285 mc = "Intel 5000X"; 286 break; 287 case INTEL_NB_5000Z: 288 mc = "Intel 5000Z"; 289 break; 290 default: 291 mc = "Intel 5000"; 292 break; 293 } 294 return (mc); 295 } 296 297 static void 298 inb_create_nvl() 299 { 300 nvlist_t *nvl; 301 302 (void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP); 303 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR, 304 MCINTEL_NVLIST_VERS); 305 (void) nvlist_add_string(nvl, "memory-controller", inb_mc_name()); 306 inb_dimmlist(nvl); 307 308 if (inb_mc_nvl) 309 nvlist_free(inb_mc_nvl); 310 inb_mc_nvl = nvl; 311 } 312 313 static void 314 inb_mc_snapshot_destroy() 315 { 316 ASSERT(RW_LOCK_HELD(&inb_mc_lock)); 317 318 if (inb_mc_snapshot == NULL) 319 return; 320 321 kmem_free(inb_mc_snapshot, inb_mc_snapshotsz); 322 inb_mc_snapshot = NULL; 323 inb_mc_snapshotsz = 0; 324 inb_mc_snapshotgen++; 325 } 326 327 static int 328 inb_mc_snapshot_update() 329 { 330 ASSERT(RW_LOCK_HELD(&inb_mc_lock)); 331 332 if (inb_mc_snapshot != NULL) 333 return (0); 334 335 if (nvlist_pack(inb_mc_nvl, &inb_mc_snapshot, &inb_mc_snapshotsz, 336 NV_ENCODE_XDR, KM_SLEEP) != 0) 337 return (-1); 338 339 return (0); 340 } 341 342 /*ARGSUSED*/ 343 static int 344 inb_mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 345 int *rvalp) 346 { 347 int rc = 0; 348 mc_snapshot_info_t mcs; 349 350 if (cmd != MC_IOC_SNAPSHOT_INFO && cmd != MC_IOC_SNAPSHOT) 351 return (EINVAL); 352 353 rw_enter(&inb_mc_lock, RW_READER); 354 if (inb_mc_nvl == NULL || inb_mc_snapshotgen != nb_config_gen) { 355 if (!rw_tryupgrade(&inb_mc_lock)) { 356 rw_exit(&inb_mc_lock); 357 return (EAGAIN); 358 } 359 if (inb_mc_nvl) 360 inb_mc_snapshot_destroy(); 361 inb_create_nvl(); 362 nb_config_gen = inb_mc_snapshotgen; 363 (void) inb_mc_snapshot_update(); 364 } 365 switch (cmd) { 366 case MC_IOC_SNAPSHOT_INFO: 367 mcs.mcs_size = (uint32_t)inb_mc_snapshotsz; 368 mcs.mcs_gen = inb_mc_snapshotgen; 369 370 if (ddi_copyout(&mcs, (void *)arg, sizeof (mc_snapshot_info_t), 371 mode) < 0) 372 rc = EFAULT; 373 break; 374 case MC_IOC_SNAPSHOT: 375 if (ddi_copyout(inb_mc_snapshot, (void *)arg, inb_mc_snapshotsz, 376 mode) < 0) 377 rc = EFAULT; 378 break; 379 } 380 rw_exit(&inb_mc_lock); 381 return (rc); 382 } 383 384 /*ARGSUSED*/ 385 static int 386 inb_mc_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, 387 void **result) 388 { 389 if ((infocmd != DDI_INFO_DEVT2DEVINFO && 390 infocmd != DDI_INFO_DEVT2INSTANCE) || inb_dip == NULL) { 391 *result = NULL; 392 return (DDI_FAILURE); 393 } 394 if (infocmd == DDI_INFO_DEVT2DEVINFO) 395 *result = inb_dip; 396 else 397 *result = (void *)(uintptr_t)ddi_get_instance(inb_dip); 398 return (0); 399 } 400 401 static int 402 inb_mc_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 403 { 404 if (cmd == DDI_RESUME) { 405 nb_dev_reinit(); 406 return (DDI_SUCCESS); 407 } 408 if (cmd != DDI_ATTACH) 409 return (DDI_FAILURE); 410 if (inb_dip == NULL) { 411 inb_dip = dip; 412 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model", 413 inb_mc_name()); 414 nb_pci_cfg_setup(dip); 415 if (nb_dev_init()) { 416 nb_pci_cfg_free(); 417 inb_dip = NULL; 418 return (DDI_FAILURE); 419 } 420 if (ddi_create_minor_node(dip, "mc-intel", S_IFCHR, 0, 421 "ddi_mem_ctrl", 0) != DDI_SUCCESS) { 422 cmn_err(CE_WARN, "failed to create minor node" 423 " for memory controller\n"); 424 } 425 cmi_hdl_walk(inb_mc_register, NULL, NULL, NULL); 426 } 427 428 return (DDI_SUCCESS); 429 } 430 431 /*ARGSUSED*/ 432 static int 433 inb_mc_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 434 { 435 if (nb_allow_detach && cmd == DDI_DETACH && dip == inb_dip) { 436 rw_enter(&inb_mc_lock, RW_WRITER); 437 inb_mc_snapshot_destroy(); 438 rw_exit(&inb_mc_lock); 439 inb_dip = NULL; 440 return (DDI_SUCCESS); 441 } else if (cmd == DDI_SUSPEND || cmd == DDI_PM_SUSPEND) { 442 return (DDI_SUCCESS); 443 } else { 444 return (DDI_FAILURE); 445 } 446 } 447 448 /*ARGSUSED*/ 449 static int 450 inb_mc_open(dev_t *devp, int flag, int otyp, cred_t *credp) 451 { 452 if (otyp != OTYP_CHR) 453 return (EINVAL); 454 455 rw_enter(&inb_mc_lock, RW_READER); 456 if (getminor(*devp) >= 1) { 457 rw_exit(&inb_mc_lock); 458 return (EINVAL); 459 } 460 rw_exit(&inb_mc_lock); 461 462 return (0); 463 } 464 465 /*ARGSUSED*/ 466 static int 467 inb_mc_close(dev_t dev, int flag, int otyp, cred_t *credp) 468 { 469 return (0); 470 } 471 472 473 static struct cb_ops inb_mc_cb_ops = { 474 inb_mc_open, 475 inb_mc_close, 476 nodev, /* not a block driver */ 477 nodev, /* no print routine */ 478 nodev, /* no dump routine */ 479 nodev, /* no read routine */ 480 nodev, /* no write routine */ 481 inb_mc_ioctl, 482 nodev, /* no devmap routine */ 483 nodev, /* no mmap routine */ 484 nodev, /* no segmap routine */ 485 nochpoll, /* no chpoll routine */ 486 ddi_prop_op, 487 0, /* not a STREAMS driver */ 488 D_NEW | D_MP, /* safe for multi-thread/multi-processor */ 489 }; 490 491 static struct dev_ops inb_mc_ops = { 492 DEVO_REV, /* devo_rev */ 493 0, /* devo_refcnt */ 494 inb_mc_getinfo, /* devo_getinfo */ 495 nulldev, /* devo_identify */ 496 nulldev, /* devo_probe */ 497 inb_mc_attach, /* devo_attach */ 498 inb_mc_detach, /* devo_detach */ 499 nodev, /* devo_reset */ 500 &inb_mc_cb_ops, /* devo_cb_ops */ 501 NULL, /* devo_bus_ops */ 502 NULL /* devo_power */ 503 }; 504 505 static struct modldrv modldrv = { 506 &mod_driverops, 507 "Intel 5000 Memory Controller Hub Module", 508 &inb_mc_ops 509 }; 510 511 static struct modlinkage modlinkage = { 512 MODREV_1, 513 (void *)&modldrv, 514 NULL 515 }; 516 517 int 518 _init(void) 519 { 520 int err; 521 522 err = nb_init(); 523 if (err == 0 && (err = mod_install(&modlinkage)) == 0) 524 rw_init(&inb_mc_lock, NULL, RW_DRIVER, NULL); 525 526 return (err); 527 } 528 529 int 530 _info(struct modinfo *modinfop) 531 { 532 return (mod_info(&modlinkage, modinfop)); 533 } 534 535 int 536 _fini(void) 537 { 538 int err; 539 540 if ((err = mod_remove(&modlinkage)) == 0) { 541 nb_unload(); 542 rw_destroy(&inb_mc_lock); 543 } 544 545 return (err); 546 } 547