1507c3241Smlf /* 2507c3241Smlf * CDDL HEADER START 3507c3241Smlf * 4507c3241Smlf * The contents of this file are subject to the terms of the 5*2d6eb4a5SToomas Soome * Common Development and Distribution License (the "License"). 6507c3241Smlf * You may not use this file except in compliance with the License. 7507c3241Smlf * 8507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9507c3241Smlf * or http://www.opensolaris.org/os/licensing. 10507c3241Smlf * See the License for the specific language governing permissions 11507c3241Smlf * and limitations under the License. 12507c3241Smlf * 13507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each 14507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the 16507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18507c3241Smlf * 19507c3241Smlf * CDDL HEADER END 20507c3241Smlf */ 21507c3241Smlf 22507c3241Smlf /* 23507c3241Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24507c3241Smlf * Use is subject to license terms. 25507c3241Smlf */ 26507c3241Smlf 27507c3241Smlf #ifndef _PCIIDE_H 28507c3241Smlf #define _PCIIDE_H 29507c3241Smlf 30507c3241Smlf #ifdef __cplusplus 31507c3241Smlf extern "C" { 32507c3241Smlf #endif 33507c3241Smlf 34507c3241Smlf 35507c3241Smlf /* 36507c3241Smlf * Bus Mastering devices have a PCI class-code of 0x010180 to 0x0101ff 37507c3241Smlf */ 38507c3241Smlf #define PCIIDE_BM_CAP_MASK 0x80 39507c3241Smlf #define PCIIDE_BM_CLASS ((PCI_CLASS_MASS << 16) | (PCI_MASS_IDE << 8) | 0x80) 40507c3241Smlf #define PCIIDE_BM_CLASS_MASK 0xffffff80 41507c3241Smlf 42507c3241Smlf 43507c3241Smlf #define PCIIDE_BMICX_REG 0 /* Bus Master IDE Command Register */ 44507c3241Smlf 45507c3241Smlf #define PCIIDE_BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 46507c3241Smlf #define PCIIDE_BMICX_SSBM_E 0x01 /* 1=Start (Enable) */ 47507c3241Smlf /* 0=Start (Disable) */ 48507c3241Smlf 49507c3241Smlf /* 50507c3241Smlf * NOTE: "read" and "write" are the actions of the DMA 51507c3241Smlf * engine on the PCI bus. Not the DMA engine's action on the ATA 52507c3241Smlf * BUS. Therefore for a ATA READ command, program the DMA engine to 53507c3241Smlf * "write to memory" mode (and vice versa). 54507c3241Smlf */ 55507c3241Smlf #define PCIIDE_BMICX_RWCON 0x08 /* Read/Write Control */ 56507c3241Smlf #define PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 57507c3241Smlf #define PCIIDE_BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 58507c3241Smlf 59507c3241Smlf /* preserve these bits during updates */ 60507c3241Smlf #define PCIIDE_BMICX_MASK (~(PCIIDE_BMICX_SSBM | PCIIDE_BMICX_RWCON)) 61507c3241Smlf 62507c3241Smlf 63507c3241Smlf 64507c3241Smlf #define PCIIDE_BMISX_REG 2 /* Bus Master IDE Status Register */ 65507c3241Smlf 66507c3241Smlf #define PCIIDE_BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 67507c3241Smlf #define PCIIDE_BMISX_IDERR 0x02 /* IDE DMA Error */ 68507c3241Smlf #define PCIIDE_BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 69507c3241Smlf #define PCIIDE_BMISX_DMA0CAP 0x20 /* Drive 0 DMA Capable */ 70507c3241Smlf #define PCIIDE_BMISX_DMA1CAP 0x40 /* Drive 1 DMA Capable */ 71507c3241Smlf #define PCIIDE_BMISX_SIMPLEX 0x80 /* Simplex only */ 72507c3241Smlf 73507c3241Smlf /* preserve these bits during updates */ 74507c3241Smlf #define PCIIDE_BMISX_MASK 0xf8 75507c3241Smlf 76507c3241Smlf #define PCIIDE_BMIDTPX_REG 4 /* Bus Master IDE Desc. Table Ptr */ 77507c3241Smlf #define PCIIDE_BMIDTPX_MASK 0x00000003 /* must be zeros */ 78507c3241Smlf 79507c3241Smlf 80507c3241Smlf typedef struct PhysicalRegionDescriptorTableEntry { 81507c3241Smlf uint_t p_address; /* physical address */ 82507c3241Smlf uint_t p_count; /* byte count, EOT in high order bit */ 83507c3241Smlf } prde_t; 84507c3241Smlf 85507c3241Smlf /* 86507c3241Smlf * Some specs say the p_address must 32-bit aligned, and some claim 87507c3241Smlf * 16-bit alignment. Use 32-bit alignment just to be safe. 88507c3241Smlf */ 89507c3241Smlf #ifdef __not_yet__ 90507c3241Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (short) -1)) 91507c3241Smlf #else 92507c3241Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (int) -1)) 93507c3241Smlf #endif 94507c3241Smlf 95507c3241Smlf #define PCIIDE_PRDE_CNT_MASK ((uint_t)0x0001) /* must be even */ 96507c3241Smlf #define PCIIDE_PRDE_CNT_MAX ((uint_t)0x10000) /* 0 == 64k */ 97507c3241Smlf #define PCIIDE_PRDE_EOT ((uint_t)0x80000000) 98507c3241Smlf 99507c3241Smlf #ifdef __cplusplus 100507c3241Smlf } 101507c3241Smlf #endif 102507c3241Smlf 103507c3241Smlf #endif /* _PCIIDE_H */ 104