175ab5f91Slh /*
20dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
375ab5f91Slh * Use is subject to license terms.
475ab5f91Slh */
575ab5f91Slh
675ab5f91Slh /*
775ab5f91Slh * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved.
875ab5f91Slh *
975ab5f91Slh * Redistribution and use in source and binary forms, with or without
1075ab5f91Slh * modification, are permitted provided that the following conditions are met:
1175ab5f91Slh *
1275ab5f91Slh * + Redistributions of source code must retain the above copyright notice,
1375ab5f91Slh * + this list of conditions and the following disclaimer.
1475ab5f91Slh *
1575ab5f91Slh * + Redistributions in binary form must reproduce the above copyright
1675ab5f91Slh * + notice, this list of conditions and the following disclaimer in the
1775ab5f91Slh * + documentation and/or other materials provided with the distribution.
1875ab5f91Slh *
1975ab5f91Slh * + Neither the name of Advanced Micro Devices, Inc. nor the names of its
2075ab5f91Slh * + contributors may be used to endorse or promote products derived from
2175ab5f91Slh * + this software without specific prior written permission.
2275ab5f91Slh *
2375ab5f91Slh * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
2475ab5f91Slh * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
2575ab5f91Slh * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2675ab5f91Slh * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2775ab5f91Slh * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
2875ab5f91Slh * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2975ab5f91Slh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3075ab5f91Slh * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3175ab5f91Slh * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
3275ab5f91Slh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
3375ab5f91Slh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
3475ab5f91Slh * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
3575ab5f91Slh * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3675ab5f91Slh *
3775ab5f91Slh * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
3875ab5f91Slh * Compliance with Applicable Laws. Notice is hereby given that
3975ab5f91Slh * the software may be subject to restrictions on use, release,
4075ab5f91Slh * transfer, importation, exportation and/or re-exportation under
4175ab5f91Slh * the laws and regulations of the United States or other
4275ab5f91Slh * countries ("Applicable Laws"), which include but are not
4375ab5f91Slh * limited to U.S. export control laws such as the Export
4475ab5f91Slh * Administration Regulations and national security controls as
4575ab5f91Slh * defined thereunder, as well as State Department controls under
4675ab5f91Slh * the U.S. Munitions List. Permission to use and/or
4775ab5f91Slh * redistribute the software is conditioned upon compliance with
4875ab5f91Slh * all Applicable Laws, including U.S. export control laws
4975ab5f91Slh * regarding specifically designated persons, countries and
5075ab5f91Slh * nationals of countries subject to national security controls.
5175ab5f91Slh */
5275ab5f91Slh
5375ab5f91Slh /* include files */
5475ab5f91Slh #include <sys/disp.h>
5575ab5f91Slh #include <sys/atomic.h>
56d62bc4baSyz #include <sys/vlan.h>
5775ab5f91Slh #include "amd8111s_main.h"
5875ab5f91Slh
5975ab5f91Slh /* Global macro Definations */
6075ab5f91Slh #define ROUNDUP(x, a) (((x) + (a) - 1) & ~((a) - 1))
6175ab5f91Slh #define INTERFACE_NAME "amd8111s"
6275ab5f91Slh #define AMD8111S_SPLIT 128
6375ab5f91Slh #define AMD8111S_SEND_MAX 64
6475ab5f91Slh
6519397407SSherry Moore static char ident[] = "AMD8111 10/100M Ethernet";
6675ab5f91Slh
6775ab5f91Slh /*
6875ab5f91Slh * Driver Entry Points
6975ab5f91Slh */
7075ab5f91Slh static int amd8111s_attach(dev_info_t *, ddi_attach_cmd_t);
7175ab5f91Slh static int amd8111s_detach(dev_info_t *, ddi_detach_cmd_t);
7275ab5f91Slh
7375ab5f91Slh /*
7475ab5f91Slh * GLD Entry points prototype
7575ab5f91Slh */
7675ab5f91Slh static int amd8111s_m_unicst(void *, const uint8_t *);
7775ab5f91Slh static int amd8111s_m_promisc(void *, boolean_t);
7875ab5f91Slh static int amd8111s_m_stat(void *, uint_t, uint64_t *);
7975ab5f91Slh static void amd8111s_m_ioctl(void *, queue_t *, mblk_t *);
8075ab5f91Slh static int amd8111s_m_multicst(void *, boolean_t, const uint8_t *addr);
8175ab5f91Slh static int amd8111s_m_start(void *);
8275ab5f91Slh static void amd8111s_m_stop(void *);
8375ab5f91Slh static mblk_t *amd8111s_m_tx(void *, mblk_t *mp);
8475ab5f91Slh static uint_t amd8111s_intr(caddr_t);
8575ab5f91Slh
8675ab5f91Slh static int amd8111s_unattach(dev_info_t *, struct LayerPointers *);
8775ab5f91Slh
8875ab5f91Slh static boolean_t amd8111s_allocate_buffers(struct LayerPointers *);
8975ab5f91Slh static int amd8111s_odlInit(struct LayerPointers *);
9075ab5f91Slh static boolean_t amd8111s_allocate_descriptors(struct LayerPointers *);
9175ab5f91Slh static void amd8111s_free_descriptors(struct LayerPointers *);
9275ab5f91Slh static boolean_t amd8111s_alloc_dma_ringbuf(struct LayerPointers *,
9375ab5f91Slh struct amd8111s_dma_ringbuf *, uint32_t, uint32_t);
9475ab5f91Slh static void amd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *);
9575ab5f91Slh
9675ab5f91Slh
9775ab5f91Slh static void amd8111s_log(struct LayerPointers *adapter, int level,
9875ab5f91Slh char *fmt, ...);
9975ab5f91Slh
10075ab5f91Slh static struct cb_ops amd8111s_cb_ops = {
10175ab5f91Slh nulldev,
10275ab5f91Slh nulldev,
10375ab5f91Slh nodev,
10475ab5f91Slh nodev,
10575ab5f91Slh nodev,
10675ab5f91Slh nodev,
10775ab5f91Slh nodev,
10875ab5f91Slh nodev,
10975ab5f91Slh nodev,
11075ab5f91Slh nodev,
11175ab5f91Slh nodev,
11275ab5f91Slh nochpoll,
11375ab5f91Slh ddi_prop_op,
11475ab5f91Slh NULL,
11575ab5f91Slh D_NEW | D_MP,
11675ab5f91Slh CB_REV, /* cb_rev */
11775ab5f91Slh nodev, /* cb_aread */
11875ab5f91Slh nodev /* cb_awrite */
11975ab5f91Slh };
12075ab5f91Slh
12175ab5f91Slh static struct dev_ops amd8111s_dev_ops = {
12275ab5f91Slh DEVO_REV, /* devo_rev */
12375ab5f91Slh 0, /* devo_refcnt */
12475ab5f91Slh NULL, /* devo_getinfo */
12575ab5f91Slh nulldev, /* devo_identify */
12675ab5f91Slh nulldev, /* devo_probe */
12775ab5f91Slh amd8111s_attach, /* devo_attach */
12875ab5f91Slh amd8111s_detach, /* devo_detach */
12975ab5f91Slh nodev, /* devo_reset */
13075ab5f91Slh &amd8111s_cb_ops, /* devo_cb_ops */
13175ab5f91Slh NULL, /* devo_bus_ops */
13219397407SSherry Moore nodev, /* devo_power */
13319397407SSherry Moore ddi_quiesce_not_supported, /* devo_quiesce */
13475ab5f91Slh };
13575ab5f91Slh
13675ab5f91Slh struct modldrv amd8111s_modldrv = {
13775ab5f91Slh &mod_driverops, /* Type of module. This one is a driver */
13875ab5f91Slh ident, /* short description */
13975ab5f91Slh &amd8111s_dev_ops /* driver specific ops */
14075ab5f91Slh };
14175ab5f91Slh
14275ab5f91Slh struct modlinkage amd8111s_modlinkage = {
14375ab5f91Slh MODREV_1, (void *)&amd8111s_modldrv, NULL
14475ab5f91Slh };
14575ab5f91Slh
14675ab5f91Slh /*
14775ab5f91Slh * Global Variables
14875ab5f91Slh */
14975ab5f91Slh struct LayerPointers *amd8111sadapter;
15075ab5f91Slh
15175ab5f91Slh static ddi_dma_attr_t pcn_buff_dma_attr_t = {
15275ab5f91Slh DMA_ATTR_V0, /* dma_attr_version */
15375ab5f91Slh (uint64_t)0, /* dma_attr_addr_lo */
15475ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_addr_hi */
15575ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_count_max */
15675ab5f91Slh (uint64_t)1, /* dma_attr_align */
15775ab5f91Slh (uint_t)0x7F, /* dma_attr_burstsizes */
15875ab5f91Slh (uint32_t)1, /* dma_attr_minxfer */
15975ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_maxxfer */
16075ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_seg */
16175ab5f91Slh (int)1, /* dma_attr_sgllen */
16275ab5f91Slh (uint32_t)1, /* granularity */
16375ab5f91Slh (uint_t)0 /* dma_attr_flags */
16475ab5f91Slh };
16575ab5f91Slh
16675ab5f91Slh static ddi_dma_attr_t pcn_desc_dma_attr_t = {
16775ab5f91Slh DMA_ATTR_V0, /* dma_attr_version */
16875ab5f91Slh (uint64_t)0, /* dma_attr_addr_lo */
16975ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_addr_hi */
17075ab5f91Slh (uint64_t)0x7FFFFFFF, /* dma_attr_count_max */
17175ab5f91Slh (uint64_t)0x10, /* dma_attr_align */
17275ab5f91Slh (uint_t)0xFFFFFFFFU, /* dma_attr_burstsizes */
17375ab5f91Slh (uint32_t)1, /* dma_attr_minxfer */
17475ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_maxxfer */
17575ab5f91Slh (uint64_t)0xFFFFFFFF, /* dma_attr_seg */
17675ab5f91Slh (int)1, /* dma_attr_sgllen */
17775ab5f91Slh (uint32_t)1, /* granularity */
17875ab5f91Slh (uint_t)0 /* dma_attr_flags */
17975ab5f91Slh };
18075ab5f91Slh
18175ab5f91Slh /* PIO access attributes for registers */
18275ab5f91Slh static ddi_device_acc_attr_t pcn_acc_attr = {
18375ab5f91Slh DDI_DEVICE_ATTR_V0,
18475ab5f91Slh DDI_STRUCTURE_LE_ACC,
18575ab5f91Slh DDI_STRICTORDER_ACC
18675ab5f91Slh };
18775ab5f91Slh
18875ab5f91Slh
18975ab5f91Slh static mac_callbacks_t amd8111s_m_callbacks = {
190da14cebeSEric Cheng MC_IOCTL,
19175ab5f91Slh amd8111s_m_stat,
19275ab5f91Slh amd8111s_m_start,
19375ab5f91Slh amd8111s_m_stop,
19475ab5f91Slh amd8111s_m_promisc,
19575ab5f91Slh amd8111s_m_multicst,
19675ab5f91Slh amd8111s_m_unicst,
19775ab5f91Slh amd8111s_m_tx,
1980dc2366fSVenugopal Iyer NULL,
19975ab5f91Slh amd8111s_m_ioctl
20075ab5f91Slh };
20175ab5f91Slh
20275ab5f91Slh
20375ab5f91Slh /*
20475ab5f91Slh * Standard Driver Load Entry Point
20575ab5f91Slh * It will be called at load time of driver.
20675ab5f91Slh */
20775ab5f91Slh int
_init()20875ab5f91Slh _init()
20975ab5f91Slh {
21075ab5f91Slh int status;
21175ab5f91Slh mac_init_ops(&amd8111s_dev_ops, "amd8111s");
21275ab5f91Slh
21375ab5f91Slh status = mod_install(&amd8111s_modlinkage);
21475ab5f91Slh if (status != DDI_SUCCESS) {
21575ab5f91Slh mac_fini_ops(&amd8111s_dev_ops);
21675ab5f91Slh }
21775ab5f91Slh
21875ab5f91Slh return (status);
21975ab5f91Slh }
22075ab5f91Slh
22175ab5f91Slh /*
22275ab5f91Slh * Standard Driver Entry Point for Query.
22375ab5f91Slh * It will be called at any time to get Driver info.
22475ab5f91Slh */
22575ab5f91Slh int
_info(struct modinfo * modinfop)22675ab5f91Slh _info(struct modinfo *modinfop)
22775ab5f91Slh {
22875ab5f91Slh return (mod_info(&amd8111s_modlinkage, modinfop));
22975ab5f91Slh }
23075ab5f91Slh
23175ab5f91Slh /*
23275ab5f91Slh * Standard Driver Entry Point for Unload.
23375ab5f91Slh * It will be called at unload time of driver.
23475ab5f91Slh */
23575ab5f91Slh int
_fini()23675ab5f91Slh _fini()
23775ab5f91Slh {
23875ab5f91Slh int status;
23975ab5f91Slh
24075ab5f91Slh status = mod_remove(&amd8111s_modlinkage);
24175ab5f91Slh if (status == DDI_SUCCESS) {
24275ab5f91Slh mac_fini_ops(&amd8111s_dev_ops);
24375ab5f91Slh }
24475ab5f91Slh
24575ab5f91Slh return (status);
24675ab5f91Slh }
24775ab5f91Slh
24875ab5f91Slh /*
24975ab5f91Slh * Loopback Support
25075ab5f91Slh */
25175ab5f91Slh static lb_property_t loopmodes[] = {
25275ab5f91Slh { normal, "normal", AMD8111S_LB_NONE },
25375ab5f91Slh { external, "100Mbps", AMD8111S_LB_EXTERNAL_100 },
25475ab5f91Slh { external, "10Mbps", AMD8111S_LB_EXTERNAL_10 },
25575ab5f91Slh { internal, "MAC", AMD8111S_LB_INTERNAL_MAC }
25675ab5f91Slh };
25775ab5f91Slh
25875ab5f91Slh static void
amd8111s_set_loop_mode(struct LayerPointers * adapter,uint32_t mode)25975ab5f91Slh amd8111s_set_loop_mode(struct LayerPointers *adapter, uint32_t mode)
26075ab5f91Slh {
26175ab5f91Slh
26275ab5f91Slh /*
26375ab5f91Slh * If the mode isn't being changed, there's nothing to do ...
26475ab5f91Slh */
26575ab5f91Slh if (mode == adapter->pOdl->loopback_mode)
26675ab5f91Slh return;
26775ab5f91Slh
26875ab5f91Slh /*
26975ab5f91Slh * Validate the requested mode and prepare a suitable message
27075ab5f91Slh * to explain the link down/up cycle that the change will
27175ab5f91Slh * probably induce ...
27275ab5f91Slh */
27375ab5f91Slh switch (mode) {
27475ab5f91Slh default:
27575ab5f91Slh return;
27675ab5f91Slh
27775ab5f91Slh case AMD8111S_LB_NONE:
27875ab5f91Slh mdlStopChip(adapter);
27975ab5f91Slh if (adapter->pOdl->loopback_mode == AMD8111S_LB_INTERNAL_MAC) {
28075ab5f91Slh cmn_err(CE_NOTE, "LB_NONE restored from Interanl LB");
28175ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
28275ab5f91Slh INLOOP);
28375ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
28475ab5f91Slh FORCE_FULL_DUPLEX | FORCE_LINK_STATUS);
28575ab5f91Slh } else {
28675ab5f91Slh cmn_err(CE_NOTE, "LB_NONE restored from Exteranl LB");
28775ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
28875ab5f91Slh EXLOOP);
28975ab5f91Slh }
29075ab5f91Slh
29175ab5f91Slh amd8111s_reset(adapter);
29275ab5f91Slh adapter->pOdl->LinkStatus = LINK_STATE_DOWN;
29375ab5f91Slh adapter->pOdl->rx_fcs_stripped = B_FALSE;
29475ab5f91Slh mdlStartChip(adapter);
29575ab5f91Slh break;
29675ab5f91Slh
29775ab5f91Slh case AMD8111S_LB_EXTERNAL_100:
29875ab5f91Slh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_100");
29975ab5f91Slh mdlStopChip(adapter);
30075ab5f91Slh amd8111s_reset(adapter);
30175ab5f91Slh SetIntrCoalesc(adapter, B_FALSE);
30275ab5f91Slh mdlPHYAutoNegotiation(adapter, PHY_FORCE_FD_100);
30375ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
30475ab5f91Slh VAL0 | EXLOOP);
30575ab5f91Slh adapter->pOdl->LinkStatus = LINK_STATE_UP;
30675ab5f91Slh adapter->pMdl->Speed = 100;
30775ab5f91Slh adapter->pMdl->FullDuplex = B_TRUE;
30875ab5f91Slh /* Tell GLD the state of the physical link. */
30975ab5f91Slh mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
31075ab5f91Slh
31175ab5f91Slh adapter->pOdl->rx_fcs_stripped = B_TRUE;
31275ab5f91Slh
31375ab5f91Slh mdlStartChip(adapter);
31475ab5f91Slh break;
31575ab5f91Slh
31675ab5f91Slh case AMD8111S_LB_EXTERNAL_10:
31775ab5f91Slh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_EXTERNAL_10");
31875ab5f91Slh mdlStopChip(adapter);
31975ab5f91Slh amd8111s_reset(adapter);
32075ab5f91Slh SetIntrCoalesc(adapter, B_FALSE);
32175ab5f91Slh mdlPHYAutoNegotiation(adapter, PHY_FORCE_FD_10);
32275ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
32375ab5f91Slh VAL0 | EXLOOP);
32475ab5f91Slh adapter->pOdl->LinkStatus = LINK_STATE_UP;
32575ab5f91Slh adapter->pMdl->Speed = 10;
32675ab5f91Slh adapter->pMdl->FullDuplex = B_TRUE;
32775ab5f91Slh /* Tell GLD the state of the physical link. */
32875ab5f91Slh mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
32975ab5f91Slh
33075ab5f91Slh adapter->pOdl->rx_fcs_stripped = B_TRUE;
33175ab5f91Slh
33275ab5f91Slh mdlStartChip(adapter);
33375ab5f91Slh break;
33475ab5f91Slh
33575ab5f91Slh case AMD8111S_LB_INTERNAL_MAC:
33675ab5f91Slh cmn_err(CE_NOTE, "amd8111s_set_loop_mode LB_INTERNAL_MAC");
33775ab5f91Slh mdlStopChip(adapter);
33875ab5f91Slh amd8111s_reset(adapter);
33975ab5f91Slh SetIntrCoalesc(adapter, B_FALSE);
34075ab5f91Slh /* Disable Port Manager */
34175ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
34275ab5f91Slh EN_PMGR);
34375ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD2,
34475ab5f91Slh VAL0 | INLOOP);
34575ab5f91Slh
34675ab5f91Slh WRITE_REG32(adapter, adapter->pMdl->Mem_Address + CMD3,
34775ab5f91Slh VAL1 | FORCE_FULL_DUPLEX | FORCE_LINK_STATUS);
34875ab5f91Slh
34975ab5f91Slh adapter->pOdl->LinkStatus = LINK_STATE_UP;
35075ab5f91Slh adapter->pMdl->FullDuplex = B_TRUE;
35175ab5f91Slh /* Tell GLD the state of the physical link. */
35275ab5f91Slh mac_link_update(adapter->pOdl->mh, LINK_STATE_UP);
35375ab5f91Slh
35475ab5f91Slh adapter->pOdl->rx_fcs_stripped = B_TRUE;
35575ab5f91Slh
35675ab5f91Slh mdlStartChip(adapter);
35775ab5f91Slh break;
35875ab5f91Slh }
35975ab5f91Slh
36075ab5f91Slh /*
36175ab5f91Slh * All OK; tell the caller to reprogram
36275ab5f91Slh * the PHY and/or MAC for the new mode ...
36375ab5f91Slh */
36475ab5f91Slh adapter->pOdl->loopback_mode = mode;
36575ab5f91Slh }
36675ab5f91Slh
36775ab5f91Slh static enum ioc_reply
amd8111s_loopback_ioctl(struct LayerPointers * adapter,struct iocblk * iocp,mblk_t * mp)36875ab5f91Slh amd8111s_loopback_ioctl(struct LayerPointers *adapter, struct iocblk *iocp,
36975ab5f91Slh mblk_t *mp)
37075ab5f91Slh {
37175ab5f91Slh lb_info_sz_t *lbsp;
37275ab5f91Slh lb_property_t *lbpp;
37375ab5f91Slh uint32_t *lbmp;
37475ab5f91Slh int cmd;
37575ab5f91Slh
37675ab5f91Slh /*
37775ab5f91Slh * Validate format of ioctl
37875ab5f91Slh */
37975ab5f91Slh if (mp->b_cont == NULL)
38075ab5f91Slh return (IOC_INVAL);
38175ab5f91Slh
38275ab5f91Slh cmd = iocp->ioc_cmd;
38375ab5f91Slh switch (cmd) {
38475ab5f91Slh default:
38575ab5f91Slh /* NOTREACHED */
38675ab5f91Slh amd8111s_log(adapter, CE_NOTE,
38775ab5f91Slh "amd8111s_loop_ioctl: invalid cmd 0x%x", cmd);
38875ab5f91Slh return (IOC_INVAL);
38975ab5f91Slh
39075ab5f91Slh case LB_GET_INFO_SIZE:
39175ab5f91Slh if (iocp->ioc_count != sizeof (lb_info_sz_t)) {
39275ab5f91Slh amd8111s_log(adapter, CE_NOTE,
39375ab5f91Slh "wrong LB_GET_INFO_SIZE size");
39475ab5f91Slh return (IOC_INVAL);
39575ab5f91Slh }
39622eb7cb5Sgd lbsp = (void *)mp->b_cont->b_rptr;
39775ab5f91Slh *lbsp = sizeof (loopmodes);
39875ab5f91Slh break;
39975ab5f91Slh
40075ab5f91Slh case LB_GET_INFO:
40175ab5f91Slh if (iocp->ioc_count != sizeof (loopmodes)) {
40275ab5f91Slh amd8111s_log(adapter, CE_NOTE,
40375ab5f91Slh "Wrong LB_GET_INFO size");
40475ab5f91Slh return (IOC_INVAL);
40575ab5f91Slh }
40622eb7cb5Sgd lbpp = (void *)mp->b_cont->b_rptr;
40775ab5f91Slh bcopy(loopmodes, lbpp, sizeof (loopmodes));
40875ab5f91Slh break;
40975ab5f91Slh
41075ab5f91Slh case LB_GET_MODE:
41175ab5f91Slh if (iocp->ioc_count != sizeof (uint32_t)) {
41275ab5f91Slh amd8111s_log(adapter, CE_NOTE,
41375ab5f91Slh "Wrong LB_GET_MODE size");
41475ab5f91Slh return (IOC_INVAL);
41575ab5f91Slh }
41622eb7cb5Sgd lbmp = (void *)mp->b_cont->b_rptr;
41775ab5f91Slh *lbmp = adapter->pOdl->loopback_mode;
41875ab5f91Slh break;
41975ab5f91Slh
42075ab5f91Slh case LB_SET_MODE:
42175ab5f91Slh if (iocp->ioc_count != sizeof (uint32_t)) {
42275ab5f91Slh amd8111s_log(adapter, CE_NOTE,
42375ab5f91Slh "Wrong LB_SET_MODE size");
42475ab5f91Slh return (IOC_INVAL);
42575ab5f91Slh }
42622eb7cb5Sgd lbmp = (void *)mp->b_cont->b_rptr;
42775ab5f91Slh amd8111s_set_loop_mode(adapter, *lbmp);
42875ab5f91Slh break;
42975ab5f91Slh }
43075ab5f91Slh return (IOC_REPLY);
43175ab5f91Slh }
43275ab5f91Slh
43375ab5f91Slh static void
amd8111s_m_ioctl(void * arg,queue_t * q,mblk_t * mp)43475ab5f91Slh amd8111s_m_ioctl(void *arg, queue_t *q, mblk_t *mp)
43575ab5f91Slh {
43675ab5f91Slh struct iocblk *iocp;
43775ab5f91Slh struct LayerPointers *adapter;
43875ab5f91Slh enum ioc_reply status;
43975ab5f91Slh
44022eb7cb5Sgd iocp = (void *)mp->b_rptr;
44175ab5f91Slh iocp->ioc_error = 0;
44222eb7cb5Sgd adapter = arg;
44375ab5f91Slh
44475ab5f91Slh ASSERT(adapter);
44575ab5f91Slh if (adapter == NULL) {
44675ab5f91Slh miocnak(q, mp, 0, EINVAL);
44775ab5f91Slh return;
44875ab5f91Slh }
44975ab5f91Slh
45075ab5f91Slh switch (iocp->ioc_cmd) {
45175ab5f91Slh
45275ab5f91Slh case LB_GET_INFO_SIZE:
45375ab5f91Slh case LB_GET_INFO:
45475ab5f91Slh case LB_GET_MODE:
45575ab5f91Slh case LB_SET_MODE:
45675ab5f91Slh status = amd8111s_loopback_ioctl(adapter, iocp, mp);
45775ab5f91Slh break;
45875ab5f91Slh
45975ab5f91Slh default:
46075ab5f91Slh status = IOC_INVAL;
46175ab5f91Slh break;
46275ab5f91Slh }
46375ab5f91Slh
46475ab5f91Slh /*
46575ab5f91Slh * Decide how to reply
46675ab5f91Slh */
46775ab5f91Slh switch (status) {
46875ab5f91Slh default:
46975ab5f91Slh case IOC_INVAL:
47075ab5f91Slh /*
47175ab5f91Slh * Error, reply with a NAK and EINVAL or the specified error
47275ab5f91Slh */
47375ab5f91Slh miocnak(q, mp, 0, iocp->ioc_error == 0 ?
47475ab5f91Slh EINVAL : iocp->ioc_error);
47575ab5f91Slh break;
47675ab5f91Slh
47775ab5f91Slh case IOC_DONE:
47875ab5f91Slh /*
47975ab5f91Slh * OK, reply already sent
48075ab5f91Slh */
48175ab5f91Slh break;
48275ab5f91Slh
48375ab5f91Slh case IOC_ACK:
48475ab5f91Slh /*
48575ab5f91Slh * OK, reply with an ACK
48675ab5f91Slh */
48775ab5f91Slh miocack(q, mp, 0, 0);
48875ab5f91Slh break;
48975ab5f91Slh
49075ab5f91Slh case IOC_REPLY:
49175ab5f91Slh /*
49275ab5f91Slh * OK, send prepared reply as ACK or NAK
49375ab5f91Slh */
49475ab5f91Slh mp->b_datap->db_type = iocp->ioc_error == 0 ?
49575ab5f91Slh M_IOCACK : M_IOCNAK;
49675ab5f91Slh qreply(q, mp);
49775ab5f91Slh break;
49875ab5f91Slh }
49975ab5f91Slh }
50075ab5f91Slh
50175ab5f91Slh /*
50275ab5f91Slh * Copy one packet from dma memory to mblk. Inc dma descriptor pointer.
50375ab5f91Slh */
50475ab5f91Slh static boolean_t
amd8111s_recv_copy(struct LayerPointers * pLayerPointers,mblk_t ** last_mp)50575ab5f91Slh amd8111s_recv_copy(struct LayerPointers *pLayerPointers, mblk_t **last_mp)
50675ab5f91Slh {
50775ab5f91Slh int length = 0;
50875ab5f91Slh mblk_t *mp;
50975ab5f91Slh struct rx_desc *descriptor;
51075ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
51175ab5f91Slh struct amd8111s_statistics *statistics = &pOdl->statistics;
51275ab5f91Slh struct nonphysical *pNonphysical = pLayerPointers->pMil
51375ab5f91Slh ->pNonphysical;
51475ab5f91Slh
51575ab5f91Slh mutex_enter(&pOdl->mdlRcvLock);
51675ab5f91Slh descriptor = pNonphysical->RxBufDescQRead->descriptor;
51775ab5f91Slh (void) ddi_dma_sync(pOdl->rx_desc_dma_handle,
51875ab5f91Slh pNonphysical->RxBufDescQRead->descriptor -
51975ab5f91Slh pNonphysical->RxBufDescQStart->descriptor,
52075ab5f91Slh sizeof (struct rx_desc), DDI_DMA_SYNC_FORCPU);
52175ab5f91Slh if ((descriptor->Rx_OWN) == 0) {
52275ab5f91Slh /*
52375ab5f91Slh * If the frame is received with errors, then set MCNT
52475ab5f91Slh * of that pkt in ReceiveArray to 0. This packet would
52575ab5f91Slh * be discarded later and not indicated to OS.
52675ab5f91Slh */
52775ab5f91Slh if (descriptor->Rx_ERR) {
52875ab5f91Slh statistics->rx_desc_err ++;
52975ab5f91Slh descriptor->Rx_ERR = 0;
53075ab5f91Slh if (descriptor->Rx_FRAM == 1) {
53175ab5f91Slh statistics->rx_desc_err_FRAM ++;
53275ab5f91Slh descriptor->Rx_FRAM = 0;
53375ab5f91Slh }
53475ab5f91Slh if (descriptor->Rx_OFLO == 1) {
53575ab5f91Slh statistics->rx_desc_err_OFLO ++;
53675ab5f91Slh descriptor->Rx_OFLO = 0;
53775ab5f91Slh pOdl->rx_overflow_counter ++;
53875ab5f91Slh if ((pOdl->rx_overflow_counter > 5) &&
53975ab5f91Slh (pOdl->pause_interval == 0)) {
54075ab5f91Slh statistics->rx_double_overflow ++;
54175ab5f91Slh mdlSendPause(pLayerPointers);
54275ab5f91Slh pOdl->rx_overflow_counter = 0;
54375ab5f91Slh pOdl->pause_interval = 25;
54475ab5f91Slh }
54575ab5f91Slh }
54675ab5f91Slh if (descriptor->Rx_CRC == 1) {
54775ab5f91Slh statistics->rx_desc_err_CRC ++;
54875ab5f91Slh descriptor->Rx_CRC = 0;
54975ab5f91Slh }
55075ab5f91Slh if (descriptor->Rx_BUFF == 1) {
55175ab5f91Slh statistics->rx_desc_err_BUFF ++;
55275ab5f91Slh descriptor->Rx_BUFF = 0;
55375ab5f91Slh }
55475ab5f91Slh goto Next_Descriptor;
55575ab5f91Slh }
55675ab5f91Slh
55775ab5f91Slh /* Length of incoming packet */
55875ab5f91Slh if (pOdl->rx_fcs_stripped) {
55975ab5f91Slh length = descriptor->Rx_MCNT -4;
56075ab5f91Slh } else {
56175ab5f91Slh length = descriptor->Rx_MCNT;
56275ab5f91Slh }
56375ab5f91Slh if (length < 62) {
56475ab5f91Slh statistics->rx_error_zerosize ++;
56575ab5f91Slh }
56675ab5f91Slh
56775ab5f91Slh if ((mp = allocb(length, BPRI_MED)) == NULL) {
56875ab5f91Slh statistics->rx_allocfail ++;
56975ab5f91Slh goto failed;
57075ab5f91Slh }
57175ab5f91Slh /* Copy from virtual address of incoming packet */
57275ab5f91Slh bcopy((long *)*(pNonphysical->RxBufDescQRead->USpaceMap),
57375ab5f91Slh mp->b_rptr, length);
57475ab5f91Slh mp->b_wptr = mp->b_rptr + length;
57575ab5f91Slh statistics->rx_ok_packets ++;
57675ab5f91Slh if (*last_mp == NULL) {
57775ab5f91Slh *last_mp = mp;
57875ab5f91Slh } else {
57975ab5f91Slh (*last_mp)->b_next = mp;
58075ab5f91Slh *last_mp = mp;
58175ab5f91Slh }
58275ab5f91Slh
58375ab5f91Slh Next_Descriptor:
58475ab5f91Slh descriptor->Rx_MCNT = 0;
58575ab5f91Slh descriptor->Rx_SOP = 0;
58675ab5f91Slh descriptor->Rx_EOP = 0;
58775ab5f91Slh descriptor->Rx_PAM = 0;
58875ab5f91Slh descriptor->Rx_BAM = 0;
58975ab5f91Slh descriptor->TT = 0;
59075ab5f91Slh descriptor->Rx_OWN = 1;
59175ab5f91Slh pNonphysical->RxBufDescQRead->descriptor++;
59275ab5f91Slh pNonphysical->RxBufDescQRead->USpaceMap++;
59375ab5f91Slh if (pNonphysical->RxBufDescQRead->descriptor >
59475ab5f91Slh pNonphysical->RxBufDescQEnd->descriptor) {
59575ab5f91Slh pNonphysical->RxBufDescQRead->descriptor =
59675ab5f91Slh pNonphysical->RxBufDescQStart->descriptor;
59775ab5f91Slh pNonphysical->RxBufDescQRead->USpaceMap =
59875ab5f91Slh pNonphysical->RxBufDescQStart->USpaceMap;
59975ab5f91Slh }
60075ab5f91Slh mutex_exit(&pOdl->mdlRcvLock);
60175ab5f91Slh
60275ab5f91Slh return (B_TRUE);
60375ab5f91Slh }
60475ab5f91Slh
60575ab5f91Slh failed:
60675ab5f91Slh mutex_exit(&pOdl->mdlRcvLock);
60775ab5f91Slh return (B_FALSE);
60875ab5f91Slh }
60975ab5f91Slh
61075ab5f91Slh /*
61175ab5f91Slh * Get the received packets from NIC card and send them to GLD.
61275ab5f91Slh */
61375ab5f91Slh static void
amd8111s_receive(struct LayerPointers * pLayerPointers)61475ab5f91Slh amd8111s_receive(struct LayerPointers *pLayerPointers)
61575ab5f91Slh {
61675ab5f91Slh int numOfPkts = 0;
61775ab5f91Slh struct odl *pOdl;
61875ab5f91Slh mblk_t *ret_mp = NULL, *last_mp = NULL;
61975ab5f91Slh
62075ab5f91Slh pOdl = pLayerPointers->pOdl;
62175ab5f91Slh
62275ab5f91Slh rw_enter(&pOdl->chip_lock, RW_READER);
62375ab5f91Slh if (!pLayerPointers->run) {
62475ab5f91Slh rw_exit(&pOdl->chip_lock);
62575ab5f91Slh return;
62675ab5f91Slh }
62775ab5f91Slh
62875ab5f91Slh if (pOdl->pause_interval > 0)
62975ab5f91Slh pOdl->pause_interval --;
63075ab5f91Slh
63175ab5f91Slh while (numOfPkts < RX_RING_SIZE) {
63275ab5f91Slh
63375ab5f91Slh if (!amd8111s_recv_copy(pLayerPointers, &last_mp)) {
63475ab5f91Slh break;
63575ab5f91Slh }
63675ab5f91Slh if (ret_mp == NULL)
63775ab5f91Slh ret_mp = last_mp;
63875ab5f91Slh numOfPkts++;
63975ab5f91Slh }
64075ab5f91Slh
64175ab5f91Slh if (ret_mp) {
642da14cebeSEric Cheng mac_rx(pOdl->mh, NULL, ret_mp);
64375ab5f91Slh }
64475ab5f91Slh
64575ab5f91Slh (void) ddi_dma_sync(pOdl->rx_desc_dma_handle, 0, 0,
64675ab5f91Slh DDI_DMA_SYNC_FORDEV);
64775ab5f91Slh
64875ab5f91Slh mdlReceive(pLayerPointers);
64975ab5f91Slh
65075ab5f91Slh rw_exit(&pOdl->chip_lock);
65175ab5f91Slh
65275ab5f91Slh }
65375ab5f91Slh
65475ab5f91Slh /*
65575ab5f91Slh * Print message in release-version driver.
65675ab5f91Slh */
65775ab5f91Slh static void
amd8111s_log(struct LayerPointers * adapter,int level,char * fmt,...)65875ab5f91Slh amd8111s_log(struct LayerPointers *adapter, int level, char *fmt, ...)
65975ab5f91Slh {
66075ab5f91Slh auto char name[32];
66175ab5f91Slh auto char buf[256];
66275ab5f91Slh va_list ap;
66375ab5f91Slh
66475ab5f91Slh if (adapter != NULL) {
66575ab5f91Slh (void) sprintf(name, "amd8111s%d",
66675ab5f91Slh ddi_get_instance(adapter->pOdl->devinfo));
66775ab5f91Slh } else {
66875ab5f91Slh (void) sprintf(name, "amd8111s");
66975ab5f91Slh }
67075ab5f91Slh va_start(ap, fmt);
67175ab5f91Slh (void) vsprintf(buf, fmt, ap);
67275ab5f91Slh va_end(ap);
67375ab5f91Slh cmn_err(level, "%s: %s", name, buf);
67475ab5f91Slh }
67575ab5f91Slh
67675ab5f91Slh /*
67775ab5f91Slh * To allocate & initilize all resources.
67875ab5f91Slh * Called by amd8111s_attach().
67975ab5f91Slh */
68075ab5f91Slh static int
amd8111s_odlInit(struct LayerPointers * pLayerPointers)68175ab5f91Slh amd8111s_odlInit(struct LayerPointers *pLayerPointers)
68275ab5f91Slh {
68375ab5f91Slh unsigned long mem_req_array[MEM_REQ_MAX];
68475ab5f91Slh unsigned long mem_set_array[MEM_REQ_MAX];
68575ab5f91Slh unsigned long *pmem_req_array;
68675ab5f91Slh unsigned long *pmem_set_array;
68775ab5f91Slh int i, size;
68875ab5f91Slh
68975ab5f91Slh for (i = 0; i < MEM_REQ_MAX; i++) {
69075ab5f91Slh mem_req_array[i] = 0;
69175ab5f91Slh mem_set_array[i] = 0;
69275ab5f91Slh }
69375ab5f91Slh
69475ab5f91Slh milRequestResources(mem_req_array);
69575ab5f91Slh
69675ab5f91Slh pmem_req_array = mem_req_array;
69775ab5f91Slh pmem_set_array = mem_set_array;
69875ab5f91Slh while (*pmem_req_array) {
69975ab5f91Slh switch (*pmem_req_array) {
70075ab5f91Slh case VIRTUAL:
70175ab5f91Slh *pmem_set_array = VIRTUAL;
70275ab5f91Slh pmem_req_array++;
70375ab5f91Slh pmem_set_array++;
70475ab5f91Slh *(pmem_set_array) = *(pmem_req_array);
70575ab5f91Slh pmem_set_array++;
70675ab5f91Slh *(pmem_set_array) = (unsigned long) kmem_zalloc(
70775ab5f91Slh *(pmem_req_array), KM_NOSLEEP);
708*0f36d2f1SToomas Soome if (*pmem_set_array == 0)
70975ab5f91Slh goto odl_init_failure;
71075ab5f91Slh break;
71175ab5f91Slh }
71275ab5f91Slh pmem_req_array++;
71375ab5f91Slh pmem_set_array++;
71475ab5f91Slh }
71575ab5f91Slh
71675ab5f91Slh /*
71775ab5f91Slh * Initilize memory on lower layers
71875ab5f91Slh */
71975ab5f91Slh milSetResources(pLayerPointers, mem_set_array);
72075ab5f91Slh
72175ab5f91Slh /* Allocate Rx/Tx descriptors */
72275ab5f91Slh if (amd8111s_allocate_descriptors(pLayerPointers) != B_TRUE) {
723*0f36d2f1SToomas Soome *pmem_set_array = 0;
72475ab5f91Slh goto odl_init_failure;
72575ab5f91Slh }
72675ab5f91Slh
72775ab5f91Slh /*
72875ab5f91Slh * Allocate Rx buffer for each Rx descriptor. Then call mil layer
72975ab5f91Slh * routine to fill physical address of Rx buffer into Rx descriptor.
73075ab5f91Slh */
73175ab5f91Slh if (amd8111s_allocate_buffers(pLayerPointers) == B_FALSE) {
73275ab5f91Slh amd8111s_free_descriptors(pLayerPointers);
733*0f36d2f1SToomas Soome *pmem_set_array = 0;
73475ab5f91Slh goto odl_init_failure;
73575ab5f91Slh }
73675ab5f91Slh milInitGlbds(pLayerPointers);
73775ab5f91Slh
73875ab5f91Slh return (0);
73975ab5f91Slh
74075ab5f91Slh odl_init_failure:
74175ab5f91Slh /*
74275ab5f91Slh * Free All memory allocated so far
74375ab5f91Slh */
74475ab5f91Slh pmem_req_array = mem_set_array;
74575ab5f91Slh while ((*pmem_req_array) && (pmem_req_array != pmem_set_array)) {
74675ab5f91Slh switch (*pmem_req_array) {
74775ab5f91Slh case VIRTUAL:
74875ab5f91Slh pmem_req_array++; /* Size */
74975ab5f91Slh size = *(pmem_req_array);
75075ab5f91Slh pmem_req_array++; /* Virtual Address */
75175ab5f91Slh if (pmem_req_array == NULL)
75275ab5f91Slh return (1);
75375ab5f91Slh kmem_free((int *)*pmem_req_array, size);
75475ab5f91Slh break;
75575ab5f91Slh }
75675ab5f91Slh pmem_req_array++;
75775ab5f91Slh }
75875ab5f91Slh return (1);
75975ab5f91Slh }
76075ab5f91Slh
76175ab5f91Slh /*
76275ab5f91Slh * Allocate and initialize Tx/Rx descriptors
76375ab5f91Slh */
76475ab5f91Slh static boolean_t
amd8111s_allocate_descriptors(struct LayerPointers * pLayerPointers)76575ab5f91Slh amd8111s_allocate_descriptors(struct LayerPointers *pLayerPointers)
76675ab5f91Slh {
76775ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
76875ab5f91Slh struct mil *pMil = pLayerPointers->pMil;
76975ab5f91Slh dev_info_t *devinfo = pOdl->devinfo;
77075ab5f91Slh uint_t length, count, i;
77175ab5f91Slh size_t real_length;
77275ab5f91Slh
77375ab5f91Slh /*
77475ab5f91Slh * Allocate Rx descriptors
77575ab5f91Slh */
77675ab5f91Slh if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
77775ab5f91Slh NULL, &pOdl->rx_desc_dma_handle) != DDI_SUCCESS) {
77875ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
77975ab5f91Slh "ddi_dma_alloc_handle for Rx desc failed");
78075ab5f91Slh pOdl->rx_desc_dma_handle = NULL;
78175ab5f91Slh return (B_FALSE);
78275ab5f91Slh }
78375ab5f91Slh
78475ab5f91Slh length = sizeof (struct rx_desc) * RX_RING_SIZE + ALIGNMENT;
78575ab5f91Slh if (ddi_dma_mem_alloc(pOdl->rx_desc_dma_handle, length,
78675ab5f91Slh &pcn_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
78775ab5f91Slh NULL, (caddr_t *)&pMil->Rx_desc_original, &real_length,
78875ab5f91Slh &pOdl->rx_desc_acc_handle) != DDI_SUCCESS) {
78975ab5f91Slh
79075ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
79175ab5f91Slh "ddi_dma_mem_handle for Rx desc failed");
79275ab5f91Slh ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
79375ab5f91Slh pOdl->rx_desc_dma_handle = NULL;
79475ab5f91Slh return (B_FALSE);
79575ab5f91Slh }
79675ab5f91Slh
79775ab5f91Slh if (ddi_dma_addr_bind_handle(pOdl->rx_desc_dma_handle,
79875ab5f91Slh NULL, (caddr_t)pMil->Rx_desc_original, real_length,
79975ab5f91Slh DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
80075ab5f91Slh NULL, &pOdl->rx_desc_dma_cookie,
80175ab5f91Slh &count) != DDI_SUCCESS) {
80275ab5f91Slh
80375ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
80475ab5f91Slh "ddi_dma_addr_bind_handle for Rx desc failed");
80575ab5f91Slh ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
80675ab5f91Slh ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
80775ab5f91Slh pOdl->rx_desc_dma_handle = NULL;
80875ab5f91Slh return (B_FALSE);
80975ab5f91Slh }
81075ab5f91Slh ASSERT(count == 1);
81175ab5f91Slh
81275ab5f91Slh /* Initialize Rx descriptors related variables */
81375ab5f91Slh pMil->Rx_desc = (struct rx_desc *)
81475ab5f91Slh ((pMil->Rx_desc_original + ALIGNMENT) & ~ALIGNMENT);
81575ab5f91Slh pMil->Rx_desc_pa = (unsigned int)
81675ab5f91Slh ((pOdl->rx_desc_dma_cookie.dmac_laddress + ALIGNMENT) & ~ALIGNMENT);
81775ab5f91Slh
81875ab5f91Slh pLayerPointers->pMdl->init_blk->RDRA = pMil->Rx_desc_pa;
81975ab5f91Slh
82075ab5f91Slh
82175ab5f91Slh /*
82275ab5f91Slh * Allocate Tx descriptors
82375ab5f91Slh */
82475ab5f91Slh if (ddi_dma_alloc_handle(devinfo, &pcn_desc_dma_attr_t, DDI_DMA_SLEEP,
82575ab5f91Slh NULL, &pOdl->tx_desc_dma_handle) != DDI_SUCCESS) {
82675ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
82775ab5f91Slh "ddi_dma_alloc_handle for Tx desc failed");
82875ab5f91Slh goto allocate_desc_fail;
82975ab5f91Slh }
83075ab5f91Slh
83175ab5f91Slh length = sizeof (struct tx_desc) * TX_RING_SIZE + ALIGNMENT;
83275ab5f91Slh if (ddi_dma_mem_alloc(pOdl->tx_desc_dma_handle, length,
83375ab5f91Slh &pcn_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
83475ab5f91Slh NULL, (caddr_t *)&pMil->Tx_desc_original, &real_length,
83575ab5f91Slh &pOdl->tx_desc_acc_handle) != DDI_SUCCESS) {
83675ab5f91Slh
83775ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
83875ab5f91Slh "ddi_dma_mem_handle for Tx desc failed");
83975ab5f91Slh ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
84075ab5f91Slh goto allocate_desc_fail;
84175ab5f91Slh }
84275ab5f91Slh
84375ab5f91Slh if (ddi_dma_addr_bind_handle(pOdl->tx_desc_dma_handle,
84475ab5f91Slh NULL, (caddr_t)pMil->Tx_desc_original, real_length,
84575ab5f91Slh DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
84675ab5f91Slh NULL, &pOdl->tx_desc_dma_cookie,
84775ab5f91Slh &count) != DDI_SUCCESS) {
84875ab5f91Slh
84975ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
85075ab5f91Slh "ddi_dma_addr_bind_handle for Tx desc failed");
85175ab5f91Slh ddi_dma_mem_free(&pOdl->tx_desc_acc_handle);
85275ab5f91Slh ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
85375ab5f91Slh goto allocate_desc_fail;
85475ab5f91Slh }
85575ab5f91Slh ASSERT(count == 1);
85675ab5f91Slh /* Set the DMA area to all zeros */
85775ab5f91Slh bzero((caddr_t)pMil->Tx_desc_original, length);
85875ab5f91Slh
85975ab5f91Slh /* Initialize Tx descriptors related variables */
86075ab5f91Slh pMil->Tx_desc = (struct tx_desc *)
86175ab5f91Slh ((pMil->Tx_desc_original + ALIGNMENT) & ~ALIGNMENT);
86275ab5f91Slh pMil->pNonphysical->TxDescQRead = pMil->Tx_desc;
86375ab5f91Slh pMil->pNonphysical->TxDescQWrite = pMil->Tx_desc;
86475ab5f91Slh pMil->pNonphysical->TxDescQStart = pMil->Tx_desc;
86575ab5f91Slh pMil->pNonphysical->TxDescQEnd = &(pMil->Tx_desc[TX_RING_SIZE -1]);
86675ab5f91Slh
86775ab5f91Slh /* Physical Addr of Tx_desc_original & Tx_desc */
86875ab5f91Slh pLayerPointers->pMil->Tx_desc_pa =
86975ab5f91Slh ((pOdl->tx_desc_dma_cookie.dmac_laddress + ALIGNMENT) &
87075ab5f91Slh ~ALIGNMENT);
87175ab5f91Slh
87275ab5f91Slh /* Setting the reserved bits in the tx descriptors */
87375ab5f91Slh for (i = 0; i < TX_RING_SIZE; i++) {
87475ab5f91Slh pMil->pNonphysical->TxDescQWrite->Tx_RES0 = 0x0f;
87575ab5f91Slh pMil->pNonphysical->TxDescQWrite->Tx_OWN = 0;
87675ab5f91Slh pMil->pNonphysical->TxDescQWrite++;
87775ab5f91Slh }
87875ab5f91Slh pMil->pNonphysical->TxDescQWrite = pMil->pNonphysical->TxDescQStart;
87975ab5f91Slh
88075ab5f91Slh pLayerPointers->pMdl->init_blk->TDRA = pMil->Tx_desc_pa;
88175ab5f91Slh
88275ab5f91Slh return (B_TRUE);
88375ab5f91Slh
88475ab5f91Slh allocate_desc_fail:
88575ab5f91Slh pOdl->tx_desc_dma_handle = NULL;
88675ab5f91Slh (void) ddi_dma_unbind_handle(pOdl->rx_desc_dma_handle);
88775ab5f91Slh ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
88875ab5f91Slh ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
88975ab5f91Slh pOdl->rx_desc_dma_handle = NULL;
89075ab5f91Slh return (B_FALSE);
89175ab5f91Slh }
89275ab5f91Slh
89375ab5f91Slh /*
89475ab5f91Slh * Free Tx/Rx descriptors
89575ab5f91Slh */
89675ab5f91Slh static void
amd8111s_free_descriptors(struct LayerPointers * pLayerPointers)89775ab5f91Slh amd8111s_free_descriptors(struct LayerPointers *pLayerPointers)
89875ab5f91Slh {
89975ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
90075ab5f91Slh
90175ab5f91Slh /* Free Rx descriptors */
90275ab5f91Slh if (pOdl->rx_desc_dma_handle) {
90375ab5f91Slh (void) ddi_dma_unbind_handle(pOdl->rx_desc_dma_handle);
90475ab5f91Slh ddi_dma_mem_free(&pOdl->rx_desc_acc_handle);
90575ab5f91Slh ddi_dma_free_handle(&pOdl->rx_desc_dma_handle);
90675ab5f91Slh pOdl->rx_desc_dma_handle = NULL;
90775ab5f91Slh }
90875ab5f91Slh
90975ab5f91Slh /* Free Rx descriptors */
91075ab5f91Slh if (pOdl->tx_desc_dma_handle) {
91175ab5f91Slh (void) ddi_dma_unbind_handle(pOdl->tx_desc_dma_handle);
91275ab5f91Slh ddi_dma_mem_free(&pOdl->tx_desc_acc_handle);
91375ab5f91Slh ddi_dma_free_handle(&pOdl->tx_desc_dma_handle);
91475ab5f91Slh pOdl->tx_desc_dma_handle = NULL;
91575ab5f91Slh }
91675ab5f91Slh }
91775ab5f91Slh
91875ab5f91Slh /*
91975ab5f91Slh * Allocate Tx/Rx Ring buffer
92075ab5f91Slh */
92175ab5f91Slh static boolean_t
amd8111s_alloc_dma_ringbuf(struct LayerPointers * pLayerPointers,struct amd8111s_dma_ringbuf * pRing,uint32_t ring_size,uint32_t msg_size)92275ab5f91Slh amd8111s_alloc_dma_ringbuf(struct LayerPointers *pLayerPointers,
923*0f36d2f1SToomas Soome struct amd8111s_dma_ringbuf *pRing, uint32_t ring_size, uint32_t msg_size)
92475ab5f91Slh {
92575ab5f91Slh uint32_t idx, msg_idx = 0, msg_acc;
92675ab5f91Slh dev_info_t *devinfo = pLayerPointers->pOdl->devinfo;
92775ab5f91Slh size_t real_length;
92875ab5f91Slh uint_t count = 0;
92975ab5f91Slh
93075ab5f91Slh ASSERT(pcn_buff_dma_attr_t.dma_attr_align == 1);
93175ab5f91Slh pRing->dma_buf_sz = msg_size;
93275ab5f91Slh pRing->ring_size = ring_size;
93375ab5f91Slh pRing->trunk_num = AMD8111S_SPLIT;
93475ab5f91Slh pRing->buf_sz = msg_size * ring_size;
93575ab5f91Slh if (ring_size < pRing->trunk_num)
93675ab5f91Slh pRing->trunk_num = ring_size;
93775ab5f91Slh ASSERT((pRing->buf_sz % pRing->trunk_num) == 0);
93875ab5f91Slh
93975ab5f91Slh pRing->trunk_sz = pRing->buf_sz / pRing->trunk_num;
94075ab5f91Slh ASSERT((pRing->trunk_sz % pRing->dma_buf_sz) == 0);
94175ab5f91Slh
94275ab5f91Slh pRing->msg_buf = kmem_zalloc(sizeof (struct amd8111s_msgbuf) *
94375ab5f91Slh ring_size, KM_NOSLEEP);
94475ab5f91Slh pRing->dma_hdl = kmem_zalloc(sizeof (ddi_dma_handle_t) *
94575ab5f91Slh pRing->trunk_num, KM_NOSLEEP);
94675ab5f91Slh pRing->acc_hdl = kmem_zalloc(sizeof (ddi_acc_handle_t) *
94775ab5f91Slh pRing->trunk_num, KM_NOSLEEP);
94875ab5f91Slh pRing->dma_cookie = kmem_zalloc(sizeof (ddi_dma_cookie_t) *
94975ab5f91Slh pRing->trunk_num, KM_NOSLEEP);
95075ab5f91Slh pRing->trunk_addr = kmem_zalloc(sizeof (caddr_t) *
95175ab5f91Slh pRing->trunk_num, KM_NOSLEEP);
95275ab5f91Slh if (pRing->msg_buf == NULL || pRing->dma_hdl == NULL ||
95375ab5f91Slh pRing->acc_hdl == NULL || pRing->trunk_addr == NULL ||
95475ab5f91Slh pRing->dma_cookie == NULL) {
95575ab5f91Slh amd8111s_log(pLayerPointers, CE_NOTE,
95675ab5f91Slh "kmem_zalloc failed");
95775ab5f91Slh goto failed;
95875ab5f91Slh }
95975ab5f91Slh
96075ab5f91Slh for (idx = 0; idx < pRing->trunk_num; ++idx) {
96175ab5f91Slh if (ddi_dma_alloc_handle(devinfo, &pcn_buff_dma_attr_t,
96275ab5f91Slh DDI_DMA_SLEEP, NULL, &(pRing->dma_hdl[idx]))
96375ab5f91Slh != DDI_SUCCESS) {
96475ab5f91Slh
96575ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
96675ab5f91Slh "ddi_dma_alloc_handle failed");
96775ab5f91Slh goto failed;
96875ab5f91Slh } else if (ddi_dma_mem_alloc(pRing->dma_hdl[idx],
96975ab5f91Slh pRing->trunk_sz, &pcn_acc_attr, DDI_DMA_STREAMING,
97075ab5f91Slh DDI_DMA_SLEEP, NULL,
97175ab5f91Slh (caddr_t *)&(pRing->trunk_addr[idx]),
97275ab5f91Slh (size_t *)(&real_length), &pRing->acc_hdl[idx])
97375ab5f91Slh != DDI_SUCCESS) {
97475ab5f91Slh
97575ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
97675ab5f91Slh "ddi_dma_mem_alloc failed");
97775ab5f91Slh goto failed;
97875ab5f91Slh } else if (real_length != pRing->trunk_sz) {
97975ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
98075ab5f91Slh "ddi_dma_mem_alloc failed");
98175ab5f91Slh goto failed;
98275ab5f91Slh } else if (ddi_dma_addr_bind_handle(pRing->dma_hdl[idx],
98375ab5f91Slh NULL, (caddr_t)pRing->trunk_addr[idx], real_length,
98475ab5f91Slh DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
98575ab5f91Slh &pRing->dma_cookie[idx], &count) != DDI_DMA_MAPPED) {
98675ab5f91Slh
98775ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
98875ab5f91Slh "ddi_dma_addr_bind_handle failed");
98975ab5f91Slh goto failed;
99075ab5f91Slh } else {
99175ab5f91Slh for (msg_acc = 0;
99275ab5f91Slh msg_acc < pRing->trunk_sz / pRing->dma_buf_sz;
99375ab5f91Slh ++ msg_acc) {
99475ab5f91Slh pRing->msg_buf[msg_idx].offset =
99575ab5f91Slh msg_acc * pRing->dma_buf_sz;
99675ab5f91Slh pRing->msg_buf[msg_idx].vir_addr =
99775ab5f91Slh pRing->trunk_addr[idx] +
99875ab5f91Slh pRing->msg_buf[msg_idx].offset;
99975ab5f91Slh pRing->msg_buf[msg_idx].phy_addr =
100075ab5f91Slh pRing->dma_cookie[idx].dmac_laddress +
100175ab5f91Slh pRing->msg_buf[msg_idx].offset;
100275ab5f91Slh pRing->msg_buf[msg_idx].p_hdl =
100375ab5f91Slh pRing->dma_hdl[idx];
100475ab5f91Slh msg_idx ++;
100575ab5f91Slh }
100675ab5f91Slh }
100775ab5f91Slh }
100875ab5f91Slh
100975ab5f91Slh pRing->free = pRing->msg_buf;
101075ab5f91Slh pRing->next = pRing->msg_buf;
101175ab5f91Slh pRing->curr = pRing->msg_buf;
101275ab5f91Slh
101375ab5f91Slh return (B_TRUE);
101475ab5f91Slh failed:
101575ab5f91Slh amd8111s_free_dma_ringbuf(pRing);
101675ab5f91Slh return (B_FALSE);
101775ab5f91Slh }
101875ab5f91Slh
101975ab5f91Slh /*
102075ab5f91Slh * Free Tx/Rx ring buffer
102175ab5f91Slh */
102275ab5f91Slh static void
amd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf * pRing)102375ab5f91Slh amd8111s_free_dma_ringbuf(struct amd8111s_dma_ringbuf *pRing)
102475ab5f91Slh {
102575ab5f91Slh int idx;
102675ab5f91Slh
102775ab5f91Slh if (pRing->dma_cookie != NULL) {
102875ab5f91Slh for (idx = 0; idx < pRing->trunk_num; idx ++) {
102975ab5f91Slh if (pRing->dma_cookie[idx].dmac_laddress == 0) {
103075ab5f91Slh break;
103175ab5f91Slh }
103275ab5f91Slh (void) ddi_dma_unbind_handle(pRing->dma_hdl[idx]);
103375ab5f91Slh }
103475ab5f91Slh kmem_free(pRing->dma_cookie,
103575ab5f91Slh sizeof (ddi_dma_cookie_t) * pRing->trunk_num);
103675ab5f91Slh }
103775ab5f91Slh
103875ab5f91Slh if (pRing->acc_hdl != NULL) {
103975ab5f91Slh for (idx = 0; idx < pRing->trunk_num; idx ++) {
104075ab5f91Slh if (pRing->acc_hdl[idx] == NULL)
104175ab5f91Slh break;
104275ab5f91Slh ddi_dma_mem_free(&pRing->acc_hdl[idx]);
104375ab5f91Slh }
104475ab5f91Slh kmem_free(pRing->acc_hdl,
104575ab5f91Slh sizeof (ddi_acc_handle_t) * pRing->trunk_num);
104675ab5f91Slh }
104775ab5f91Slh
104875ab5f91Slh if (pRing->dma_hdl != NULL) {
104975ab5f91Slh for (idx = 0; idx < pRing->trunk_num; idx ++) {
105075ab5f91Slh if (pRing->dma_hdl[idx] == 0) {
105175ab5f91Slh break;
105275ab5f91Slh }
105375ab5f91Slh ddi_dma_free_handle(&pRing->dma_hdl[idx]);
105475ab5f91Slh }
105575ab5f91Slh kmem_free(pRing->dma_hdl,
105675ab5f91Slh sizeof (ddi_dma_handle_t) * pRing->trunk_num);
105775ab5f91Slh }
105875ab5f91Slh
105975ab5f91Slh if (pRing->msg_buf != NULL) {
106075ab5f91Slh kmem_free(pRing->msg_buf,
106175ab5f91Slh sizeof (struct amd8111s_msgbuf) * pRing->ring_size);
106275ab5f91Slh }
106375ab5f91Slh
106475ab5f91Slh if (pRing->trunk_addr != NULL) {
106575ab5f91Slh kmem_free(pRing->trunk_addr,
106675ab5f91Slh sizeof (caddr_t) * pRing->trunk_num);
106775ab5f91Slh }
106875ab5f91Slh
106975ab5f91Slh bzero(pRing, sizeof (*pRing));
107075ab5f91Slh }
107175ab5f91Slh
107275ab5f91Slh
107375ab5f91Slh /*
107475ab5f91Slh * Allocate all Tx buffer.
107575ab5f91Slh * Allocate a Rx buffer for each Rx descriptor. Then
107675ab5f91Slh * call mil routine to fill physical address of Rx
107775ab5f91Slh * buffer into Rx descriptors
107875ab5f91Slh */
107975ab5f91Slh static boolean_t
amd8111s_allocate_buffers(struct LayerPointers * pLayerPointers)108075ab5f91Slh amd8111s_allocate_buffers(struct LayerPointers *pLayerPointers)
108175ab5f91Slh {
108275ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
108375ab5f91Slh
108475ab5f91Slh /*
108575ab5f91Slh * Allocate rx Buffers
108675ab5f91Slh */
108775ab5f91Slh if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->rx_buf,
108875ab5f91Slh RX_RING_SIZE, RX_BUF_SIZE) == B_FALSE) {
108975ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
109075ab5f91Slh "amd8111s_alloc_dma_ringbuf for tx failed");
109175ab5f91Slh goto allocate_buf_fail;
109275ab5f91Slh }
109375ab5f91Slh
109475ab5f91Slh /*
109575ab5f91Slh * Allocate Tx buffers
109675ab5f91Slh */
109775ab5f91Slh if (amd8111s_alloc_dma_ringbuf(pLayerPointers, &pOdl->tx_buf,
109875ab5f91Slh TX_COALESC_SIZE, TX_BUF_SIZE) == B_FALSE) {
109975ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
110075ab5f91Slh "amd8111s_alloc_dma_ringbuf for tx failed");
110175ab5f91Slh goto allocate_buf_fail;
110275ab5f91Slh }
110375ab5f91Slh
110475ab5f91Slh /*
110575ab5f91Slh * Initilize the mil Queues
110675ab5f91Slh */
110775ab5f91Slh milInitGlbds(pLayerPointers);
110875ab5f91Slh
110975ab5f91Slh milInitRxQ(pLayerPointers);
111075ab5f91Slh
111175ab5f91Slh return (B_TRUE);
111275ab5f91Slh
111375ab5f91Slh allocate_buf_fail:
111475ab5f91Slh
111575ab5f91Slh amd8111s_log(pLayerPointers, CE_WARN,
111675ab5f91Slh "amd8111s_allocate_buffers failed");
111775ab5f91Slh return (B_FALSE);
111875ab5f91Slh }
111975ab5f91Slh
112075ab5f91Slh /*
112175ab5f91Slh * Free all Rx/Tx buffer
112275ab5f91Slh */
112375ab5f91Slh
112475ab5f91Slh static void
amd8111s_free_buffers(struct LayerPointers * pLayerPointers)112575ab5f91Slh amd8111s_free_buffers(struct LayerPointers *pLayerPointers)
112675ab5f91Slh {
112775ab5f91Slh /* Free Tx buffers */
112875ab5f91Slh amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->tx_buf);
112975ab5f91Slh
113075ab5f91Slh /* Free Rx Buffers */
113175ab5f91Slh amd8111s_free_dma_ringbuf(&pLayerPointers->pOdl->rx_buf);
113275ab5f91Slh }
113375ab5f91Slh
113475ab5f91Slh /*
113575ab5f91Slh * Try to recycle all the descriptors and Tx buffers
113675ab5f91Slh * which are already freed by hardware.
113775ab5f91Slh */
113875ab5f91Slh static int
amd8111s_recycle_tx(struct LayerPointers * pLayerPointers)113975ab5f91Slh amd8111s_recycle_tx(struct LayerPointers *pLayerPointers)
114075ab5f91Slh {
114175ab5f91Slh struct nonphysical *pNonphysical;
114275ab5f91Slh uint32_t count = 0;
114375ab5f91Slh
114475ab5f91Slh pNonphysical = pLayerPointers->pMil->pNonphysical;
114575ab5f91Slh while (pNonphysical->TxDescQRead->Tx_OWN == 0 &&
114675ab5f91Slh pNonphysical->TxDescQRead != pNonphysical->TxDescQWrite) {
114775ab5f91Slh pLayerPointers->pOdl->tx_buf.free =
114875ab5f91Slh NEXT(pLayerPointers->pOdl->tx_buf, free);
114975ab5f91Slh pNonphysical->TxDescQRead++;
115075ab5f91Slh if (pNonphysical->TxDescQRead > pNonphysical->TxDescQEnd) {
115175ab5f91Slh pNonphysical->TxDescQRead = pNonphysical->TxDescQStart;
115275ab5f91Slh }
115375ab5f91Slh count ++;
115475ab5f91Slh }
115575ab5f91Slh
115675ab5f91Slh if (pLayerPointers->pMil->tx_reschedule)
115775ab5f91Slh ddi_trigger_softintr(pLayerPointers->pOdl->drain_id);
115875ab5f91Slh
115975ab5f91Slh return (count);
116075ab5f91Slh }
116175ab5f91Slh
116275ab5f91Slh /*
116375ab5f91Slh * Get packets in the Tx buffer, then copy them to the send buffer.
116475ab5f91Slh * Trigger hardware to send out packets.
116575ab5f91Slh */
116675ab5f91Slh static void
amd8111s_send_serial(struct LayerPointers * pLayerPointers)116775ab5f91Slh amd8111s_send_serial(struct LayerPointers *pLayerPointers)
116875ab5f91Slh {
116975ab5f91Slh struct nonphysical *pNonphysical;
117075ab5f91Slh uint32_t count;
117175ab5f91Slh
117275ab5f91Slh pNonphysical = pLayerPointers->pMil->pNonphysical;
117375ab5f91Slh
117475ab5f91Slh mutex_enter(&pLayerPointers->pOdl->mdlSendLock);
117575ab5f91Slh
117675ab5f91Slh for (count = 0; count < AMD8111S_SEND_MAX; count ++) {
117775ab5f91Slh if (pLayerPointers->pOdl->tx_buf.curr ==
117875ab5f91Slh pLayerPointers->pOdl->tx_buf.next) {
117975ab5f91Slh break;
118075ab5f91Slh }
118175ab5f91Slh /* to verify if it needs to recycle the tx Buf */
118275ab5f91Slh if (((pNonphysical->TxDescQWrite + 1 >
118375ab5f91Slh pNonphysical->TxDescQEnd) ? pNonphysical->TxDescQStart :
118475ab5f91Slh (pNonphysical->TxDescQWrite + 1)) ==
118575ab5f91Slh pNonphysical->TxDescQRead)
118675ab5f91Slh if (amd8111s_recycle_tx(pLayerPointers) == 0) {
118775ab5f91Slh pLayerPointers->pOdl
118875ab5f91Slh ->statistics.tx_no_descriptor ++;
118975ab5f91Slh break;
119075ab5f91Slh }
119175ab5f91Slh
119275ab5f91Slh /* Fill packet length */
119375ab5f91Slh pNonphysical->TxDescQWrite->Tx_BCNT = (uint16_t)pLayerPointers
119475ab5f91Slh ->pOdl->tx_buf.curr->msg_size;
119575ab5f91Slh
119675ab5f91Slh /* Fill physical buffer address */
119775ab5f91Slh pNonphysical->TxDescQWrite->Tx_Base_Addr = (unsigned int)
119875ab5f91Slh pLayerPointers->pOdl->tx_buf.curr->phy_addr;
119975ab5f91Slh
120075ab5f91Slh pNonphysical->TxDescQWrite->Tx_SOP = 1;
120175ab5f91Slh pNonphysical->TxDescQWrite->Tx_EOP = 1;
120275ab5f91Slh pNonphysical->TxDescQWrite->Tx_ADD_FCS = 1;
120375ab5f91Slh pNonphysical->TxDescQWrite->Tx_LTINT = 1;
120475ab5f91Slh pNonphysical->TxDescQWrite->Tx_USPACE = 0;
120575ab5f91Slh pNonphysical->TxDescQWrite->Tx_OWN = 1;
120675ab5f91Slh
120775ab5f91Slh pNonphysical->TxDescQWrite++;
120875ab5f91Slh if (pNonphysical->TxDescQWrite > pNonphysical->TxDescQEnd) {
120975ab5f91Slh pNonphysical->TxDescQWrite = pNonphysical->TxDescQStart;
121075ab5f91Slh }
121175ab5f91Slh
121275ab5f91Slh pLayerPointers->pOdl->tx_buf.curr =
121375ab5f91Slh NEXT(pLayerPointers->pOdl->tx_buf, curr);
121475ab5f91Slh
121575ab5f91Slh }
121675ab5f91Slh
121775ab5f91Slh pLayerPointers->pOdl->statistics.tx_ok_packets += count;
121875ab5f91Slh
121975ab5f91Slh mutex_exit(&pLayerPointers->pOdl->mdlSendLock);
122075ab5f91Slh
122175ab5f91Slh /* Call mdlTransmit to send the pkt out on the network */
122275ab5f91Slh mdlTransmit(pLayerPointers);
122375ab5f91Slh
122475ab5f91Slh }
122575ab5f91Slh
122675ab5f91Slh /*
122775ab5f91Slh * Softintr entrance. try to send out packets in the Tx buffer.
122875ab5f91Slh * If reschedule is True, call mac_tx_update to re-enable the
122975ab5f91Slh * transmit
123075ab5f91Slh */
123175ab5f91Slh static uint_t
amd8111s_send_drain(caddr_t arg)123275ab5f91Slh amd8111s_send_drain(caddr_t arg)
123375ab5f91Slh {
123422eb7cb5Sgd struct LayerPointers *pLayerPointers = (void *)arg;
123575ab5f91Slh
123675ab5f91Slh amd8111s_send_serial(pLayerPointers);
123775ab5f91Slh
123875ab5f91Slh if (pLayerPointers->pMil->tx_reschedule &&
123975ab5f91Slh NEXT(pLayerPointers->pOdl->tx_buf, next) !=
124075ab5f91Slh pLayerPointers->pOdl->tx_buf.free) {
124175ab5f91Slh mac_tx_update(pLayerPointers->pOdl->mh);
124275ab5f91Slh pLayerPointers->pMil->tx_reschedule = B_FALSE;
124375ab5f91Slh }
124475ab5f91Slh
124575ab5f91Slh return (DDI_INTR_CLAIMED);
124675ab5f91Slh }
124775ab5f91Slh
124875ab5f91Slh /*
124975ab5f91Slh * Get a Tx buffer
125075ab5f91Slh */
125175ab5f91Slh static struct amd8111s_msgbuf *
amd8111s_getTxbuf(struct LayerPointers * pLayerPointers)125275ab5f91Slh amd8111s_getTxbuf(struct LayerPointers *pLayerPointers)
125375ab5f91Slh {
125475ab5f91Slh struct amd8111s_msgbuf *tmp, *next;
125575ab5f91Slh
125675ab5f91Slh mutex_enter(&pLayerPointers->pOdl->mdlSendLock);
125775ab5f91Slh next = NEXT(pLayerPointers->pOdl->tx_buf, next);
125875ab5f91Slh if (next == pLayerPointers->pOdl->tx_buf.free) {
125975ab5f91Slh tmp = NULL;
126075ab5f91Slh } else {
126175ab5f91Slh tmp = pLayerPointers->pOdl->tx_buf.next;
126275ab5f91Slh pLayerPointers->pOdl->tx_buf.next = next;
126375ab5f91Slh }
126475ab5f91Slh mutex_exit(&pLayerPointers->pOdl->mdlSendLock);
126575ab5f91Slh
126675ab5f91Slh return (tmp);
126775ab5f91Slh }
126875ab5f91Slh
126975ab5f91Slh static boolean_t
amd8111s_send(struct LayerPointers * pLayerPointers,mblk_t * mp)127075ab5f91Slh amd8111s_send(struct LayerPointers *pLayerPointers, mblk_t *mp)
127175ab5f91Slh {
127275ab5f91Slh struct odl *pOdl;
127375ab5f91Slh size_t frag_len;
127475ab5f91Slh mblk_t *tmp;
127575ab5f91Slh struct amd8111s_msgbuf *txBuf;
127675ab5f91Slh uint8_t *pMsg;
127775ab5f91Slh
127875ab5f91Slh pOdl = pLayerPointers->pOdl;
127975ab5f91Slh
128075ab5f91Slh /* alloc send buffer */
128175ab5f91Slh txBuf = amd8111s_getTxbuf(pLayerPointers);
128275ab5f91Slh if (txBuf == NULL) {
128375ab5f91Slh pOdl->statistics.tx_no_buffer ++;
128475ab5f91Slh pLayerPointers->pMil->tx_reschedule = B_TRUE;
128575ab5f91Slh amd8111s_send_serial(pLayerPointers);
128675ab5f91Slh return (B_FALSE);
128775ab5f91Slh }
128875ab5f91Slh
128975ab5f91Slh /* copy packet to send buffer */
129075ab5f91Slh txBuf->msg_size = 0;
129175ab5f91Slh pMsg = (uint8_t *)txBuf->vir_addr;
129275ab5f91Slh for (tmp = mp; tmp; tmp = tmp->b_cont) {
129375ab5f91Slh frag_len = MBLKL(tmp);
129475ab5f91Slh bcopy(tmp->b_rptr, pMsg, frag_len);
129575ab5f91Slh txBuf->msg_size += frag_len;
129675ab5f91Slh pMsg += frag_len;
129775ab5f91Slh }
129875ab5f91Slh freemsg(mp);
129975ab5f91Slh
130075ab5f91Slh amd8111s_send_serial(pLayerPointers);
130175ab5f91Slh
130275ab5f91Slh return (B_TRUE);
130375ab5f91Slh }
130475ab5f91Slh
130575ab5f91Slh /*
130675ab5f91Slh * (GLD Entry Point) Send the message block to lower layer
130775ab5f91Slh */
130875ab5f91Slh static mblk_t *
amd8111s_m_tx(void * arg,mblk_t * mp)130975ab5f91Slh amd8111s_m_tx(void *arg, mblk_t *mp)
131075ab5f91Slh {
131175ab5f91Slh struct LayerPointers *pLayerPointers = arg;
131275ab5f91Slh mblk_t *next;
131375ab5f91Slh
131475ab5f91Slh rw_enter(&pLayerPointers->pOdl->chip_lock, RW_READER);
131575ab5f91Slh if (!pLayerPointers->run) {
131675ab5f91Slh pLayerPointers->pOdl->statistics.tx_afterunplumb ++;
131775ab5f91Slh freemsgchain(mp);
131875ab5f91Slh mp = NULL;
131975ab5f91Slh }
132075ab5f91Slh
132175ab5f91Slh while (mp != NULL) {
132275ab5f91Slh next = mp->b_next;
132375ab5f91Slh mp->b_next = NULL;
132475ab5f91Slh if (!amd8111s_send(pLayerPointers, mp)) {
132575ab5f91Slh /* Send fail */
132675ab5f91Slh mp->b_next = next;
132775ab5f91Slh break;
132875ab5f91Slh }
132975ab5f91Slh mp = next;
133075ab5f91Slh }
133175ab5f91Slh
133275ab5f91Slh rw_exit(&pLayerPointers->pOdl->chip_lock);
133375ab5f91Slh return (mp);
133475ab5f91Slh }
133575ab5f91Slh
133675ab5f91Slh /*
133775ab5f91Slh * (GLD Entry Point) Interrupt Service Routine
133875ab5f91Slh */
133975ab5f91Slh static uint_t
amd8111s_intr(caddr_t arg)134075ab5f91Slh amd8111s_intr(caddr_t arg)
134175ab5f91Slh {
134275ab5f91Slh unsigned int intrCauses;
134322eb7cb5Sgd struct LayerPointers *pLayerPointers = (void *)arg;
134475ab5f91Slh
134575ab5f91Slh /* Read the interrupt status from mdl */
134675ab5f91Slh intrCauses = mdlReadInterrupt(pLayerPointers);
134775ab5f91Slh
134875ab5f91Slh if (intrCauses == 0) {
134975ab5f91Slh pLayerPointers->pOdl->statistics.intr_OTHER ++;
135075ab5f91Slh return (DDI_INTR_UNCLAIMED);
135175ab5f91Slh }
135275ab5f91Slh
135375ab5f91Slh if (intrCauses & LCINT) {
135475ab5f91Slh if (mdlReadLink(pLayerPointers) == LINK_UP) {
135575ab5f91Slh mdlGetActiveMediaInfo(pLayerPointers);
135675ab5f91Slh /* Link status changed */
135775ab5f91Slh if (pLayerPointers->pOdl->LinkStatus !=
135875ab5f91Slh LINK_STATE_UP) {
135975ab5f91Slh pLayerPointers->pOdl->LinkStatus =
136075ab5f91Slh LINK_STATE_UP;
136175ab5f91Slh mac_link_update(pLayerPointers->pOdl->mh,
136275ab5f91Slh LINK_STATE_UP);
136375ab5f91Slh }
136475ab5f91Slh } else {
136575ab5f91Slh if (pLayerPointers->pOdl->LinkStatus !=
136675ab5f91Slh LINK_STATE_DOWN) {
136775ab5f91Slh pLayerPointers->pOdl->LinkStatus =
136875ab5f91Slh LINK_STATE_DOWN;
136975ab5f91Slh mac_link_update(pLayerPointers->pOdl->mh,
137075ab5f91Slh LINK_STATE_DOWN);
137175ab5f91Slh }
137275ab5f91Slh }
137375ab5f91Slh }
137475ab5f91Slh /*
137575ab5f91Slh * RINT0: Receive Interrupt is set by the controller after the last
137675ab5f91Slh * descriptor of a receive frame for this ring has been updated by
137775ab5f91Slh * writing a 0 to the OWNership bit.
137875ab5f91Slh */
137975ab5f91Slh if (intrCauses & RINT0) {
138075ab5f91Slh pLayerPointers->pOdl->statistics.intr_RINT0 ++;
138175ab5f91Slh amd8111s_receive(pLayerPointers);
138275ab5f91Slh }
138375ab5f91Slh
138475ab5f91Slh /*
138575ab5f91Slh * TINT0: Transmit Interrupt is set by the controller after the OWN bit
138675ab5f91Slh * in the last descriptor of a transmit frame in this particular ring
138775ab5f91Slh * has been cleared to indicate the frame has been copied to the
138875ab5f91Slh * transmit FIFO.
138975ab5f91Slh */
139075ab5f91Slh if (intrCauses & TINT0) {
139175ab5f91Slh pLayerPointers->pOdl->statistics.intr_TINT0 ++;
139275ab5f91Slh /*
139375ab5f91Slh * if desc ring is NULL and tx buf is not NULL, it should
139475ab5f91Slh * drain tx buffer
139575ab5f91Slh */
139675ab5f91Slh amd8111s_send_serial(pLayerPointers);
139775ab5f91Slh }
139875ab5f91Slh
139975ab5f91Slh if (intrCauses & STINT) {
140075ab5f91Slh pLayerPointers->pOdl->statistics.intr_STINT ++;
140175ab5f91Slh }
140275ab5f91Slh
140375ab5f91Slh
140475ab5f91Slh return (DDI_INTR_CLAIMED);
140575ab5f91Slh }
140675ab5f91Slh
140775ab5f91Slh /*
140875ab5f91Slh * To re-initilize data structures.
140975ab5f91Slh */
141075ab5f91Slh static void
amd8111s_sw_reset(struct LayerPointers * pLayerPointers)141175ab5f91Slh amd8111s_sw_reset(struct LayerPointers *pLayerPointers)
141275ab5f91Slh {
141375ab5f91Slh /* Reset all Tx/Rx queues and descriptors */
141475ab5f91Slh milResetTxQ(pLayerPointers);
141575ab5f91Slh milInitRxQ(pLayerPointers);
141675ab5f91Slh }
141775ab5f91Slh
141875ab5f91Slh /*
141975ab5f91Slh * Send all pending tx packets
142075ab5f91Slh */
142175ab5f91Slh static void
amd8111s_tx_drain(struct LayerPointers * adapter)142275ab5f91Slh amd8111s_tx_drain(struct LayerPointers *adapter)
142375ab5f91Slh {
142475ab5f91Slh struct tx_desc *pTx_desc = adapter->pMil->pNonphysical->TxDescQStart;
142575ab5f91Slh int i, desc_count = 0;
142675ab5f91Slh for (i = 0; i < 30; i++) {
142775ab5f91Slh while ((pTx_desc->Tx_OWN == 0) && (desc_count < TX_RING_SIZE)) {
142875ab5f91Slh /* This packet has been transmitted */
142975ab5f91Slh pTx_desc ++;
143075ab5f91Slh desc_count ++;
143175ab5f91Slh }
143275ab5f91Slh if (desc_count == TX_RING_SIZE) {
143375ab5f91Slh break;
143475ab5f91Slh }
143575ab5f91Slh /* Wait 1 ms */
143675ab5f91Slh drv_usecwait(1000);
143775ab5f91Slh }
143875ab5f91Slh adapter->pOdl->statistics.tx_draintime = i;
143975ab5f91Slh }
144075ab5f91Slh
144175ab5f91Slh /*
144275ab5f91Slh * (GLD Entry Point) To start card will be called at
144375ab5f91Slh * ifconfig plumb
144475ab5f91Slh */
144575ab5f91Slh static int
amd8111s_m_start(void * arg)144675ab5f91Slh amd8111s_m_start(void *arg)
144775ab5f91Slh {
144875ab5f91Slh struct LayerPointers *pLayerPointers = arg;
144975ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
145075ab5f91Slh
145175ab5f91Slh amd8111s_sw_reset(pLayerPointers);
145275ab5f91Slh mdlHWReset(pLayerPointers);
145375ab5f91Slh rw_enter(&pOdl->chip_lock, RW_WRITER);
145475ab5f91Slh pLayerPointers->run = B_TRUE;
145575ab5f91Slh rw_exit(&pOdl->chip_lock);
145675ab5f91Slh return (0);
145775ab5f91Slh }
145875ab5f91Slh
145975ab5f91Slh /*
146075ab5f91Slh * (GLD Entry Point) To stop card will be called at
146175ab5f91Slh * ifconfig unplumb
146275ab5f91Slh */
146375ab5f91Slh static void
amd8111s_m_stop(void * arg)146475ab5f91Slh amd8111s_m_stop(void *arg)
146575ab5f91Slh {
146675ab5f91Slh struct LayerPointers *pLayerPointers = (struct LayerPointers *)arg;
146775ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
146875ab5f91Slh
146975ab5f91Slh /* Ensure send all pending tx packets */
147075ab5f91Slh amd8111s_tx_drain(pLayerPointers);
147175ab5f91Slh /*
147275ab5f91Slh * Stop the controller and disable the controller interrupt
147375ab5f91Slh */
147475ab5f91Slh rw_enter(&pOdl->chip_lock, RW_WRITER);
147575ab5f91Slh mdlStopChip(pLayerPointers);
147675ab5f91Slh pLayerPointers->run = B_FALSE;
147775ab5f91Slh rw_exit(&pOdl->chip_lock);
147875ab5f91Slh }
147975ab5f91Slh
148075ab5f91Slh /*
148175ab5f91Slh * To clean up all
148275ab5f91Slh */
148375ab5f91Slh static void
amd8111s_free_resource(struct LayerPointers * pLayerPointers)148475ab5f91Slh amd8111s_free_resource(struct LayerPointers *pLayerPointers)
148575ab5f91Slh {
148675ab5f91Slh unsigned long mem_free_array[100];
148775ab5f91Slh unsigned long *pmem_free_array, size;
148875ab5f91Slh
148975ab5f91Slh /* Free Rx/Tx descriptors */
149075ab5f91Slh amd8111s_free_descriptors(pLayerPointers);
149175ab5f91Slh
149275ab5f91Slh /* Free memory on lower layers */
149375ab5f91Slh milFreeResources(pLayerPointers, mem_free_array);
149475ab5f91Slh pmem_free_array = mem_free_array;
149575ab5f91Slh while (*pmem_free_array) {
149675ab5f91Slh switch (*pmem_free_array) {
149775ab5f91Slh case VIRTUAL:
149875ab5f91Slh size = *(++pmem_free_array);
149975ab5f91Slh pmem_free_array++;
150075ab5f91Slh kmem_free((void *)*(pmem_free_array), size);
150175ab5f91Slh break;
150275ab5f91Slh }
150375ab5f91Slh pmem_free_array++;
150475ab5f91Slh }
150575ab5f91Slh
150675ab5f91Slh amd8111s_free_buffers(pLayerPointers);
150775ab5f91Slh }
150875ab5f91Slh
150975ab5f91Slh /*
151075ab5f91Slh * (GLD Enty pointer) To add/delete multi cast addresses
151175ab5f91Slh *
151275ab5f91Slh */
151375ab5f91Slh static int
amd8111s_m_multicst(void * arg,boolean_t add,const uint8_t * addr)151475ab5f91Slh amd8111s_m_multicst(void *arg, boolean_t add, const uint8_t *addr)
151575ab5f91Slh {
151675ab5f91Slh struct LayerPointers *pLayerPointers = arg;
151775ab5f91Slh
151875ab5f91Slh if (add) {
151975ab5f91Slh /* Add a multicast entry */
152075ab5f91Slh mdlAddMulticastAddress(pLayerPointers, (UCHAR *)addr);
152175ab5f91Slh } else {
152275ab5f91Slh /* Delete a multicast entry */
152375ab5f91Slh mdlDeleteMulticastAddress(pLayerPointers, (UCHAR *)addr);
152475ab5f91Slh }
152575ab5f91Slh
152675ab5f91Slh return (0);
152775ab5f91Slh }
152875ab5f91Slh
152975ab5f91Slh #ifdef AMD8111S_DEBUG
153075ab5f91Slh /*
153175ab5f91Slh * The size of MIB registers is only 32 bits. Dump them before one
153275ab5f91Slh * of them overflows.
153375ab5f91Slh */
153475ab5f91Slh static void
amd8111s_dump_mib(struct LayerPointers * pLayerPointers)153575ab5f91Slh amd8111s_dump_mib(struct LayerPointers *pLayerPointers)
153675ab5f91Slh {
153775ab5f91Slh struct amd8111s_statistics *adapterStat;
153875ab5f91Slh
153975ab5f91Slh adapterStat = &pLayerPointers->pOdl->statistics;
154075ab5f91Slh
154175ab5f91Slh adapterStat->mib_dump_counter ++;
154275ab5f91Slh
154375ab5f91Slh /*
154475ab5f91Slh * Rx Counters
154575ab5f91Slh */
154675ab5f91Slh adapterStat->rx_mib_unicst_packets +=
154775ab5f91Slh mdlReadMib(pLayerPointers, RcvUniCastPkts);
154875ab5f91Slh adapterStat->rx_mib_multicst_packets +=
154975ab5f91Slh mdlReadMib(pLayerPointers, RcvMultiCastPkts);
155075ab5f91Slh adapterStat->rx_mib_broadcst_packets +=
155175ab5f91Slh mdlReadMib(pLayerPointers, RcvBroadCastPkts);
155275ab5f91Slh adapterStat->rx_mib_macctrl_packets +=
155375ab5f91Slh mdlReadMib(pLayerPointers, RcvMACCtrl);
155475ab5f91Slh adapterStat->rx_mib_flowctrl_packets +=
155575ab5f91Slh mdlReadMib(pLayerPointers, RcvFlowCtrl);
155675ab5f91Slh
155775ab5f91Slh adapterStat->rx_mib_bytes +=
155875ab5f91Slh mdlReadMib(pLayerPointers, RcvOctets);
155975ab5f91Slh adapterStat->rx_mib_good_bytes +=
156075ab5f91Slh mdlReadMib(pLayerPointers, RcvGoodOctets);
156175ab5f91Slh
156275ab5f91Slh adapterStat->rx_mib_undersize_packets +=
156375ab5f91Slh mdlReadMib(pLayerPointers, RcvUndersizePkts);
156475ab5f91Slh adapterStat->rx_mib_oversize_packets +=
156575ab5f91Slh mdlReadMib(pLayerPointers, RcvOversizePkts);
156675ab5f91Slh
156775ab5f91Slh adapterStat->rx_mib_drop_packets +=
156875ab5f91Slh mdlReadMib(pLayerPointers, RcvDropPktsRing0);
156975ab5f91Slh adapterStat->rx_mib_align_err_packets +=
157075ab5f91Slh mdlReadMib(pLayerPointers, RcvAlignmentErrors);
157175ab5f91Slh adapterStat->rx_mib_fcs_err_packets +=
157275ab5f91Slh mdlReadMib(pLayerPointers, RcvFCSErrors);
157375ab5f91Slh adapterStat->rx_mib_symbol_err_packets +=
157475ab5f91Slh mdlReadMib(pLayerPointers, RcvSymbolErrors);
157575ab5f91Slh adapterStat->rx_mib_miss_packets +=
157675ab5f91Slh mdlReadMib(pLayerPointers, RcvMissPkts);
157775ab5f91Slh
157875ab5f91Slh /*
157975ab5f91Slh * Tx Counters
158075ab5f91Slh */
158175ab5f91Slh adapterStat->tx_mib_packets +=
158275ab5f91Slh mdlReadMib(pLayerPointers, XmtPackets);
158375ab5f91Slh adapterStat->tx_mib_multicst_packets +=
158475ab5f91Slh mdlReadMib(pLayerPointers, XmtMultiCastPkts);
158575ab5f91Slh adapterStat->tx_mib_broadcst_packets +=
158675ab5f91Slh mdlReadMib(pLayerPointers, XmtBroadCastPkts);
158775ab5f91Slh adapterStat->tx_mib_flowctrl_packets +=
158875ab5f91Slh mdlReadMib(pLayerPointers, XmtFlowCtrl);
158975ab5f91Slh
159075ab5f91Slh adapterStat->tx_mib_bytes +=
159175ab5f91Slh mdlReadMib(pLayerPointers, XmtOctets);
159275ab5f91Slh
159375ab5f91Slh adapterStat->tx_mib_defer_trans_packets +=
159475ab5f91Slh mdlReadMib(pLayerPointers, XmtDeferredTransmit);
159575ab5f91Slh adapterStat->tx_mib_collision_packets +=
159675ab5f91Slh mdlReadMib(pLayerPointers, XmtCollisions);
159775ab5f91Slh adapterStat->tx_mib_one_coll_packets +=
159875ab5f91Slh mdlReadMib(pLayerPointers, XmtOneCollision);
159975ab5f91Slh adapterStat->tx_mib_multi_coll_packets +=
160075ab5f91Slh mdlReadMib(pLayerPointers, XmtMultipleCollision);
160175ab5f91Slh adapterStat->tx_mib_late_coll_packets +=
160275ab5f91Slh mdlReadMib(pLayerPointers, XmtLateCollision);
160375ab5f91Slh adapterStat->tx_mib_ex_coll_packets +=
160475ab5f91Slh mdlReadMib(pLayerPointers, XmtExcessiveCollision);
160575ab5f91Slh
160675ab5f91Slh
160775ab5f91Slh /* Clear all MIB registers */
160875ab5f91Slh WRITE_REG16(pLayerPointers, pLayerPointers->pMdl->Mem_Address
160975ab5f91Slh + MIB_ADDR, MIB_CLEAR);
161075ab5f91Slh }
161175ab5f91Slh #endif
161275ab5f91Slh
161375ab5f91Slh /*
161475ab5f91Slh * (GLD Entry Point) set/unset promiscus mode
161575ab5f91Slh */
161675ab5f91Slh static int
amd8111s_m_promisc(void * arg,boolean_t on)161775ab5f91Slh amd8111s_m_promisc(void *arg, boolean_t on)
161875ab5f91Slh {
161975ab5f91Slh struct LayerPointers *pLayerPointers = arg;
162075ab5f91Slh
162175ab5f91Slh if (on) {
162275ab5f91Slh mdlSetPromiscuous(pLayerPointers);
162375ab5f91Slh } else {
162475ab5f91Slh mdlDisablePromiscuous(pLayerPointers);
162575ab5f91Slh }
162675ab5f91Slh
162775ab5f91Slh return (0);
162875ab5f91Slh }
162975ab5f91Slh
163075ab5f91Slh /*
163175ab5f91Slh * (Gld Entry point) Changes the Mac address of card
163275ab5f91Slh */
163375ab5f91Slh static int
amd8111s_m_unicst(void * arg,const uint8_t * macaddr)163475ab5f91Slh amd8111s_m_unicst(void *arg, const uint8_t *macaddr)
163575ab5f91Slh {
163675ab5f91Slh struct LayerPointers *pLayerPointers = arg;
163775ab5f91Slh
163875ab5f91Slh mdlDisableInterrupt(pLayerPointers);
163975ab5f91Slh mdlSetMacAddress(pLayerPointers, (unsigned char *)macaddr);
164075ab5f91Slh mdlEnableInterrupt(pLayerPointers);
164175ab5f91Slh
164275ab5f91Slh return (0);
164375ab5f91Slh }
164475ab5f91Slh
164575ab5f91Slh /*
164675ab5f91Slh * Reset the card
164775ab5f91Slh */
164875ab5f91Slh void
amd8111s_reset(struct LayerPointers * pLayerPointers)164975ab5f91Slh amd8111s_reset(struct LayerPointers *pLayerPointers)
165075ab5f91Slh {
165175ab5f91Slh amd8111s_sw_reset(pLayerPointers);
165275ab5f91Slh mdlHWReset(pLayerPointers);
165375ab5f91Slh }
165475ab5f91Slh
165575ab5f91Slh /*
165675ab5f91Slh * attach(9E) -- Attach a device to the system
165775ab5f91Slh *
165875ab5f91Slh * Called once for each board after successfully probed.
165975ab5f91Slh * will do
1660*0f36d2f1SToomas Soome * a. creating minor device node for the instance.
166175ab5f91Slh * b. allocate & Initilize four layers (call odlInit)
166275ab5f91Slh * c. get MAC address
166375ab5f91Slh * d. initilize pLayerPointers to gld private pointer
166475ab5f91Slh * e. register with GLD
166575ab5f91Slh * if any action fails does clean up & returns DDI_FAILURE
166675ab5f91Slh * else retursn DDI_SUCCESS
166775ab5f91Slh */
166875ab5f91Slh static int
amd8111s_attach(dev_info_t * devinfo,ddi_attach_cmd_t cmd)166975ab5f91Slh amd8111s_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
167075ab5f91Slh {
167175ab5f91Slh mac_register_t *macp;
167275ab5f91Slh struct LayerPointers *pLayerPointers;
167375ab5f91Slh struct odl *pOdl;
167475ab5f91Slh ddi_acc_handle_t *pci_handle;
167575ab5f91Slh ddi_device_acc_attr_t dev_attr;
167675ab5f91Slh caddr_t addrp = NULL;
167775ab5f91Slh
167875ab5f91Slh switch (cmd) {
167975ab5f91Slh case DDI_ATTACH:
168075ab5f91Slh break;
168175ab5f91Slh default:
168275ab5f91Slh return (DDI_FAILURE);
168375ab5f91Slh }
168475ab5f91Slh
168575ab5f91Slh pLayerPointers = (struct LayerPointers *)
168675ab5f91Slh kmem_zalloc(sizeof (struct LayerPointers), KM_SLEEP);
168775ab5f91Slh amd8111sadapter = pLayerPointers;
168875ab5f91Slh
168975ab5f91Slh /* Get device instance number */
169075ab5f91Slh pLayerPointers->instance = ddi_get_instance(devinfo);
169175ab5f91Slh ddi_set_driver_private(devinfo, (caddr_t)pLayerPointers);
169275ab5f91Slh
169375ab5f91Slh pOdl = (struct odl *)kmem_zalloc(sizeof (struct odl), KM_SLEEP);
169475ab5f91Slh pLayerPointers->pOdl = pOdl;
169575ab5f91Slh
169675ab5f91Slh pOdl->devinfo = devinfo;
169775ab5f91Slh
169875ab5f91Slh /*
169975ab5f91Slh * Here, we only allocate memory for struct odl and initilize it.
170075ab5f91Slh * All other memory allocation & initilization will be done in odlInit
170175ab5f91Slh * later on this routine.
170275ab5f91Slh */
170375ab5f91Slh if (ddi_get_iblock_cookie(devinfo, 0, &pLayerPointers->pOdl->iblock)
170475ab5f91Slh != DDI_SUCCESS) {
170575ab5f91Slh amd8111s_log(pLayerPointers, CE_NOTE,
170675ab5f91Slh "attach: get iblock cookies failed");
170775ab5f91Slh goto attach_failure;
170875ab5f91Slh }
170975ab5f91Slh
171075ab5f91Slh rw_init(&pOdl->chip_lock, NULL, RW_DRIVER, (void *)pOdl->iblock);
171175ab5f91Slh mutex_init(&pOdl->mdlSendLock, "amd8111s Send Protection Lock",
171275ab5f91Slh MUTEX_DRIVER, (void *)pOdl->iblock);
171375ab5f91Slh mutex_init(&pOdl->mdlRcvLock, "amd8111s Rcv Protection Lock",
171475ab5f91Slh MUTEX_DRIVER, (void *)pOdl->iblock);
171575ab5f91Slh
171675ab5f91Slh /* Setup PCI space */
171775ab5f91Slh if (pci_config_setup(devinfo, &pOdl->pci_handle) != DDI_SUCCESS) {
171875ab5f91Slh return (DDI_FAILURE);
171975ab5f91Slh }
172075ab5f91Slh pLayerPointers->attach_progress = AMD8111S_ATTACH_PCI;
172175ab5f91Slh pci_handle = &pOdl->pci_handle;
172275ab5f91Slh
172375ab5f91Slh pOdl->vendor_id = pci_config_get16(*pci_handle, PCI_CONF_VENID);
172475ab5f91Slh pOdl->device_id = pci_config_get16(*pci_handle, PCI_CONF_DEVID);
172575ab5f91Slh
172675ab5f91Slh /*
172775ab5f91Slh * Allocate and initialize all resource and map device registers.
172875ab5f91Slh * If failed, it returns a non-zero value.
172975ab5f91Slh */
173075ab5f91Slh if (amd8111s_odlInit(pLayerPointers) != 0) {
173175ab5f91Slh goto attach_failure;
173275ab5f91Slh }
173375ab5f91Slh pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESOURCE;
173475ab5f91Slh
173575ab5f91Slh dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
173675ab5f91Slh dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
173775ab5f91Slh dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
173875ab5f91Slh
173975ab5f91Slh if (ddi_regs_map_setup(devinfo, 1, &addrp, 0, 4096, &dev_attr,
174075ab5f91Slh &(pLayerPointers->pOdl->MemBasehandle)) != 0) {
174175ab5f91Slh amd8111s_log(pLayerPointers, CE_NOTE,
174275ab5f91Slh "attach: ddi_regs_map_setup failed");
174375ab5f91Slh goto attach_failure;
174475ab5f91Slh }
174575ab5f91Slh pLayerPointers->pMdl->Mem_Address = (unsigned long)addrp;
174675ab5f91Slh
174775ab5f91Slh /* Initialize HW */
174875ab5f91Slh mdlOpen(pLayerPointers);
174975ab5f91Slh mdlGetActiveMediaInfo(pLayerPointers);
175075ab5f91Slh pLayerPointers->attach_progress |= AMD8111S_ATTACH_REGS;
175175ab5f91Slh
175275ab5f91Slh /*
175375ab5f91Slh * Setup the interrupt
175475ab5f91Slh */
175575ab5f91Slh if (ddi_add_intr(devinfo, 0, &pOdl->iblock, 0, amd8111s_intr,
175675ab5f91Slh (caddr_t)pLayerPointers) != DDI_SUCCESS) {
175775ab5f91Slh goto attach_failure;
175875ab5f91Slh }
175975ab5f91Slh pLayerPointers->attach_progress |= AMD8111S_ATTACH_INTRADDED;
176075ab5f91Slh
176175ab5f91Slh /*
176275ab5f91Slh * Setup soft intr
176375ab5f91Slh */
176475ab5f91Slh if (ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &pOdl->drain_id,
176575ab5f91Slh NULL, NULL, amd8111s_send_drain,
176675ab5f91Slh (caddr_t)pLayerPointers) != DDI_SUCCESS) {
176775ab5f91Slh goto attach_failure;
176875ab5f91Slh }
176975ab5f91Slh pLayerPointers->attach_progress |= AMD8111S_ATTACH_RESCHED;
177075ab5f91Slh
177175ab5f91Slh /*
177275ab5f91Slh * Initilize the mac structure
177375ab5f91Slh */
177475ab5f91Slh if ((macp = mac_alloc(MAC_VERSION)) == NULL)
177575ab5f91Slh goto attach_failure;
177675ab5f91Slh
177775ab5f91Slh macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
177875ab5f91Slh macp->m_driver = pLayerPointers;
177975ab5f91Slh macp->m_dip = devinfo;
178075ab5f91Slh /* Get MAC address */
178175ab5f91Slh mdlGetMacAddress(pLayerPointers, (unsigned char *)pOdl->MacAddress);
178275ab5f91Slh macp->m_src_addr = pOdl->MacAddress;
178375ab5f91Slh macp->m_callbacks = &amd8111s_m_callbacks;
178475ab5f91Slh macp->m_min_sdu = 0;
178575ab5f91Slh /* 1518 - 14 (ether header) - 4 (CRC) */
178675ab5f91Slh macp->m_max_sdu = ETHERMTU;
1787d62bc4baSyz macp->m_margin = VLAN_TAGSZ;
178875ab5f91Slh
178975ab5f91Slh /*
179075ab5f91Slh * Finally, we're ready to register ourselves with the MAC layer
179175ab5f91Slh * interface; if this succeeds, we're ready to start.
179275ab5f91Slh */
179375ab5f91Slh if (mac_register(macp, &pOdl->mh) != DDI_SUCCESS) {
179475ab5f91Slh mac_free(macp);
179575ab5f91Slh goto attach_failure;
179675ab5f91Slh }
179775ab5f91Slh mac_free(macp);
179875ab5f91Slh
179975ab5f91Slh pLayerPointers->attach_progress |= AMD8111S_ATTACH_MACREGED;
180075ab5f91Slh
180175ab5f91Slh return (DDI_SUCCESS);
180275ab5f91Slh
180375ab5f91Slh attach_failure:
180475ab5f91Slh (void) amd8111s_unattach(devinfo, pLayerPointers);
180575ab5f91Slh return (DDI_FAILURE);
180675ab5f91Slh
180775ab5f91Slh }
180875ab5f91Slh
180975ab5f91Slh /*
181075ab5f91Slh * detach(9E) -- Detach a device from the system
181175ab5f91Slh *
181275ab5f91Slh * It is called for each device instance when the system is preparing to
181375ab5f91Slh * unload a dynamically unloadable driver.
181475ab5f91Slh * will Do
1815*0f36d2f1SToomas Soome * a. check if any driver buffers are held by OS.
181675ab5f91Slh * b. do clean up of all allocated memory if it is not in use by OS.
181775ab5f91Slh * c. un register with GLD
181875ab5f91Slh * d. return DDI_SUCCESS on succes full free & unregister
181975ab5f91Slh * else GLD_FAILURE
182075ab5f91Slh */
182175ab5f91Slh static int
amd8111s_detach(dev_info_t * devinfo,ddi_detach_cmd_t cmd)182275ab5f91Slh amd8111s_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
182375ab5f91Slh {
182475ab5f91Slh struct LayerPointers *pLayerPointers;
182575ab5f91Slh
182675ab5f91Slh switch (cmd) {
182775ab5f91Slh case DDI_DETACH:
182875ab5f91Slh break;
182975ab5f91Slh default:
183075ab5f91Slh return (DDI_FAILURE);
183175ab5f91Slh }
183275ab5f91Slh
183375ab5f91Slh /*
183475ab5f91Slh * Get the driver private (struct LayerPointers *) structure
183575ab5f91Slh */
183675ab5f91Slh if ((pLayerPointers = (struct LayerPointers *)ddi_get_driver_private
183775ab5f91Slh (devinfo)) == NULL) {
183875ab5f91Slh return (DDI_FAILURE);
183975ab5f91Slh }
184075ab5f91Slh
184175ab5f91Slh return (amd8111s_unattach(devinfo, pLayerPointers));
184275ab5f91Slh }
184375ab5f91Slh
184475ab5f91Slh static int
amd8111s_unattach(dev_info_t * devinfo,struct LayerPointers * pLayerPointers)184575ab5f91Slh amd8111s_unattach(dev_info_t *devinfo, struct LayerPointers *pLayerPointers)
184675ab5f91Slh {
184775ab5f91Slh struct odl *pOdl = pLayerPointers->pOdl;
184875ab5f91Slh
184975ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_MACREGED) {
185075ab5f91Slh /* Unregister driver from the GLD interface */
185175ab5f91Slh if (mac_unregister(pOdl->mh) != DDI_SUCCESS) {
185275ab5f91Slh return (DDI_FAILURE);
185375ab5f91Slh }
185475ab5f91Slh }
185575ab5f91Slh
185675ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_INTRADDED) {
185775ab5f91Slh ddi_remove_intr(devinfo, 0, pOdl->iblock);
185875ab5f91Slh }
185975ab5f91Slh
186075ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESCHED) {
186175ab5f91Slh ddi_remove_softintr(pOdl->drain_id);
186275ab5f91Slh }
186375ab5f91Slh
186475ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_REGS) {
186575ab5f91Slh /* Stop HW */
186675ab5f91Slh mdlStopChip(pLayerPointers);
186775ab5f91Slh ddi_regs_map_free(&(pOdl->MemBasehandle));
186875ab5f91Slh }
186975ab5f91Slh
187075ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_RESOURCE) {
187175ab5f91Slh /* Free All memory allocated */
187275ab5f91Slh amd8111s_free_resource(pLayerPointers);
187375ab5f91Slh }
187475ab5f91Slh
187575ab5f91Slh if (pLayerPointers->attach_progress & AMD8111S_ATTACH_PCI) {
187675ab5f91Slh pci_config_teardown(&pOdl->pci_handle);
187775ab5f91Slh mutex_destroy(&pOdl->mdlSendLock);
187875ab5f91Slh mutex_destroy(&pOdl->mdlRcvLock);
187975ab5f91Slh rw_destroy(&pOdl->chip_lock);
188075ab5f91Slh }
188175ab5f91Slh
188275ab5f91Slh kmem_free(pOdl, sizeof (struct odl));
188375ab5f91Slh kmem_free(pLayerPointers, sizeof (struct LayerPointers));
188475ab5f91Slh
188575ab5f91Slh return (DDI_SUCCESS);
188675ab5f91Slh }
188775ab5f91Slh
188875ab5f91Slh /*
188975ab5f91Slh * (GLD Entry Point)GLD will call this entry point perodicaly to
189075ab5f91Slh * get driver statistices.
189175ab5f91Slh */
189275ab5f91Slh static int
amd8111s_m_stat(void * arg,uint_t stat,uint64_t * val)189375ab5f91Slh amd8111s_m_stat(void *arg, uint_t stat, uint64_t *val)
189475ab5f91Slh {
189575ab5f91Slh struct LayerPointers *pLayerPointers = arg;
189675ab5f91Slh struct amd8111s_statistics *adapterStat;
189775ab5f91Slh
189875ab5f91Slh adapterStat = &pLayerPointers->pOdl->statistics;
189975ab5f91Slh
190075ab5f91Slh switch (stat) {
190175ab5f91Slh
190275ab5f91Slh /*
190375ab5f91Slh * Current Status
190475ab5f91Slh */
190575ab5f91Slh case MAC_STAT_IFSPEED:
1906*0f36d2f1SToomas Soome *val = pLayerPointers->pMdl->Speed * 1000000;
190775ab5f91Slh break;
190875ab5f91Slh
190975ab5f91Slh case ETHER_STAT_LINK_DUPLEX:
191075ab5f91Slh if (pLayerPointers->pMdl->FullDuplex) {
191175ab5f91Slh *val = LINK_DUPLEX_FULL;
191275ab5f91Slh } else {
191375ab5f91Slh *val = LINK_DUPLEX_HALF;
191475ab5f91Slh }
191575ab5f91Slh break;
191675ab5f91Slh
191775ab5f91Slh /*
191875ab5f91Slh * Capabilities
191975ab5f91Slh */
192075ab5f91Slh case ETHER_STAT_CAP_1000FDX:
192175ab5f91Slh *val = 0;
192275ab5f91Slh break;
192375ab5f91Slh
192475ab5f91Slh case ETHER_STAT_CAP_1000HDX:
192575ab5f91Slh *val = 0;
192675ab5f91Slh break;
192775ab5f91Slh
192875ab5f91Slh case ETHER_STAT_CAP_100FDX:
192975ab5f91Slh *val = 1;
193075ab5f91Slh break;
193175ab5f91Slh
193275ab5f91Slh case ETHER_STAT_CAP_100HDX:
193375ab5f91Slh *val = 1;
193475ab5f91Slh break;
193575ab5f91Slh
193675ab5f91Slh case ETHER_STAT_CAP_10FDX:
193775ab5f91Slh *val = 1;
193875ab5f91Slh break;
193975ab5f91Slh
194075ab5f91Slh case ETHER_STAT_CAP_10HDX:
194175ab5f91Slh *val = 1;
194275ab5f91Slh break;
194375ab5f91Slh
194475ab5f91Slh case ETHER_STAT_CAP_ASMPAUSE:
194575ab5f91Slh *val = 1;
194675ab5f91Slh break;
194775ab5f91Slh
194875ab5f91Slh case ETHER_STAT_CAP_PAUSE:
194975ab5f91Slh *val = 1;
195075ab5f91Slh break;
195175ab5f91Slh
195275ab5f91Slh case ETHER_STAT_CAP_AUTONEG:
195375ab5f91Slh *val = 1;
195475ab5f91Slh break;
195575ab5f91Slh
195675ab5f91Slh case ETHER_STAT_ADV_CAP_1000FDX:
195775ab5f91Slh *val = 0;
195875ab5f91Slh break;
195975ab5f91Slh
196075ab5f91Slh case ETHER_STAT_ADV_CAP_1000HDX:
196175ab5f91Slh *val = 0;
196275ab5f91Slh break;
196375ab5f91Slh
196475ab5f91Slh case ETHER_STAT_ADV_CAP_100FDX:
196575ab5f91Slh *val = 1;
196675ab5f91Slh break;
196775ab5f91Slh
196875ab5f91Slh case ETHER_STAT_ADV_CAP_100HDX:
196975ab5f91Slh *val = 1;
197075ab5f91Slh break;
197175ab5f91Slh
197275ab5f91Slh case ETHER_STAT_ADV_CAP_10FDX:
197375ab5f91Slh *val = 1;
197475ab5f91Slh break;
197575ab5f91Slh
197675ab5f91Slh case ETHER_STAT_ADV_CAP_10HDX:
197775ab5f91Slh *val = 1;
197875ab5f91Slh break;
197975ab5f91Slh
198075ab5f91Slh case ETHER_STAT_ADV_CAP_ASMPAUSE:
198175ab5f91Slh *val = 1;
198275ab5f91Slh break;
198375ab5f91Slh
198475ab5f91Slh case ETHER_STAT_ADV_CAP_PAUSE:
198575ab5f91Slh *val = 1;
198675ab5f91Slh break;
198775ab5f91Slh
198875ab5f91Slh case ETHER_STAT_ADV_CAP_AUTONEG:
198975ab5f91Slh *val = 1;
199075ab5f91Slh break;
199175ab5f91Slh
199275ab5f91Slh /*
199375ab5f91Slh * Rx Counters
199475ab5f91Slh */
199575ab5f91Slh case MAC_STAT_IPACKETS:
199675ab5f91Slh *val = adapterStat->rx_mib_unicst_packets +
199775ab5f91Slh adapterStat->rx_mib_multicst_packets +
199875ab5f91Slh adapterStat->rx_mib_broadcst_packets +
199975ab5f91Slh mdlReadMib(pLayerPointers, RcvUniCastPkts) +
200075ab5f91Slh mdlReadMib(pLayerPointers, RcvMultiCastPkts) +
200175ab5f91Slh mdlReadMib(pLayerPointers, RcvBroadCastPkts);
200275ab5f91Slh break;
200375ab5f91Slh
200475ab5f91Slh case MAC_STAT_RBYTES:
200575ab5f91Slh *val = adapterStat->rx_mib_bytes +
200675ab5f91Slh mdlReadMib(pLayerPointers, RcvOctets);
200775ab5f91Slh break;
200875ab5f91Slh
200975ab5f91Slh case MAC_STAT_MULTIRCV:
201075ab5f91Slh *val = adapterStat->rx_mib_multicst_packets +
201175ab5f91Slh mdlReadMib(pLayerPointers, RcvMultiCastPkts);
201275ab5f91Slh break;
201375ab5f91Slh
201475ab5f91Slh case MAC_STAT_BRDCSTRCV:
201575ab5f91Slh *val = adapterStat->rx_mib_broadcst_packets +
201675ab5f91Slh mdlReadMib(pLayerPointers, RcvBroadCastPkts);
201775ab5f91Slh break;
201875ab5f91Slh
201975ab5f91Slh case MAC_STAT_NORCVBUF:
202075ab5f91Slh *val = adapterStat->rx_allocfail +
202175ab5f91Slh adapterStat->rx_mib_drop_packets +
202275ab5f91Slh mdlReadMib(pLayerPointers, RcvDropPktsRing0);
202375ab5f91Slh break;
202475ab5f91Slh
202575ab5f91Slh case MAC_STAT_IERRORS:
202675ab5f91Slh *val = adapterStat->rx_mib_align_err_packets +
202775ab5f91Slh adapterStat->rx_mib_fcs_err_packets +
202875ab5f91Slh adapterStat->rx_mib_symbol_err_packets +
202975ab5f91Slh mdlReadMib(pLayerPointers, RcvAlignmentErrors) +
203075ab5f91Slh mdlReadMib(pLayerPointers, RcvFCSErrors) +
203175ab5f91Slh mdlReadMib(pLayerPointers, RcvSymbolErrors);
203275ab5f91Slh break;
203375ab5f91Slh
203475ab5f91Slh case ETHER_STAT_ALIGN_ERRORS:
203575ab5f91Slh *val = adapterStat->rx_mib_align_err_packets +
203675ab5f91Slh mdlReadMib(pLayerPointers, RcvAlignmentErrors);
203775ab5f91Slh break;
203875ab5f91Slh
203975ab5f91Slh case ETHER_STAT_FCS_ERRORS:
204075ab5f91Slh *val = adapterStat->rx_mib_fcs_err_packets +
204175ab5f91Slh mdlReadMib(pLayerPointers, RcvFCSErrors);
204275ab5f91Slh break;
204375ab5f91Slh
204475ab5f91Slh /*
204575ab5f91Slh * Tx Counters
204675ab5f91Slh */
204775ab5f91Slh case MAC_STAT_OPACKETS:
204875ab5f91Slh *val = adapterStat->tx_mib_packets +
204975ab5f91Slh mdlReadMib(pLayerPointers, XmtPackets);
205075ab5f91Slh break;
205175ab5f91Slh
205275ab5f91Slh case MAC_STAT_OBYTES:
205375ab5f91Slh *val = adapterStat->tx_mib_bytes +
205475ab5f91Slh mdlReadMib(pLayerPointers, XmtOctets);
205575ab5f91Slh break;
205675ab5f91Slh
205775ab5f91Slh case MAC_STAT_MULTIXMT:
205875ab5f91Slh *val = adapterStat->tx_mib_multicst_packets +
205975ab5f91Slh mdlReadMib(pLayerPointers, XmtMultiCastPkts);
206075ab5f91Slh break;
206175ab5f91Slh
206275ab5f91Slh case MAC_STAT_BRDCSTXMT:
206375ab5f91Slh *val = adapterStat->tx_mib_broadcst_packets +
206475ab5f91Slh mdlReadMib(pLayerPointers, XmtBroadCastPkts);
206575ab5f91Slh break;
206675ab5f91Slh
206775ab5f91Slh case MAC_STAT_NOXMTBUF:
206875ab5f91Slh *val = adapterStat->tx_no_descriptor;
206975ab5f91Slh break;
207075ab5f91Slh
207175ab5f91Slh case MAC_STAT_OERRORS:
207275ab5f91Slh *val = adapterStat->tx_mib_ex_coll_packets +
207375ab5f91Slh mdlReadMib(pLayerPointers, XmtExcessiveCollision);
207475ab5f91Slh break;
207575ab5f91Slh
207675ab5f91Slh case MAC_STAT_COLLISIONS:
207775ab5f91Slh *val = adapterStat->tx_mib_ex_coll_packets +
207875ab5f91Slh mdlReadMib(pLayerPointers, XmtCollisions);
207975ab5f91Slh break;
208075ab5f91Slh
208175ab5f91Slh case ETHER_STAT_FIRST_COLLISIONS:
208275ab5f91Slh *val = adapterStat->tx_mib_one_coll_packets +
208375ab5f91Slh mdlReadMib(pLayerPointers, XmtOneCollision);
208475ab5f91Slh break;
208575ab5f91Slh
208675ab5f91Slh case ETHER_STAT_MULTI_COLLISIONS:
208775ab5f91Slh *val = adapterStat->tx_mib_multi_coll_packets +
208875ab5f91Slh mdlReadMib(pLayerPointers, XmtMultipleCollision);
208975ab5f91Slh break;
209075ab5f91Slh
209175ab5f91Slh case ETHER_STAT_EX_COLLISIONS:
209275ab5f91Slh *val = adapterStat->tx_mib_ex_coll_packets +
209375ab5f91Slh mdlReadMib(pLayerPointers, XmtExcessiveCollision);
209475ab5f91Slh break;
209575ab5f91Slh
209675ab5f91Slh case ETHER_STAT_TX_LATE_COLLISIONS:
209775ab5f91Slh *val = adapterStat->tx_mib_late_coll_packets +
209875ab5f91Slh mdlReadMib(pLayerPointers, XmtLateCollision);
209975ab5f91Slh break;
210075ab5f91Slh
210175ab5f91Slh case ETHER_STAT_DEFER_XMTS:
210275ab5f91Slh *val = adapterStat->tx_mib_defer_trans_packets +
210375ab5f91Slh mdlReadMib(pLayerPointers, XmtDeferredTransmit);
210475ab5f91Slh break;
210575ab5f91Slh
210675ab5f91Slh default:
210775ab5f91Slh return (ENOTSUP);
210875ab5f91Slh }
210975ab5f91Slh return (0);
211075ab5f91Slh }
211175ab5f91Slh
211275ab5f91Slh /*
211375ab5f91Slh * Memory Read Function Used by MDL to set card registers.
211475ab5f91Slh */
211575ab5f91Slh unsigned char
READ_REG8(struct LayerPointers * pLayerPointers,long x)211675ab5f91Slh READ_REG8(struct LayerPointers *pLayerPointers, long x)
211775ab5f91Slh {
211875ab5f91Slh return (ddi_get8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)x));
211975ab5f91Slh }
212075ab5f91Slh
212175ab5f91Slh int
READ_REG16(struct LayerPointers * pLayerPointers,long x)212275ab5f91Slh READ_REG16(struct LayerPointers *pLayerPointers, long x)
212375ab5f91Slh {
212475ab5f91Slh return (ddi_get16(pLayerPointers->pOdl->MemBasehandle,
212575ab5f91Slh (uint16_t *)(x)));
212675ab5f91Slh }
212775ab5f91Slh
212875ab5f91Slh long
READ_REG32(struct LayerPointers * pLayerPointers,long x)212975ab5f91Slh READ_REG32(struct LayerPointers *pLayerPointers, long x)
213075ab5f91Slh {
213175ab5f91Slh return (ddi_get32(pLayerPointers->pOdl->MemBasehandle,
213275ab5f91Slh (uint32_t *)(x)));
213375ab5f91Slh }
213475ab5f91Slh
213575ab5f91Slh void
WRITE_REG8(struct LayerPointers * pLayerPointers,long x,int y)213675ab5f91Slh WRITE_REG8(struct LayerPointers *pLayerPointers, long x, int y)
213775ab5f91Slh {
213875ab5f91Slh ddi_put8(pLayerPointers->pOdl->MemBasehandle, (uint8_t *)(x), y);
213975ab5f91Slh }
214075ab5f91Slh
214175ab5f91Slh void
WRITE_REG16(struct LayerPointers * pLayerPointers,long x,int y)214275ab5f91Slh WRITE_REG16(struct LayerPointers *pLayerPointers, long x, int y)
214375ab5f91Slh {
214475ab5f91Slh ddi_put16(pLayerPointers->pOdl->MemBasehandle, (uint16_t *)(x), y);
214575ab5f91Slh }
214675ab5f91Slh
214775ab5f91Slh void
WRITE_REG32(struct LayerPointers * pLayerPointers,long x,int y)214875ab5f91Slh WRITE_REG32(struct LayerPointers *pLayerPointers, long x, int y)
214975ab5f91Slh {
215075ab5f91Slh ddi_put32(pLayerPointers->pOdl->MemBasehandle, (uint32_t *)(x), y);
215175ab5f91Slh }
215275ab5f91Slh
215375ab5f91Slh void
WRITE_REG64(struct LayerPointers * pLayerPointers,long x,char * y)215475ab5f91Slh WRITE_REG64(struct LayerPointers *pLayerPointers, long x, char *y)
215575ab5f91Slh {
215675ab5f91Slh int i;
215775ab5f91Slh for (i = 0; i < 8; i++) {
215875ab5f91Slh WRITE_REG8(pLayerPointers, (x + i), y[i]);
215975ab5f91Slh }
216075ab5f91Slh }
2161