1*75ab5f91Slh /* 2*75ab5f91Slh * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3*75ab5f91Slh * Use is subject to license terms. 4*75ab5f91Slh */ 5*75ab5f91Slh 6*75ab5f91Slh #ifndef AMD8111S_HW_H 7*75ab5f91Slh #define AMD8111S_HW_H 8*75ab5f91Slh 9*75ab5f91Slh /* 10*75ab5f91Slh * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 11*75ab5f91Slh * 12*75ab5f91Slh * Redistribution and use in source and binary forms, with or without 13*75ab5f91Slh * modification, are permitted provided that the following conditions are met: 14*75ab5f91Slh * 15*75ab5f91Slh * + Redistributions of source code must retain the above copyright notice, 16*75ab5f91Slh * + this list of conditions and the following disclaimer. 17*75ab5f91Slh * 18*75ab5f91Slh * + Redistributions in binary form must reproduce the above copyright 19*75ab5f91Slh * + notice, this list of conditions and the following disclaimer in the 20*75ab5f91Slh * + documentation and/or other materials provided with the distribution. 21*75ab5f91Slh * 22*75ab5f91Slh * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 23*75ab5f91Slh * + contributors may be used to endorse or promote products derived from 24*75ab5f91Slh * + this software without specific prior written permission. 25*75ab5f91Slh * 26*75ab5f91Slh * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 27*75ab5f91Slh * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 28*75ab5f91Slh * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29*75ab5f91Slh * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 30*75ab5f91Slh * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 31*75ab5f91Slh * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32*75ab5f91Slh * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33*75ab5f91Slh * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34*75ab5f91Slh * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35*75ab5f91Slh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36*75ab5f91Slh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 37*75ab5f91Slh * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 38*75ab5f91Slh * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39*75ab5f91Slh * 40*75ab5f91Slh * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 41*75ab5f91Slh * Compliance with Applicable Laws. Notice is hereby given that 42*75ab5f91Slh * the software may be subject to restrictions on use, release, 43*75ab5f91Slh * transfer, importation, exportation and/or re-exportation under 44*75ab5f91Slh * the laws and regulations of the United States or other 45*75ab5f91Slh * countries ("Applicable Laws"), which include but are not 46*75ab5f91Slh * limited to U.S. export control laws such as the Export 47*75ab5f91Slh * Administration Regulations and national security controls as 48*75ab5f91Slh * defined thereunder, as well as State Department controls under 49*75ab5f91Slh * the U.S. Munitions List. Permission to use and/or 50*75ab5f91Slh * redistribute the software is conditioned upon compliance with 51*75ab5f91Slh * all Applicable Laws, including U.S. export control laws 52*75ab5f91Slh * regarding specifically designated persons, countries and 53*75ab5f91Slh * nationals of countries subject to national security controls. 54*75ab5f91Slh */ 55*75ab5f91Slh 56*75ab5f91Slh 57*75ab5f91Slh /* Definitions for the type of Memory allocations needed */ 58*75ab5f91Slh 59*75ab5f91Slh #define ETH_LENGTH_OF_ADDRESS 6 60*75ab5f91Slh #define ETH_MAC_HDR_SIZE 14 61*75ab5f91Slh 62*75ab5f91Slh 63*75ab5f91Slh #define ADD_MULTICAST 1 64*75ab5f91Slh 65*75ab5f91Slh #define ENABLE_MULTICAST 2 66*75ab5f91Slh #define DISABLE_MULTICAST 3 67*75ab5f91Slh 68*75ab5f91Slh #define ENABLE_ALL_MULTICAST 4 69*75ab5f91Slh #define DISABLE_ALL_MULTICAST 5 70*75ab5f91Slh 71*75ab5f91Slh #define ENABLE_BROADCAST 6 72*75ab5f91Slh #define DISABLE_BROADCAST 7 73*75ab5f91Slh 74*75ab5f91Slh #define ADD_WAKE_UP_PATTERN 8 75*75ab5f91Slh #define REMOVE_WAKE_UP_PATTERN 9 76*75ab5f91Slh #define ENABLE_MAGIC_PACKET_WAKE_UP 10 77*75ab5f91Slh 78*75ab5f91Slh #define SET_SINGLE_MULTICAST 11 79*75ab5f91Slh #define UNSET_SINGLE_MULTICAST 12 80*75ab5f91Slh #define DELETE_MULTICAST 13 81*75ab5f91Slh 82*75ab5f91Slh #define LINK_DOWN 1 83*75ab5f91Slh #define LINK_UP 2 84*75ab5f91Slh #define LINK_UNKNOWN 3 85*75ab5f91Slh 86*75ab5f91Slh /* Setting the MODE */ 87*75ab5f91Slh #define PROMISCOUS 1 88*75ab5f91Slh #define DISABLE_PROM 2 89*75ab5f91Slh 90*75ab5f91Slh #define VIRTUAL 1 91*75ab5f91Slh 92*75ab5f91Slh #define ALIGNMENT 0x0f 93*75ab5f91Slh 94*75ab5f91Slh #define TX_RING_LEN_BITS 10 /* 1024 descriptors */ 95*75ab5f91Slh #define RX_RING_LEN_BITS 10 /* 1024 descriptors */ 96*75ab5f91Slh #define TX_BUF_SIZE 2048 97*75ab5f91Slh #define RX_BUF_SIZE 2048 98*75ab5f91Slh 99*75ab5f91Slh #define TX_RING_SIZE (1 << (TX_RING_LEN_BITS)) 100*75ab5f91Slh #define TX_COALESC_SIZE (1 << 11) 101*75ab5f91Slh #define TX_RING_MOD_MASK (2 * TX_RING_SIZE - 1) 102*75ab5f91Slh 103*75ab5f91Slh #define TX_RESCHEDULE_THRESHOLD (TX_RING_SIZE >> 1) 104*75ab5f91Slh 105*75ab5f91Slh #define RX_RING_SIZE (1 << (RX_RING_LEN_BITS)) 106*75ab5f91Slh #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 107*75ab5f91Slh 108*75ab5f91Slh #define MAX_MULTICAST_ADDRESSES 32 109*75ab5f91Slh #define JUMBO_ENABLED 0 110*75ab5f91Slh #define JUMBO_DISABLED 1 111*75ab5f91Slh 112*75ab5f91Slh /* Default value of IPG convergence time */ 113*75ab5f91Slh #define MIN_IPG_DEFAULT 96 114*75ab5f91Slh #define MAX_IPG_DEFAULT 255 115*75ab5f91Slh #define MAX_BUFFER_COUNT 8 /* full coalesce */ 116*75ab5f91Slh 117*75ab5f91Slh #define ULONG unsigned long 118*75ab5f91Slh #define UCHAR unsigned char 119*75ab5f91Slh 120*75ab5f91Slh /* Generic MII registers. */ 121*75ab5f91Slh #define MII_BMCR 0x00 /* Basic mode control register */ 122*75ab5f91Slh #define MII_BMSR 0x01 /* Basic mode status register */ 123*75ab5f91Slh #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 124*75ab5f91Slh #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 125*75ab5f91Slh #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 126*75ab5f91Slh #define MII_LPA 0x05 /* Link partner ability reg */ 127*75ab5f91Slh #define MII_EXPANSION 0x06 /* Expansion register */ 128*75ab5f91Slh #define MII_DCOUNTER 0x12 /* Disconnect counter */ 129*75ab5f91Slh #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 130*75ab5f91Slh #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 131*75ab5f91Slh #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 132*75ab5f91Slh #define MII_SREVISION 0x16 /* Silicon revision */ 133*75ab5f91Slh #define MII_RESV1 0x17 /* Reserved... */ 134*75ab5f91Slh #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 135*75ab5f91Slh #define MII_PHYADDR 0x19 /* PHY address */ 136*75ab5f91Slh #define MII_RESV2 0x1a /* Reserved... */ 137*75ab5f91Slh #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 138*75ab5f91Slh #define MII_NCONFIG 0x1c /* Network interface config */ 139*75ab5f91Slh 140*75ab5f91Slh 141*75ab5f91Slh #define DEVICE_ID 0x744b 142*75ab5f91Slh #define VENDOR_ID 0x1022 143*75ab5f91Slh 144*75ab5f91Slh /* L4 Chip Name */ 145*75ab5f91Slh #define DEVICE_CHIPNAME "Memory_Map_L7 AMDIDC" 146*75ab5f91Slh 147*75ab5f91Slh /* Error Status Registers */ 148*75ab5f91Slh #define MIB_OFFSET 0x28 149*75ab5f91Slh 150*75ab5f91Slh /* 151*75ab5f91Slh * MIB counter definitions 152*75ab5f91Slh */ 153*75ab5f91Slh #define RcvMissPkts 0x00 154*75ab5f91Slh #define RcvOctets 0x01 155*75ab5f91Slh #define RcvBroadCastPkts 0x02 156*75ab5f91Slh #define RcvMultiCastPkts 0x03 157*75ab5f91Slh #define RcvUndersizePkts 0x04 158*75ab5f91Slh #define RcvOversizePkts 0x05 159*75ab5f91Slh #define RcvFragments 0x06 160*75ab5f91Slh #define RcvJabbers 0x07 161*75ab5f91Slh #define RcvUniCastPkts 0x08 162*75ab5f91Slh #define RcvAlignmentErrors 0x09 163*75ab5f91Slh #define RcvFCSErrors 0x0a 164*75ab5f91Slh #define RcvGoodOctets 0x0b 165*75ab5f91Slh #define RcvMACCtrl 0x0c 166*75ab5f91Slh #define RcvFlowCtrl 0x0d 167*75ab5f91Slh #define RcvPkts64Octets 0x0e 168*75ab5f91Slh #define RcvPkts65to127Octets 0x0f 169*75ab5f91Slh #define RcvPkts128to255Octets 0x10 170*75ab5f91Slh #define RcvPkts256to511Octets 0x11 171*75ab5f91Slh #define RcvPkts512to1023Octets 0x12 172*75ab5f91Slh #define RcvPkts1024to1518Octets 0x13 173*75ab5f91Slh #define RcvUnsupportedOpcode 0x14 174*75ab5f91Slh #define RcvSymbolErrors 0x15 175*75ab5f91Slh #define RcvDropPktsRing0 0x16 176*75ab5f91Slh 177*75ab5f91Slh #define XmtUnderrunPkts 0x20 178*75ab5f91Slh #define XmtOctets 0x21 179*75ab5f91Slh #define XmtPackets 0x22 180*75ab5f91Slh #define XmtBroadCastPkts 0x23 181*75ab5f91Slh #define XmtMultiCastPkts 0x24 182*75ab5f91Slh #define XmtCollisions 0x25 183*75ab5f91Slh #define XmtUniCastPkts 0x26 184*75ab5f91Slh #define XmtOneCollision 0x27 185*75ab5f91Slh #define XmtMultipleCollision 0x28 186*75ab5f91Slh #define XmtDeferredTransmit 0x29 187*75ab5f91Slh #define XmtLateCollision 0x2a 188*75ab5f91Slh #define XmtExcessiveDefer 0x2b 189*75ab5f91Slh #define XmtLossCarrier 0x2c 190*75ab5f91Slh #define XmtExcessiveCollision 0x2d 191*75ab5f91Slh #define XmtBackPressure 0x2e 192*75ab5f91Slh #define XmtFlowCtrl 0x2f 193*75ab5f91Slh #define XmtPkts64Octets 0x30 194*75ab5f91Slh #define XmtPkts65to127Octets 0x31 195*75ab5f91Slh #define XmtPkts128to255Octets 0x32 196*75ab5f91Slh #define XmtPkts256to511Octets 0x33 197*75ab5f91Slh #define XmtPkts512to1023Octets 0x34 198*75ab5f91Slh #define XmtPkts1024to1518Octets 0x35 199*75ab5f91Slh #define XmtOversizePkts 0x36 200*75ab5f91Slh 201*75ab5f91Slh /* Link Status */ 202*75ab5f91Slh #define SPEED_MASK 0x0380 /* B9 .. B7 */ 203*75ab5f91Slh #define SPEED_100Mbps 0x0180 204*75ab5f91Slh #define SPEED_10Mbps 0x0100 205*75ab5f91Slh 206*75ab5f91Slh 207*75ab5f91Slh /* PMR (Pattern Match RAM) */ 208*75ab5f91Slh #define MAX_ALLOWED_PATTERNS 8 209*75ab5f91Slh #define MAX_PATTERNS 1024 210*75ab5f91Slh #define ALL_MULTI B16_MASK 211*75ab5f91Slh #define ONLY_MULTI B15_MASK 212*75ab5f91Slh 213*75ab5f91Slh #define B31_MASK 0x80000000 214*75ab5f91Slh #define B30_MASK 0x40000000 215*75ab5f91Slh #define B29_MASK 0x20000000 216*75ab5f91Slh #define B28_MASK 0x10000000 217*75ab5f91Slh #define B27_MASK 0x08000000 218*75ab5f91Slh #define B26_MASK 0x04000000 219*75ab5f91Slh #define B25_MASK 0x02000000 220*75ab5f91Slh #define B24_MASK 0x01000000 221*75ab5f91Slh #define B23_MASK 0x00800000 222*75ab5f91Slh #define B22_MASK 0x00400000 223*75ab5f91Slh #define B21_MASK 0x00200000 224*75ab5f91Slh #define B20_MASK 0x00100000 225*75ab5f91Slh #define B19_MASK 0x00080000 226*75ab5f91Slh #define B18_MASK 0x00040000 227*75ab5f91Slh #define B17_MASK 0x00020000 228*75ab5f91Slh #define B16_MASK 0x00010000 229*75ab5f91Slh 230*75ab5f91Slh #define B15_MASK 0x8000 231*75ab5f91Slh #define B14_MASK 0x4000 232*75ab5f91Slh #define B13_MASK 0x2000 233*75ab5f91Slh #define B12_MASK 0x1000 234*75ab5f91Slh #define B11_MASK 0x0800 235*75ab5f91Slh #define B10_MASK 0x0400 236*75ab5f91Slh #define B9_MASK 0x0200 237*75ab5f91Slh #define B8_MASK 0x0100 238*75ab5f91Slh #define B7_MASK 0x0080 239*75ab5f91Slh #define B6_MASK 0x0040 240*75ab5f91Slh #define B5_MASK 0x0020 241*75ab5f91Slh #define B4_MASK 0x0010 242*75ab5f91Slh #define B3_MASK 0x0008 243*75ab5f91Slh #define B2_MASK 0x0004 244*75ab5f91Slh #define B1_MASK 0x0002 245*75ab5f91Slh #define B0_MASK 0x0001 246*75ab5f91Slh 247*75ab5f91Slh /* PCI register offset */ 248*75ab5f91Slh /* required by odl in getting the Memory Base Address */ 249*75ab5f91Slh #define MEMBASE_MASK 0xFFFFF000 250*75ab5f91Slh #define PCI_CAP_ID_REG_OFFSET 0x34 251*75ab5f91Slh #define PCI_PMC_REG_OFFSET 0x36 252*75ab5f91Slh #define PCI_PMCSR_REG_OFFSET 0x38 253*75ab5f91Slh #define MIB_OFFSET 0x28 254*75ab5f91Slh #define STAT_ASF 0x00 /* 32bit register */ 255*75ab5f91Slh 256*75ab5f91Slh #define FORCED_PHY_MASK 0xFF07 257*75ab5f91Slh 258*75ab5f91Slh /* Offset of Drifrent Registers */ 259*75ab5f91Slh #define AP_VALUE 0x98 /* 32bit register */ 260*75ab5f91Slh #define AUTOPOLL0 0x88 /* 16bit register */ 261*75ab5f91Slh #define AUTOPOLL1 0x8A /* 16bit register */ 262*75ab5f91Slh #define AUTOPOLL2 0x8C /* 16bit register */ 263*75ab5f91Slh #define AUTOPOLL3 0x8E /* 16bit register */ 264*75ab5f91Slh #define AUTOPOLL4 0x90 /* 16bit register */ 265*75ab5f91Slh #define AUTOPOLL5 0x92 /* 16bit register */ 266*75ab5f91Slh /* Receive Ring Base Address Registers . */ 267*75ab5f91Slh #define RCV_RING_BASE_ADDR0 0x120 /* 64bit register */ 268*75ab5f91Slh /* Transmit Ring Base Address */ 269*75ab5f91Slh #define XMT_RING_BASE_ADDR0 0x100 /* 64bit register */ 270*75ab5f91Slh #define XMT_RING_BASE_ADDR1 0x108 /* 64bit register */ 271*75ab5f91Slh #define XMT_RING_BASE_ADDR2 0x110 /* 64bit register */ 272*75ab5f91Slh #define XMT_RING_BASE_ADDR3 0x118 /* 64bit register */ 273*75ab5f91Slh /* CAM ADDRESS */ 274*75ab5f91Slh #define CAM_ADDR 0x1A0 /* 16bit register */ 275*75ab5f91Slh #define CAM_DATA 0x198 /* 64bit register */ 276*75ab5f91Slh /* CHIP ID */ 277*75ab5f91Slh #define CHIPID 0x004 /* 32bit register */ 278*75ab5f91Slh /* COMMAND STYLE REGISTERS */ 279*75ab5f91Slh #define CMD0 0x48 /* 32bit register */ 280*75ab5f91Slh #define CMD2 0x50 /* 32bit register */ 281*75ab5f91Slh #define CMD3 0x54 /* 32bit register */ 282*75ab5f91Slh #define CMD7 0x64 /* 32bit register */ 283*75ab5f91Slh /* CONTRIOL REGISTER */ 284*75ab5f91Slh #define CTRL1 0x6C /* 32bit register */ 285*75ab5f91Slh #define CTRL2 0x70 /* 32bit register */ 286*75ab5f91Slh /* DELAY INTERRUPT REGISTER */ 287*75ab5f91Slh #define DLY_INT_A 0xA8 /* 32bit register */ 288*75ab5f91Slh #define DLY_INT_B 0xAC /* 32bit register */ 289*75ab5f91Slh /* FLOW CONTROL REGISTER */ 290*75ab5f91Slh #define FLOW_CONTROL 0xC8 /* 32bit register */ 291*75ab5f91Slh /* INTER FRAME SPACING */ 292*75ab5f91Slh #define IFS 0x18E /* 16bit register */ 293*75ab5f91Slh #define IFS1 0x18C /* 8bit register */ 294*75ab5f91Slh /* INTERRUPT REGISTER */ 295*75ab5f91Slh #define INT0 0x38 /* 32bit register */ 296*75ab5f91Slh #define INTEN0 0x40 /* 32bit register */ 297*75ab5f91Slh /* LOGICAL ADDRESS */ 298*75ab5f91Slh #define LADRF1 0x168 /* 64bit register */ 299*75ab5f91Slh /* MIB ADDRESS REGISTER */ 300*75ab5f91Slh #define MIB_ADDR 0x14 /* 16bit register */ 301*75ab5f91Slh #define MIB_DATA 0x10 /* 32bit register */ 302*75ab5f91Slh /* MAC ADDRESS */ 303*75ab5f91Slh #define PADR 0x160 /* 48bit register */ 304*75ab5f91Slh /* PHY ADDRESS */ 305*75ab5f91Slh #define PHY_ACCESS 0xD0 /* 32bit register */ 306*75ab5f91Slh /* PATTERN REGISTER */ 307*75ab5f91Slh #define PMAT0 0x190 /* 32bit register */ 308*75ab5f91Slh #define PMAT1 0x194 /* 32bit register */ 309*75ab5f91Slh /* RECEIVE RING LENGTH OFFSET */ 310*75ab5f91Slh #define RCV_RING_LEN0 0x150 /* 16bit register */ 311*75ab5f91Slh /* SRAM BOUNDARY */ 312*75ab5f91Slh #define SRAM_BOUNDARY 0x17A /* 16bit register */ 313*75ab5f91Slh #define SRAM_SIZE 0x178 /* 16bit register */ 314*75ab5f91Slh /* STATUS REGISTER */ 315*75ab5f91Slh #define STAT0 0x30 /* 32bit register */ 316*75ab5f91Slh #define STVAL 0xD8 /* 32bit register */ 317*75ab5f91Slh #define TEST0 0x1A8 /* 32bit register */ 318*75ab5f91Slh #define XMT_RING_LEN0 0x140 /* 16bit register */ 319*75ab5f91Slh #define XMT_RING_LEN1 0x144 /* 16bit register */ 320*75ab5f91Slh #define XMT_RING_LEN2 0x148 /* 16bit register */ 321*75ab5f91Slh #define XMT_RING_LEN3 0x14C /* 16bit register */ 322*75ab5f91Slh #define XMT_RING_LIMIT 0x7C /* 32bit register */ 323*75ab5f91Slh 324*75ab5f91Slh 325*75ab5f91Slh 326*75ab5f91Slh #define RCV_RING_LEN1 0x154 /* 16bit register */ 327*75ab5f91Slh #define RCV_RING_LEN2 0x158 /* 16bit register */ 328*75ab5f91Slh #define RCV_RING_LEN3 0x15C /* 16bit register */ 329*75ab5f91Slh #define FFC_THRESH 0xCC /* 32bit register */ 330*75ab5f91Slh #define RCV_RING_BASE_ADDR1 0x128 /* 64bit register */ 331*75ab5f91Slh #define RCV_RING_BASE_ADDR2 0x130 /* 64bit register */ 332*75ab5f91Slh #define RCV_RING_BASE_ADDR3 0x138 /* 64bit register */ 333*75ab5f91Slh #define RCV_RING_CFG 0x78 /* 16bit register */ 334*75ab5f91Slh #define PCS_ANEG 0x9C /* 32bit register */ 335*75ab5f91Slh #define PCS_RCFG 0xA0 /* 32bit register */ 336*75ab5f91Slh #define PCS_XCFG 0xA4 /* 32bit register */ 337*75ab5f91Slh #define DFC_INDEX2 0xB8 /* 16bit register */ 338*75ab5f91Slh #define DFC_INDEX3 0xBA /* 16bit register */ 339*75ab5f91Slh #define DFC_INDEX0 0xBC /* 16bit register */ 340*75ab5f91Slh #define DFC_INDEX1 0xBE /* 16bit register */ 341*75ab5f91Slh #define DFC_THRESH2 0xC0 /* 16bit register */ 342*75ab5f91Slh #define DFC_THRESH3 0xC2 /* 16bit register */ 343*75ab5f91Slh #define DFC_THRESH0 0xC4 /* 16bit register */ 344*75ab5f91Slh #define DFC_THRESH1 0xC6 /* 16bit register */ 345*75ab5f91Slh #define PAUSE_CNT 0xDE /* 32bit register */ 346*75ab5f91Slh #define LED0 0xE0 /* 16bit register */ 347*75ab5f91Slh #define LED1 0xE2 /* 16bit register */ 348*75ab5f91Slh #define LED2 0xE4 /* 16bit register */ 349*75ab5f91Slh #define LED3 0xE6 /* 16bit register */ 350*75ab5f91Slh 351*75ab5f91Slh 352*75ab5f91Slh #define EEPROM_ACC 0x17C /* 16bit register */ 353*75ab5f91Slh 354*75ab5f91Slh 355*75ab5f91Slh /* Register Bit Definitions */ 356*75ab5f91Slh /* STAT_ASF 0x00, 32bit register */ 357*75ab5f91Slh #define ASF_INIT_DONE B1_MASK 358*75ab5f91Slh #define ASF_INIT_PRESENT B0_MASK 359*75ab5f91Slh 360*75ab5f91Slh /* MIB_ADDR 0x14, 16bit register */ 361*75ab5f91Slh #define MIB_CMD_ACTIVE B15_MASK 362*75ab5f91Slh #define MIB_RD_CMD B13_MASK 363*75ab5f91Slh #define MIB_CLEAR B12_MASK 364*75ab5f91Slh #define MIB_ADDRESS 0x0000003F /* 5:0 */ 365*75ab5f91Slh 366*75ab5f91Slh /* QOS_ADDR 0x1C, 16bit register */ 367*75ab5f91Slh #define QOS_CMD_ACTIVE B15_MASK 368*75ab5f91Slh #define QOS_WR_CMD B14_MASK 369*75ab5f91Slh #define QOS_RD_CMD B13_MASK 370*75ab5f91Slh #define QOS_ADDRESS 0x0000001F /* 4:0 */ 371*75ab5f91Slh 372*75ab5f91Slh /* STAT0 0x30, 32bit register */ 373*75ab5f91Slh #define PAUSE_PEND B14_MASK 374*75ab5f91Slh #define PAUSING B13_MASK 375*75ab5f91Slh #define PMAT_DET B12_MASK 376*75ab5f91Slh #define MP_DET B11_MASK 377*75ab5f91Slh #define LC_DET B10_MASK 378*75ab5f91Slh #define SPEED_MASK 0x0380 /* 9:7 */ 379*75ab5f91Slh #define FULL_DPLX B6_MASK 380*75ab5f91Slh #define LINK_STAT B5_MASK 381*75ab5f91Slh #define AUTONEG_COMPLETE B4_MASK 382*75ab5f91Slh /* #define MIIPD B3_MASK */ 383*75ab5f91Slh #define RX_SUSPENDED B2_MASK 384*75ab5f91Slh #define TX_SUSPENDED B1_MASK 385*75ab5f91Slh #define RUNNING B0_MASK 386*75ab5f91Slh 387*75ab5f91Slh 388*75ab5f91Slh /* INTEN0 0x40, 32bit register */ 389*75ab5f91Slh 390*75ab5f91Slh #define VAL3 B31_MASK 391*75ab5f91Slh #define VAL2 B23_MASK 392*75ab5f91Slh #define VAL1 B15_MASK 393*75ab5f91Slh #define VAL0 B7_MASK 394*75ab5f91Slh 395*75ab5f91Slh /* VAL3 */ 396*75ab5f91Slh #define PSCINTEN B28_MASK 397*75ab5f91Slh #define LCINTEN B27_MASK 398*75ab5f91Slh #define APINT5EN B26_MASK 399*75ab5f91Slh #define APINT4EN B25_MASK 400*75ab5f91Slh #define APINT3EN B24_MASK 401*75ab5f91Slh 402*75ab5f91Slh /* VAL2 */ 403*75ab5f91Slh #define APINT2EN B22_MASK 404*75ab5f91Slh #define APINT1EN B21_MASK 405*75ab5f91Slh #define APINT0EN B20_MASK 406*75ab5f91Slh #define MIIPDTINTEN B19_MASK 407*75ab5f91Slh #define MCCIINTEN B18_MASK 408*75ab5f91Slh #define MCCINTEN B17_MASK 409*75ab5f91Slh #define MREINTEN B16_MASK 410*75ab5f91Slh 411*75ab5f91Slh /* VAL1 */ 412*75ab5f91Slh #define SPNDINTEN B14_MASK 413*75ab5f91Slh #define MPINTEN B13_MASK 414*75ab5f91Slh #define SINTEN B12_MASK 415*75ab5f91Slh #define TINTEN3 B11_MASK 416*75ab5f91Slh #define TINTEN2 B10_MASK 417*75ab5f91Slh #define TINTEN1 B9_MASK 418*75ab5f91Slh #define TINTEN0 B8_MASK 419*75ab5f91Slh 420*75ab5f91Slh /* VAL0 */ 421*75ab5f91Slh #define STINTEN B4_MASK 422*75ab5f91Slh #define RINTEN3 B3_MASK 423*75ab5f91Slh #define RINTEN2 B2_MASK 424*75ab5f91Slh #define RINTEN1 B1_MASK 425*75ab5f91Slh #define RINTEN0 B0_MASK 426*75ab5f91Slh 427*75ab5f91Slh /* CMD0 0x48, 32bit register */ 428*75ab5f91Slh /* VAL2 */ 429*75ab5f91Slh #define RDMD3 B19_MASK 430*75ab5f91Slh #define RDMD2 B18_MASK 431*75ab5f91Slh #define RDMD1 B17_MASK 432*75ab5f91Slh #define RDMD0 B16_MASK 433*75ab5f91Slh 434*75ab5f91Slh /* VAL1 */ 435*75ab5f91Slh #define TDMD3 B11_MASK 436*75ab5f91Slh #define TDMD2 B10_MASK 437*75ab5f91Slh #define TDMD1 B9_MASK 438*75ab5f91Slh #define TDMD0 B8_MASK 439*75ab5f91Slh 440*75ab5f91Slh /* VAL0 */ 441*75ab5f91Slh #define UINTCMD B6_MASK 442*75ab5f91Slh #define RX_FAST_SPND B5_MASK 443*75ab5f91Slh #define TX_FAST_SPND B4_MASK 444*75ab5f91Slh #define RX_SPND B3_MASK 445*75ab5f91Slh #define TX_SPND B2_MASK 446*75ab5f91Slh #define INTREN B1_MASK 447*75ab5f91Slh #define RUN B0_MASK 448*75ab5f91Slh 449*75ab5f91Slh /* CMD2 0x50, 32bit register */ 450*75ab5f91Slh /* VAL3 */ 451*75ab5f91Slh #define CONDUIT_MODE B29_MASK 452*75ab5f91Slh #define PREF_QTAG B28_MASK 453*75ab5f91Slh #define ALT_PRI_OK B27_MASK 454*75ab5f91Slh 455*75ab5f91Slh /* VAL2 */ 456*75ab5f91Slh #define CAM_ENABLE B22_MASK 457*75ab5f91Slh #define QOS_ENABLE B21_MASK 458*75ab5f91Slh #define HASH_ENABLE B20_MASK 459*75ab5f91Slh #define RPA B19_MASK 460*75ab5f91Slh #define DRCVPA B18_MASK 461*75ab5f91Slh #define DRCVBC B17_MASK 462*75ab5f91Slh #define PROM B16_MASK 463*75ab5f91Slh 464*75ab5f91Slh /* VAL1 */ 465*75ab5f91Slh #define ASTRIP_RCV B13_MASK 466*75ab5f91Slh #define CMD2_RCV_DROP0 B12_MASK 467*75ab5f91Slh #define EMBA B11_MASK 468*75ab5f91Slh #define DXMT2PD B10_MASK 469*75ab5f91Slh #define LTINTEN B9_MASK 470*75ab5f91Slh #define DXMTFCS B8_MASK 471*75ab5f91Slh 472*75ab5f91Slh /* VAL0 */ 473*75ab5f91Slh #define APAD_XMT B6_MASK 474*75ab5f91Slh #define DRTY B5_MASK 475*75ab5f91Slh #define INLOOP B4_MASK 476*75ab5f91Slh #define EXLOOP B3_MASK 477*75ab5f91Slh #define REX_RTRY B2_MASK 478*75ab5f91Slh #define REX_UFLO B1_MASK 479*75ab5f91Slh #define REX_LCOL B0_MASK 480*75ab5f91Slh 481*75ab5f91Slh /* CMD3 0x54, 32bit register */ 482*75ab5f91Slh 483*75ab5f91Slh /* VAL3 */ 484*75ab5f91Slh #define ASF_INIT_DONE_ALIAS B29_MASK 485*75ab5f91Slh 486*75ab5f91Slh /* VAL2 */ 487*75ab5f91Slh #define JUMBO B21_MASK 488*75ab5f91Slh #define VSIZE B20_MASK 489*75ab5f91Slh #define VLONLY B19_MASK 490*75ab5f91Slh #define VL_TAG_DEL B18_MASK 491*75ab5f91Slh 492*75ab5f91Slh /* VAL1 */ 493*75ab5f91Slh #define EN_PMGR B14_MASK 494*75ab5f91Slh #define INTLEVEL B13_MASK 495*75ab5f91Slh #define FORCE_FULL_DUPLEX B12_MASK 496*75ab5f91Slh #define FORCE_LINK_STATUS B11_MASK 497*75ab5f91Slh #define APEP B10_MASK 498*75ab5f91Slh #define MPPLBA B9_MASK 499*75ab5f91Slh 500*75ab5f91Slh /* VAL0 */ 501*75ab5f91Slh #define RESET_PHY_PULSE B2_MASK 502*75ab5f91Slh #define RESET_PHY B1_MASK 503*75ab5f91Slh #define PHY_RST_POL B0_MASK 504*75ab5f91Slh 505*75ab5f91Slh /* CMD7 0x64, 32bit register */ 506*75ab5f91Slh /* VAL0 */ 507*75ab5f91Slh #define PMAT_SAVE_MATCH B4_MASK 508*75ab5f91Slh #define PMAT_MODE B3_MASK 509*75ab5f91Slh #define MPEN_SW B1_MASK 510*75ab5f91Slh #define LCMODE_SW B0_MASK 511*75ab5f91Slh 512*75ab5f91Slh /* CTRL0 0x68, 32bit register */ 513*75ab5f91Slh #define PHY_SEL 0x03000000 /* 25:24 */ 514*75ab5f91Slh #define RESET_PHY_WIDTH 0x00FF0000 /* 23:16 */ 515*75ab5f91Slh #define BSWP_REGS B10_MASK 516*75ab5f91Slh #define BSWP_DESC B9_MASK 517*75ab5f91Slh #define BSWP_DATA B8_MASK 518*75ab5f91Slh #define CACHE_ALIGN B4_MASK 519*75ab5f91Slh #define BURST_LIMIT 0x0000000F /* 3:0 */ 520*75ab5f91Slh 521*75ab5f91Slh /* CTRL1 0x6C, 32bit register */ 522*75ab5f91Slh #define SLOTMOD_MASK 0x03000000 /* 25:24 */ 523*75ab5f91Slh #define XMTSP_MASK 0x300 /* 17:16 */ 524*75ab5f91Slh #define XMTSP_128 0x200 525*75ab5f91Slh #define XMTSP_64 0x100 526*75ab5f91Slh 527*75ab5f91Slh /* CTRL2 0x70, 32bit register */ 528*75ab5f91Slh #define FS_MASK 0x00070000 /* 18:16 */ 529*75ab5f91Slh #define FMDC_MASK 0x00000300 /* 9:8 */ 530*75ab5f91Slh #define XPHYRST B7_MASK 531*75ab5f91Slh #define XPHYANE B6_MASK 532*75ab5f91Slh #define XPHYFD B5_MASK 533*75ab5f91Slh #define XPHYSP_100 B3_MASK /* 4:3, 100 Mbps */ 534*75ab5f91Slh #define APDW_MASK 0x00000007 /* 2:0 */ 535*75ab5f91Slh 536*75ab5f91Slh /* RCV_RING_CFG 0x78, 16bit register */ 537*75ab5f91Slh #define RCV_DROP3 B11_MASK 538*75ab5f91Slh #define RCV_DROP2 B10_MASK 539*75ab5f91Slh #define RCV_DROP1 B9_MASK 540*75ab5f91Slh #define RCV_DROP0 B8_MASK 541*75ab5f91Slh #define RCV_RING_DEFAULT 0x0030 /* 5:4 */ 542*75ab5f91Slh #define RCV_RING3_EN B3_MASK 543*75ab5f91Slh #define RCV_RING2_EN B2_MASK 544*75ab5f91Slh #define RCV_RING1_EN B1_MASK 545*75ab5f91Slh #define RCV_RING0_EN B0_MASK 546*75ab5f91Slh 547*75ab5f91Slh /* XMT_RING_LIMIT 0x7C, 32bit register */ 548*75ab5f91Slh #define XMT_RING2_LIMIT 0x00FF0000 /* 23:16 */ 549*75ab5f91Slh #define XMT_RING1_LIMIT 0x0000FF00 /* 15:8 */ 550*75ab5f91Slh #define XMT_RING0_LIMIT 0x000000FF /* 7:0 */ 551*75ab5f91Slh 552*75ab5f91Slh /* AUTOPOLL0 0x88, 16bit register */ 553*75ab5f91Slh #define AP_REG0_EN B15_MASK 554*75ab5f91Slh #define AP_REG0_ADDR_MASK 0x1F00 /* 12:8 */ 555*75ab5f91Slh #define AP_PHY0_ADDR_MASK 0x001F /* 4:0 */ 556*75ab5f91Slh 557*75ab5f91Slh /* AUTOPOLL1 0x8A, 16bit register */ 558*75ab5f91Slh #define AP_REG1_EN B15_MASK 559*75ab5f91Slh #define AP_REG1_ADDR_MASK 0x1F00 /* 12:8 */ 560*75ab5f91Slh #define AP_PRE_SUP1 B6_MASK 561*75ab5f91Slh #define AP_PHY1_DFLT B5_MASK 562*75ab5f91Slh #define AP_PHY1_ADDR_MASK 0x001F /* 4:0 */ 563*75ab5f91Slh 564*75ab5f91Slh /* AUTOPOLL2 0x8C, 16bit register */ 565*75ab5f91Slh #define AP_REG2_EN B15_MASK 566*75ab5f91Slh #define AP_REG2_ADDR_MASK 0x1F00 /* 12:8 */ 567*75ab5f91Slh #define AP_PRE_SUP2 B6_MASK 568*75ab5f91Slh #define AP_PHY2_DFLT B5_MASK 569*75ab5f91Slh #define AP_PHY2_ADDR_MASK 0x001F /* 4:0 */ 570*75ab5f91Slh 571*75ab5f91Slh /* AUTOPOLL3 0x8E, 16bit register */ 572*75ab5f91Slh #define AP_REG3_EN B15_MASK 573*75ab5f91Slh #define AP_REG3_ADDR_MASK 0x1F00 /* 12:8 */ 574*75ab5f91Slh #define AP_PRE_SUP3 B6_MASK 575*75ab5f91Slh #define AP_PHY3_DFLT B5_MASK 576*75ab5f91Slh #define AP_PHY3_ADDR_MASK 0x001F /* 4:0 */ 577*75ab5f91Slh 578*75ab5f91Slh /* AUTOPOLL4 0x90, 16bit register */ 579*75ab5f91Slh #define AP_REG4_EN B15_MASK 580*75ab5f91Slh #define AP_REG4_ADDR_MASK 0x1F00 /* 12:8 */ 581*75ab5f91Slh #define AP_PRE_SUP4 B6_MASK 582*75ab5f91Slh #define AP_PHY4_DFLT B5_MASK 583*75ab5f91Slh #define AP_PHY4_ADDR_MASK 0x001F /* 4:0 */ 584*75ab5f91Slh 585*75ab5f91Slh /* AUTOPOLL5 0x92, 16bit register */ 586*75ab5f91Slh #define AP_REG5_EN B15_MASK 587*75ab5f91Slh #define AP_REG5_ADDR_MASK 0x1F00 /* 12:8 */ 588*75ab5f91Slh #define AP_PRE_SUP5 B6_MASK 589*75ab5f91Slh #define AP_PHY5_DFLT B5_MASK 590*75ab5f91Slh #define AP_PHY5_ADDR_MASK 0x001F /* 4:0 */ 591*75ab5f91Slh 592*75ab5f91Slh /* AP_VALUE 0x98, 32bit ragister */ 593*75ab5f91Slh #define AP_VAL_ACTIVE B31_MASK 594*75ab5f91Slh #define AP_VAL_RD_CMD B29_MASK 595*75ab5f91Slh #define AP_ADDR 0x00070000 /* 18:16 */ 596*75ab5f91Slh #define AP_VAL 0x0000FFFF /* 15:0 */ 597*75ab5f91Slh 598*75ab5f91Slh /* PCS_ANEG 0x9C, 32bit register */ 599*75ab5f91Slh #define SYNC_LOST B10_MASK 600*75ab5f91Slh #define IMATCH B9_MASK 601*75ab5f91Slh #define CMATCH B8_MASK 602*75ab5f91Slh #define PCS_AN_IDLE B1_MASK 603*75ab5f91Slh #define PCS_AN_CFG B0_MASK 604*75ab5f91Slh 605*75ab5f91Slh /* DLY_INT_A 0xA8, 32bit register */ 606*75ab5f91Slh #define DLY_INT_A_R3 B31_MASK 607*75ab5f91Slh #define DLY_INT_A_R2 B30_MASK 608*75ab5f91Slh #define DLY_INT_A_R1 B29_MASK 609*75ab5f91Slh #define DLY_INT_A_R0 B28_MASK 610*75ab5f91Slh #define DLY_INT_A_T3 B27_MASK 611*75ab5f91Slh #define DLY_INT_A_T2 B26_MASK 612*75ab5f91Slh #define DLY_INT_A_T1 B25_MASK 613*75ab5f91Slh #define DLY_INT_A_T0 B24_MASK 614*75ab5f91Slh #define EVENT_COUNT_A 0x00FF0000 /* 20:16 */ 615*75ab5f91Slh #define MAX_DELAY_TIME_A 0x000007FF /* 10:0 */ 616*75ab5f91Slh 617*75ab5f91Slh /* DLY_INT_B 0xAC, 32bit register */ 618*75ab5f91Slh #define DLY_INT_B_R3 B31_MASK 619*75ab5f91Slh #define DLY_INT_B_R2 B30_MASK 620*75ab5f91Slh #define DLY_INT_B_R1 B29_MASK 621*75ab5f91Slh #define DLY_INT_B_R0 B28_MASK 622*75ab5f91Slh #define DLY_INT_B_T3 B27_MASK 623*75ab5f91Slh #define DLY_INT_B_T2 B26_MASK 624*75ab5f91Slh #define DLY_INT_B_T1 B25_MASK 625*75ab5f91Slh #define DLY_INT_B_T0 B24_MASK 626*75ab5f91Slh #define EVENT_COUNT_B 0x00FF0000 /* 20:16 */ 627*75ab5f91Slh #define MAX_DELAY_TIME_B 0x000007FF /* 10:0 */ 628*75ab5f91Slh 629*75ab5f91Slh /* DFC_THRESH2 0xC0, 16bit register */ 630*75ab5f91Slh #define DFC_THRESH2_HIGH 0xFF00 /* 15:8 */ 631*75ab5f91Slh #define DFC_THRESH2_LOW 0x00FF /* 7:0 */ 632*75ab5f91Slh 633*75ab5f91Slh /* DFC_THRESH3 0xC2, 16bit register */ 634*75ab5f91Slh #define DFC_THRESH3_HIGH 0xFF00 /* 15:8 */ 635*75ab5f91Slh #define DFC_THRESH3_LOW 0x00FF /* 7:0 */ 636*75ab5f91Slh 637*75ab5f91Slh /* DFC_THRESH0 0xC4, 16bit register */ 638*75ab5f91Slh #define DFC_THRESH0_HIGH 0xFF00 /* 15:8 */ 639*75ab5f91Slh #define DFC_THRESH0_LOW 0x00FF /* 7:0 */ 640*75ab5f91Slh 641*75ab5f91Slh /* DFC_THRESH1 0xC6, 16bit register */ 642*75ab5f91Slh #define DFC_THRESH1_HIGH 0xFF00 /* 15:8 */ 643*75ab5f91Slh #define DFC_THRESH1_LOW 0x00FF /* 7:0 */ 644*75ab5f91Slh 645*75ab5f91Slh /* FLOW_CONTROL 0xC8, 32bit register */ 646*75ab5f91Slh #define PAUSE_LEN_CHG B30_MASK 647*75ab5f91Slh #define FFC_EN B28_MASK 648*75ab5f91Slh #define DFC_RING3_EN B27_MASK 649*75ab5f91Slh #define DFC_RING2_EN B26_MASK 650*75ab5f91Slh #define DFC_RING1_EN B25_MASK 651*75ab5f91Slh #define DFC_RING0_EN B24_MASK 652*75ab5f91Slh #define FIXP_CONGEST B21_MASK 653*75ab5f91Slh #define NAPA B20_MASK 654*75ab5f91Slh #define NPA B19_MASK 655*75ab5f91Slh #define FIXP B18_MASK 656*75ab5f91Slh #define FCPEN B17_MASK 657*75ab5f91Slh #define FCCMD B16_MASK 658*75ab5f91Slh #define PAUSE_LEN 0x0000FFFF /* 15:0 */ 659*75ab5f91Slh 660*75ab5f91Slh /* FFC THRESH 0xCC, 32bit register */ 661*75ab5f91Slh #define FFC_HIGH 0xFFFF0000 /* 31:16 */ 662*75ab5f91Slh #define FFC_LOW 0x0000FFFF /* 15:0 */ 663*75ab5f91Slh 664*75ab5f91Slh /* PHY_ACCESS 0xD0, 32bit register */ 665*75ab5f91Slh #define PHY_CMD_ACTIVE B31_MASK 666*75ab5f91Slh #define PHY_WR_CMD B30_MASK 667*75ab5f91Slh #define PHY_RD_CMD B29_MASK 668*75ab5f91Slh #define PHY_RD_ERR B28_MASK 669*75ab5f91Slh #define PHY_PRE_SUP B27_MASK 670*75ab5f91Slh #define PHY_ADDR 0x03E00000 /* 25:21 */ 671*75ab5f91Slh #define PHY_REG_ADDR 0x001F0000 /* 20:16 */ 672*75ab5f91Slh #define PHY_DATA 0x0000FFFF /* 15:0 */ 673*75ab5f91Slh #define PHY_ADDR_SHIFT 21 674*75ab5f91Slh #define PHY_REG_ADDR_SHIFT 16 675*75ab5f91Slh 676*75ab5f91Slh #define PHY_MAX_RETRY 30 677*75ab5f91Slh 678*75ab5f91Slh 679*75ab5f91Slh /* EEPROM_ACC 0x17C, 16bit register */ 680*75ab5f91Slh #define PVALID B15_MASK 681*75ab5f91Slh #define PREAD B14_MASK 682*75ab5f91Slh #define EEDET B13_MASK 683*75ab5f91Slh #define EEN B4_MASK 684*75ab5f91Slh #define ECS B2_MASK 685*75ab5f91Slh #define EESK B1_MASK 686*75ab5f91Slh #define EDI_EDO B0_MASK 687*75ab5f91Slh 688*75ab5f91Slh /* PMAT0 0x190, 32bit register */ 689*75ab5f91Slh #define PMR_ACTIVE B31_MASK 690*75ab5f91Slh #define PMR_WR_CMD B30_MASK 691*75ab5f91Slh #define PMR_RD_CMD B29_MASK 692*75ab5f91Slh #define PMR_BANK B28_MASK 693*75ab5f91Slh #define PMR_ADDR 0x007F0000 /* 22:16 */ 694*75ab5f91Slh #define PMR_B4 0x000000FF /* 15:0 */ 695*75ab5f91Slh 696*75ab5f91Slh /* PMAT1 0x194, 32bit register */ 697*75ab5f91Slh #define PMR_B3 0xFF000000 /* 31:24 */ 698*75ab5f91Slh #define PMR_B2 0x00FF0000 /* 23:16 */ 699*75ab5f91Slh #define PMR_B1 0x0000FF00 /* 15:8 */ 700*75ab5f91Slh #define PMR_B0 0x000000FF /* 7:0 */ 701*75ab5f91Slh 702*75ab5f91Slh /* CAMDATA 0x198, 16bit register */ 703*75ab5f91Slh #define CAM_DATA_MASK 0x000000FFFFFFFFFFFF 704*75ab5f91Slh 705*75ab5f91Slh /* CAM_ADDR 0x1A0, 16bit register */ 706*75ab5f91Slh #define CAM_CMD_ACTIVE B15_MASK 707*75ab5f91Slh #define CAM_WR_CMD B14_MASK 708*75ab5f91Slh #define CAM_RD_CMD B13_MASK 709*75ab5f91Slh #define CAM_CLEAR B12_MASK 710*75ab5f91Slh #define CAM_ADDRESS 0x001F 711*75ab5f91Slh 712*75ab5f91Slh /* INT0 0x38, 32bit register */ 713*75ab5f91Slh #define INTR B31_MASK 714*75ab5f91Slh #define LCINT B27_MASK 715*75ab5f91Slh #define TINT0 B8_MASK 716*75ab5f91Slh #define STINT B4_MASK 717*75ab5f91Slh #define RINT0 B0_MASK 718*75ab5f91Slh 719*75ab5f91Slh /* TEST0 0x1A8, 32bit register */ 720*75ab5f91Slh 721*75ab5f91Slh /* VAL1 */ 722*75ab5f91Slh #define MFSM_RESET B10_MASK 723*75ab5f91Slh #define BFD_SCALE_DOWN B9_MASK 724*75ab5f91Slh 725*75ab5f91Slh /* VAL0 */ 726*75ab5f91Slh #define LEDCNTTST B5_MASK 727*75ab5f91Slh #define RTYTST_RANGEN B2_MASK 728*75ab5f91Slh #define RTYTST_SLOT B1_MASK 729*75ab5f91Slh #define SERRLEVEL B0_MASK 730*75ab5f91Slh 731*75ab5f91Slh #define CABLE_CHK_TIME 100 732*75ab5f91Slh 733*75ab5f91Slh #define PCI_IOMAP_BASE_REG 0x00 734*75ab5f91Slh #define PCI_MEM_BASE_REG 0x10 735*75ab5f91Slh 736*75ab5f91Slh #define XPHYFD B5_MASK 737*75ab5f91Slh #define XPHYSP B3_MASK /* 4:3 */ 738*75ab5f91Slh 739*75ab5f91Slh #define TX_RATE 0x1 740*75ab5f91Slh #define RX_RATE 0x2 741*75ab5f91Slh #define RX_BYTES 0xb 742*75ab5f91Slh #define TX_BYTES 0xc 743*75ab5f91Slh 744*75ab5f91Slh #define LOW_COALESC 1 745*75ab5f91Slh #define MEDIUM_COALESC 2 746*75ab5f91Slh #define HIGH_COALESC 3 747*75ab5f91Slh #define NO_COALESC 4 748*75ab5f91Slh 749*75ab5f91Slh #define CLIENT 0x1 750*75ab5f91Slh #define SERVER 0x2 751*75ab5f91Slh #define DISABLE 0x3 752*75ab5f91Slh #define PCI_OPT 0x4 753*75ab5f91Slh 754*75ab5f91Slh #define MULTICAST_BITMAP_ARRAY_SIZE 64 755*75ab5f91Slh 756*75ab5f91Slh #define PHY_AUTO_NEGOTIATION 0 757*75ab5f91Slh #define PHY_FORCE_HD_100 1 /* HD: Half Duplex */ 758*75ab5f91Slh #define PHY_FORCE_FD_100 2 /* FD: Full Duplex */ 759*75ab5f91Slh #define PHY_FORCE_HD_10 3 760*75ab5f91Slh #define PHY_FORCE_FD_10 4 761*75ab5f91Slh 762*75ab5f91Slh struct tx_desc { 763*75ab5f91Slh unsigned int Tx_BCNT :16; /* Buffer Byte Count */ 764*75ab5f91Slh unsigned int Tx_RES4 :6; /* RESVERD 6 bits */ 765*75ab5f91Slh /* 766*75ab5f91Slh * This bit causes the transmission of the corresponding frame to be 767*75ab5f91Slh * aborted. If the transmitter has not started sending the frame at the 768*75ab5f91Slh * time that the descriptor 769*75ab5f91Slh */ 770*75ab5f91Slh unsigned int KILL :1; 771*75ab5f91Slh unsigned int Tx_RES3 :1; /* RESVERD 1 bits */ 772*75ab5f91Slh /* End Of packet to indicates the last Buffer */ 773*75ab5f91Slh unsigned int Tx_EOP :1; 774*75ab5f91Slh unsigned int Tx_SOP :1; /* Defer to Transmit */ 775*75ab5f91Slh unsigned int Tx_RES2 :2; 776*75ab5f91Slh unsigned int Tx_LTINT :1; /* Start of packet for the Buffer */ 777*75ab5f91Slh /* 778*75ab5f91Slh * ADD_FCS dynamically controls the generation of FCS on a frame by 779*75ab5f91Slh * frame basis. 780*75ab5f91Slh */ 781*75ab5f91Slh unsigned int Tx_ADD_FCS :1; 782*75ab5f91Slh unsigned int Tx_RES1 :1; /* Reserved Location */ 783*75ab5f91Slh unsigned int Tx_OWN :1; /* Own Bit for the Transmit */ 784*75ab5f91Slh unsigned int TCI :16; /* VLAN Tag Control Command. */ 785*75ab5f91Slh unsigned int TCC :2; /* Tag Control Information. */ 786*75ab5f91Slh unsigned int Tx_RES0 :14; /* Resvered Location */ 787*75ab5f91Slh /* 788*75ab5f91Slh * TBADR[31:0] Transmit Buffer Address. This field contains the address 789*75ab5f91Slh * of the Transmit buffer that is associated with this descriptor 790*75ab5f91Slh */ 791*75ab5f91Slh unsigned int Tx_Base_Addr :32; 792*75ab5f91Slh unsigned int Tx_USPACE :32; /* User Space */ 793*75ab5f91Slh }; 794*75ab5f91Slh 795*75ab5f91Slh /* Receive Descriptor For the L7 */ 796*75ab5f91Slh struct rx_desc { 797*75ab5f91Slh 798*75ab5f91Slh /* User Reserved amar - Its just reservered. */ 799*75ab5f91Slh unsigned int Rx_USPACE :32; 800*75ab5f91Slh /* 801*75ab5f91Slh * Message Byte Count is the number of bytes of the received message 802*75ab5f91Slh * written 803*75ab5f91Slh */ 804*75ab5f91Slh unsigned int Rx_MCNT :16; 805*75ab5f91Slh unsigned int TCI :16; 806*75ab5f91Slh /* 807*75ab5f91Slh * Buffer Byte Count is the length of the buffer pointed to by this 808*75ab5f91Slh * descriptor 809*75ab5f91Slh */ 810*75ab5f91Slh unsigned int Rx_BCNT :16; 811*75ab5f91Slh unsigned int Rx_RES1 :2; /* Reserved Location */ 812*75ab5f91Slh /* 813*75ab5f91Slh * VLAN Tag Type. Indicates what type of VLAN tag, if any, is included 814*75ab5f91Slh * in the received 815*75ab5f91Slh */ 816*75ab5f91Slh unsigned int TT :2; 817*75ab5f91Slh /* 818*75ab5f91Slh * Broadcast Address Match is set by the Am79C976 controller when it 819*75ab5f91Slh * accepts the reveice buffer 820*75ab5f91Slh */ 821*75ab5f91Slh unsigned int Rx_BAM :1; 822*75ab5f91Slh /* 823*75ab5f91Slh * Logical Address Filter Match is set by the Am79C976 controller 824*75ab5f91Slh * to the Receive Buffer 825*75ab5f91Slh */ 826*75ab5f91Slh unsigned int Rx_LAFM :1; 827*75ab5f91Slh /* Physical Address Match is set by the Am79C976 controller */ 828*75ab5f91Slh unsigned int Rx_PAM :1; 829*75ab5f91Slh unsigned int Rx_RES0 :1; /* Resvered Location */ 830*75ab5f91Slh /* End Of packet to indicates the last Buffer */ 831*75ab5f91Slh unsigned int Rx_EOP :1; 832*75ab5f91Slh unsigned int Rx_SOP :1; /* Start of packet for the Buffer */ 833*75ab5f91Slh unsigned int Rx_BUFF :1; /* Reserved location */ 834*75ab5f91Slh /* 835*75ab5f91Slh * CRC indicates that the receiver has detected a CRC (FCS) error on the 836*75ab5f91Slh * incoming frame. 837*75ab5f91Slh */ 838*75ab5f91Slh unsigned int Rx_CRC :1; 839*75ab5f91Slh /* 840*75ab5f91Slh * Overflow error indicates that the receiver has lost all or part of 841*75ab5f91Slh * the incoming frame. 842*75ab5f91Slh */ 843*75ab5f91Slh unsigned int Rx_OFLO :1; 844*75ab5f91Slh unsigned int Rx_FRAM :1; /* Framing Error */ 845*75ab5f91Slh unsigned int Rx_ERR :1; /* Error is Set By the Controller */ 846*75ab5f91Slh unsigned int Rx_OWN :1; /* Own Bit of Descriptor */ 847*75ab5f91Slh /* 848*75ab5f91Slh * RBADR[31:0] Receive Buffer Address. This field contains the address 849*75ab5f91Slh * of the receive buffer that is associated with this descriptor. 850*75ab5f91Slh */ 851*75ab5f91Slh unsigned int Rx_Base_Addr:32; 852*75ab5f91Slh }; 853*75ab5f91Slh 854*75ab5f91Slh 855*75ab5f91Slh /* Initialization Block (SSIZE32 = 1) */ 856*75ab5f91Slh struct init_block { 857*75ab5f91Slh unsigned int MODE :16; /* Mode */ 858*75ab5f91Slh unsigned int RES1 :4; /* Reserved Location */ 859*75ab5f91Slh /* Receive software structure is defined for 16 bit */ 860*75ab5f91Slh unsigned int RLEN :4; 861*75ab5f91Slh unsigned int RES2 :4; /* Reserved bits */ 862*75ab5f91Slh /* Transmit software structure is defined for the 16 bit */ 863*75ab5f91Slh unsigned int TLEN :4; 864*75ab5f91Slh unsigned int PADDR0 :8; 865*75ab5f91Slh unsigned int PADDR1 :8; 866*75ab5f91Slh unsigned int PADDR2 :8; 867*75ab5f91Slh unsigned int PADDR3 :8; 868*75ab5f91Slh unsigned int PADDR4 :8; 869*75ab5f91Slh unsigned int PADDR5 :8; 870*75ab5f91Slh unsigned int RES3 :16; 871*75ab5f91Slh unsigned char LADRF[8]; 872*75ab5f91Slh /* RDRA indicate where the receive descriptor ring begins */ 873*75ab5f91Slh unsigned int RDRA :32; 874*75ab5f91Slh /* TDRA indicate where the transmit descriptor ring begins */ 875*75ab5f91Slh unsigned int TDRA :32; 876*75ab5f91Slh }; 877*75ab5f91Slh 878*75ab5f91Slh /* MDL Physical and Normal Structure */ 879*75ab5f91Slh struct mdl { 880*75ab5f91Slh ULONG Io_Address; 881*75ab5f91Slh ULONG Mem_Address; 882*75ab5f91Slh 883*75ab5f91Slh volatile int CSR; 884*75ab5f91Slh volatile int CardStatus; 885*75ab5f91Slh 886*75ab5f91Slh /* PMR (Pattern Match RAM) */ 887*75ab5f91Slh /* 888*75ab5f91Slh * An array to store the indexes of each of the patterns in 889*75ab5f91Slh * Pattern List. 890*75ab5f91Slh */ 891*75ab5f91Slh unsigned int *PMR_PtrList; 892*75ab5f91Slh /* An array of pattern controls and pattern data bytes */ 893*75ab5f91Slh unsigned char *PatternList; 894*75ab5f91Slh unsigned int *PatternLength; 895*75ab5f91Slh int EnableMulticast; 896*75ab5f91Slh /* The begining of the free area in the PatternList array */ 897*75ab5f91Slh unsigned short PatternList_FreeIndex; 898*75ab5f91Slh /* The total number of patterns present in the PMR */ 899*75ab5f91Slh unsigned short TotalPatterns; 900*75ab5f91Slh unsigned short PatternEnableBit; 901*75ab5f91Slh 902*75ab5f91Slh unsigned char Mac[6]; 903*75ab5f91Slh unsigned char TEMP_MAC[6]; 904*75ab5f91Slh unsigned int FLAGS; 905*75ab5f91Slh unsigned char TempLADRF[8]; 906*75ab5f91Slh 907*75ab5f91Slh ULONG Speed; 908*75ab5f91Slh ULONG FullDuplex; 909*75ab5f91Slh 910*75ab5f91Slh struct init_block *init_blk; 911*75ab5f91Slh 912*75ab5f91Slh int tmpPtrArray[8]; 913*75ab5f91Slh 914*75ab5f91Slh int MulticastBitMapArray[MULTICAST_BITMAP_ARRAY_SIZE]; 915*75ab5f91Slh int External_Phy; 916*75ab5f91Slh unsigned int phy_id; 917*75ab5f91Slh 918*75ab5f91Slh /* For interrupt delay */ 919*75ab5f91Slh /* Unit is 10 us. Its value must < 0x800 (2^11) */ 920*75ab5f91Slh unsigned int rx_intrcoalesc_time; 921*75ab5f91Slh /* Its value must < 32 (2^5) */ 922*75ab5f91Slh unsigned int rx_intrcoalesc_events; 923*75ab5f91Slh unsigned int tx_intrcoalesc_time; 924*75ab5f91Slh unsigned int tx_intrcoalesc_events; 925*75ab5f91Slh int IntrCoalescFlag; 926*75ab5f91Slh 927*75ab5f91Slh int RxRingLenBits; 928*75ab5f91Slh int TxRingLenBits; 929*75ab5f91Slh int TxRingSize; 930*75ab5f91Slh int RxRingSize; 931*75ab5f91Slh 932*75ab5f91Slh int IpgValue; 933*75ab5f91Slh }; 934*75ab5f91Slh 935*75ab5f91Slh struct Rx_Buf_Desc { 936*75ab5f91Slh struct rx_desc *descriptor; 937*75ab5f91Slh long *USpaceMap; 938*75ab5f91Slh }; 939*75ab5f91Slh 940*75ab5f91Slh struct nonphysical 941*75ab5f91Slh { 942*75ab5f91Slh /* Tx descriptors queue */ 943*75ab5f91Slh struct tx_desc *TxDescQRead; /* The next ring entry to be freed */ 944*75ab5f91Slh struct tx_desc *TxDescQWrite; /* The next free ring entry */ 945*75ab5f91Slh struct tx_desc *TxDescQStart; /* The start of the ring entries */ 946*75ab5f91Slh struct tx_desc *TxDescQEnd; /* The end of the ring entries */ 947*75ab5f91Slh 948*75ab5f91Slh /* struct Rx_Buf_Desc * queue */ 949*75ab5f91Slh struct Rx_Buf_Desc *RxBufDescQRead; 950*75ab5f91Slh struct Rx_Buf_Desc *RxBufDescQStart; 951*75ab5f91Slh struct Rx_Buf_Desc *RxBufDescQEnd; 952*75ab5f91Slh 953*75ab5f91Slh }; 954*75ab5f91Slh 955*75ab5f91Slh struct mil 956*75ab5f91Slh { 957*75ab5f91Slh /* 958*75ab5f91Slh * 1) For memory allocation and free 959*75ab5f91Slh */ 960*75ab5f91Slh 961*75ab5f91Slh /* 962*75ab5f91Slh * Tx_desc: address of all tx descriptors block 963*75ab5f91Slh * Tx_desc_pa: physical address of Tx_desc 964*75ab5f91Slh */ 965*75ab5f91Slh struct tx_desc *Tx_desc; 966*75ab5f91Slh unsigned int Tx_desc_pa; 967*75ab5f91Slh /* Original address, because Tx_desc needs 16 bytes alignment */ 968*75ab5f91Slh ULONG Tx_desc_original; 969*75ab5f91Slh 970*75ab5f91Slh struct rx_desc *Rx_desc; 971*75ab5f91Slh unsigned int Rx_desc_pa; 972*75ab5f91Slh /* Original address, because Rx_desc needs 16 bytes alignment */ 973*75ab5f91Slh ULONG Rx_desc_original; 974*75ab5f91Slh 975*75ab5f91Slh long *USpaceMapArray; /* Queue of struct rxBufInfo * */ 976*75ab5f91Slh 977*75ab5f91Slh /* 978*75ab5f91Slh * 2) For descriptor queue/buffer queue operation 979*75ab5f91Slh */ 980*75ab5f91Slh struct nonphysical *pNonphysical; 981*75ab5f91Slh 982*75ab5f91Slh /* 983*75ab5f91Slh * 3) Parameters 984*75ab5f91Slh */ 985*75ab5f91Slh int RxRingSize; 986*75ab5f91Slh int TxRingSize; 987*75ab5f91Slh int RxBufSize; 988*75ab5f91Slh 989*75ab5f91Slh /* 990*75ab5f91Slh * 4) Other 991*75ab5f91Slh */ 992*75ab5f91Slh int tx_reschedule; 993*75ab5f91Slh char *name; 994*75ab5f91Slh }; 995*75ab5f91Slh 996*75ab5f91Slh struct LayerPointers 997*75ab5f91Slh { 998*75ab5f91Slh struct odl *pOdl; 999*75ab5f91Slh struct mil *pMil; 1000*75ab5f91Slh struct mdl *pMdl; 1001*75ab5f91Slh 1002*75ab5f91Slh int instance; 1003*75ab5f91Slh int attach_progress; 1004*75ab5f91Slh int run; /* B_TRUE on plumb; B_FALSE on unplumb */ 1005*75ab5f91Slh }; 1006*75ab5f91Slh 1007*75ab5f91Slh /* MIL Function Prototypes. */ 1008*75ab5f91Slh 1009*75ab5f91Slh /* 1010*75ab5f91Slh * Initialisation of MIL data structures and External Interface Function 1011*75ab5f91Slh * Pointers. 1012*75ab5f91Slh */ 1013*75ab5f91Slh void milInitGlbds(struct LayerPointers *); 1014*75ab5f91Slh 1015*75ab5f91Slh void milInitRxQ(struct LayerPointers *); 1016*75ab5f91Slh 1017*75ab5f91Slh void milResetTxQ(struct LayerPointers *); 1018*75ab5f91Slh 1019*75ab5f91Slh void milFreeResources(struct LayerPointers *, ULONG *); 1020*75ab5f91Slh 1021*75ab5f91Slh void milRequestResources(ULONG *); 1022*75ab5f91Slh void milSetResources(struct LayerPointers *, ULONG *); 1023*75ab5f91Slh 1024*75ab5f91Slh /* Open Functions. */ 1025*75ab5f91Slh void mdlOpen(struct LayerPointers *); 1026*75ab5f91Slh 1027*75ab5f91Slh void mdlHWReset(struct LayerPointers *); 1028*75ab5f91Slh 1029*75ab5f91Slh /* Multicast */ 1030*75ab5f91Slh void mdlDeleteMulticastAddress(struct LayerPointers *, UCHAR *); 1031*75ab5f91Slh void mdlAddMulticastAddress(struct LayerPointers *, UCHAR *); 1032*75ab5f91Slh 1033*75ab5f91Slh /* Transmit/Receive Interface provided by MDL */ 1034*75ab5f91Slh void mdlTransmit(struct LayerPointers *); 1035*75ab5f91Slh void mdlReceive(struct LayerPointers *); 1036*75ab5f91Slh 1037*75ab5f91Slh unsigned int mdlReadMib(struct LayerPointers *, char); 1038*75ab5f91Slh 1039*75ab5f91Slh /* Read Link Status */ 1040*75ab5f91Slh int mdlReadLink(struct LayerPointers *); 1041*75ab5f91Slh 1042*75ab5f91Slh /* Interrupt Handling */ 1043*75ab5f91Slh unsigned int mdlReadInterrupt(struct LayerPointers *); 1044*75ab5f91Slh 1045*75ab5f91Slh void mdlEnableInterrupt(struct LayerPointers *); 1046*75ab5f91Slh void mdlDisableInterrupt(struct LayerPointers *); 1047*75ab5f91Slh 1048*75ab5f91Slh void mdlGetActiveMediaInfo(struct LayerPointers *); 1049*75ab5f91Slh 1050*75ab5f91Slh void mdlStartChip(struct LayerPointers *); 1051*75ab5f91Slh void mdlStopChip(struct LayerPointers *); 1052*75ab5f91Slh 1053*75ab5f91Slh void mdlGetMacAddress(struct LayerPointers *, unsigned char *); 1054*75ab5f91Slh void mdlSetMacAddress(struct LayerPointers *, unsigned char *); 1055*75ab5f91Slh 1056*75ab5f91Slh void mdlAddMulticastAddresses(struct LayerPointers *, int, unsigned char *); 1057*75ab5f91Slh 1058*75ab5f91Slh void mdlSetPromiscuous(struct LayerPointers *); 1059*75ab5f91Slh void mdlDisablePromiscuous(struct LayerPointers *); 1060*75ab5f91Slh 1061*75ab5f91Slh void mdlSendPause(struct LayerPointers *); 1062*75ab5f91Slh 1063*75ab5f91Slh void SetIntrCoalesc(struct LayerPointers *, boolean_t); 1064*75ab5f91Slh void mdlPHYAutoNegotiation(struct LayerPointers *, unsigned int); 1065*75ab5f91Slh void mdlRxFastSuspend(struct LayerPointers *); 1066*75ab5f91Slh void mdlRxFastSuspendClear(struct LayerPointers *); 1067*75ab5f91Slh 1068*75ab5f91Slh /* Externs */ 1069*75ab5f91Slh 1070*75ab5f91Slh /* ODL functions */ 1071*75ab5f91Slh extern void amd8111s_reset(struct LayerPointers *); 1072*75ab5f91Slh extern unsigned char READ_REG8(struct LayerPointers *, long); 1073*75ab5f91Slh extern void WRITE_REG8(struct LayerPointers *, long, int); 1074*75ab5f91Slh extern int READ_REG16(struct LayerPointers *, long); 1075*75ab5f91Slh extern void WRITE_REG16(struct LayerPointers *, long, int); 1076*75ab5f91Slh extern long READ_REG32(struct LayerPointers *, long); 1077*75ab5f91Slh extern void WRITE_REG32(struct LayerPointers *, long, int); 1078*75ab5f91Slh extern void WRITE_REG64(struct LayerPointers *, long, char *); 1079*75ab5f91Slh 1080*75ab5f91Slh #endif /* AMD8111S_HW_H */ 1081