1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2021 Oxide Computer Company 25 */ 26 27 #ifndef _SYS_PCI_CFGSPACE_IMPL_H 28 #define _SYS_PCI_CFGSPACE_IMPL_H 29 30 /* 31 * Routines to support particular PCI chipsets 32 */ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * Generic Mechanism 1 routines 40 * XX64 putb -> put8, putw -> put16 etc. 41 */ 42 extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg); 43 extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg); 44 extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg); 45 extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val); 46 extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val); 47 extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val); 48 49 /* 50 * AMD family >= 0x10 Mechanism 1 routines with ECS support 51 */ 52 extern boolean_t pci_check_amd_ioecs(void); 53 extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg); 54 extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg); 55 extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg); 56 extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg, 57 uint8_t val); 58 extern void pci_mech1_amd_putw(int bus, int dev, int func, int reg, 59 uint16_t val); 60 extern void pci_mech1_amd_putl(int bus, int dev, int func, int reg, 61 uint32_t val); 62 63 /* 64 * Generic Mechanism 2 routines 65 */ 66 extern uint8_t pci_mech2_getb(int bus, int dev, int func, int reg); 67 extern uint16_t pci_mech2_getw(int bus, int dev, int func, int reg); 68 extern uint32_t pci_mech2_getl(int bus, int dev, int func, int reg); 69 extern void pci_mech2_putb(int bus, int dev, int func, int reg, uint8_t val); 70 extern void pci_mech2_putw(int bus, int dev, int func, int reg, uint16_t val); 71 extern void pci_mech2_putl(int bus, int dev, int func, int reg, uint32_t val); 72 73 /* 74 * Intel Neptune routines. Neptune is Mech 1, except that BIOSes 75 * often initialize it into Mech 2 so we dynamically switch it to 76 * Mech 1. The chipset's buggy, so we have to do it carefully. 77 */ 78 extern boolean_t pci_check_neptune(void); 79 extern uint8_t pci_neptune_getb(int bus, int dev, int func, int reg); 80 extern uint16_t pci_neptune_getw(int bus, int dev, int func, int reg); 81 extern uint32_t pci_neptune_getl(int bus, int dev, int func, int reg); 82 extern void pci_neptune_putb(int bus, int dev, int func, int reg, uint8_t val); 83 extern void pci_neptune_putw(int bus, int dev, int func, int reg, uint16_t val); 84 extern void pci_neptune_putl(int bus, int dev, int func, int reg, uint32_t val); 85 86 /* 87 * Intel Orion routines. Orion is Mech 1, except that there's a bug 88 * in the peer bridge that requires that it be tweaked specially 89 * around accesses to config space. 90 */ 91 extern boolean_t pci_is_broken_orion(void); 92 extern uint8_t pci_orion_getb(int bus, int dev, int func, int reg); 93 extern uint16_t pci_orion_getw(int bus, int dev, int func, int reg); 94 extern uint32_t pci_orion_getl(int bus, int dev, int func, int reg); 95 extern void pci_orion_putb(int bus, int dev, int func, int reg, uint8_t val); 96 extern void pci_orion_putw(int bus, int dev, int func, int reg, uint16_t val); 97 extern void pci_orion_putl(int bus, int dev, int func, int reg, uint32_t val); 98 99 /* 100 * Generic PCI constants. Probably these should be in pci.h. 101 */ 102 #define PCI_MAX_BUSSES 256 103 #define PCI_MAX_DEVS 32 104 #define PCI_MAX_FUNCS 8 105 /* 106 * PCI access mechanism constants. Probably these should be in pci_impl.h. 107 */ 108 #define PCI_MECH2_CONFIG_ENABLE 0x10 /* any nonzero high nibble works */ 109 110 #define PCI_MECH1_SPEC_CYCLE_DEV 0x1f /* dev to request spec cyc */ 111 #define PCI_MECH1_SPEC_CYCLE_FUNC 0x07 /* func to request spec cyc */ 112 113 extern uint64_t mcfg_mem_base; 114 extern uint8_t mcfg_bus_start; 115 extern uint8_t mcfg_bus_end; 116 117 /* 118 * Mutexes for pci config space routines 119 */ 120 extern kmutex_t pcicfg_mutex; 121 extern kmutex_t pcicfg_mmio_mutex; 122 123 /* 124 * The maximum offset that these I/O space mechanisms can read. Generally either 125 * 0xff to indicate that PCIe extended configuration space is not available or 126 * 0xfff to indicate that it is. 127 */ 128 extern uint_t pci_iocfg_max_offset; 129 130 /* 131 * Orion/Neptune cfg access wraps mech1 cfg access, so needs a separate mutex 132 */ 133 134 extern kmutex_t pcicfg_chipset_mutex; 135 136 /* 137 * pci get irq routing information support 138 */ 139 #define PCI_GET_IRQ_ROUTING 0x0e 140 141 #define PCI_FUNCTION_ID (0xb1) 142 #define PCI_BIOS_PRESENT (0x1) 143 144 /* 145 * low-mem addresses for irq routing bios operations 146 * We set up the initial request for up to 32 table entries, and will 147 * re-issue for up to 255 entries if the bios indicates it requires 148 * a larger table. 255 entries plus the header would consume the 149 * memory between 0x7000-0x7fff. 150 */ 151 #define BIOS_IRQ_ROUTING_HDR 0x7000 152 #define BIOS_IRQ_ROUTING_DATA 0x7010 153 154 #define N_PCI_IRQ_ROUTES 32 155 #define N_PCI_IRQ_ROUTES_MAX 255 156 157 #define MCFG_PROPNAME "ecfg" 158 159 #define FP_OFF(fp) (((uintptr_t)(fp)) & 0xFFFF) 160 #define FP_SEG(fp) ((((uintptr_t)(fp)) >> 16) & 0xFFFF) 161 162 #pragma pack(1) 163 typedef struct pci_irq_route { 164 uchar_t pir_bus; 165 uchar_t pir_dev; 166 uchar_t pir_inta_link; 167 uint16_t pir_inta_irq_map; 168 uchar_t pir_intb_link; 169 uint16_t pir_intb_irq_map; 170 uchar_t pir_intc_link; 171 uint16_t pir_intc_irq_map; 172 uchar_t pir_intd_link; 173 uint16_t pir_intd_irq_map; 174 uchar_t pir_slot; 175 uchar_t pir_reserved; 176 } pci_irq_route_t; 177 #pragma pack() 178 179 #pragma pack(1) 180 typedef struct pci_irq_route_hdr { 181 uint16_t pir_size; 182 uint32_t pir_addr; 183 } pci_irq_route_hdr_t; 184 #pragma pack() 185 186 #ifdef __cplusplus 187 } 188 #endif 189 190 #endif /* _SYS_PCI_CFGSPACE_IMPL_H */ 191