17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 50ccf9e79Sjohnny * Common Development and Distribution License (the "License"). 60ccf9e79Sjohnny * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22e7c3cdaeSjiang.liu@intel.com * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 231c2d0470SPatrick Mooney * Copyright 2018 Joyent, Inc. 24e8763682SPavel Zakharov * Copyright (c) 2017 by Delphix. All rights reserved. 257c478bd9Sstevel@tonic-gate */ 2641afdfa7SKrishnendu Sadhukhan - Sun Microsystems /* 2741afdfa7SKrishnendu Sadhukhan - Sun Microsystems * Copyright (c) 2010, Intel Corporation. 2841afdfa7SKrishnendu Sadhukhan - Sun Microsystems * All rights reserved. 2941afdfa7SKrishnendu Sadhukhan - Sun Microsystems */ 3041afdfa7SKrishnendu Sadhukhan - Sun Microsystems 317c478bd9Sstevel@tonic-gate #ifndef _SYS_APIC_APIC_H 327c478bd9Sstevel@tonic-gate #define _SYS_APIC_APIC_H 337c478bd9Sstevel@tonic-gate 34ae115bc7Smrj #include <sys/psm_types.h> 35c8589f13Ssethg #include <sys/avintr.h> 36c8589f13Ssethg #include <sys/pci.h> 37ae115bc7Smrj 387c478bd9Sstevel@tonic-gate #ifdef __cplusplus 397c478bd9Sstevel@tonic-gate extern "C" { 407c478bd9Sstevel@tonic-gate #endif 417c478bd9Sstevel@tonic-gate 427c478bd9Sstevel@tonic-gate #include <sys/psm_common.h> 437c478bd9Sstevel@tonic-gate 442917a9c9Sschwartz #define APIC_PCPLUSMP_NAME "pcplusmp" 457ff178cdSJimmy Vetayases #define APIC_APIX_NAME "apix" 462917a9c9Sschwartz 477c478bd9Sstevel@tonic-gate #define APIC_IO_ADDR 0xfec00000 487c478bd9Sstevel@tonic-gate #define APIC_LOCAL_ADDR 0xfee00000 497c478bd9Sstevel@tonic-gate #define APIC_IO_MEMLEN 0xf 507c478bd9Sstevel@tonic-gate #define APIC_LOCAL_MEMLEN 0xfffff 517c478bd9Sstevel@tonic-gate 527c478bd9Sstevel@tonic-gate /* Local Unit ID register */ 537c478bd9Sstevel@tonic-gate #define APIC_LID_REG 0x8 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate /* I/o Unit Version Register */ 567c478bd9Sstevel@tonic-gate #define APIC_VERS_REG 0xc 577c478bd9Sstevel@tonic-gate 587c478bd9Sstevel@tonic-gate /* Task Priority register */ 597c478bd9Sstevel@tonic-gate #define APIC_TASK_REG 0x20 607c478bd9Sstevel@tonic-gate 617c478bd9Sstevel@tonic-gate /* EOI register */ 627c478bd9Sstevel@tonic-gate #define APIC_EOI_REG 0x2c 637c478bd9Sstevel@tonic-gate 647c478bd9Sstevel@tonic-gate /* Remote Read register */ 657c478bd9Sstevel@tonic-gate #define APIC_REMOTE_READ 0x30 667c478bd9Sstevel@tonic-gate 677c478bd9Sstevel@tonic-gate /* Logical Destination register */ 687c478bd9Sstevel@tonic-gate #define APIC_DEST_REG 0x34 697c478bd9Sstevel@tonic-gate 7087cc6269SSaurabh Misra /* Destination Format register */ 717c478bd9Sstevel@tonic-gate #define APIC_FORMAT_REG 0x38 727c478bd9Sstevel@tonic-gate 737c478bd9Sstevel@tonic-gate /* Spurious Interrupt Vector register */ 747c478bd9Sstevel@tonic-gate #define APIC_SPUR_INT_REG 0x3c 757c478bd9Sstevel@tonic-gate 767c478bd9Sstevel@tonic-gate /* Error Status Register */ 777c478bd9Sstevel@tonic-gate #define APIC_ERROR_STATUS 0xa0 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate /* Interrupt Command registers */ 807c478bd9Sstevel@tonic-gate #define APIC_INT_CMD1 0xc0 817c478bd9Sstevel@tonic-gate #define APIC_INT_CMD2 0xc4 827c478bd9Sstevel@tonic-gate 837c478bd9Sstevel@tonic-gate /* Local Interrupt Vector registers */ 84e3d60c9bSAdrian Frost #define APIC_CMCI_VECT 0xbc 85da2743adSdmick #define APIC_THERM_VECT 0xcc 867c478bd9Sstevel@tonic-gate #define APIC_PCINT_VECT 0xd0 877c478bd9Sstevel@tonic-gate #define APIC_INT_VECT0 0xd4 887c478bd9Sstevel@tonic-gate #define APIC_INT_VECT1 0xd8 897c478bd9Sstevel@tonic-gate #define APIC_ERR_VECT 0xdc 907c478bd9Sstevel@tonic-gate 917c478bd9Sstevel@tonic-gate /* IPL for performance counter interrupts */ 927c478bd9Sstevel@tonic-gate #define APIC_PCINT_IPL 0xe 937c478bd9Sstevel@tonic-gate #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 947c478bd9Sstevel@tonic-gate 957c478bd9Sstevel@tonic-gate /* Initial Count register */ 967c478bd9Sstevel@tonic-gate #define APIC_INIT_COUNT 0xe0 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate /* Current Count Register */ 997c478bd9Sstevel@tonic-gate #define APIC_CURR_COUNT 0xe4 1007c478bd9Sstevel@tonic-gate #define APIC_CURR_ADD 0x39 /* used for remote read command */ 1017c478bd9Sstevel@tonic-gate #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 1027c478bd9Sstevel@tonic-gate 1037c478bd9Sstevel@tonic-gate /* Divider Configuration Register */ 1047c478bd9Sstevel@tonic-gate #define APIC_DIVIDE_REG 0xf8 1057c478bd9Sstevel@tonic-gate 106b6917abeSmishra /* Various mode for local APIC. Modes are mutually exclusive */ 1079b1d70f8SJosef 'Jeff' Sipek typedef enum apic_mode { 1089b1d70f8SJosef 'Jeff' Sipek APIC_IS_DISABLED = 0, 1099b1d70f8SJosef 'Jeff' Sipek APIC_MODE_NOTSET, 1109b1d70f8SJosef 'Jeff' Sipek LOCAL_APIC, 1119b1d70f8SJosef 'Jeff' Sipek LOCAL_X2APIC 1129b1d70f8SJosef 'Jeff' Sipek } apic_mode_t; 113b6917abeSmishra 1145d8efbbcSSaurabh Misra /* x2APIC SELF IPI Register */ 11587cc6269SSaurabh Misra #define X2APIC_SELF_IPI 0xFC 116b6917abeSmishra 117b6917abeSmishra /* General x2APIC constants used at various places */ 118e511d54dSSaurabh Misra #define APIC_SVR_SUPPRESS_BROADCAST_EOI 0x1000 119e511d54dSSaurabh Misra #define APIC_DIRECTED_EOI_BIT 0x1000000 120b6917abeSmishra 121583cd330SHans Rosenfeld /* x2APIC enable bit in REG_APIC_BASE_MSR */ 122583cd330SHans Rosenfeld #define X2APIC_ENABLE_BIT 10 123583cd330SHans Rosenfeld 1247c478bd9Sstevel@tonic-gate /* IRR register */ 1257c478bd9Sstevel@tonic-gate #define APIC_IRR_REG 0x80 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate /* ISR register */ 1287c478bd9Sstevel@tonic-gate #define APIC_ISR_REG 0x40 1297c478bd9Sstevel@tonic-gate 1307c478bd9Sstevel@tonic-gate #define APIC_IO_REG 0x0 1317c478bd9Sstevel@tonic-gate #define APIC_IO_DATA 0x4 132b6917abeSmishra #define APIC_IO_EOI 0x10 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 1357c478bd9Sstevel@tonic-gate #define APIC_ID_BIT_OFFSET 24 1367c478bd9Sstevel@tonic-gate #define APIC_ICR_ID_BIT_OFFSET 24 1377c478bd9Sstevel@tonic-gate #define APIC_LDR_ID_BIT_OFFSET 24 1387c478bd9Sstevel@tonic-gate 1397c478bd9Sstevel@tonic-gate /* 1407c478bd9Sstevel@tonic-gate * Choose between flat and clustered models by writing the following to the 1417c478bd9Sstevel@tonic-gate * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 1427c478bd9Sstevel@tonic-gate * disable logical destination mode. 1437c478bd9Sstevel@tonic-gate * Does not seem to be in the docs for local APICs on the processors. 1447c478bd9Sstevel@tonic-gate */ 1457c478bd9Sstevel@tonic-gate #define APIC_FLAT_MODEL 0xFFFFFFFFUL 1467c478bd9Sstevel@tonic-gate #define APIC_CLUSTER_MODEL 0x0FFFFFFF 1477c478bd9Sstevel@tonic-gate 1487c478bd9Sstevel@tonic-gate /* 1497c478bd9Sstevel@tonic-gate * The commands which follow are window selectors written to APIC_IO_REG 1507c478bd9Sstevel@tonic-gate * before data can be read/written from/to APIC_IO_DATA 1517c478bd9Sstevel@tonic-gate */ 1527c478bd9Sstevel@tonic-gate 1537c478bd9Sstevel@tonic-gate #define APIC_ID_CMD 0x0 1547c478bd9Sstevel@tonic-gate #define APIC_VERS_CMD 0x1 1557c478bd9Sstevel@tonic-gate #define APIC_RDT_CMD 0x10 1567c478bd9Sstevel@tonic-gate #define APIC_RDT_CMD2 0x11 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 1597c478bd9Sstevel@tonic-gate #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 1607c478bd9Sstevel@tonic-gate 1617c478bd9Sstevel@tonic-gate #define APIC_INT_SPURIOUS -1 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 1647c478bd9Sstevel@tonic-gate #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 1657c478bd9Sstevel@tonic-gate #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 1667c478bd9Sstevel@tonic-gate #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 1677c478bd9Sstevel@tonic-gate #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate #define APIC_CT_VECT 0x4ac /* conf table vector */ 1707c478bd9Sstevel@tonic-gate #define APIC_CT_SIZE 1024 /* conf table size */ 1717c478bd9Sstevel@tonic-gate 172*bd97c7ceSRobert Mustacchi #define APIC_ID 'MPAT' /* conf table signature */ 1737c478bd9Sstevel@tonic-gate 174c8589f13Ssethg #define VENID_AMD 0x1022 175c8589f13Ssethg #define DEVID_8131_IOAPIC 0x7451 176c8589f13Ssethg #define DEVID_8132_IOAPIC 0x7459 177c8589f13Ssethg 178c8589f13Ssethg #define IOAPICS_NODE_NAME "ioapics" 179c8589f13Ssethg #define IOAPICS_CHILD_NAME "ioapic" 180c8589f13Ssethg #define IOAPICS_DEV_TYPE "ioapic" 181c8589f13Ssethg #define IOAPICS_PROP_VENID "vendor-id" 182c8589f13Ssethg #define IOAPICS_PROP_DEVID "device-id" 183c8589f13Ssethg 184b6917abeSmishra /* 185b6917abeSmishra * These macros are used in frequently called routines like 186b6917abeSmishra * apic_intr_enter(). 187b6917abeSmishra */ 188b6917abeSmishra #define X2APIC_WRITE(reg, v) \ 189b6917abeSmishra wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v) 190b6917abeSmishra 191b6917abeSmishra #define LOCAL_APIC_WRITE_REG(reg, v) \ 192b6917abeSmishra apicadr[reg] = v 1937c478bd9Sstevel@tonic-gate 1947c478bd9Sstevel@tonic-gate /* 1957c478bd9Sstevel@tonic-gate * MP floating pointer structure defined in Intel MP Spec 1.1 1967c478bd9Sstevel@tonic-gate */ 1977c478bd9Sstevel@tonic-gate struct apic_mpfps_hdr { 1987c478bd9Sstevel@tonic-gate uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 1997c478bd9Sstevel@tonic-gate uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 2007c478bd9Sstevel@tonic-gate uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 2017c478bd9Sstevel@tonic-gate uchar_t mpfps_spec_rev; /* version number of MP spec */ 2027c478bd9Sstevel@tonic-gate uchar_t mpfps_checksum; /* checksum of complete structure */ 2037c478bd9Sstevel@tonic-gate uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 2047c478bd9Sstevel@tonic-gate uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 2057c478bd9Sstevel@tonic-gate uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 2067c478bd9Sstevel@tonic-gate uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 2077c478bd9Sstevel@tonic-gate uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 2087c478bd9Sstevel@tonic-gate }; 2097c478bd9Sstevel@tonic-gate 2107c478bd9Sstevel@tonic-gate #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 2117c478bd9Sstevel@tonic-gate 2127c478bd9Sstevel@tonic-gate #define APIC_MPS_OEM_ID_LEN 8 2137c478bd9Sstevel@tonic-gate #define APIC_MPS_PROD_ID_LEN 12 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate struct apic_mp_cnf_hdr { 2167c478bd9Sstevel@tonic-gate uint_t mpcnf_sig; 2177c478bd9Sstevel@tonic-gate 2187c478bd9Sstevel@tonic-gate uint_t mpcnf_tbl_length: 16, 2197c478bd9Sstevel@tonic-gate mpcnf_spec: 8, 2207c478bd9Sstevel@tonic-gate mpcnf_cksum: 8; 2217c478bd9Sstevel@tonic-gate 2227c478bd9Sstevel@tonic-gate char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 2237c478bd9Sstevel@tonic-gate 2247c478bd9Sstevel@tonic-gate char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate uint_t mpcnf_oem_ptr; 2277c478bd9Sstevel@tonic-gate 2287c478bd9Sstevel@tonic-gate uint_t mpcnf_oem_tbl_size: 16, 2297c478bd9Sstevel@tonic-gate mpcnf_entry_cnt: 16; 2307c478bd9Sstevel@tonic-gate 2317c478bd9Sstevel@tonic-gate uint_t mpcnf_local_apic; 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate uint_t mpcnf_resv; 2347c478bd9Sstevel@tonic-gate }; 2357c478bd9Sstevel@tonic-gate 2367c478bd9Sstevel@tonic-gate struct apic_procent { 2377c478bd9Sstevel@tonic-gate uint_t proc_entry: 8, 2387c478bd9Sstevel@tonic-gate proc_apicid: 8, 2397c478bd9Sstevel@tonic-gate proc_version: 8, 2407c478bd9Sstevel@tonic-gate proc_cpuflags: 8; 2417c478bd9Sstevel@tonic-gate 2427c478bd9Sstevel@tonic-gate uint_t proc_stepping: 4, 2437c478bd9Sstevel@tonic-gate proc_model: 4, 2447c478bd9Sstevel@tonic-gate proc_family: 4, 2457c478bd9Sstevel@tonic-gate proc_type: 2, /* undocumented feature */ 2467c478bd9Sstevel@tonic-gate proc_resv1: 18; 2477c478bd9Sstevel@tonic-gate 2487c478bd9Sstevel@tonic-gate uint_t proc_feature; 2497c478bd9Sstevel@tonic-gate 2507c478bd9Sstevel@tonic-gate uint_t proc_resv2; 2517c478bd9Sstevel@tonic-gate 2527c478bd9Sstevel@tonic-gate uint_t proc_resv3; 2537c478bd9Sstevel@tonic-gate }; 2547c478bd9Sstevel@tonic-gate 2557c478bd9Sstevel@tonic-gate /* 2567c478bd9Sstevel@tonic-gate * proc_cpuflags definitions 2577c478bd9Sstevel@tonic-gate */ 2587c478bd9Sstevel@tonic-gate #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 2597c478bd9Sstevel@tonic-gate #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 2607c478bd9Sstevel@tonic-gate 2617c478bd9Sstevel@tonic-gate 2627c478bd9Sstevel@tonic-gate struct apic_bus { 2637c478bd9Sstevel@tonic-gate uchar_t bus_entry; 2647c478bd9Sstevel@tonic-gate uchar_t bus_id; 2657c478bd9Sstevel@tonic-gate ushort_t bus_str1; 2667c478bd9Sstevel@tonic-gate uint_t bus_str2; 2677c478bd9Sstevel@tonic-gate }; 2687c478bd9Sstevel@tonic-gate 2697c478bd9Sstevel@tonic-gate struct apic_io_entry { 2707c478bd9Sstevel@tonic-gate uint_t io_entry: 8, 2717c478bd9Sstevel@tonic-gate io_apicid: 8, 2727c478bd9Sstevel@tonic-gate io_version: 8, 2737c478bd9Sstevel@tonic-gate io_flags: 8; 2747c478bd9Sstevel@tonic-gate 2757c478bd9Sstevel@tonic-gate uint_t io_apic_addr; 2767c478bd9Sstevel@tonic-gate }; 2777c478bd9Sstevel@tonic-gate 2787c478bd9Sstevel@tonic-gate #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 2797c478bd9Sstevel@tonic-gate 280ae115bc7Smrj #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 2817c478bd9Sstevel@tonic-gate 2827c478bd9Sstevel@tonic-gate struct apic_io_intr { 2837c478bd9Sstevel@tonic-gate uint_t intr_entry: 8, 2847c478bd9Sstevel@tonic-gate intr_type: 8, 2857c478bd9Sstevel@tonic-gate intr_po: 2, 2867c478bd9Sstevel@tonic-gate intr_el: 2, 2877c478bd9Sstevel@tonic-gate intr_resv: 12; 2887c478bd9Sstevel@tonic-gate 2897c478bd9Sstevel@tonic-gate uint_t intr_busid: 8, 2907c478bd9Sstevel@tonic-gate intr_irq: 8, 2917c478bd9Sstevel@tonic-gate intr_destid: 8, 2927c478bd9Sstevel@tonic-gate intr_destintin: 8; 2937c478bd9Sstevel@tonic-gate }; 2947c478bd9Sstevel@tonic-gate 2957c478bd9Sstevel@tonic-gate /* 2967c478bd9Sstevel@tonic-gate * intr_type definitions 2977c478bd9Sstevel@tonic-gate */ 2987c478bd9Sstevel@tonic-gate #define IO_INTR_INT 0x00 2997c478bd9Sstevel@tonic-gate #define IO_INTR_NMI 0x01 3007c478bd9Sstevel@tonic-gate #define IO_INTR_SMI 0x02 3017c478bd9Sstevel@tonic-gate #define IO_INTR_EXTINT 0x03 3027c478bd9Sstevel@tonic-gate 3037c478bd9Sstevel@tonic-gate /* 3047c478bd9Sstevel@tonic-gate * destination APIC ID 3057c478bd9Sstevel@tonic-gate */ 3067c478bd9Sstevel@tonic-gate #define INTR_ALL_APIC 0xff 3077c478bd9Sstevel@tonic-gate 3087c478bd9Sstevel@tonic-gate 3097c478bd9Sstevel@tonic-gate /* local vector table */ 3107c478bd9Sstevel@tonic-gate #define AV_MASK 0x10000 3117c478bd9Sstevel@tonic-gate 3127c478bd9Sstevel@tonic-gate /* interrupt command register 32-63 */ 3137c478bd9Sstevel@tonic-gate #define AV_TOALL 0x7fffffff 3147c478bd9Sstevel@tonic-gate #define AV_HIGH_ORDER 0x40000000 3157c478bd9Sstevel@tonic-gate #define AV_IM_OFF 0x40000000 3167c478bd9Sstevel@tonic-gate 3177c478bd9Sstevel@tonic-gate /* interrupt command register 0-31 */ 318da2743adSdmick #define AV_DELIV_MODE 0x700 319da2743adSdmick 3207c478bd9Sstevel@tonic-gate #define AV_FIXED 0x000 3217c478bd9Sstevel@tonic-gate #define AV_LOPRI 0x100 322da2743adSdmick #define AV_SMI 0x200 3237c478bd9Sstevel@tonic-gate #define AV_REMOTE 0x300 3247c478bd9Sstevel@tonic-gate #define AV_NMI 0x400 3257c478bd9Sstevel@tonic-gate #define AV_RESET 0x500 3267c478bd9Sstevel@tonic-gate #define AV_STARTUP 0x600 3277c478bd9Sstevel@tonic-gate #define AV_EXTINT 0x700 3287c478bd9Sstevel@tonic-gate 3297c478bd9Sstevel@tonic-gate #define AV_PDEST 0x000 3307c478bd9Sstevel@tonic-gate #define AV_LDEST 0x800 3317c478bd9Sstevel@tonic-gate 3327c478bd9Sstevel@tonic-gate /* IO & Local APIC Bit Definitions */ 333e250f1e2Ssethg #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 3347c478bd9Sstevel@tonic-gate #define AV_PENDING 0x1000 3357c478bd9Sstevel@tonic-gate #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 3367c478bd9Sstevel@tonic-gate #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 3377c478bd9Sstevel@tonic-gate #define AV_LEVEL 0x8000 3387c478bd9Sstevel@tonic-gate #define AV_DEASSERT AV_LEVEL 3397c478bd9Sstevel@tonic-gate #define AV_ASSERT 0xc000 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate #define AV_READ_PENDING 0x10000 3427c478bd9Sstevel@tonic-gate #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 3437c478bd9Sstevel@tonic-gate 3447c478bd9Sstevel@tonic-gate #define AV_SH_SELF 0x40000 /* Short hand for self */ 3457c478bd9Sstevel@tonic-gate #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 3467c478bd9Sstevel@tonic-gate #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 3477c478bd9Sstevel@tonic-gate /* spurious interrupt vector register */ 3487c478bd9Sstevel@tonic-gate #define AV_UNIT_ENABLE 0x100 3497c478bd9Sstevel@tonic-gate 3507c478bd9Sstevel@tonic-gate #define APIC_MAXVAL 0xffffffffUL 3517c478bd9Sstevel@tonic-gate #define APIC_TIME_MIN 0x5000 3527c478bd9Sstevel@tonic-gate #define APIC_TIME_COUNT 0x4000 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate /* 3557c478bd9Sstevel@tonic-gate * Range of the low byte value in apic_tick before starting calibration 3567c478bd9Sstevel@tonic-gate */ 3577c478bd9Sstevel@tonic-gate #define APIC_LB_MIN 0x60 3587c478bd9Sstevel@tonic-gate #define APIC_LB_MAX 0xe0 3597c478bd9Sstevel@tonic-gate 3607c478bd9Sstevel@tonic-gate #define APIC_MAX_VECTOR 255 3617c478bd9Sstevel@tonic-gate #define APIC_RESV_VECT 0x00 3627c478bd9Sstevel@tonic-gate #define APIC_RESV_IRQ 0xfe 3637c478bd9Sstevel@tonic-gate #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 3647c478bd9Sstevel@tonic-gate #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 3657c478bd9Sstevel@tonic-gate #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 3667c478bd9Sstevel@tonic-gate #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 3677c478bd9Sstevel@tonic-gate #define APIC_VECTOR_MASK 0x0f 3687c478bd9Sstevel@tonic-gate #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 3697c478bd9Sstevel@tonic-gate #define APIC_IPL_MASK 0xf0 3707c478bd9Sstevel@tonic-gate #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 3717c478bd9Sstevel@tonic-gate #define APIC_FIRST_FREE_IRQ 0x10 3727c478bd9Sstevel@tonic-gate #define APIC_MAX_ISA_IRQ 15 3737c478bd9Sstevel@tonic-gate #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 3747c478bd9Sstevel@tonic-gate #define APIC_IDLE_IPL 0x00 3757c478bd9Sstevel@tonic-gate 3767c478bd9Sstevel@tonic-gate #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 3777c478bd9Sstevel@tonic-gate 3787c478bd9Sstevel@tonic-gate /* spurious interrupt vector */ 3797c478bd9Sstevel@tonic-gate #define APIC_SPUR_INTR 0xFF 3807c478bd9Sstevel@tonic-gate 3810ccf9e79Sjohnny /* special or reserve vectors */ 3820ccf9e79Sjohnny #define APIC_CHECK_RESERVE_VECTORS(v) \ 383a7639048Sjohnny (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 384eb5a5c78SSurya Prakki ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET)) 3850ccf9e79Sjohnny 3867c478bd9Sstevel@tonic-gate /* cmos shutdown code for BIOS */ 3877c478bd9Sstevel@tonic-gate #define BIOS_SHUTDOWN 0x0a 3887c478bd9Sstevel@tonic-gate 3897c478bd9Sstevel@tonic-gate /* define the entry types for BIOS information tables as defined in PC+MP */ 3907c478bd9Sstevel@tonic-gate #define APIC_CPU_ENTRY 0 3917c478bd9Sstevel@tonic-gate #define APIC_BUS_ENTRY 1 3927c478bd9Sstevel@tonic-gate #define APIC_IO_ENTRY 2 3937c478bd9Sstevel@tonic-gate #define APIC_IO_INTR_ENTRY 3 3947c478bd9Sstevel@tonic-gate #define APIC_LOCAL_INTR_ENTRY 4 3957c478bd9Sstevel@tonic-gate #define APIC_MPTBL_ADDR (639 * 1024) 3967c478bd9Sstevel@tonic-gate /* 3977c478bd9Sstevel@tonic-gate * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 3987c478bd9Sstevel@tonic-gate * of system base memory or in ROM between 0xF0000 and 0xFFFFF 3997c478bd9Sstevel@tonic-gate */ 4007c478bd9Sstevel@tonic-gate #define MPFPS_RAM_WIN_LEN 1024 4017c478bd9Sstevel@tonic-gate #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 4027c478bd9Sstevel@tonic-gate #define MPFPS_ROM_WIN_LEN 0x10000 4037c478bd9Sstevel@tonic-gate 4047c478bd9Sstevel@tonic-gate #define EISA_LEVEL_CNTL 0x4D0 4057c478bd9Sstevel@tonic-gate 4067c478bd9Sstevel@tonic-gate /* definitions for apic_irq_table */ 4077c478bd9Sstevel@tonic-gate #define FREE_INDEX (short)-1 /* empty slot */ 4087c478bd9Sstevel@tonic-gate #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 4097c478bd9Sstevel@tonic-gate #define ACPI_INDEX (short)-3 /* ACPI */ 4107c478bd9Sstevel@tonic-gate #define MSI_INDEX (short)-4 /* MSI */ 4117c478bd9Sstevel@tonic-gate #define MSIX_INDEX (short)-5 /* MSI-X */ 4127c478bd9Sstevel@tonic-gate #define DEFAULT_INDEX (short)0x7FFF 4137c478bd9Sstevel@tonic-gate /* biggest positive no. to avoid conflict with actual index */ 4147c478bd9Sstevel@tonic-gate 4157c478bd9Sstevel@tonic-gate #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 4167c478bd9Sstevel@tonic-gate ((index) == MSI_INDEX || (index) == MSIX_INDEX) 4177c478bd9Sstevel@tonic-gate 4187c478bd9Sstevel@tonic-gate /* 4197c478bd9Sstevel@tonic-gate * definitions for MSI Address 4207c478bd9Sstevel@tonic-gate */ 4217c478bd9Sstevel@tonic-gate #define MSI_ADDR_HDR APIC_LOCAL_ADDR 4227c478bd9Sstevel@tonic-gate #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 4237c478bd9Sstevel@tonic-gate #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 4247c478bd9Sstevel@tonic-gate #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 4257c478bd9Sstevel@tonic-gate #define MSI_ADDR_RH_SHIFT 3 4267c478bd9Sstevel@tonic-gate #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 4277c478bd9Sstevel@tonic-gate #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 4287c478bd9Sstevel@tonic-gate #define MSI_ADDR_DM_SHIFT 2 4297c478bd9Sstevel@tonic-gate 430e511d54dSSaurabh Misra /* 431e511d54dSSaurabh Misra * TM is either edge or level. 432e511d54dSSaurabh Misra */ 433e511d54dSSaurabh Misra #define TRIGGER_MODE_EDGE 0x0 /* edge sensitive */ 434e511d54dSSaurabh Misra #define TRIGGER_MODE_LEVEL 0x1 /* level sensitive */ 435e511d54dSSaurabh Misra 4367c478bd9Sstevel@tonic-gate /* 4377c478bd9Sstevel@tonic-gate * definitions for MSI Data 4387c478bd9Sstevel@tonic-gate */ 4397c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 4407c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 4417c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_SMI 0x2 4427c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_NMI 0x4 4437c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_INIT 0x5 4447c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_EXTINT 0x7 4457c478bd9Sstevel@tonic-gate #define MSI_DATA_DELIVERY_SHIFT 8 446e511d54dSSaurabh Misra #define MSI_DATA_TM_EDGE TRIGGER_MODE_EDGE 447e511d54dSSaurabh Misra #define MSI_DATA_TM_LEVEL TRIGGER_MODE_LEVEL 4487c478bd9Sstevel@tonic-gate #define MSI_DATA_TM_SHIFT 15 4497c478bd9Sstevel@tonic-gate #define MSI_DATA_LEVEL_DEASSERT 0x0 4507c478bd9Sstevel@tonic-gate #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 4517c478bd9Sstevel@tonic-gate #define MSI_DATA_LEVEL_SHIFT 14 4527c478bd9Sstevel@tonic-gate 4537c478bd9Sstevel@tonic-gate /* 4547c478bd9Sstevel@tonic-gate * use to define each irq setup by the apic 4557c478bd9Sstevel@tonic-gate */ 4567c478bd9Sstevel@tonic-gate typedef struct apic_irq { 4577c478bd9Sstevel@tonic-gate short airq_mps_intr_index; /* index into mps interrupt entries */ 4587c478bd9Sstevel@tonic-gate /* table */ 4597c478bd9Sstevel@tonic-gate uchar_t airq_intin_no; 4607c478bd9Sstevel@tonic-gate uchar_t airq_ioapicindex; 4617c478bd9Sstevel@tonic-gate dev_info_t *airq_dip; /* device corresponding to this interrupt */ 4627c478bd9Sstevel@tonic-gate /* 4637c478bd9Sstevel@tonic-gate * IRQ could be shared (in H/W) in which case dip & major will be 4647c478bd9Sstevel@tonic-gate * for the one that was last added at this level. We cannot keep a 4657c478bd9Sstevel@tonic-gate * linked list as delspl does not tell us which device has just 4667c478bd9Sstevel@tonic-gate * been unloaded. For most servers where we are worried about 4677c478bd9Sstevel@tonic-gate * performance, interrupt should not be shared & should not be 4687c478bd9Sstevel@tonic-gate * a problem. This does not cause any correctness issue - dip is 4697c478bd9Sstevel@tonic-gate * used only as an optimisation to avoid going thru all the tables 4707c478bd9Sstevel@tonic-gate * in translate IRQ (which is always called twice due to brokenness 4717c478bd9Sstevel@tonic-gate * in the way IPLs are determined for devices). major is used only 4727c478bd9Sstevel@tonic-gate * to bind interrupts corresponding to the same device on the same 4737c478bd9Sstevel@tonic-gate * CPU. Not finding major will just cause it to be potentially bound 4747c478bd9Sstevel@tonic-gate * to another CPU. 4757c478bd9Sstevel@tonic-gate */ 4767c478bd9Sstevel@tonic-gate major_t airq_major; /* major number corresponding to the device */ 477ae115bc7Smrj ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 4784e30c628SEvan Yan uint32_t airq_cpu; /* target CPU, non-reserved IRQ only */ 4794e30c628SEvan Yan uint32_t airq_temp_cpu; /* non-reserved IRQ only, for disable_intr */ 4807c478bd9Sstevel@tonic-gate uchar_t airq_vector; /* Vector chosen for this irq */ 4817c478bd9Sstevel@tonic-gate uchar_t airq_share; /* number of interrupts at this irq */ 4827c478bd9Sstevel@tonic-gate uchar_t airq_share_id; /* id to identify source from irqno */ 4837c478bd9Sstevel@tonic-gate uchar_t airq_ipl; /* The ipl at which this is handled */ 4847c478bd9Sstevel@tonic-gate iflag_t airq_iflag; /* interrupt flag */ 4857c478bd9Sstevel@tonic-gate uchar_t airq_origirq; /* original irq passed in */ 4867c478bd9Sstevel@tonic-gate uint_t airq_busy; /* How frequently did clock find */ 4877c478bd9Sstevel@tonic-gate /* us in this */ 48886a9c507SGuoli Shu struct apic_irq *airq_next; /* chain of intpts sharing a vector */ 4893a634bfcSVikram Hegde void *airq_intrmap_private; /* intr remap private data */ 4907c478bd9Sstevel@tonic-gate } apic_irq_t; 4917c478bd9Sstevel@tonic-gate 492b6917abeSmishra #define IRQ_USER_BOUND 0x80000000 /* user requested bind if set in airq_cpu */ 493b6917abeSmishra #define IRQ_UNBOUND (uint32_t)-1 /* set in airq_cpu and airq_temp_cpu */ 494b6917abeSmishra #define IRQ_UNINIT (uint32_t)-2 /* in airq_temp_cpu till addspl called */ 4957c478bd9Sstevel@tonic-gate 4967c478bd9Sstevel@tonic-gate /* Macros to help deal with shared interrupts */ 4977c478bd9Sstevel@tonic-gate #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 4987c478bd9Sstevel@tonic-gate #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 4997c478bd9Sstevel@tonic-gate 50078a542e2SSaurabh Misra /* 50178a542e2SSaurabh Misra * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we 50278a542e2SSaurabh Misra * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also 50378a542e2SSaurabh Misra * don't want the compiler to optimize apic_cpus_info. 50478a542e2SSaurabh Misra */ 505a3114836SGerry Liu #define APIC_PADSZ 15 50678a542e2SSaurabh Misra 50778a542e2SSaurabh Misra #pragma pack(1) 5087c478bd9Sstevel@tonic-gate typedef struct apic_cpus_info { 509b6917abeSmishra uint32_t aci_local_id; 5107c478bd9Sstevel@tonic-gate uchar_t aci_local_ver; 5117c478bd9Sstevel@tonic-gate uchar_t aci_status; 5127c478bd9Sstevel@tonic-gate uchar_t aci_redistribute; /* Selected for redistribution */ 5137c478bd9Sstevel@tonic-gate uint_t aci_busy; /* Number of ticks we were in ISR */ 5147c478bd9Sstevel@tonic-gate uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 5157c478bd9Sstevel@tonic-gate uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 5167c478bd9Sstevel@tonic-gate uchar_t aci_curipl; /* IPL of current ISR */ 5177c478bd9Sstevel@tonic-gate uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 5187c478bd9Sstevel@tonic-gate uint32_t aci_bound; /* # of user requested binds ? */ 5197c478bd9Sstevel@tonic-gate uint32_t aci_temp_bound; /* # of non user IRQ binds */ 520a3114836SGerry Liu uint32_t aci_processor_id; /* Only used in ACPI mode. */ 5217c478bd9Sstevel@tonic-gate uchar_t aci_idle; /* The CPU is idle */ 5227c478bd9Sstevel@tonic-gate /* 52378a542e2SSaurabh Misra * Fill to make sure each struct is in separate 64-byte cache line. 5247c478bd9Sstevel@tonic-gate */ 52578a542e2SSaurabh Misra uchar_t aci_pad[APIC_PADSZ]; /* padding for 64-byte cache line */ 5267c478bd9Sstevel@tonic-gate } apic_cpus_info_t; 52778a542e2SSaurabh Misra #pragma pack() 5287c478bd9Sstevel@tonic-gate 5297ff178cdSJimmy Vetayases #define APIC_CPU_ONLINE 0x1 5307ff178cdSJimmy Vetayases #define APIC_CPU_INTR_ENABLE 0x2 5317ff178cdSJimmy Vetayases #define APIC_CPU_FREE 0x4 /* APIC CPU slot is free */ 5327ff178cdSJimmy Vetayases #define APIC_CPU_DIRTY 0x8 /* Slot was once used */ 5337ff178cdSJimmy Vetayases #define APIC_CPU_SUSPEND 0x10 5347c478bd9Sstevel@tonic-gate 535b6917abeSmishra /* 536b6917abeSmishra * APIC ops to support various flavors of APIC like APIC and x2APIC. 537b6917abeSmishra */ 538b6917abeSmishra typedef struct apic_regs_ops { 539b6917abeSmishra uint64_t (*apic_read)(uint32_t); 540*bd97c7ceSRobert Mustacchi void (*apic_write)(uint32_t, uint64_t); 541b6917abeSmishra int (*apic_get_pri)(void); 542b6917abeSmishra void (*apic_write_task_reg)(uint64_t); 543b6917abeSmishra void (*apic_write_int_cmd)(uint32_t, uint32_t); 544b6917abeSmishra void (*apic_send_eoi)(uint32_t); 545b6917abeSmishra } apic_reg_ops_t; 546b6917abeSmishra 547bb8220baSVikram Hegde /* 548bb8220baSVikram Hegde * interrupt structure for ioapic and msi 549bb8220baSVikram Hegde */ 550bb8220baSVikram Hegde typedef struct ioapic_rdt { 551bb8220baSVikram Hegde uint32_t ir_lo; 552bb8220baSVikram Hegde uint32_t ir_hi; 553bb8220baSVikram Hegde } ioapic_rdt_t; 554bb8220baSVikram Hegde 555bb8220baSVikram Hegde typedef struct msi_regs { 556bb8220baSVikram Hegde uint32_t mr_data; 557bb8220baSVikram Hegde uint64_t mr_addr; 558bb8220baSVikram Hegde }msi_regs_t; 559bb8220baSVikram Hegde 560bb8220baSVikram Hegde /* 561bb8220baSVikram Hegde * APIC ops to support intel interrupt remapping 562bb8220baSVikram Hegde */ 5633a634bfcSVikram Hegde typedef struct apic_intrmap_ops { 5643a634bfcSVikram Hegde int (*apic_intrmap_init)(int); 5653a634bfcSVikram Hegde void (*apic_intrmap_enable)(int); 5667ff178cdSJimmy Vetayases void (*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t, 5677ff178cdSJimmy Vetayases int, uchar_t); 5687ff178cdSJimmy Vetayases void (*apic_intrmap_map_entry)(void *, void *, uint16_t, int); 5697ff178cdSJimmy Vetayases void (*apic_intrmap_free_entry)(void **); 5707ff178cdSJimmy Vetayases void (*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *); 5717ff178cdSJimmy Vetayases void (*apic_intrmap_record_msi)(void *, msi_regs_t *); 5723a634bfcSVikram Hegde } apic_intrmap_ops_t; 573bb8220baSVikram Hegde 5747c478bd9Sstevel@tonic-gate /* 5757c478bd9Sstevel@tonic-gate * Various poweroff methods and ports & bits for them 5767c478bd9Sstevel@tonic-gate */ 5777c478bd9Sstevel@tonic-gate #define APIC_POWEROFF_NONE 0 5787c478bd9Sstevel@tonic-gate #define APIC_POWEROFF_VIA_RTC 1 5797c478bd9Sstevel@tonic-gate #define APIC_POWEROFF_VIA_ASPEN_BMC 2 5807c478bd9Sstevel@tonic-gate #define APIC_POWEROFF_VIA_SITKA_BMC 3 5817c478bd9Sstevel@tonic-gate 5827c478bd9Sstevel@tonic-gate /* For RTC */ 5837c478bd9Sstevel@tonic-gate #define RTC_REGA 0x0a 5847c478bd9Sstevel@tonic-gate #define PFR_REG 0x4a /* extended control register */ 5857c478bd9Sstevel@tonic-gate #define PAB_CBIT 0x08 5867c478bd9Sstevel@tonic-gate #define WF_FLAG 0x02 5877c478bd9Sstevel@tonic-gate #define KS_FLAG 0x01 5887c478bd9Sstevel@tonic-gate #define EXT_BANK 0x10 5897c478bd9Sstevel@tonic-gate 5907c478bd9Sstevel@tonic-gate /* For Aspen/Drake BMC */ 5917c478bd9Sstevel@tonic-gate 5927c478bd9Sstevel@tonic-gate #define CC_SMS_GET_STATUS 0x40 5937c478bd9Sstevel@tonic-gate #define CC_SMS_WR_START 0x41 5947c478bd9Sstevel@tonic-gate #define CC_SMS_WR_NEXT 0x42 5957c478bd9Sstevel@tonic-gate #define CC_SMS_WR_END 0x43 5967c478bd9Sstevel@tonic-gate 5977c478bd9Sstevel@tonic-gate #define MISMIC_DATA_REGISTER 0x0ca9 5987c478bd9Sstevel@tonic-gate #define MISMIC_CNTL_REGISTER 0x0caa 5997c478bd9Sstevel@tonic-gate #define MISMIC_FLAG_REGISTER 0x0cab 6007c478bd9Sstevel@tonic-gate 6017c478bd9Sstevel@tonic-gate #define MISMIC_BUSY_MASK 0x01 6027c478bd9Sstevel@tonic-gate 6037c478bd9Sstevel@tonic-gate /* For Sitka/Cabrillo BMC */ 6047c478bd9Sstevel@tonic-gate 6057c478bd9Sstevel@tonic-gate #define SMS_GET_STATUS 0x60 6067c478bd9Sstevel@tonic-gate #define SMS_WRITE_START 0x61 6077c478bd9Sstevel@tonic-gate #define SMS_WRITE_END 0x62 6087c478bd9Sstevel@tonic-gate 6097c478bd9Sstevel@tonic-gate #define SMS_DATA_REGISTER 0x0ca2 6107c478bd9Sstevel@tonic-gate #define SMS_STATUS_REGISTER 0x0ca3 6117c478bd9Sstevel@tonic-gate #define SMS_COMMAND_REGISTER 0x0ca3 6127c478bd9Sstevel@tonic-gate 6137c478bd9Sstevel@tonic-gate #define SMS_IBF_MASK 0x02 6147c478bd9Sstevel@tonic-gate #define SMS_STATE_MASK 0xc0 6157c478bd9Sstevel@tonic-gate 6167c478bd9Sstevel@tonic-gate #define SMS_IDLE_STATE 0x00 6177c478bd9Sstevel@tonic-gate #define SMS_READ_STATE 0x40 6187c478bd9Sstevel@tonic-gate #define SMS_WRITE_STATE 0x80 6197c478bd9Sstevel@tonic-gate #define SMS_ERROR_STATE 0xc0 6207c478bd9Sstevel@tonic-gate 621ae115bc7Smrj extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 622ae115bc7Smrj extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 623b6917abeSmishra extern void ioapic_write_eoi(int ioapic_ix, uint32_t value); 624ae115bc7Smrj 6257c478bd9Sstevel@tonic-gate /* Macros for reading/writing the IOAPIC RDT entries */ 626ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 627ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 6287c478bd9Sstevel@tonic-gate 629ae115bc7Smrj #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 630ae115bc7Smrj ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 6317c478bd9Sstevel@tonic-gate 632ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 633ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 6347c478bd9Sstevel@tonic-gate 635ae115bc7Smrj #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 636ae115bc7Smrj ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 6377c478bd9Sstevel@tonic-gate 6387a364d25Sschwartz /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 6397a364d25Sschwartz typedef struct { 6407a364d25Sschwartz uint16_t avgi_req_flags; /* request flags - to kernel */ 6417a364d25Sschwartz uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 6427a364d25Sschwartz uint8_t avgi_vector; /* vector */ 6437a364d25Sschwartz uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 6447a364d25Sschwartz dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 6457a364d25Sschwartz /* Contains num_devs elements. */ 6467a364d25Sschwartz } apic_get_intr_t; 6477a364d25Sschwartz 6487ff178cdSJimmy Vetayases /* Used by PSM_INTR_OP_GET_TYPE to return platform information. */ 6497ff178cdSJimmy Vetayases typedef struct { 6507ff178cdSJimmy Vetayases char *avgi_type; /* platform type - from kernel */ 6517ff178cdSJimmy Vetayases uint32_t avgi_num_intr; /* max intr number - from kernel */ 6527ff178cdSJimmy Vetayases uint32_t avgi_num_cpu; /* max cpu number - from kernel */ 6537ff178cdSJimmy Vetayases } apic_get_type_t; 6547ff178cdSJimmy Vetayases 6557a364d25Sschwartz /* Masks for avgi_req_flags. */ 6567a364d25Sschwartz #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 6577a364d25Sschwartz #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 6587a364d25Sschwartz #define PSMGI_REQ_VECTOR 0x4 6597a364d25Sschwartz #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 6607a364d25Sschwartz #define PSMGI_REQ_ALL 0xf /* Request everything */ 6617a364d25Sschwartz 6627a364d25Sschwartz /* Other flags */ 6637a364d25Sschwartz #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 6647a364d25Sschwartz #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 6657ff178cdSJimmy Vetayases #define PSMGI_INTRBY_DEFAULT 0x4000 /* PSM specific default value */ 6667ff178cdSJimmy Vetayases #define PSMGI_INTRBY_FLAGS 0xc000 /* Mask for this flag */ 6677a364d25Sschwartz 668ae115bc7Smrj extern int apic_verbose; 669ae115bc7Smrj 670ae115bc7Smrj /* Flag definitions for apic_verbose */ 671ae115bc7Smrj #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 672ae115bc7Smrj #define APIC_VERBOSE_IRQ_FLAG 0x00000002 673ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 674ae115bc7Smrj #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 6757ff178cdSJimmy Vetayases #define APIC_VERBOSE_INIT 0x00000010 6767ff178cdSJimmy Vetayases #define APIC_VERBOSE_REBIND 0x00000020 6777ff178cdSJimmy Vetayases #define APIC_VERBOSE_ALLOC 0x00000040 6787ff178cdSJimmy Vetayases #define APIC_VERBOSE_IPI 0x00000080 6797ff178cdSJimmy Vetayases #define APIC_VERBOSE_INTR 0x00000100 680ae115bc7Smrj 6817ff178cdSJimmy Vetayases /* required test to wait until APIC command is sent on the bus */ 6825d8efbbcSSaurabh Misra #define APIC_AV_PENDING_SET() \ 6835d8efbbcSSaurabh Misra while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \ 6845d8efbbcSSaurabh Misra apic_ret(); 6855d8efbbcSSaurabh Misra 6867ff178cdSJimmy Vetayases #ifdef DEBUG 687ae115bc7Smrj 688ae115bc7Smrj #define DENT 0x0001 689ae115bc7Smrj extern int apic_debug; 690ae115bc7Smrj /* 691ae115bc7Smrj * set apic_restrict_vector to the # of vectors we want to allow per range 692ae115bc7Smrj * useful in testing shared interrupt logic by setting it to 2 or 3 693ae115bc7Smrj */ 694ae115bc7Smrj extern int apic_restrict_vector; 695ae115bc7Smrj 696ae115bc7Smrj #define APIC_DEBUG_MSGBUFSIZE 2048 697ae115bc7Smrj extern int apic_debug_msgbuf[]; 698ae115bc7Smrj extern int apic_debug_msgbufindex; 699ae115bc7Smrj 700ae115bc7Smrj /* 701ae115bc7Smrj * Put "int" info into debug buffer. No MP consistency, but light weight. 702ae115bc7Smrj * Good enough for most debugging. 703ae115bc7Smrj */ 704ae115bc7Smrj #define APIC_DEBUG_BUF_PUT(x) \ 705ae115bc7Smrj apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 706ae115bc7Smrj if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 707ae115bc7Smrj apic_debug_msgbufindex = 0; 708ae115bc7Smrj 7097ff178cdSJimmy Vetayases #define APIC_VERBOSE(flag, fmt) \ 7107ff178cdSJimmy Vetayases if (apic_verbose & APIC_VERBOSE_##flag) \ 7117ff178cdSJimmy Vetayases cmn_err fmt; 7127ff178cdSJimmy Vetayases 7137ff178cdSJimmy Vetayases #define APIC_VERBOSE_POWEROFF(fmt) \ 7147ff178cdSJimmy Vetayases if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 7157ff178cdSJimmy Vetayases prom_printf fmt; 7167ff178cdSJimmy Vetayases 7177ff178cdSJimmy Vetayases #else /* DEBUG */ 7187ff178cdSJimmy Vetayases 7197ff178cdSJimmy Vetayases #define APIC_VERBOSE(flag, fmt) 7207ff178cdSJimmy Vetayases #define APIC_VERBOSE_POWEROFF(fmt) 7217ff178cdSJimmy Vetayases 7227ff178cdSJimmy Vetayases #endif /* DEBUG */ 7237ff178cdSJimmy Vetayases 7247ff178cdSJimmy Vetayases #define APIC_VERBOSE_IOAPIC(fmt) APIC_VERBOSE(IOAPIC_FLAG, fmt) 7257ff178cdSJimmy Vetayases #define APIC_VERBOSE_IRQ(fmt) APIC_VERBOSE(IRQ_FLAG, fmt) 726ae115bc7Smrj 727ae115bc7Smrj extern int apic_error; 728ae115bc7Smrj /* values which apic_error can take. Not catastrophic, but may help debug */ 729ae115bc7Smrj #define APIC_ERR_BOOT_EOI 0x1 730ae115bc7Smrj #define APIC_ERR_GET_IPIVECT_FAIL 0x2 731ae115bc7Smrj #define APIC_ERR_INVALID_INDEX 0x4 732ae115bc7Smrj #define APIC_ERR_MARK_VECTOR_FAIL 0x8 733ae115bc7Smrj #define APIC_ERR_APIC_ERROR 0x40000000 734ae115bc7Smrj #define APIC_ERR_NMI 0x80000000 735ae115bc7Smrj 736ae115bc7Smrj /* 737ae115bc7Smrj * ACPI definitions 738ae115bc7Smrj */ 739ae115bc7Smrj /* _PIC method arguments */ 740ae115bc7Smrj #define ACPI_PIC_MODE 0 741ae115bc7Smrj #define ACPI_APIC_MODE 1 742ae115bc7Smrj 743ae115bc7Smrj /* APIC error flags we care about */ 744ae115bc7Smrj #define APIC_SEND_CS_ERROR 0x01 745ae115bc7Smrj #define APIC_RECV_CS_ERROR 0x02 746ae115bc7Smrj #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 747ae115bc7Smrj 748ae115bc7Smrj /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 749ae115bc7Smrj #define APIC_REPROGRAM_MAX_TRIES 10000 750ae115bc7Smrj 751ae115bc7Smrj /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 752ae115bc7Smrj #define IOAPIC_MASK 1 753ae115bc7Smrj #define IOAPIC_NOMASK 0 754ae115bc7Smrj 755ae115bc7Smrj #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 756ae115bc7Smrj #define INTR_ROUND_ROBIN 1 757ae115bc7Smrj #define INTR_LOWEST_PRIORITY 2 758ae115bc7Smrj 759ae115bc7Smrj struct ioapic_reprogram_data { 760ae115bc7Smrj boolean_t done; 761ae115bc7Smrj apic_irq_t *irqp; 762ae115bc7Smrj /* The CPU to which the int will be bound */ 763ae115bc7Smrj int bindcpu; 764ae115bc7Smrj /* # times the reprogram timeout was called */ 765ae115bc7Smrj unsigned tries; 766ae115bc7Smrj }; 767ae115bc7Smrj 768ae115bc7Smrj /* The irq # is implicit in the array index: */ 769ae115bc7Smrj extern struct ioapic_reprogram_data apic_reprogram_info[]; 770ae115bc7Smrj 771ae115bc7Smrj extern void apic_intr_exit(int ipl, int irq); 772b6917abeSmishra extern void x2apic_intr_exit(int ipl, int irq); 773ae115bc7Smrj extern int apic_probe_common(); 774ae115bc7Smrj extern void apic_init_common(); 775ae115bc7Smrj extern void ioapic_init_intr(); 776ae115bc7Smrj extern void ioapic_disable_redirection(); 777ae115bc7Smrj extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 778ae115bc7Smrj extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 779ae115bc7Smrj extern void apic_cleanup_busy(); 780ae115bc7Smrj extern void apic_intr_redistribute(); 781ae115bc7Smrj extern uchar_t apic_xlate_vector(uchar_t vector); 782ae115bc7Smrj extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 783ae115bc7Smrj extern void apic_free_vector(uchar_t vector); 784ae115bc7Smrj extern int apic_allocate_irq(int irq); 785b6917abeSmishra extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 786ae115bc7Smrj uchar_t intin); 787ae115bc7Smrj extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 788ae115bc7Smrj struct ioapic_reprogram_data *drep); 789ae115bc7Smrj extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 790ae115bc7Smrj extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 791ae115bc7Smrj extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 792ae115bc7Smrj psm_intr_op_t intr_op, int *result); 7932df1fe9cSrandyf extern int apic_state(psm_state_request_t *); 794e250f1e2Ssethg extern boolean_t apic_cpu_in_range(int cpu); 795ae115bc7Smrj extern int apic_check_msi_support(); 796ae115bc7Smrj extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 797ae115bc7Smrj int type); 798ae115bc7Smrj extern int apic_navail_vector(dev_info_t *dip, int pri); 799a7639048Sjohnny extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 800a7639048Sjohnny int pri, int behavior); 801a7639048Sjohnny extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 802a7639048Sjohnny int pri, int behavior); 803ae115bc7Smrj extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 804ae115bc7Smrj int type); 805843e1988Sjohnlev extern int apic_get_vector_intr_info(int vecirq, 806843e1988Sjohnlev apic_get_intr_t *intr_params_p); 807ae115bc7Smrj extern uchar_t apic_find_multi_vectors(int pri, int count); 808ae115bc7Smrj extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 809ae115bc7Smrj extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 810ae115bc7Smrj extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 811ae115bc7Smrj extern void mapout_apic(caddr_t addr, size_t len); 812ae115bc7Smrj extern void mapout_ioapic(caddr_t addr, size_t len); 813ae115bc7Smrj extern uchar_t apic_modify_vector(uchar_t vector, int irq); 814a7639048Sjohnny extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 815a7639048Sjohnny extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 816a7639048Sjohnny extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 817bb8220baSVikram Hegde extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum, 818a7639048Sjohnny int vector, int count, int target_apic_id); 8192917a9c9Sschwartz extern char *apic_get_apic_type(); 8202917a9c9Sschwartz extern uint16_t apic_get_apic_version(); 821b6917abeSmishra extern void x2apic_send_ipi(); 822b6917abeSmishra extern void apic_ret(); 823b6917abeSmishra extern int apic_detect_x2apic(); 824b6917abeSmishra extern void apic_enable_x2apic(); 825325e77f4SSaurabh Misra extern int apic_local_mode(); 826b6917abeSmishra extern void apic_change_eoi(); 827b6917abeSmishra extern void apic_send_EOI(uint32_t); 828b6917abeSmishra extern void apic_send_directed_EOI(uint32_t); 829e8763682SPavel Zakharov extern uint64_t apic_calibrate(); 8301c2d0470SPatrick Mooney extern void x2apic_send_pir_ipi(processorid_t); 831ae115bc7Smrj 832ae115bc7Smrj extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 833ae115bc7Smrj extern int apic_forceload; 834ae115bc7Smrj extern apic_cpus_info_t *apic_cpus; 835c8589f13Ssethg #ifdef _MACHDEP 836ae115bc7Smrj extern cpuset_t apic_cpumask; 837c8589f13Ssethg #endif 838843e1988Sjohnlev extern uint_t apic_picinit_called; 839ae115bc7Smrj extern uchar_t apic_ipltopri[MAXIPL+1]; 840ae115bc7Smrj extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 841ae115bc7Smrj extern int apic_max_device_irq; 842ae115bc7Smrj extern int apic_min_device_irq; 843ae115bc7Smrj extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 844ae115bc7Smrj extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 845ae115bc7Smrj extern uchar_t apic_io_id[MAX_IO_APIC]; 846ae115bc7Smrj extern lock_t apic_ioapic_lock; 847ae115bc7Smrj extern uint32_t apic_physaddr[MAX_IO_APIC]; 848ae115bc7Smrj extern kmutex_t airq_mutex; 849ae115bc7Smrj extern int apic_first_avail_irq; 850ae115bc7Smrj extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 851ae115bc7Smrj extern int apic_imcrp; 852ae115bc7Smrj extern int apic_revector_pending; 853ae115bc7Smrj extern char apic_level_intr[APIC_MAX_VECTOR+1]; 854ae115bc7Smrj extern uchar_t apic_resv_vector[MAXIPL+1]; 855ae115bc7Smrj extern int apic_sample_factor_redistribution; 856ae115bc7Smrj extern int apic_int_busy_mark; 857ae115bc7Smrj extern int apic_int_free_mark; 858ae115bc7Smrj extern int apic_diff_for_redistribution; 859ae115bc7Smrj extern int apic_poweroff_method; 860ae115bc7Smrj extern int apic_enable_acpi; 861ae115bc7Smrj extern int apic_nproc; 862a3114836SGerry Liu extern int apic_max_nproc; 863ae115bc7Smrj extern int apic_next_bind_cpu; 864ae115bc7Smrj extern int apic_redistribute_sample_interval; 865ae115bc7Smrj extern int apic_multi_msi_enable; 866ae115bc7Smrj extern int apic_sci_vect; 8677ff178cdSJimmy Vetayases extern int apic_hpet_vect; 868c8589f13Ssethg extern uchar_t apic_ipls[]; 869b6917abeSmishra extern apic_reg_ops_t *apic_reg_ops; 870583cd330SHans Rosenfeld extern apic_reg_ops_t local_apic_regs_ops; 8719b1d70f8SJosef 'Jeff' Sipek extern apic_mode_t apic_mode; 872b6917abeSmishra extern void x2apic_update_psm(); 873325e77f4SSaurabh Misra extern void apic_change_ops(); 874325e77f4SSaurabh Misra extern void apic_common_send_ipi(int, int); 875e511d54dSSaurabh Misra extern void apic_set_directed_EOI_handler(); 876e511d54dSSaurabh Misra extern int apic_directed_EOI_supported(); 8771c2d0470SPatrick Mooney extern void apic_common_send_pir_ipi(processorid_t); 878ae115bc7Smrj 8793a634bfcSVikram Hegde extern apic_intrmap_ops_t *apic_vt_ops; 880e250f1e2Ssethg 8817c478bd9Sstevel@tonic-gate #ifdef __cplusplus 8827c478bd9Sstevel@tonic-gate } 8837c478bd9Sstevel@tonic-gate #endif 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate #endif /* _SYS_APIC_APIC_H */ 886