17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
77c478bd9Sstevel@tonic-gate * with the License.
87c478bd9Sstevel@tonic-gate *
97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
127c478bd9Sstevel@tonic-gate * and limitations under the License.
137c478bd9Sstevel@tonic-gate *
147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
197c478bd9Sstevel@tonic-gate *
207c478bd9Sstevel@tonic-gate * CDDL HEADER END
217c478bd9Sstevel@tonic-gate */
227c478bd9Sstevel@tonic-gate /*
23*c88420b3Sdmick * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
247c478bd9Sstevel@tonic-gate * Use is subject to license terms.
257c478bd9Sstevel@tonic-gate *
267c478bd9Sstevel@tonic-gate * Derived from pseudocode supplied by Intel.
277c478bd9Sstevel@tonic-gate */
287c478bd9Sstevel@tonic-gate
297c478bd9Sstevel@tonic-gate /*
307c478bd9Sstevel@tonic-gate * Workaround for Intel Orion chipset bug
317c478bd9Sstevel@tonic-gate *
327c478bd9Sstevel@tonic-gate * It is intended that this code implements exactly the workaround
337c478bd9Sstevel@tonic-gate * described in the errata. There is one exception, described below.
347c478bd9Sstevel@tonic-gate */
357c478bd9Sstevel@tonic-gate
367c478bd9Sstevel@tonic-gate #include <sys/types.h>
377c478bd9Sstevel@tonic-gate #include <sys/pci.h>
38*c88420b3Sdmick #include <sys/mutex.h>
39*c88420b3Sdmick #include <sys/pci_cfgspace_impl.h>
407c478bd9Sstevel@tonic-gate
417c478bd9Sstevel@tonic-gate #define PCI_82454_RW_CONTROL 0x54
427c478bd9Sstevel@tonic-gate
437c478bd9Sstevel@tonic-gate static int ncDevNo;
447c478bd9Sstevel@tonic-gate
457c478bd9Sstevel@tonic-gate boolean_t
pci_is_broken_orion()467c478bd9Sstevel@tonic-gate pci_is_broken_orion()
477c478bd9Sstevel@tonic-gate {
487c478bd9Sstevel@tonic-gate int Num82454 = 0;
497c478bd9Sstevel@tonic-gate boolean_t A2B0Found = B_FALSE;
507c478bd9Sstevel@tonic-gate boolean_t c82454PostingEnabled = B_FALSE;
517c478bd9Sstevel@tonic-gate uint8_t PciReg;
527c478bd9Sstevel@tonic-gate uint16_t VendorID;
537c478bd9Sstevel@tonic-gate uint16_t DeviceID;
547c478bd9Sstevel@tonic-gate boolean_t A2B0WorkAroundReqd;
557c478bd9Sstevel@tonic-gate
567c478bd9Sstevel@tonic-gate int BusNo = 0;
577c478bd9Sstevel@tonic-gate int FunctionNo = 0;
587c478bd9Sstevel@tonic-gate int DeviceNo;
597c478bd9Sstevel@tonic-gate uint8_t RevisionID;
607c478bd9Sstevel@tonic-gate
617c478bd9Sstevel@tonic-gate for (DeviceNo = 0; DeviceNo < PCI_MAX_DEVS; DeviceNo++) {
627c478bd9Sstevel@tonic-gate VendorID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo,
637c478bd9Sstevel@tonic-gate PCI_CONF_VENID);
647c478bd9Sstevel@tonic-gate DeviceID = pci_mech1_getw(BusNo, DeviceNo, FunctionNo,
657c478bd9Sstevel@tonic-gate PCI_CONF_DEVID);
667c478bd9Sstevel@tonic-gate RevisionID = pci_mech1_getb(BusNo, DeviceNo, FunctionNo,
677c478bd9Sstevel@tonic-gate PCI_CONF_REVID);
687c478bd9Sstevel@tonic-gate if (VendorID == 0x8086 && DeviceID == 0x84c4) {
697c478bd9Sstevel@tonic-gate /* Found 82454 PCI Bridge */
707c478bd9Sstevel@tonic-gate Num82454++;
717c478bd9Sstevel@tonic-gate if (RevisionID <= 4) {
727c478bd9Sstevel@tonic-gate A2B0Found = B_TRUE;
737c478bd9Sstevel@tonic-gate }
747c478bd9Sstevel@tonic-gate if (DeviceNo == (0xc8 >> 3)) {
757c478bd9Sstevel@tonic-gate /*
767c478bd9Sstevel@tonic-gate * c82454 Found - determine the status of
777c478bd9Sstevel@tonic-gate * inbound posting.
787c478bd9Sstevel@tonic-gate */
797c478bd9Sstevel@tonic-gate PciReg = pci_mech1_getb(BusNo, DeviceNo,
807c478bd9Sstevel@tonic-gate FunctionNo, PCI_82454_RW_CONTROL);
817c478bd9Sstevel@tonic-gate if (PciReg & 0x01) {
827c478bd9Sstevel@tonic-gate c82454PostingEnabled = B_TRUE;
837c478bd9Sstevel@tonic-gate }
847c478bd9Sstevel@tonic-gate } else {
857c478bd9Sstevel@tonic-gate /* nc82454 Found - store device no. */
867c478bd9Sstevel@tonic-gate ncDevNo = DeviceNo;
877c478bd9Sstevel@tonic-gate }
887c478bd9Sstevel@tonic-gate }
897c478bd9Sstevel@tonic-gate } /* DeviceNo */
907c478bd9Sstevel@tonic-gate /*
917c478bd9Sstevel@tonic-gate * Determine if nc82454 posting is to be enabled
927c478bd9Sstevel@tonic-gate * and need of workaround.
937c478bd9Sstevel@tonic-gate *
947c478bd9Sstevel@tonic-gate * [[ This is a deviation from the pseudocode in the errata.
957c478bd9Sstevel@tonic-gate * The errata has mismatched braces, leading to uncertainty
967c478bd9Sstevel@tonic-gate * as to whether this code is inside the test for 8086/84c4.
977c478bd9Sstevel@tonic-gate * The errata has this code clearly inside the DeviceNo loop.
987c478bd9Sstevel@tonic-gate * This code is obviously pointless until you've at least found
997c478bd9Sstevel@tonic-gate * the second 82454, and there's no need to execute it more
1007c478bd9Sstevel@tonic-gate * than once, so I'm moving it outside that loop to execute
1017c478bd9Sstevel@tonic-gate * once on completion of the scan. ]]
1027c478bd9Sstevel@tonic-gate */
1037c478bd9Sstevel@tonic-gate if (Num82454 >= 2 && A2B0Found &&
1047c478bd9Sstevel@tonic-gate c82454PostingEnabled) {
1057c478bd9Sstevel@tonic-gate A2B0WorkAroundReqd = B_TRUE;
1067c478bd9Sstevel@tonic-gate /* Enable inbound posting on nc82454 */
1077c478bd9Sstevel@tonic-gate PciReg = pci_mech1_getb(0, ncDevNo, 0,
1087c478bd9Sstevel@tonic-gate PCI_82454_RW_CONTROL);
1097c478bd9Sstevel@tonic-gate PciReg |= 0x01;
1107c478bd9Sstevel@tonic-gate pci_mech1_putb(0, ncDevNo, 0,
1117c478bd9Sstevel@tonic-gate PCI_82454_RW_CONTROL, PciReg);
1127c478bd9Sstevel@tonic-gate } else {
1137c478bd9Sstevel@tonic-gate A2B0WorkAroundReqd = B_FALSE;
1147c478bd9Sstevel@tonic-gate }
1157c478bd9Sstevel@tonic-gate
1167c478bd9Sstevel@tonic-gate return (A2B0WorkAroundReqd);
1177c478bd9Sstevel@tonic-gate }
1187c478bd9Sstevel@tonic-gate
1197c478bd9Sstevel@tonic-gate /*
1207c478bd9Sstevel@tonic-gate * When I first read this code in the errata document, I asked "why doesn't
1217c478bd9Sstevel@tonic-gate * the initial read of CFC (possibly) lead to the 'two responses' problem?"
1227c478bd9Sstevel@tonic-gate *
1237c478bd9Sstevel@tonic-gate * After thinking about it for a while, the answer is that we're trying to
1247c478bd9Sstevel@tonic-gate * talk to the nc82454 itself. The c82454 doesn't have the problem, so it
1257c478bd9Sstevel@tonic-gate * will recognize that this request is *not* for it, and won't respond.
1267c478bd9Sstevel@tonic-gate * The nc82454 will either respond or not, depending on whether it "saw"
1277c478bd9Sstevel@tonic-gate * the CF8 write, and if it responds it might or might not return the
1287c478bd9Sstevel@tonic-gate * right data. That's all pretty much OK, if we're willing to assume
1297c478bd9Sstevel@tonic-gate * that the only way that 84C48086 will come back is from the vendor ID/
1307c478bd9Sstevel@tonic-gate * device ID registers on the nc82454. This is probabilistic, of course,
1317c478bd9Sstevel@tonic-gate * because the nc82454 *could* be pointing at a register on some device
1327c478bd9Sstevel@tonic-gate * that just *happened* to have that value, but that seems unlikely.
1337c478bd9Sstevel@tonic-gate */
1347c478bd9Sstevel@tonic-gate static void
FuncDisableInboundPostingnc82454()1357c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454()
1367c478bd9Sstevel@tonic-gate {
1377c478bd9Sstevel@tonic-gate uint32_t test;
1387c478bd9Sstevel@tonic-gate uint8_t PciReg;
1397c478bd9Sstevel@tonic-gate
1407c478bd9Sstevel@tonic-gate mutex_enter(&pcicfg_chipset_mutex);
1417c478bd9Sstevel@tonic-gate do {
1427c478bd9Sstevel@tonic-gate test = pci_mech1_getl(0, ncDevNo, 0, PCI_CONF_VENID);
1437c478bd9Sstevel@tonic-gate } while (test != 0x84c48086UL);
1447c478bd9Sstevel@tonic-gate
1457c478bd9Sstevel@tonic-gate /*
1467c478bd9Sstevel@tonic-gate * At this point we are guaranteed to be pointing to the nc82454 PCI
1477c478bd9Sstevel@tonic-gate * bridge Vendor ID register.
1487c478bd9Sstevel@tonic-gate */
1497c478bd9Sstevel@tonic-gate do {
1507c478bd9Sstevel@tonic-gate /*
1517c478bd9Sstevel@tonic-gate * Impact of the erratum is that the configuration read will
1527c478bd9Sstevel@tonic-gate * return the value which was last read.
1537c478bd9Sstevel@tonic-gate * Hence read register 0x54 until the previous read value
1547c478bd9Sstevel@tonic-gate * (VendorId/DeviceId) is not read anymore.
1557c478bd9Sstevel@tonic-gate */
1567c478bd9Sstevel@tonic-gate test = pci_mech1_getl(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
1577c478bd9Sstevel@tonic-gate } while (test == 0x84c48086UL);
1587c478bd9Sstevel@tonic-gate /*
1597c478bd9Sstevel@tonic-gate * At this point we are guaranteed to be pointing to the PCI
1607c478bd9Sstevel@tonic-gate * Read/Write Control Register in the nc82454 PCI Bridge.
1617c478bd9Sstevel@tonic-gate */
1627c478bd9Sstevel@tonic-gate PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
1637c478bd9Sstevel@tonic-gate PciReg &= ~0x01;
1647c478bd9Sstevel@tonic-gate pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg);
1657c478bd9Sstevel@tonic-gate }
1667c478bd9Sstevel@tonic-gate
1677c478bd9Sstevel@tonic-gate static void
FuncEnableInboundPostingnc82454()1687c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454()
1697c478bd9Sstevel@tonic-gate {
1707c478bd9Sstevel@tonic-gate uint8_t PciReg;
1717c478bd9Sstevel@tonic-gate
1727c478bd9Sstevel@tonic-gate PciReg = pci_mech1_getb(0, ncDevNo, 0, PCI_82454_RW_CONTROL);
1737c478bd9Sstevel@tonic-gate PciReg |= 0x01;
1747c478bd9Sstevel@tonic-gate pci_mech1_putb(0, ncDevNo, 0, PCI_82454_RW_CONTROL, PciReg);
1757c478bd9Sstevel@tonic-gate mutex_exit(&pcicfg_chipset_mutex);
1767c478bd9Sstevel@tonic-gate }
1777c478bd9Sstevel@tonic-gate
1787c478bd9Sstevel@tonic-gate uint8_t
pci_orion_getb(int bus,int device,int function,int reg)1797c478bd9Sstevel@tonic-gate pci_orion_getb(int bus, int device, int function, int reg)
1807c478bd9Sstevel@tonic-gate {
1817c478bd9Sstevel@tonic-gate uint8_t val;
1827c478bd9Sstevel@tonic-gate
1837c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
1847c478bd9Sstevel@tonic-gate
1857c478bd9Sstevel@tonic-gate val = pci_mech1_getb(bus, device, function, reg);
1867c478bd9Sstevel@tonic-gate
1877c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
1887c478bd9Sstevel@tonic-gate return (val);
1897c478bd9Sstevel@tonic-gate }
1907c478bd9Sstevel@tonic-gate
1917c478bd9Sstevel@tonic-gate uint16_t
pci_orion_getw(int bus,int device,int function,int reg)1927c478bd9Sstevel@tonic-gate pci_orion_getw(int bus, int device, int function, int reg)
1937c478bd9Sstevel@tonic-gate {
1947c478bd9Sstevel@tonic-gate uint16_t val;
1957c478bd9Sstevel@tonic-gate
1967c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
1977c478bd9Sstevel@tonic-gate
1987c478bd9Sstevel@tonic-gate val = pci_mech1_getw(bus, device, function, reg);
1997c478bd9Sstevel@tonic-gate
2007c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
2017c478bd9Sstevel@tonic-gate return (val);
2027c478bd9Sstevel@tonic-gate }
2037c478bd9Sstevel@tonic-gate
2047c478bd9Sstevel@tonic-gate uint32_t
pci_orion_getl(int bus,int device,int function,int reg)2057c478bd9Sstevel@tonic-gate pci_orion_getl(int bus, int device, int function, int reg)
2067c478bd9Sstevel@tonic-gate {
2077c478bd9Sstevel@tonic-gate uint32_t val;
2087c478bd9Sstevel@tonic-gate
2097c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
2107c478bd9Sstevel@tonic-gate
2117c478bd9Sstevel@tonic-gate val = pci_mech1_getl(bus, device, function, reg);
2127c478bd9Sstevel@tonic-gate
2137c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
2147c478bd9Sstevel@tonic-gate return (val);
2157c478bd9Sstevel@tonic-gate }
2167c478bd9Sstevel@tonic-gate
2177c478bd9Sstevel@tonic-gate void
pci_orion_putb(int bus,int device,int function,int reg,uint8_t val)2187c478bd9Sstevel@tonic-gate pci_orion_putb(int bus, int device, int function, int reg, uint8_t val)
2197c478bd9Sstevel@tonic-gate {
2207c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
2217c478bd9Sstevel@tonic-gate
2227c478bd9Sstevel@tonic-gate pci_mech1_putb(bus, device, function, reg, val);
2237c478bd9Sstevel@tonic-gate
2247c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
2257c478bd9Sstevel@tonic-gate }
2267c478bd9Sstevel@tonic-gate
2277c478bd9Sstevel@tonic-gate void
pci_orion_putw(int bus,int device,int function,int reg,uint16_t val)2287c478bd9Sstevel@tonic-gate pci_orion_putw(int bus, int device, int function, int reg, uint16_t val)
2297c478bd9Sstevel@tonic-gate {
2307c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
2317c478bd9Sstevel@tonic-gate
2327c478bd9Sstevel@tonic-gate pci_mech1_putw(bus, device, function, reg, val);
2337c478bd9Sstevel@tonic-gate
2347c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
2357c478bd9Sstevel@tonic-gate }
2367c478bd9Sstevel@tonic-gate
2377c478bd9Sstevel@tonic-gate void
pci_orion_putl(int bus,int device,int function,int reg,uint32_t val)2387c478bd9Sstevel@tonic-gate pci_orion_putl(int bus, int device, int function, int reg, uint32_t val)
2397c478bd9Sstevel@tonic-gate {
2407c478bd9Sstevel@tonic-gate FuncDisableInboundPostingnc82454();
2417c478bd9Sstevel@tonic-gate
2427c478bd9Sstevel@tonic-gate pci_mech1_putl(bus, device, function, reg, val);
2437c478bd9Sstevel@tonic-gate
2447c478bd9Sstevel@tonic-gate FuncEnableInboundPostingnc82454();
2457c478bd9Sstevel@tonic-gate }
246