1*8d7fafffSZhi-Jun Robin Fu /* 2*8d7fafffSZhi-Jun Robin Fu * CDDL HEADER START 3*8d7fafffSZhi-Jun Robin Fu * 4*8d7fafffSZhi-Jun Robin Fu * The contents of this file are subject to the terms of the 5*8d7fafffSZhi-Jun Robin Fu * Common Development and Distribution License (the "License"). 6*8d7fafffSZhi-Jun Robin Fu * You may not use this file except in compliance with the License. 7*8d7fafffSZhi-Jun Robin Fu * 8*8d7fafffSZhi-Jun Robin Fu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*8d7fafffSZhi-Jun Robin Fu * or http://www.opensolaris.org/os/licensing. 10*8d7fafffSZhi-Jun Robin Fu * See the License for the specific language governing permissions 11*8d7fafffSZhi-Jun Robin Fu * and limitations under the License. 12*8d7fafffSZhi-Jun Robin Fu * 13*8d7fafffSZhi-Jun Robin Fu * When distributing Covered Code, include this CDDL HEADER in each 14*8d7fafffSZhi-Jun Robin Fu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*8d7fafffSZhi-Jun Robin Fu * If applicable, add the following below this CDDL HEADER, with the 16*8d7fafffSZhi-Jun Robin Fu * fields enclosed by brackets "[]" replaced with your own identifying 17*8d7fafffSZhi-Jun Robin Fu * information: Portions Copyright [yyyy] [name of copyright owner] 18*8d7fafffSZhi-Jun Robin Fu * 19*8d7fafffSZhi-Jun Robin Fu * CDDL HEADER END 20*8d7fafffSZhi-Jun Robin Fu */ 21*8d7fafffSZhi-Jun Robin Fu /* 22*8d7fafffSZhi-Jun Robin Fu * Copyright 2010 Advanced Micro Devices, Inc. 23*8d7fafffSZhi-Jun Robin Fu * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 24*8d7fafffSZhi-Jun Robin Fu */ 25*8d7fafffSZhi-Jun Robin Fu 26*8d7fafffSZhi-Jun Robin Fu /* 27*8d7fafffSZhi-Jun Robin Fu * PCI Mechanism 1 low-level routines with ECS support for AMD family >= 0x10 28*8d7fafffSZhi-Jun Robin Fu */ 29*8d7fafffSZhi-Jun Robin Fu 30*8d7fafffSZhi-Jun Robin Fu #include <sys/controlregs.h> 31*8d7fafffSZhi-Jun Robin Fu #include <sys/cpuvar.h> 32*8d7fafffSZhi-Jun Robin Fu #include <sys/types.h> 33*8d7fafffSZhi-Jun Robin Fu #include <sys/pci.h> 34*8d7fafffSZhi-Jun Robin Fu #include <sys/pci_impl.h> 35*8d7fafffSZhi-Jun Robin Fu #include <sys/sunddi.h> 36*8d7fafffSZhi-Jun Robin Fu #include <sys/pci_cfgspace_impl.h> 37*8d7fafffSZhi-Jun Robin Fu #include <sys/x86_archext.h> 38*8d7fafffSZhi-Jun Robin Fu 39*8d7fafffSZhi-Jun Robin Fu boolean_t 40*8d7fafffSZhi-Jun Robin Fu pci_check_amd_ioecs(void) 41*8d7fafffSZhi-Jun Robin Fu { 42*8d7fafffSZhi-Jun Robin Fu struct cpuid_regs cp; 43*8d7fafffSZhi-Jun Robin Fu int family; 44*8d7fafffSZhi-Jun Robin Fu 45*8d7fafffSZhi-Jun Robin Fu if ((x86_feature & X86_CPUID) == 0) 46*8d7fafffSZhi-Jun Robin Fu return (B_FALSE); 47*8d7fafffSZhi-Jun Robin Fu 48*8d7fafffSZhi-Jun Robin Fu /* 49*8d7fafffSZhi-Jun Robin Fu * Get the CPU vendor string from CPUID. 50*8d7fafffSZhi-Jun Robin Fu * This PCI mechanism only applies to AMD CPUs. 51*8d7fafffSZhi-Jun Robin Fu */ 52*8d7fafffSZhi-Jun Robin Fu cp.cp_eax = 0; 53*8d7fafffSZhi-Jun Robin Fu (void) __cpuid_insn(&cp); 54*8d7fafffSZhi-Jun Robin Fu 55*8d7fafffSZhi-Jun Robin Fu if ((cp.cp_ebx != 0x68747541) || /* Auth */ 56*8d7fafffSZhi-Jun Robin Fu (cp.cp_edx != 0x69746e65) || /* enti */ 57*8d7fafffSZhi-Jun Robin Fu (cp.cp_ecx != 0x444d4163)) /* cAMD */ 58*8d7fafffSZhi-Jun Robin Fu return (B_FALSE); 59*8d7fafffSZhi-Jun Robin Fu 60*8d7fafffSZhi-Jun Robin Fu /* 61*8d7fafffSZhi-Jun Robin Fu * Get the CPU family from CPUID. 62*8d7fafffSZhi-Jun Robin Fu * This PCI mechanism is only available on family 0x10 or higher. 63*8d7fafffSZhi-Jun Robin Fu */ 64*8d7fafffSZhi-Jun Robin Fu cp.cp_eax = 1; 65*8d7fafffSZhi-Jun Robin Fu (void) __cpuid_insn(&cp); 66*8d7fafffSZhi-Jun Robin Fu family = ((cp.cp_eax >> 8) & 0xf) + ((cp.cp_eax >> 20) & 0xff); 67*8d7fafffSZhi-Jun Robin Fu 68*8d7fafffSZhi-Jun Robin Fu if (family < 0x10) 69*8d7fafffSZhi-Jun Robin Fu return (B_FALSE); 70*8d7fafffSZhi-Jun Robin Fu 71*8d7fafffSZhi-Jun Robin Fu /* 72*8d7fafffSZhi-Jun Robin Fu * Set the EnableCf8ExtCfg bit in the Northbridge Configuration Register 73*8d7fafffSZhi-Jun Robin Fu * to enable accessing PCI ECS using in/out instructions. 74*8d7fafffSZhi-Jun Robin Fu */ 75*8d7fafffSZhi-Jun Robin Fu wrmsr(MSR_AMD_NB_CFG, rdmsr(MSR_AMD_NB_CFG) | AMD_GH_NB_CFG_EN_ECS); 76*8d7fafffSZhi-Jun Robin Fu return (B_TRUE); 77*8d7fafffSZhi-Jun Robin Fu } 78*8d7fafffSZhi-Jun Robin Fu 79*8d7fafffSZhi-Jun Robin Fu /* 80*8d7fafffSZhi-Jun Robin Fu * Macro to setup PCI Extended Configuration Space (ECS) address to give to 81*8d7fafffSZhi-Jun Robin Fu * "in/out" instructions 82*8d7fafffSZhi-Jun Robin Fu */ 83*8d7fafffSZhi-Jun Robin Fu #define PCI_CADDR1_ECS(b, d, f, r) \ 84*8d7fafffSZhi-Jun Robin Fu (PCI_CADDR1((b), (d), (f), (r)) | ((((r) >> 8) & 0xf) << 24)) 85*8d7fafffSZhi-Jun Robin Fu 86*8d7fafffSZhi-Jun Robin Fu /* 87*8d7fafffSZhi-Jun Robin Fu * Per PCI 2.1 section 3.7.4.1 and PCI-PCI Bridge Architecture 1.0 section 88*8d7fafffSZhi-Jun Robin Fu * 5.3.1.2: dev=31 func=7 reg=0 means a special cycle. We don't want to 89*8d7fafffSZhi-Jun Robin Fu * trigger that by accident, so we pretend that dev 31, func 7 doesn't 90*8d7fafffSZhi-Jun Robin Fu * exist. If we ever want special cycle support, we'll add explicit 91*8d7fafffSZhi-Jun Robin Fu * special cycle support. 92*8d7fafffSZhi-Jun Robin Fu */ 93*8d7fafffSZhi-Jun Robin Fu 94*8d7fafffSZhi-Jun Robin Fu uint8_t 95*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_getb(int bus, int device, int function, int reg) 96*8d7fafffSZhi-Jun Robin Fu { 97*8d7fafffSZhi-Jun Robin Fu uint8_t val; 98*8d7fafffSZhi-Jun Robin Fu 99*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 100*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 101*8d7fafffSZhi-Jun Robin Fu return (0xff); 102*8d7fafffSZhi-Jun Robin Fu } 103*8d7fafffSZhi-Jun Robin Fu 104*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 105*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 106*8d7fafffSZhi-Jun Robin Fu val = inb(PCI_CONFDATA | (reg & 0x3)); 107*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 108*8d7fafffSZhi-Jun Robin Fu return (val); 109*8d7fafffSZhi-Jun Robin Fu } 110*8d7fafffSZhi-Jun Robin Fu 111*8d7fafffSZhi-Jun Robin Fu uint16_t 112*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_getw(int bus, int device, int function, int reg) 113*8d7fafffSZhi-Jun Robin Fu { 114*8d7fafffSZhi-Jun Robin Fu uint16_t val; 115*8d7fafffSZhi-Jun Robin Fu 116*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 117*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 118*8d7fafffSZhi-Jun Robin Fu return (0xffff); 119*8d7fafffSZhi-Jun Robin Fu } 120*8d7fafffSZhi-Jun Robin Fu 121*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 122*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 123*8d7fafffSZhi-Jun Robin Fu val = inw(PCI_CONFDATA | (reg & 0x2)); 124*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 125*8d7fafffSZhi-Jun Robin Fu return (val); 126*8d7fafffSZhi-Jun Robin Fu } 127*8d7fafffSZhi-Jun Robin Fu 128*8d7fafffSZhi-Jun Robin Fu uint32_t 129*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_getl(int bus, int device, int function, int reg) 130*8d7fafffSZhi-Jun Robin Fu { 131*8d7fafffSZhi-Jun Robin Fu uint32_t val; 132*8d7fafffSZhi-Jun Robin Fu 133*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 134*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 135*8d7fafffSZhi-Jun Robin Fu return (0xffffffffu); 136*8d7fafffSZhi-Jun Robin Fu } 137*8d7fafffSZhi-Jun Robin Fu 138*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 139*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 140*8d7fafffSZhi-Jun Robin Fu val = inl(PCI_CONFDATA); 141*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 142*8d7fafffSZhi-Jun Robin Fu return (val); 143*8d7fafffSZhi-Jun Robin Fu } 144*8d7fafffSZhi-Jun Robin Fu 145*8d7fafffSZhi-Jun Robin Fu void 146*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_putb(int bus, int device, int function, int reg, uint8_t val) 147*8d7fafffSZhi-Jun Robin Fu { 148*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 149*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 150*8d7fafffSZhi-Jun Robin Fu return; 151*8d7fafffSZhi-Jun Robin Fu } 152*8d7fafffSZhi-Jun Robin Fu 153*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 154*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 155*8d7fafffSZhi-Jun Robin Fu outb(PCI_CONFDATA | (reg & 0x3), val); 156*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 157*8d7fafffSZhi-Jun Robin Fu } 158*8d7fafffSZhi-Jun Robin Fu 159*8d7fafffSZhi-Jun Robin Fu void 160*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_putw(int bus, int device, int function, int reg, uint16_t val) 161*8d7fafffSZhi-Jun Robin Fu { 162*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 163*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 164*8d7fafffSZhi-Jun Robin Fu return; 165*8d7fafffSZhi-Jun Robin Fu } 166*8d7fafffSZhi-Jun Robin Fu 167*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 168*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 169*8d7fafffSZhi-Jun Robin Fu outw(PCI_CONFDATA | (reg & 0x2), val); 170*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 171*8d7fafffSZhi-Jun Robin Fu } 172*8d7fafffSZhi-Jun Robin Fu 173*8d7fafffSZhi-Jun Robin Fu void 174*8d7fafffSZhi-Jun Robin Fu pci_mech1_amd_putl(int bus, int device, int function, int reg, uint32_t val) 175*8d7fafffSZhi-Jun Robin Fu { 176*8d7fafffSZhi-Jun Robin Fu if (device == PCI_MECH1_SPEC_CYCLE_DEV && 177*8d7fafffSZhi-Jun Robin Fu function == PCI_MECH1_SPEC_CYCLE_FUNC) { 178*8d7fafffSZhi-Jun Robin Fu return; 179*8d7fafffSZhi-Jun Robin Fu } 180*8d7fafffSZhi-Jun Robin Fu 181*8d7fafffSZhi-Jun Robin Fu mutex_enter(&pcicfg_mutex); 182*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); 183*8d7fafffSZhi-Jun Robin Fu outl(PCI_CONFDATA, val); 184*8d7fafffSZhi-Jun Robin Fu mutex_exit(&pcicfg_mutex); 185*8d7fafffSZhi-Jun Robin Fu } 186