xref: /illumos-gate/usr/src/uts/i86pc/os/pci_cfgspace.c (revision eb00b1c8a31c2253a353644606388dff5b0e0275)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24  * Copyright 2019 Joyent, Inc.
25  */
26 
27 /*
28  * PCI configuration space access routines
29  */
30 
31 #include <sys/systm.h>
32 #include <sys/psw.h>
33 #include <sys/bootconf.h>
34 #include <sys/reboot.h>
35 #include <sys/pci_impl.h>
36 #include <sys/pci_cfgspace.h>
37 #include <sys/pci_cfgspace_impl.h>
38 #include <sys/pci_cfgacc.h>
39 #if defined(__xpv)
40 #include <sys/hypervisor.h>
41 #endif
42 
43 #if defined(__xpv)
44 int pci_max_nbus = 0xFE;
45 #else
46 int pci_max_nbus = 0xFF;
47 #endif
48 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
49 int pci_bios_maxbus;
50 int pci_bios_mech;
51 int pci_bios_vers;
52 
53 /*
54  * These two variables can be used to force a configuration mechanism or
55  * to force which function is used to probe for the presence of the PCI bus.
56  */
57 int	PCI_CFG_TYPE = 0;
58 int	PCI_PROBE_TYPE = 0;
59 
60 /*
61  * No valid mcfg_mem_base by default, and accessing pci config space
62  * in mem-mapped way is disabled.
63  */
64 uint64_t mcfg_mem_base = 0;
65 uint8_t mcfg_bus_start = 0;
66 uint8_t mcfg_bus_end = 0xff;
67 
68 /*
69  * Maximum offset in config space when not using MMIO
70  */
71 uint_t pci_iocfg_max_offset = 0xff;
72 
73 /*
74  * These function pointers lead to the actual implementation routines
75  * for configuration space access.  Normally they lead to either the
76  * pci_mech1_* or pci_mech2_* routines, but they can also lead to
77  * routines that work around chipset bugs.
78  * These functions are accessing pci config space via I/O way.
79  * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
80  * which also provide accessing pci config space via mem-mapped way.
81  */
82 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
83 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
84 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
85 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
86 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
87 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
88 
89 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
90 
91 /*
92  * Internal routines
93  */
94 static int pci_check(void);
95 
96 #if !defined(__xpv)
97 static int pci_check_bios(void);
98 static int pci_get_cfg_type(void);
99 #endif
100 
101 /* for legacy io-based config space access */
102 kmutex_t pcicfg_mutex;
103 
104 /* for mmio-based config space access */
105 kmutex_t pcicfg_mmio_mutex;
106 
107 /* ..except Orion and Neptune, which have to have their own */
108 kmutex_t pcicfg_chipset_mutex;
109 
110 void
111 pci_cfgspace_init(void)
112 {
113 	mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
114 	    (ddi_iblock_cookie_t)ipltospl(15));
115 	mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
116 	    (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
117 	mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
118 	    (ddi_iblock_cookie_t)ipltospl(15));
119 	if (!pci_check()) {
120 		mutex_destroy(&pcicfg_mutex);
121 		mutex_destroy(&pcicfg_mmio_mutex);
122 		mutex_destroy(&pcicfg_chipset_mutex);
123 	}
124 }
125 
126 /*
127  * This code determines if this system supports PCI/PCIE and which
128  * type of configuration access method is used
129  */
130 static int
131 pci_check(void)
132 {
133 	uint64_t ecfginfo[4];
134 
135 	/*
136 	 * Only do this once.  NB:  If this is not a PCI system, and we
137 	 * get called twice, we can't detect it and will probably die
138 	 * horribly when we try to ask the BIOS whether PCI is present.
139 	 * This code is safe *ONLY* during system startup when the
140 	 * BIOS is still available.
141 	 */
142 	if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
143 		return (TRUE);
144 
145 #if defined(__xpv)
146 	/*
147 	 * only support PCI config mechanism 1 in i86xpv. This should be fine
148 	 * since the other ones are workarounds for old broken H/W which won't
149 	 * be supported in i86xpv anyway.
150 	 */
151 	if (DOMAIN_IS_INITDOMAIN(xen_info)) {
152 		pci_bios_cfg_type = PCI_MECHANISM_1;
153 		pci_getb_func = pci_mech1_getb;
154 		pci_getw_func = pci_mech1_getw;
155 		pci_getl_func = pci_mech1_getl;
156 		pci_putb_func = pci_mech1_putb;
157 		pci_putw_func = pci_mech1_putw;
158 		pci_putl_func = pci_mech1_putl;
159 
160 		/*
161 		 * Since we can't get the BIOS info in i86xpv, we will do an
162 		 * exhaustive search of all PCI buses. We have to do this until
163 		 * we start using the PCI information in ACPI.
164 		 */
165 		pci_bios_maxbus = pci_max_nbus;
166 	}
167 #else /* !__xpv */
168 
169 	pci_bios_cfg_type = pci_check_bios();
170 
171 	if (pci_bios_cfg_type == PCI_MECHANISM_NONE)
172 		pci_bios_cfg_type = PCI_MECHANISM_1;	/* default to mech 1 */
173 
174 	switch (pci_get_cfg_type()) {
175 	case PCI_MECHANISM_1:
176 		if (pci_is_broken_orion()) {
177 			pci_getb_func = pci_orion_getb;
178 			pci_getw_func = pci_orion_getw;
179 			pci_getl_func = pci_orion_getl;
180 			pci_putb_func = pci_orion_putb;
181 			pci_putw_func = pci_orion_putw;
182 			pci_putl_func = pci_orion_putl;
183 		} else if (pci_check_amd_ioecs()) {
184 			pci_getb_func = pci_mech1_amd_getb;
185 			pci_getw_func = pci_mech1_amd_getw;
186 			pci_getl_func = pci_mech1_amd_getl;
187 			pci_putb_func = pci_mech1_amd_putb;
188 			pci_putw_func = pci_mech1_amd_putw;
189 			pci_putl_func = pci_mech1_amd_putl;
190 			pci_iocfg_max_offset = 0xfff;
191 		} else {
192 			pci_getb_func = pci_mech1_getb;
193 			pci_getw_func = pci_mech1_getw;
194 			pci_getl_func = pci_mech1_getl;
195 			pci_putb_func = pci_mech1_putb;
196 			pci_putw_func = pci_mech1_putw;
197 			pci_putl_func = pci_mech1_putl;
198 		}
199 		break;
200 
201 	case PCI_MECHANISM_2:
202 		if (pci_check_neptune()) {
203 			/*
204 			 * The BIOS for some systems with the Intel
205 			 * Neptune chipset seem to default to #2 even
206 			 * though the chipset can do #1.  Override
207 			 * the BIOS so that MP systems will work
208 			 * correctly.
209 			 */
210 
211 			pci_getb_func = pci_neptune_getb;
212 			pci_getw_func = pci_neptune_getw;
213 			pci_getl_func = pci_neptune_getl;
214 			pci_putb_func = pci_neptune_putb;
215 			pci_putw_func = pci_neptune_putw;
216 			pci_putl_func = pci_neptune_putl;
217 		} else {
218 			pci_getb_func = pci_mech2_getb;
219 			pci_getw_func = pci_mech2_getw;
220 			pci_getl_func = pci_mech2_getl;
221 			pci_putb_func = pci_mech2_putb;
222 			pci_putw_func = pci_mech2_putw;
223 			pci_putl_func = pci_mech2_putl;
224 		}
225 		break;
226 
227 	default:
228 		return (FALSE);
229 	}
230 #endif /* __xpv */
231 
232 	/*
233 	 * Try to get a valid mcfg_mem_base in early boot
234 	 * If failed, leave mem-mapped pci config space accessing disabled
235 	 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
236 	 * platform.
237 	 */
238 	if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
239 		mcfg_mem_base = ecfginfo[0];
240 		mcfg_bus_start = ecfginfo[2];
241 		mcfg_bus_end = ecfginfo[3];
242 	}
243 
244 	/* See pci_cfgacc.c */
245 	pci_cfgacc_acc_p = pci_cfgacc_acc;
246 
247 	return (TRUE);
248 }
249 
250 #if !defined(__xpv)
251 
252 static int
253 pci_check_bios(void)
254 {
255 	struct bop_regs regs;
256 	uint32_t	carryflag;
257 	uint16_t	ax, dx;
258 
259 	/*
260 	 * This mechanism uses a legacy BIOS call to detect PCI configuration,
261 	 * but such calls are not available on systems with UEFI firmware.
262 	 * For UEFI systems we must assume some reasonable defaults and scan
263 	 * all possible buses.
264 	 */
265 	if (BOP_GETPROPLEN(bootops, "efi-systab") > 0) {
266 		pci_bios_mech = 1;
267 		pci_bios_vers = 0;
268 		pci_bios_maxbus = pci_max_nbus;
269 		return (PCI_MECHANISM_1);
270 	}
271 
272 	bzero(&regs, sizeof (regs));
273 	regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
274 
275 	BOP_DOINT(bootops, 0x1a, &regs);
276 	carryflag = regs.eflags & PS_C;
277 	ax = regs.eax.word.ax;
278 	dx = regs.edx.word.dx;
279 
280 	/* the carry flag must not be set */
281 	if (carryflag != 0)
282 		return (PCI_MECHANISM_NONE);
283 
284 	if (dx != ('P' | 'C'<<8))
285 		return (PCI_MECHANISM_NONE);
286 
287 	/* ah (the high byte of ax) must be zero */
288 	if ((ax & 0xff00) != 0)
289 		return (PCI_MECHANISM_NONE);
290 
291 	pci_bios_mech = (ax & 0x3);
292 	pci_bios_vers = regs.ebx.word.bx;
293 
294 	/*
295 	 * Several BIOS implementations have known problems where they don't end
296 	 * up correctly telling us to scan all PCI buses in the system. In
297 	 * particular, many on-die CPU PCI devices are on a last bus that is
298 	 * sometimes not enumerated. As such, do not trust the BIOS.
299 	 */
300 	pci_bios_maxbus = pci_max_nbus;
301 
302 	switch (pci_bios_mech) {
303 	default:	/* ?!? */
304 	case 0:		/* supports neither? */
305 		return (PCI_MECHANISM_NONE);
306 
307 	case 1:
308 	case 3:		/* supports both */
309 		return (PCI_MECHANISM_1);
310 
311 	case 2:
312 		return (PCI_MECHANISM_2);
313 	}
314 }
315 
316 static int
317 pci_get_cfg_type(void)
318 {
319 	/* Check to see if the config mechanism has been set in /etc/system */
320 	switch (PCI_CFG_TYPE) {
321 	default:
322 	case 0:
323 		break;
324 	case 1:
325 		return (PCI_MECHANISM_1);
326 	case 2:
327 		return (PCI_MECHANISM_2);
328 	case -1:
329 		return (PCI_MECHANISM_NONE);
330 	}
331 
332 	/* call one of the PCI detection algorithms */
333 	switch (PCI_PROBE_TYPE) {
334 	default:
335 	case 0:
336 		/* From pci_check() and pci_check_bios() */
337 		return (pci_bios_cfg_type);
338 	case -1:
339 		return (PCI_MECHANISM_NONE);
340 	}
341 }
342 
343 #endif	/* __xpv */
344