17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 237417cfdeSKuriakose Kuruvilla * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 25a3114836SGerry Liu /* 26a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 27a3114836SGerry Liu * All rights reserved. 28a3114836SGerry Liu */ 29ebb8ac07SRobert Mustacchi /* 30*e25cb0e7SJohn Levon * Copyright 2020 Joyent, Inc. 31850ad55aSHans Rosenfeld * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 3239df76fbSAndy Fiddaman * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. 33ebb8ac07SRobert Mustacchi */ 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #include <sys/types.h> 367c478bd9Sstevel@tonic-gate #include <sys/thread.h> 377c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 38a3114836SGerry Liu #include <sys/cpu.h> 397c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 407c478bd9Sstevel@tonic-gate #include <sys/param.h> 417c478bd9Sstevel@tonic-gate #include <sys/proc.h> 427c478bd9Sstevel@tonic-gate #include <sys/disp.h> 437c478bd9Sstevel@tonic-gate #include <sys/class.h> 447c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 457c478bd9Sstevel@tonic-gate #include <sys/debug.h> 46a3114836SGerry Liu #include <sys/note.h> 477c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 487c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 497c478bd9Sstevel@tonic-gate #include <sys/systm.h> 507c478bd9Sstevel@tonic-gate #include <sys/var.h> 517c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 527c478bd9Sstevel@tonic-gate #include <vm/hat.h> 537c478bd9Sstevel@tonic-gate #include <vm/as.h> 547c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 55ae115bc7Smrj #include <vm/seg_kp.h> 567c478bd9Sstevel@tonic-gate #include <sys/segments.h> 577c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 587c478bd9Sstevel@tonic-gate #include <sys/stack.h> 597c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 607c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 617c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 627c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 637c478bd9Sstevel@tonic-gate #include <sys/clock.h> 647c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 65fb2f18f8Sesaxe #include <sys/pg.h> 66fb2f18f8Sesaxe #include <sys/cmt.h> 677c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 687c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 697c478bd9Sstevel@tonic-gate #include <sys/fp.h> 707c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 71ae115bc7Smrj #include <sys/kdi_machimpl.h> 727c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 73a3114836SGerry Liu #include <vm/vm_dep.h> 747c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 75ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 76ae115bc7Smrj #include <sys/mach_mmu.h> 77ae115bc7Smrj #include <sys/sysmacros.h> 78843e1988Sjohnlev #if defined(__xpv) 79843e1988Sjohnlev #include <sys/hypervisor.h> 80843e1988Sjohnlev #endif 817aec1d6eScindi #include <sys/cpu_module.h> 82850ad55aSHans Rosenfeld #include <sys/ontrap.h> 837c478bd9Sstevel@tonic-gate 8474ecdb51SJohn Levon struct cpu cpus[1] __aligned(MMU_PAGESIZE); 8574ecdb51SJohn Levon struct cpu *cpu[NCPU] = {&cpus[0]}; 8674ecdb51SJohn Levon struct cpu *cpu_free_list; 8774ecdb51SJohn Levon cpu_core_t cpu_core[NCPU]; 887c478bd9Sstevel@tonic-gate 89a3114836SGerry Liu #define cpu_next_free cpu_prev 90a3114836SGerry Liu 917c478bd9Sstevel@tonic-gate /* 92ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 937c478bd9Sstevel@tonic-gate */ 947c478bd9Sstevel@tonic-gate int use_mp = 1; 957c478bd9Sstevel@tonic-gate 9641791439Sandrei /* 97ae115bc7Smrj * to be set by a PSM to indicate what cpus 98ae115bc7Smrj * are sitting around on the system. 9941791439Sandrei */ 100ae115bc7Smrj cpuset_t mp_cpus; 1017c478bd9Sstevel@tonic-gate 1027c478bd9Sstevel@tonic-gate /* 1037c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 1047c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 1057c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 1067c478bd9Sstevel@tonic-gate * order to allow cross calls. 1077c478bd9Sstevel@tonic-gate */ 108ae115bc7Smrj int flushes_require_xcalls; 109a563a037Sbholler 110a563a037Sbholler cpuset_t cpu_ready_set; /* initialized in startup() */ 1117c478bd9Sstevel@tonic-gate 112a3114836SGerry Liu static void mp_startup_boot(void); 113a3114836SGerry Liu static void mp_startup_hotplug(void); 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1167c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1177c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1187c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1197c478bd9Sstevel@tonic-gate 1207c478bd9Sstevel@tonic-gate /* 1217c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1227c478bd9Sstevel@tonic-gate */ 1237c478bd9Sstevel@tonic-gate void 1247c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1257c478bd9Sstevel@tonic-gate { 1267c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate /* 1297c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1307c478bd9Sstevel@tonic-gate */ 1317c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1327c478bd9Sstevel@tonic-gate 1335cff7825Smh /* 1345cff7825Smh * Current frequency in Hz. 1355cff7825Smh */ 136cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1375cff7825Smh 13837d22dc0SAnup Pemmaiah /* 13937d22dc0SAnup Pemmaiah * Supported frequencies. 14037d22dc0SAnup Pemmaiah */ 14137d22dc0SAnup Pemmaiah if (cp->cpu_supp_freqs == NULL) { 14237d22dc0SAnup Pemmaiah cpu_set_supp_freqs(cp, NULL); 14337d22dc0SAnup Pemmaiah } 14437d22dc0SAnup Pemmaiah 1457c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1467c478bd9Sstevel@tonic-gate if (fpu_exists) 1477c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1487c478bd9Sstevel@tonic-gate 149a3114836SGerry Liu cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 150a3114836SGerry Liu cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 1517c478bd9Sstevel@tonic-gate 152a3114836SGerry Liu /* 153a3114836SGerry Liu * If called for the BSP, cp is equal to current CPU. 154a3114836SGerry Liu * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 155a3114836SGerry Liu * of current CPU as default values for cpu_idstr and cpu_brandstr. 156a3114836SGerry Liu * They will be corrected in mp_startup_common() after cpuid_pass1() 157a3114836SGerry Liu * has been invoked on target CPU. 158a3114836SGerry Liu */ 159a3114836SGerry Liu (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 160a3114836SGerry Liu (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 1617c478bd9Sstevel@tonic-gate } 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate /* 1647c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1657c478bd9Sstevel@tonic-gate */ 1667c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1672df1fe9cSrandyf void 1687c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1697c478bd9Sstevel@tonic-gate { 1707c478bd9Sstevel@tonic-gate kpreempt_disable(); 1717c478bd9Sstevel@tonic-gate 1727417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1737417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) { 1743ce2fcdcSRobert Mustacchi uint64_t flags; 1757c478bd9Sstevel@tonic-gate 17674ecdb51SJohn Levon #if !defined(__xpv) 1777c478bd9Sstevel@tonic-gate /* 1787c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1797c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1807c478bd9Sstevel@tonic-gate * here. 1817c478bd9Sstevel@tonic-gate */ 18274ecdb51SJohn Levon CTASSERT(KDS_SEL == KCS_SEL + 8); 18374ecdb51SJohn Levon CTASSERT(UDS_SEL == U32CS_SEL + 8); 18474ecdb51SJohn Levon CTASSERT(UCS_SEL == U32CS_SEL + 16); 1857c478bd9Sstevel@tonic-gate #endif 18674ecdb51SJohn Levon 1877c478bd9Sstevel@tonic-gate /* 1887c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1897c478bd9Sstevel@tonic-gate */ 1907c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1917c478bd9Sstevel@tonic-gate 1927c478bd9Sstevel@tonic-gate /* 1937c478bd9Sstevel@tonic-gate * Program the magic registers .. 1947c478bd9Sstevel@tonic-gate */ 195ae115bc7Smrj wrmsr(MSR_AMD_STAR, 196ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 19774ecdb51SJohn Levon if (kpti_enable == 1) { 19874ecdb51SJohn Levon wrmsr(MSR_AMD_LSTAR, 19974ecdb51SJohn Levon (uint64_t)(uintptr_t)tr_sys_syscall); 20074ecdb51SJohn Levon wrmsr(MSR_AMD_CSTAR, 20174ecdb51SJohn Levon (uint64_t)(uintptr_t)tr_sys_syscall32); 20274ecdb51SJohn Levon } else { 20374ecdb51SJohn Levon wrmsr(MSR_AMD_LSTAR, 20474ecdb51SJohn Levon (uint64_t)(uintptr_t)sys_syscall); 20574ecdb51SJohn Levon wrmsr(MSR_AMD_CSTAR, 20674ecdb51SJohn Levon (uint64_t)(uintptr_t)sys_syscall32); 20774ecdb51SJohn Levon } 2087c478bd9Sstevel@tonic-gate 2097c478bd9Sstevel@tonic-gate /* 2107c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 2117c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 2127c478bd9Sstevel@tonic-gate */ 2133ce2fcdcSRobert Mustacchi flags = PS_IE | PS_T; 2143ce2fcdcSRobert Mustacchi if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE) 2153ce2fcdcSRobert Mustacchi flags |= PS_ACHK; 2163ce2fcdcSRobert Mustacchi wrmsr(MSR_AMD_SFMASK, flags); 2177c478bd9Sstevel@tonic-gate } 2187c478bd9Sstevel@tonic-gate 2197c478bd9Sstevel@tonic-gate /* 2207c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 2217c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 2227c478bd9Sstevel@tonic-gate */ 2237417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2247417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) { 2257c478bd9Sstevel@tonic-gate 22674ecdb51SJohn Levon #if !defined(__xpv) 2277c478bd9Sstevel@tonic-gate /* 2287c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 2297c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2307c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2317c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2327c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2337c478bd9Sstevel@tonic-gate */ 23474ecdb51SJohn Levon CTASSERT(KDS_SEL == KCS_SEL + 8); 2357c478bd9Sstevel@tonic-gate 23674ecdb51SJohn Levon CTASSERT(U32CS_SEL == ((KCS_SEL + 16) | 3)); 23774ecdb51SJohn Levon CTASSERT(UDS_SEL == U32CS_SEL + 8); 2387c478bd9Sstevel@tonic-gate #endif 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2417c478bd9Sstevel@tonic-gate 2427c478bd9Sstevel@tonic-gate /* 2437c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2447c478bd9Sstevel@tonic-gate * via a context handler. 2457c478bd9Sstevel@tonic-gate */ 246ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 24774ecdb51SJohn Levon 24874ecdb51SJohn Levon if (kpti_enable == 1) { 24974ecdb51SJohn Levon wrmsr(MSR_INTC_SEP_EIP, 25074ecdb51SJohn Levon (uint64_t)(uintptr_t)tr_sys_sysenter); 25174ecdb51SJohn Levon } else { 25274ecdb51SJohn Levon wrmsr(MSR_INTC_SEP_EIP, 25374ecdb51SJohn Levon (uint64_t)(uintptr_t)sys_sysenter); 25474ecdb51SJohn Levon } 2557c478bd9Sstevel@tonic-gate } 2567c478bd9Sstevel@tonic-gate 2577c478bd9Sstevel@tonic-gate kpreempt_enable(); 2587c478bd9Sstevel@tonic-gate } 2597c478bd9Sstevel@tonic-gate 2602428aad8SPatrick Mooney #if !defined(__xpv) 2612428aad8SPatrick Mooney /* 2622428aad8SPatrick Mooney * Configure per-cpu ID GDT 2632428aad8SPatrick Mooney */ 2642428aad8SPatrick Mooney static void 2652428aad8SPatrick Mooney init_cpu_id_gdt(struct cpu *cp) 2662428aad8SPatrick Mooney { 2672428aad8SPatrick Mooney /* Write cpu_id into limit field of GDT for usermode retrieval */ 2682428aad8SPatrick Mooney #if defined(__amd64) 2692428aad8SPatrick Mooney set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id, 2702428aad8SPatrick Mooney SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32); 2712428aad8SPatrick Mooney #elif defined(__i386) 2722428aad8SPatrick Mooney set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA, 2732428aad8SPatrick Mooney SEL_UPL, SDP_BYTES, SDP_OP32); 2742428aad8SPatrick Mooney #endif 2752428aad8SPatrick Mooney } 2762428aad8SPatrick Mooney #endif /* !defined(__xpv) */ 2772428aad8SPatrick Mooney 2787c478bd9Sstevel@tonic-gate /* 2797c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2807c478bd9Sstevel@tonic-gate * 2817c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2827c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 283a3114836SGerry Liu * Parameter boot is true for boot time operations and is false for CPU 284a3114836SGerry Liu * DR operations. 2857c478bd9Sstevel@tonic-gate */ 286a3114836SGerry Liu static struct cpu * 287a3114836SGerry Liu mp_cpu_configure_common(int cpun, boolean_t boot) 2887c478bd9Sstevel@tonic-gate { 2897c478bd9Sstevel@tonic-gate struct cpu *cp; 2907c478bd9Sstevel@tonic-gate kthread_id_t tp; 2917c478bd9Sstevel@tonic-gate caddr_t sp; 2927c478bd9Sstevel@tonic-gate proc_t *procp; 293843e1988Sjohnlev #if !defined(__xpv) 2945b8a6efeSbholler extern int idle_cpu_prefer_mwait; 2950e751525SEric Saxe extern void cpu_idle_mwait(); 296843e1988Sjohnlev #endif 2977c478bd9Sstevel@tonic-gate extern void idle(); 2980e751525SEric Saxe extern void cpu_idle(); 2997c478bd9Sstevel@tonic-gate 3007c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 3017c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 3027c478bd9Sstevel@tonic-gate #endif 3037c478bd9Sstevel@tonic-gate 304a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 3057c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 3067c478bd9Sstevel@tonic-gate 307a3114836SGerry Liu if (cpu_free_list == NULL) { 308a3114836SGerry Liu cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 309a3114836SGerry Liu } else { 310a3114836SGerry Liu cp = cpu_free_list; 311a3114836SGerry Liu cpu_free_list = cp->cpu_next_free; 312a3114836SGerry Liu } 313f98fbcecSbholler 3143006ae82SFrank Van Der Linden cp->cpu_m.mcpu_istamp = cpun << 16; 3153006ae82SFrank Van Der Linden 316a3114836SGerry Liu /* Create per CPU specific threads in the process p0. */ 317a3114836SGerry Liu procp = &p0; 3187c478bd9Sstevel@tonic-gate 3197c478bd9Sstevel@tonic-gate /* 3207c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 3217c478bd9Sstevel@tonic-gate */ 3227c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 3237c478bd9Sstevel@tonic-gate 324affbd3ccSkchow cpu_vm_data_init(cp); 325affbd3ccSkchow 3267c478bd9Sstevel@tonic-gate /* 3277c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 3287c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 3297c478bd9Sstevel@tonic-gate * when the CPU starts running. 3307c478bd9Sstevel@tonic-gate */ 3317c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 3327c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 3337c478bd9Sstevel@tonic-gate 3347c478bd9Sstevel@tonic-gate /* 3357c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 3367c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 3377c478bd9Sstevel@tonic-gate * 3387c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 3397c478bd9Sstevel@tonic-gate * thread_create(). 3407c478bd9Sstevel@tonic-gate */ 3417c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 3427c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3437c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3447c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3457c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3467c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3477c478bd9Sstevel@tonic-gate 3487c478bd9Sstevel@tonic-gate /* 349a3114836SGerry Liu * Setup thread to start in mp_startup_common. 3507c478bd9Sstevel@tonic-gate */ 3517c478bd9Sstevel@tonic-gate sp = tp->t_stk; 3527c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 353ae115bc7Smrj #if defined(__amd64) 354ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 355ae115bc7Smrj #endif 356a3114836SGerry Liu /* 357a3114836SGerry Liu * Setup thread start entry point for boot or hotplug. 358a3114836SGerry Liu */ 359a3114836SGerry Liu if (boot) { 360a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_boot; 361a3114836SGerry Liu } else { 362a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_hotplug; 363a3114836SGerry Liu } 3647c478bd9Sstevel@tonic-gate 3657c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3667c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3677c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3687c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3697c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3707c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3717c478bd9Sstevel@tonic-gate 372da43ceabSsethg /* 373da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 374a3114836SGerry Liu * operations in mp_startup_common from causing the spl of the cpu 375a3114836SGerry Liu * to drop to 0 (allowing device interrupts before we're ready) in 376a3114836SGerry Liu * resume(). 377da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 378da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 379a3114836SGerry Liu * an assertion in mp_startup_common() -- before cpu_base_spl is set 380a3114836SGerry Liu * to its proper value. 381da43ceabSsethg */ 382da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 383da43ceabSsethg 3847c478bd9Sstevel@tonic-gate /* 3857c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3867c478bd9Sstevel@tonic-gate */ 3877c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3887c478bd9Sstevel@tonic-gate 3897c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3907c478bd9Sstevel@tonic-gate 3917c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3927c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3937c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3947c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3957c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3967c478bd9Sstevel@tonic-gate 397394b433dSesaxe /* 398fb2f18f8Sesaxe * Bootstrap the CPU's PG data 399394b433dSesaxe */ 400fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 401394b433dSesaxe 4027c478bd9Sstevel@tonic-gate /* 403ae115bc7Smrj * Perform CPC initialization on the new CPU. 4047c478bd9Sstevel@tonic-gate */ 4057c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 4067c478bd9Sstevel@tonic-gate 4077c478bd9Sstevel@tonic-gate /* 4087c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 4097c478bd9Sstevel@tonic-gate * for each CPU. 4107c478bd9Sstevel@tonic-gate */ 4117c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 4127c478bd9Sstevel@tonic-gate 4137c478bd9Sstevel@tonic-gate /* 414ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 4157c478bd9Sstevel@tonic-gate */ 416ae115bc7Smrj #if !defined(__lint) 417ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 418ae115bc7Smrj #endif 4190cfdb603Sjosephb cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 4200cfdb603Sjosephb bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 4217c478bd9Sstevel@tonic-gate 422ae115bc7Smrj #if defined(__i386) 4237c478bd9Sstevel@tonic-gate /* 4247c478bd9Sstevel@tonic-gate * setup kernel %gs. 4257c478bd9Sstevel@tonic-gate */ 4267c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 4277c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 428ae115bc7Smrj #endif 4297c478bd9Sstevel@tonic-gate 4307c478bd9Sstevel@tonic-gate /* 43174ecdb51SJohn Levon * Allocate pages for the CPU LDT. 43274ecdb51SJohn Levon */ 43374ecdb51SJohn Levon cp->cpu_m.mcpu_ldt = kmem_zalloc(LDT_CPU_SIZE, KM_SLEEP); 43474ecdb51SJohn Levon cp->cpu_m.mcpu_ldt_len = 0; 43574ecdb51SJohn Levon 43674ecdb51SJohn Levon /* 43774ecdb51SJohn Levon * Allocate a per-CPU IDT and initialize the new IDT to the currently 43874ecdb51SJohn Levon * runing CPU. 4397c478bd9Sstevel@tonic-gate */ 4400cfdb603Sjosephb #if !defined(__lint) 44174ecdb51SJohn Levon ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 4420cfdb603Sjosephb #endif 44374ecdb51SJohn Levon cp->cpu_idt = kmem_alloc(PAGESIZE, KM_SLEEP); 44474ecdb51SJohn Levon bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 4457c478bd9Sstevel@tonic-gate 4467c478bd9Sstevel@tonic-gate /* 447ae115bc7Smrj * alloc space for cpuid info 4487c478bd9Sstevel@tonic-gate */ 449ae115bc7Smrj cpuid_alloc_space(cp); 450a3114836SGerry Liu #if !defined(__xpv) 4517417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) && 4527417cfdeSKuriakose Kuruvilla idle_cpu_prefer_mwait) { 453a3114836SGerry Liu cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 454a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 455a3114836SGerry Liu } else 456a3114836SGerry Liu #endif 457a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle; 458a3114836SGerry Liu 459a3114836SGerry Liu init_cpu_info(cp); 4607c478bd9Sstevel@tonic-gate 4612428aad8SPatrick Mooney #if !defined(__xpv) 4622428aad8SPatrick Mooney init_cpu_id_gdt(cp); 4632428aad8SPatrick Mooney #endif 4642428aad8SPatrick Mooney 4652449e17fSsherrym /* 4662449e17fSsherrym * alloc space for ucode_info 4672449e17fSsherrym */ 4682449e17fSsherrym ucode_alloc_space(cp); 469f34a7178SJoe Bonasera xc_init_cpu(cp); 470ae115bc7Smrj hat_cpu_online(cp); 4717c478bd9Sstevel@tonic-gate 4727c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4737c478bd9Sstevel@tonic-gate /* 474ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4757c478bd9Sstevel@tonic-gate */ 4767c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4777c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4787c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4797c478bd9Sstevel@tonic-gate #endif 480a3114836SGerry Liu 4817c478bd9Sstevel@tonic-gate /* 4827c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4837c478bd9Sstevel@tonic-gate */ 4847c478bd9Sstevel@tonic-gate /* 4857c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4867c478bd9Sstevel@tonic-gate */ 487100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 488a3114836SGerry Liu 489a3114836SGerry Liu cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 490a3114836SGerry Liu cpu_set_state(cp); 491a3114836SGerry Liu 4927c478bd9Sstevel@tonic-gate /* 4937c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 494a3114836SGerry Liu * after mp_startup_common(). 4957c478bd9Sstevel@tonic-gate */ 4967c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 497ae115bc7Smrj 498ae115bc7Smrj return (cp); 499ae115bc7Smrj } 500ae115bc7Smrj 501ae115bc7Smrj /* 502a3114836SGerry Liu * Undo what was done in mp_cpu_configure_common 503ae115bc7Smrj */ 504ae115bc7Smrj static void 505a3114836SGerry Liu mp_cpu_unconfigure_common(struct cpu *cp, int error) 506ae115bc7Smrj { 507a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 508ae115bc7Smrj 509ae115bc7Smrj /* 510ae115bc7Smrj * Remove the CPU from the list of available CPUs. 511ae115bc7Smrj */ 512ae115bc7Smrj cpu_del_unit(cp->cpu_id); 513ae115bc7Smrj 514ae115bc7Smrj if (error == ETIMEDOUT) { 515ae115bc7Smrj /* 516ae115bc7Smrj * The cpu was started, but never *seemed* to run any 517ae115bc7Smrj * code in the kernel; it's probably off spinning in its 518ae115bc7Smrj * own private world, though with potential references to 519ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 520ae115bc7Smrj * 521ae115bc7Smrj * Worse still, it may actually wake up some time later, 522ae115bc7Smrj * so rather than guess what it might or might not do, we 523ae115bc7Smrj * leave the fundamental data structures intact. 524ae115bc7Smrj */ 525ae115bc7Smrj cp->cpu_flags = 0; 526ae115bc7Smrj return; 527ae115bc7Smrj } 528ae115bc7Smrj 529ae115bc7Smrj /* 530ae115bc7Smrj * At this point, the only threads bound to this CPU should 531ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 532ae115bc7Smrj * and it's interrupt threads. Clean these up. 533ae115bc7Smrj */ 534ae115bc7Smrj cpu_destroy_bound_threads(cp); 535ae115bc7Smrj cp->cpu_idle_thread = NULL; 536ae115bc7Smrj 537ae115bc7Smrj /* 538ae115bc7Smrj * Free the interrupt stack. 539ae115bc7Smrj */ 540ae115bc7Smrj segkp_release(segkp, 541ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 542a3114836SGerry Liu cp->cpu_intr_stack = NULL; 543ae115bc7Smrj 544ae115bc7Smrj #ifdef TRAPTRACE 545ae115bc7Smrj /* 546ae115bc7Smrj * Discard the trap trace buffer 547ae115bc7Smrj */ 548ae115bc7Smrj { 549ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 550ae115bc7Smrj 551ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 5528f22c1dfSToomas Soome ttc->ttc_first = (uintptr_t)NULL; 553ae115bc7Smrj } 554ae115bc7Smrj #endif 555ae115bc7Smrj 556ae115bc7Smrj hat_cpu_offline(cp); 557ae115bc7Smrj 5582449e17fSsherrym ucode_free_space(cp); 5592449e17fSsherrym 560a3114836SGerry Liu /* Free CPU ID string and brand string. */ 561a3114836SGerry Liu if (cp->cpu_idstr) { 562a3114836SGerry Liu kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 563a3114836SGerry Liu cp->cpu_idstr = NULL; 564a3114836SGerry Liu } 565a3114836SGerry Liu if (cp->cpu_brandstr) { 566a3114836SGerry Liu kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 567a3114836SGerry Liu cp->cpu_brandstr = NULL; 568a3114836SGerry Liu } 569a3114836SGerry Liu 570a3114836SGerry Liu #if !defined(__xpv) 571a3114836SGerry Liu if (cp->cpu_m.mcpu_mwait != NULL) { 572a3114836SGerry Liu cpuid_mwait_free(cp); 573a3114836SGerry Liu cp->cpu_m.mcpu_mwait = NULL; 574a3114836SGerry Liu } 575a3114836SGerry Liu #endif 576a3114836SGerry Liu cpuid_free_space(cp); 577a3114836SGerry Liu 5780cfdb603Sjosephb if (cp->cpu_idt != CPU->cpu_idt) 5790cfdb603Sjosephb kmem_free(cp->cpu_idt, PAGESIZE); 5800cfdb603Sjosephb cp->cpu_idt = NULL; 581ae115bc7Smrj 58274ecdb51SJohn Levon kmem_free(cp->cpu_m.mcpu_ldt, LDT_CPU_SIZE); 58374ecdb51SJohn Levon cp->cpu_m.mcpu_ldt = NULL; 58474ecdb51SJohn Levon cp->cpu_m.mcpu_ldt_len = 0; 58574ecdb51SJohn Levon 5860cfdb603Sjosephb kmem_free(cp->cpu_gdt, PAGESIZE); 5870cfdb603Sjosephb cp->cpu_gdt = NULL; 588ae115bc7Smrj 589a3114836SGerry Liu if (cp->cpu_supp_freqs != NULL) { 590a3114836SGerry Liu size_t len = strlen(cp->cpu_supp_freqs) + 1; 591a3114836SGerry Liu kmem_free(cp->cpu_supp_freqs, len); 592a3114836SGerry Liu cp->cpu_supp_freqs = NULL; 593a3114836SGerry Liu } 594a3114836SGerry Liu 595ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 596ae115bc7Smrj 597ae115bc7Smrj kcpc_hw_fini(cp); 598ae115bc7Smrj 599ae115bc7Smrj cp->cpu_dispthread = NULL; 600ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 601ae115bc7Smrj 602ae115bc7Smrj cpu_vm_data_destroy(cp); 603ae115bc7Smrj 604a3114836SGerry Liu xc_fini_cpu(cp); 605ae115bc7Smrj disp_cpu_fini(cp); 606ae115bc7Smrj 607a3114836SGerry Liu ASSERT(cp != CPU0); 608a3114836SGerry Liu bzero(cp, sizeof (*cp)); 609a3114836SGerry Liu cp->cpu_next_free = cpu_free_list; 610a3114836SGerry Liu cpu_free_list = cp; 6117c478bd9Sstevel@tonic-gate } 6127c478bd9Sstevel@tonic-gate 6137c478bd9Sstevel@tonic-gate /* 6147c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 6157c478bd9Sstevel@tonic-gate * 6167c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 6177c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 6187c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 6197c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 6207c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 6217c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 6227c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 6237c478bd9Sstevel@tonic-gate * system. 6247c478bd9Sstevel@tonic-gate * 625ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 626a3114836SGerry Liu * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 627a3114836SGerry Liu * prior to acknowledging their readiness to the master, so this routine will 628ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 629ef50d8c0Sesaxe * global data safe. 630ef50d8c0Sesaxe * 6312201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 6322201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 6337c478bd9Sstevel@tonic-gate */ 6347c478bd9Sstevel@tonic-gate 635ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 636ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 637ae115bc7Smrj #endif 638ae115bc7Smrj 6397c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 6407c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 6417c478bd9Sstevel@tonic-gate #endif 6427c478bd9Sstevel@tonic-gate 6437c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 6447c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 6457c478bd9Sstevel@tonic-gate #endif 6467c478bd9Sstevel@tonic-gate 647ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 648ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 649ae115bc7Smrj #endif 650ae115bc7Smrj 6517c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 6527c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 6537c478bd9Sstevel@tonic-gate #endif 6547c478bd9Sstevel@tonic-gate 655ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 656ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 657ae115bc7Smrj #endif 658ae115bc7Smrj 6597c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 6607c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 6617c478bd9Sstevel@tonic-gate #endif 6627c478bd9Sstevel@tonic-gate 6637c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 6647c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 6657c478bd9Sstevel@tonic-gate #endif 6667c478bd9Sstevel@tonic-gate 6677c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 6687c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 6697c478bd9Sstevel@tonic-gate #endif 6707c478bd9Sstevel@tonic-gate 6717c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 6727c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 6737c478bd9Sstevel@tonic-gate #endif 6747c478bd9Sstevel@tonic-gate 6752201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 6762201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 6772201b277Skucharsk #endif 6787c478bd9Sstevel@tonic-gate 679ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 680ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 681ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 682ef50d8c0Sesaxe #endif 683ef50d8c0Sesaxe 684ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 685ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 686ee88d2b9Skchow #endif 687ee88d2b9Skchow 688512cf780Skchow #if defined(OPTERON_ERRATUM_298) 689512cf780Skchow int opteron_erratum_298; 690512cf780Skchow #endif 691512cf780Skchow 6925e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 6935e54b56dSHans Rosenfeld int opteron_erratum_721; 6945e54b56dSHans Rosenfeld #endif 6955e54b56dSHans Rosenfeld 696ae115bc7Smrj static void 697ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 698ae115bc7Smrj { 699ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 700ae115bc7Smrj cp->cpu_id, erratum); 701ae115bc7Smrj } 702ae115bc7Smrj 703ae115bc7Smrj static void 704ae115bc7Smrj workaround_applied(uint_t erratum) 705ae115bc7Smrj { 706ae115bc7Smrj if (erratum > 1000000) 707ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 708ae115bc7Smrj erratum); 709ae115bc7Smrj else 710ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 711ae115bc7Smrj erratum); 712ae115bc7Smrj } 713ae115bc7Smrj 714ae115bc7Smrj static void 715ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 716ae115bc7Smrj { 717ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 718ae115bc7Smrj cp->cpu_id, rw, msr, error); 719ae115bc7Smrj } 7207c478bd9Sstevel@tonic-gate 72192564cb1Sesaxe /* 722d2aeaf66SEric Saxe * Determine the number of nodes in a Hammer / Greyhound / Griffin family 723d2aeaf66SEric Saxe * system. 72492564cb1Sesaxe */ 72592564cb1Sesaxe static uint_t 72692564cb1Sesaxe opteron_get_nnodes(void) 72792564cb1Sesaxe { 72892564cb1Sesaxe static uint_t nnodes = 0; 72992564cb1Sesaxe 730d2aeaf66SEric Saxe if (nnodes == 0) { 73192564cb1Sesaxe #ifdef DEBUG 732d2aeaf66SEric Saxe uint_t family; 73392564cb1Sesaxe 734d2aeaf66SEric Saxe /* 735d2aeaf66SEric Saxe * This routine uses a PCI config space based mechanism 736d2aeaf66SEric Saxe * for retrieving the number of nodes in the system. 737d2aeaf66SEric Saxe * Device 24, function 0, offset 0x60 as used here is not 738d2aeaf66SEric Saxe * AMD processor architectural, and may not work on processor 739d2aeaf66SEric Saxe * families other than those listed below. 740d2aeaf66SEric Saxe * 741d2aeaf66SEric Saxe * Callers of this routine must ensure that we're running on 742d2aeaf66SEric Saxe * a processor which supports this mechanism. 743d2aeaf66SEric Saxe * The assertion below is meant to catch calls on unsupported 744d2aeaf66SEric Saxe * processors. 745d2aeaf66SEric Saxe */ 746d2aeaf66SEric Saxe family = cpuid_getfamily(CPU); 747d2aeaf66SEric Saxe ASSERT(family == 0xf || family == 0x10 || family == 0x11); 74892564cb1Sesaxe #endif /* DEBUG */ 74992564cb1Sesaxe 75092564cb1Sesaxe /* 75192564cb1Sesaxe * Obtain the number of nodes in the system from 75292564cb1Sesaxe * bits [6:4] of the Node ID register on node 0. 75392564cb1Sesaxe * 75492564cb1Sesaxe * The actual node count is NodeID[6:4] + 1 75592564cb1Sesaxe * 75692564cb1Sesaxe * The Node ID register is accessed via function 0, 75792564cb1Sesaxe * offset 0x60. Node 0 is device 24. 75892564cb1Sesaxe */ 75992564cb1Sesaxe nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 76092564cb1Sesaxe } 76192564cb1Sesaxe return (nnodes); 76292564cb1Sesaxe } 76392564cb1Sesaxe 764512cf780Skchow uint_t 765512cf780Skchow do_erratum_298(struct cpu *cpu) 766512cf780Skchow { 767512cf780Skchow static int osvwrc = -3; 768512cf780Skchow extern int osvw_opteron_erratum(cpu_t *, uint_t); 769512cf780Skchow 770512cf780Skchow /* 771512cf780Skchow * L2 Eviction May Occur During Processor Operation To Set 772512cf780Skchow * Accessed or Dirty Bit. 773512cf780Skchow */ 774512cf780Skchow if (osvwrc == -3) { 775512cf780Skchow osvwrc = osvw_opteron_erratum(cpu, 298); 776512cf780Skchow } else { 777512cf780Skchow /* osvw return codes should be consistent for all cpus */ 778512cf780Skchow ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 779512cf780Skchow } 780512cf780Skchow 781512cf780Skchow switch (osvwrc) { 782512cf780Skchow case 0: /* erratum is not present: do nothing */ 783512cf780Skchow break; 784512cf780Skchow case 1: /* erratum is present: BIOS workaround applied */ 785512cf780Skchow /* 786512cf780Skchow * check if workaround is actually in place and issue warning 787512cf780Skchow * if not. 788512cf780Skchow */ 789512cf780Skchow if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 790512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 791512cf780Skchow #if defined(OPTERON_ERRATUM_298) 792512cf780Skchow opteron_erratum_298++; 793512cf780Skchow #else 794512cf780Skchow workaround_warning(cpu, 298); 795512cf780Skchow return (1); 796512cf780Skchow #endif 797512cf780Skchow } 798512cf780Skchow break; 799512cf780Skchow case -1: /* cannot determine via osvw: check cpuid */ 800512cf780Skchow if ((cpuid_opteron_erratum(cpu, 298) > 0) && 801512cf780Skchow (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 802512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 803512cf780Skchow #if defined(OPTERON_ERRATUM_298) 804512cf780Skchow opteron_erratum_298++; 805512cf780Skchow #else 806512cf780Skchow workaround_warning(cpu, 298); 807512cf780Skchow return (1); 808512cf780Skchow #endif 809512cf780Skchow } 810512cf780Skchow break; 811512cf780Skchow } 812512cf780Skchow return (0); 813512cf780Skchow } 814512cf780Skchow 8157c478bd9Sstevel@tonic-gate uint_t 8167c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 8177c478bd9Sstevel@tonic-gate { 8187c478bd9Sstevel@tonic-gate uint_t missing = 0; 8197c478bd9Sstevel@tonic-gate 8207c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 8217c478bd9Sstevel@tonic-gate 8227c478bd9Sstevel@tonic-gate /*LINTED*/ 8237c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 8247c478bd9Sstevel@tonic-gate /* 8257c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 8267c478bd9Sstevel@tonic-gate */ 8277c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 8287c478bd9Sstevel@tonic-gate /* 8297c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 8307c478bd9Sstevel@tonic-gate */ 831ae115bc7Smrj opteron_erratum_88++; 8327c478bd9Sstevel@tonic-gate #else 833ae115bc7Smrj workaround_warning(cpu, 88); 8347c478bd9Sstevel@tonic-gate missing++; 8357c478bd9Sstevel@tonic-gate #endif 8367c478bd9Sstevel@tonic-gate } 8377c478bd9Sstevel@tonic-gate 8387c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 8397c478bd9Sstevel@tonic-gate /* 8407c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 8417c478bd9Sstevel@tonic-gate */ 8427c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 8437c478bd9Sstevel@tonic-gate /* 8447c478bd9Sstevel@tonic-gate * fix is in trap.c 8457c478bd9Sstevel@tonic-gate */ 8467c478bd9Sstevel@tonic-gate opteron_erratum_91++; 8477c478bd9Sstevel@tonic-gate #else 848ae115bc7Smrj workaround_warning(cpu, 91); 8497c478bd9Sstevel@tonic-gate missing++; 8507c478bd9Sstevel@tonic-gate #endif 8517c478bd9Sstevel@tonic-gate } 8527c478bd9Sstevel@tonic-gate 8537c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 8547c478bd9Sstevel@tonic-gate /* 8557c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 8567c478bd9Sstevel@tonic-gate */ 8577c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 8587c478bd9Sstevel@tonic-gate /* 8597c478bd9Sstevel@tonic-gate * fix is in trap.c 8607c478bd9Sstevel@tonic-gate */ 8617c478bd9Sstevel@tonic-gate opteron_erratum_93++; 8627c478bd9Sstevel@tonic-gate #else 863ae115bc7Smrj workaround_warning(cpu, 93); 8647c478bd9Sstevel@tonic-gate missing++; 8657c478bd9Sstevel@tonic-gate #endif 8667c478bd9Sstevel@tonic-gate } 8677c478bd9Sstevel@tonic-gate 8687c478bd9Sstevel@tonic-gate /*LINTED*/ 8697c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 8707c478bd9Sstevel@tonic-gate /* 8717c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 8727c478bd9Sstevel@tonic-gate */ 8737c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 8747c478bd9Sstevel@tonic-gate #if defined(_LP64) 8757c478bd9Sstevel@tonic-gate /* 8767c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 8777c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 8787c478bd9Sstevel@tonic-gate * range mod 4G. 8797c478bd9Sstevel@tonic-gate */ 8807c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 8817c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 8827c478bd9Sstevel@tonic-gate 8837c478bd9Sstevel@tonic-gate /*LINTED*/ 8847c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 885ae115bc7Smrj opteron_erratum_95++; 8867c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 8877c478bd9Sstevel@tonic-gate #else 888ae115bc7Smrj workaround_warning(cpu, 95); 8897c478bd9Sstevel@tonic-gate missing++; 890ae115bc7Smrj #endif 8917c478bd9Sstevel@tonic-gate } 8927c478bd9Sstevel@tonic-gate 8937c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 8947c478bd9Sstevel@tonic-gate /* 8957c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 8967c478bd9Sstevel@tonic-gate */ 8977c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8987c478bd9Sstevel@tonic-gate /* 8997c478bd9Sstevel@tonic-gate * fix is in trap.c 9007c478bd9Sstevel@tonic-gate */ 9017c478bd9Sstevel@tonic-gate opteron_erratum_100++; 9027c478bd9Sstevel@tonic-gate #else 903ae115bc7Smrj workaround_warning(cpu, 100); 9047c478bd9Sstevel@tonic-gate missing++; 9057c478bd9Sstevel@tonic-gate #endif 9067c478bd9Sstevel@tonic-gate } 9077c478bd9Sstevel@tonic-gate 9087c478bd9Sstevel@tonic-gate /*LINTED*/ 9097c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 9107c478bd9Sstevel@tonic-gate /* 9117c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 9127c478bd9Sstevel@tonic-gate * Some Processors 9137c478bd9Sstevel@tonic-gate */ 9147c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 9157c478bd9Sstevel@tonic-gate /* 9167c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 9177c478bd9Sstevel@tonic-gate * those processors) 9187c478bd9Sstevel@tonic-gate */ 9197c478bd9Sstevel@tonic-gate #else 920ae115bc7Smrj workaround_warning(cpu, 108); 9217c478bd9Sstevel@tonic-gate missing++; 9227c478bd9Sstevel@tonic-gate #endif 9237c478bd9Sstevel@tonic-gate } 9247c478bd9Sstevel@tonic-gate 9257c478bd9Sstevel@tonic-gate /*LINTED*/ 926ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 9277c478bd9Sstevel@tonic-gate /* 928fb2caebeSRandy Fishel * Certain Reverse REP MOVS May Produce Unpredictable Behavior 9297c478bd9Sstevel@tonic-gate */ 9307c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 931ae115bc7Smrj /* 932ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 933ae115bc7Smrj */ 934ae115bc7Smrj uint64_t value; 935ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 936ae115bc7Smrj int err; 937ae115bc7Smrj 938ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 939ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 940ae115bc7Smrj workaround_warning(cpu, 109); 941ae115bc7Smrj missing++; 942ae115bc7Smrj } 943ae115bc7Smrj if (value == 0) 9447c478bd9Sstevel@tonic-gate opteron_erratum_109++; 9457c478bd9Sstevel@tonic-gate #else 946ae115bc7Smrj workaround_warning(cpu, 109); 9477c478bd9Sstevel@tonic-gate missing++; 9487c478bd9Sstevel@tonic-gate #endif 949ae115bc7Smrj /*CONSTANTCONDITION*/ 950ae115bc7Smrj } while (0); 951ae115bc7Smrj 9527c478bd9Sstevel@tonic-gate /*LINTED*/ 9537c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 9547c478bd9Sstevel@tonic-gate /* 9557c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 9567c478bd9Sstevel@tonic-gate * Processor Hang 9577c478bd9Sstevel@tonic-gate */ 9587c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 959ae115bc7Smrj #if defined(_LP64) 9607c478bd9Sstevel@tonic-gate /* 9617c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 9627c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 9637c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 9647c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 9657c478bd9Sstevel@tonic-gate */ 966ae115bc7Smrj if (opteron_erratum_121) 967ae115bc7Smrj opteron_erratum_121++; 968ae115bc7Smrj else { 969ae115bc7Smrj if (hole_start) { 970ae115bc7Smrj hole_start -= PAGESIZE; 971ae115bc7Smrj } else { 972ae115bc7Smrj /* 973ae115bc7Smrj * hole_start not yet initialized by 974ae115bc7Smrj * mmu_init. Initialize hole_start 975ae115bc7Smrj * with value to be subtracted. 976ae115bc7Smrj */ 977ae115bc7Smrj hole_start = PAGESIZE; 9787c478bd9Sstevel@tonic-gate } 979ae115bc7Smrj opteron_erratum_121++; 9807c478bd9Sstevel@tonic-gate } 981ae115bc7Smrj #endif /* _LP64 */ 9827c478bd9Sstevel@tonic-gate #else 983ae115bc7Smrj workaround_warning(cpu, 121); 9847c478bd9Sstevel@tonic-gate missing++; 9857c478bd9Sstevel@tonic-gate #endif 9867c478bd9Sstevel@tonic-gate } 9877c478bd9Sstevel@tonic-gate 9887c478bd9Sstevel@tonic-gate /*LINTED*/ 989ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 9907c478bd9Sstevel@tonic-gate /* 991ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 9927c478bd9Sstevel@tonic-gate * Multiprocessor Systems 9937c478bd9Sstevel@tonic-gate */ 9947c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 995ae115bc7Smrj uint64_t value; 996ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 997ae115bc7Smrj int error; 998ae115bc7Smrj 9997c478bd9Sstevel@tonic-gate /* 10007c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 10017c478bd9Sstevel@tonic-gate * or multi-processor). 10027c478bd9Sstevel@tonic-gate */ 1003843e1988Sjohnlev #if defined(__xpv) 1004843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1005843e1988Sjohnlev break; 1006349b53ddSStuart Maybee if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 1007843e1988Sjohnlev break; 1008843e1988Sjohnlev #else 100992564cb1Sesaxe if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 1010ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 1011ae115bc7Smrj break; 1012843e1988Sjohnlev #endif 1013ae115bc7Smrj /* disable TLB Flush Filter */ 1014ae115bc7Smrj 1015ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 1016ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1017ae115bc7Smrj workaround_warning(cpu, 122); 1018ae115bc7Smrj missing++; 1019ae115bc7Smrj } else { 1020ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 1021ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 1022ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 1023ae115bc7Smrj workaround_warning(cpu, 122); 1024ae115bc7Smrj missing++; 1025ae115bc7Smrj } 10267c478bd9Sstevel@tonic-gate } 1027ae115bc7Smrj opteron_erratum_122++; 10287c478bd9Sstevel@tonic-gate #else 1029ae115bc7Smrj workaround_warning(cpu, 122); 10307c478bd9Sstevel@tonic-gate missing++; 10317c478bd9Sstevel@tonic-gate #endif 1032ae115bc7Smrj /*CONSTANTCONDITION*/ 1033ae115bc7Smrj } while (0); 1034403c216aSkchow 10357c478bd9Sstevel@tonic-gate /*LINTED*/ 1036ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 10377c478bd9Sstevel@tonic-gate /* 10387c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 10397c478bd9Sstevel@tonic-gate * Dual Core Processors 10407c478bd9Sstevel@tonic-gate */ 1041ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 1042ae115bc7Smrj uint64_t value; 1043ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 1044ae115bc7Smrj int err; 1045ae115bc7Smrj 10467c478bd9Sstevel@tonic-gate /* 10477c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 10487c478bd9Sstevel@tonic-gate */ 1049ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 1050ae115bc7Smrj break; 1051843e1988Sjohnlev #if defined(__xpv) 1052843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1053843e1988Sjohnlev break; 1054843e1988Sjohnlev #endif 1055ae115bc7Smrj /* 1056ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 1057ae115bc7Smrj */ 1058ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 1059ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 1060ae115bc7Smrj workaround_warning(cpu, 123); 1061ae115bc7Smrj missing++; 10627c478bd9Sstevel@tonic-gate } 1063ae115bc7Smrj if (value == 0) 1064ae115bc7Smrj opteron_erratum_123++; 1065ae115bc7Smrj #else 1066ae115bc7Smrj workaround_warning(cpu, 123); 1067ae115bc7Smrj missing++; 1068ae115bc7Smrj 1069403c216aSkchow #endif 1070ae115bc7Smrj /*CONSTANTCONDITION*/ 1071ae115bc7Smrj } while (0); 10722201b277Skucharsk 10732201b277Skucharsk /*LINTED*/ 1074ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 10752201b277Skucharsk /* 10762201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 10772201b277Skucharsk * Waiting for a Probe Response 10782201b277Skucharsk */ 1079ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 1080ae115bc7Smrj uint64_t nbcfg; 1081ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 1082ae115bc7Smrj const uint64_t wabits = 1083ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1084ae115bc7Smrj int error; 1085ae115bc7Smrj 10862201b277Skucharsk /* 10872201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 10882201b277Skucharsk */ 1089ae115bc7Smrj if (opteron_erratum_131) 1090ae115bc7Smrj break; 1091843e1988Sjohnlev #if defined(__xpv) 1092843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1093843e1988Sjohnlev break; 1094349b53ddSStuart Maybee if (xpv_nr_phys_cpus() < 4) 1095843e1988Sjohnlev break; 1096843e1988Sjohnlev #else 109792564cb1Sesaxe if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1098ae115bc7Smrj break; 1099843e1988Sjohnlev #endif 1100ae115bc7Smrj /* 1101ae115bc7Smrj * Print a warning if neither of the workarounds for 1102ae115bc7Smrj * erratum 131 is present. 1103ae115bc7Smrj */ 1104ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1105ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1106ae115bc7Smrj workaround_warning(cpu, 131); 1107ae115bc7Smrj missing++; 1108ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 1109ae115bc7Smrj opteron_erratum_131++; 1110ae115bc7Smrj } else { 1111ae115bc7Smrj /* cannot have both workarounds set */ 1112ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 11132201b277Skucharsk } 1114ae115bc7Smrj #else 1115ae115bc7Smrj workaround_warning(cpu, 131); 1116ae115bc7Smrj missing++; 11172201b277Skucharsk #endif 1118ae115bc7Smrj /*CONSTANTCONDITION*/ 1119ae115bc7Smrj } while (0); 1120ef50d8c0Sesaxe 1121ef50d8c0Sesaxe /* 1122ae115bc7Smrj * This isn't really an erratum, but for convenience the 1123ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 1124bf9b145bSRobert Mustacchi * Note, the technique only is valid on families before 12h and 1125bf9b145bSRobert Mustacchi * certainly doesn't work when we're virtualized. This is checked for in 1126bf9b145bSRobert Mustacchi * the erratum workaround. 1127ef50d8c0Sesaxe */ 1128ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1129ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1130ef50d8c0Sesaxe /* 1131ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 1132ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 1133ef50d8c0Sesaxe */ 1134ef50d8c0Sesaxe if (opteron_workaround_6336786) { 1135ef50d8c0Sesaxe opteron_workaround_6336786++; 1136843e1988Sjohnlev #if defined(__xpv) 1137843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1138349b53ddSStuart Maybee xpv_nr_phys_cpus() > 1) || 1139843e1988Sjohnlev opteron_workaround_6336786_UP) { 1140843e1988Sjohnlev /* 114192564cb1Sesaxe * XXPV Hmm. We can't walk the Northbridges on 1142843e1988Sjohnlev * the hypervisor; so just complain and drive 1143843e1988Sjohnlev * on. This probably needs to be fixed in 1144843e1988Sjohnlev * the hypervisor itself. 1145843e1988Sjohnlev */ 1146843e1988Sjohnlev opteron_workaround_6336786++; 1147843e1988Sjohnlev workaround_warning(cpu, 6336786); 1148843e1988Sjohnlev #else /* __xpv */ 114992564cb1Sesaxe } else if ((opteron_get_nnodes() * 1150d38257c4Sesaxe cpuid_get_ncpu_per_chip(cpu) > 1) || 1151ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 115292564cb1Sesaxe 115392564cb1Sesaxe uint_t node, nnodes; 1154ae115bc7Smrj uint8_t data; 1155ae115bc7Smrj 115692564cb1Sesaxe nnodes = opteron_get_nnodes(); 115792564cb1Sesaxe for (node = 0; node < nnodes; node++) { 1158ef50d8c0Sesaxe /* 1159ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 1160ef50d8c0Sesaxe * Northbridge device is the node id + 24. 1161ef50d8c0Sesaxe */ 1162ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 1163ef50d8c0Sesaxe data &= 0xFC; 1164ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 1165ef50d8c0Sesaxe } 1166ef50d8c0Sesaxe opteron_workaround_6336786++; 1167843e1988Sjohnlev #endif /* __xpv */ 1168ef50d8c0Sesaxe } 1169ae115bc7Smrj #else 1170ae115bc7Smrj workaround_warning(cpu, 6336786); 1171ae115bc7Smrj missing++; 1172ef50d8c0Sesaxe #endif 1173ae115bc7Smrj } 1174ee88d2b9Skchow 1175ee88d2b9Skchow /*LINTED*/ 1176ee88d2b9Skchow /* 1177bf9b145bSRobert Mustacchi * Mutex primitives don't work as expected. This is erratum #147 from 1178bf9b145bSRobert Mustacchi * 'Revision Guide for AMD Athlon 64 and AMD Opteron Processors' 1179bf9b145bSRobert Mustacchi * document 25759. 1180ee88d2b9Skchow */ 1181ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1182ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1183ee88d2b9Skchow /* 1184ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1185512cf780Skchow * MSR_AMD_BU_CFG set, then not applicable. The workaround 1186ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1187ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1188ee88d2b9Skchow * possible subsequent read-modify-write ops. 1189ee88d2b9Skchow * 1190ee88d2b9Skchow * It is too early in boot to call the patch routine so 1191ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1192ee88d2b9Skchow */ 1193ee88d2b9Skchow if (opteron_workaround_6323525) { 1194ee88d2b9Skchow opteron_workaround_6323525++; 1195843e1988Sjohnlev #if defined(__xpv) 11967417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1197843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1198843e1988Sjohnlev /* 1199843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1200843e1988Sjohnlev * operations are supported? 1201843e1988Sjohnlev */ 1202349b53ddSStuart Maybee if (xpv_nr_phys_cpus() > 1) 1203843e1988Sjohnlev opteron_workaround_6323525++; 1204843e1988Sjohnlev } else { 1205843e1988Sjohnlev /* 1206843e1988Sjohnlev * We have no way to tell how many physical 1207843e1988Sjohnlev * cpus there are, or even if this processor 1208843e1988Sjohnlev * has the problem, so enable the workaround 1209843e1988Sjohnlev * unconditionally (at some performance cost). 1210843e1988Sjohnlev */ 1211843e1988Sjohnlev opteron_workaround_6323525++; 1212843e1988Sjohnlev } 1213843e1988Sjohnlev #else /* __xpv */ 12147417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) && 12157417cfdeSKuriakose Kuruvilla ((opteron_get_nnodes() * 1216ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 121748b2bf45SKit Chow if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1218ee88d2b9Skchow opteron_workaround_6323525++; 1219843e1988Sjohnlev #endif /* __xpv */ 1220ee88d2b9Skchow } 1221ae115bc7Smrj #else 1222ae115bc7Smrj workaround_warning(cpu, 6323525); 1223ae115bc7Smrj missing++; 1224ee88d2b9Skchow #endif 1225ae115bc7Smrj } 1226ae115bc7Smrj 1227512cf780Skchow missing += do_erratum_298(cpu); 1228512cf780Skchow 12295e54b56dSHans Rosenfeld if (cpuid_opteron_erratum(cpu, 721) > 0) { 12305e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 1231850ad55aSHans Rosenfeld on_trap_data_t otd; 1232850ad55aSHans Rosenfeld 1233850ad55aSHans Rosenfeld if (!on_trap(&otd, OT_DATA_ACCESS)) 1234850ad55aSHans Rosenfeld wrmsr(MSR_AMD_DE_CFG, 1235850ad55aSHans Rosenfeld rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721); 1236850ad55aSHans Rosenfeld no_trap(); 1237850ad55aSHans Rosenfeld 12385e54b56dSHans Rosenfeld opteron_erratum_721++; 12395e54b56dSHans Rosenfeld #else 12405e54b56dSHans Rosenfeld workaround_warning(cpu, 721); 12415e54b56dSHans Rosenfeld missing++; 12425e54b56dSHans Rosenfeld #endif 12435e54b56dSHans Rosenfeld } 12445e54b56dSHans Rosenfeld 1245843e1988Sjohnlev #ifdef __xpv 1246843e1988Sjohnlev return (0); 1247843e1988Sjohnlev #else 12487c478bd9Sstevel@tonic-gate return (missing); 1249843e1988Sjohnlev #endif 12507c478bd9Sstevel@tonic-gate } 12517c478bd9Sstevel@tonic-gate 12527c478bd9Sstevel@tonic-gate void 12537c478bd9Sstevel@tonic-gate workaround_errata_end() 12547c478bd9Sstevel@tonic-gate { 1255ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1256ae115bc7Smrj if (opteron_erratum_88) 1257ae115bc7Smrj workaround_applied(88); 1258ae115bc7Smrj #endif 1259ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1260ae115bc7Smrj if (opteron_erratum_91) 1261ae115bc7Smrj workaround_applied(91); 1262ae115bc7Smrj #endif 1263ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1264ae115bc7Smrj if (opteron_erratum_93) 1265ae115bc7Smrj workaround_applied(93); 1266ae115bc7Smrj #endif 1267ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1268ae115bc7Smrj if (opteron_erratum_95) 1269ae115bc7Smrj workaround_applied(95); 1270ae115bc7Smrj #endif 1271ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1272ae115bc7Smrj if (opteron_erratum_100) 1273ae115bc7Smrj workaround_applied(100); 1274ae115bc7Smrj #endif 1275ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1276ae115bc7Smrj if (opteron_erratum_108) 1277ae115bc7Smrj workaround_applied(108); 1278ae115bc7Smrj #endif 12797c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 12807c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 12812201b277Skucharsk cmn_err(CE_WARN, 12822201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12832201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 12842201b277Skucharsk " system's BIOS to a version\ncontaining this" 12852201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12862201b277Skucharsk " system\noperation may occur.\n"); 12877c478bd9Sstevel@tonic-gate } 1288ae115bc7Smrj #endif 1289ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1290ae115bc7Smrj if (opteron_erratum_121) 1291ae115bc7Smrj workaround_applied(121); 1292ae115bc7Smrj #endif 1293ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1294ae115bc7Smrj if (opteron_erratum_122) 1295ae115bc7Smrj workaround_applied(122); 1296ae115bc7Smrj #endif 12977c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 12987c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 12992201b277Skucharsk cmn_err(CE_WARN, 13002201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 13012201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 13022201b277Skucharsk " system's BIOS to a version\ncontaining this" 13032201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 13042201b277Skucharsk " system\noperation may occur.\n"); 13057c478bd9Sstevel@tonic-gate } 1306ae115bc7Smrj #endif 13072201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 13082201b277Skucharsk if (opteron_erratum_131) { 13092201b277Skucharsk cmn_err(CE_WARN, 13102201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 13112201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 13122201b277Skucharsk " system's BIOS to a version\ncontaining this" 13132201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 13142201b277Skucharsk " system\noperation may occur.\n"); 13152201b277Skucharsk } 1316ae115bc7Smrj #endif 1317ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1318ae115bc7Smrj if (opteron_workaround_6336786) 1319ae115bc7Smrj workaround_applied(6336786); 1320ae115bc7Smrj #endif 1321ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1322ae115bc7Smrj if (opteron_workaround_6323525) 1323ae115bc7Smrj workaround_applied(6323525); 1324ae115bc7Smrj #endif 1325512cf780Skchow #if defined(OPTERON_ERRATUM_298) 1326512cf780Skchow if (opteron_erratum_298) { 1327512cf780Skchow cmn_err(CE_WARN, 1328512cf780Skchow "BIOS microcode patch for AMD 64/Opteron(tm)" 1329512cf780Skchow " processor\nerratum 298 was not detected; updating your" 1330512cf780Skchow " system's BIOS to a version\ncontaining this" 1331512cf780Skchow " microcode patch is HIGHLY recommended or erroneous" 1332512cf780Skchow " system\noperation may occur.\n"); 1333512cf780Skchow } 1334512cf780Skchow #endif 13355e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 13365e54b56dSHans Rosenfeld if (opteron_erratum_721) 13375e54b56dSHans Rosenfeld workaround_applied(721); 13385e54b56dSHans Rosenfeld #endif 13397c478bd9Sstevel@tonic-gate } 13407c478bd9Sstevel@tonic-gate 1341ae115bc7Smrj /* 1342a3114836SGerry Liu * The procset_slave and procset_master are used to synchronize 1343a3114836SGerry Liu * between the control CPU and the target CPU when starting CPUs. 1344ae115bc7Smrj */ 1345a3114836SGerry Liu static cpuset_t procset_slave, procset_master; 1346a3114836SGerry Liu 1347a3114836SGerry Liu static void 1348a3114836SGerry Liu mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1349a3114836SGerry Liu { 1350a3114836SGerry Liu cpuset_t tempset; 1351a3114836SGerry Liu 1352a3114836SGerry Liu for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1353a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1354a3114836SGerry Liu SMT_PAUSE(); 1355a3114836SGerry Liu } 1356a3114836SGerry Liu CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1357a3114836SGerry Liu } 1358a3114836SGerry Liu 1359a3114836SGerry Liu static void 1360a3114836SGerry Liu mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1361a3114836SGerry Liu { 1362a3114836SGerry Liu cpuset_t tempset; 1363a3114836SGerry Liu 1364a3114836SGerry Liu CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1365a3114836SGerry Liu for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1366a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1367a3114836SGerry Liu SMT_PAUSE(); 1368a3114836SGerry Liu } 1369a3114836SGerry Liu } 1370a3114836SGerry Liu 1371ae115bc7Smrj int 1372a3114836SGerry Liu mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1373ae115bc7Smrj { 1374a3114836SGerry Liu _NOTE(ARGUNUSED(boot)); 1375a3114836SGerry Liu 1376ae115bc7Smrj void *ctx; 1377ae115bc7Smrj int delays; 1378ae115bc7Smrj int error = 0; 1379a3114836SGerry Liu cpuset_t tempset; 1380a3114836SGerry Liu processorid_t cpuid; 1381a3114836SGerry Liu #ifndef __xpv 1382a3114836SGerry Liu extern void cpupm_init(cpu_t *); 1383a3114836SGerry Liu #endif 1384ae115bc7Smrj 1385a3114836SGerry Liu ASSERT(cp != NULL); 1386a3114836SGerry Liu cpuid = cp->cpu_id; 1387a3114836SGerry Liu ctx = mach_cpucontext_alloc(cp); 1388a3114836SGerry Liu if (ctx == NULL) { 1389a3114836SGerry Liu cmn_err(CE_WARN, 1390a3114836SGerry Liu "cpu%d: failed to allocate context", cp->cpu_id); 1391a3114836SGerry Liu return (EAGAIN); 1392ae115bc7Smrj } 1393a3114836SGerry Liu error = mach_cpu_start(cp, ctx); 1394a3114836SGerry Liu if (error != 0) { 1395a3114836SGerry Liu cmn_err(CE_WARN, 1396a3114836SGerry Liu "cpu%d: failed to start, error %d", cp->cpu_id, error); 1397a3114836SGerry Liu mach_cpucontext_free(cp, ctx, error); 1398ae115bc7Smrj return (error); 1399ae115bc7Smrj } 1400ae115bc7Smrj 1401a3114836SGerry Liu for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1402a3114836SGerry Liu delays++) { 1403ae115bc7Smrj if (delays == 500) { 1404ae115bc7Smrj /* 1405ae115bc7Smrj * After five seconds, things are probably looking 1406ae115bc7Smrj * a bit bleak - explain the hang. 1407ae115bc7Smrj */ 1408ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1409a3114836SGerry Liu "but not running in the kernel yet", cpuid); 1410ae115bc7Smrj } else if (delays > 2000) { 1411ae115bc7Smrj /* 1412ae115bc7Smrj * We waited at least 20 seconds, bail .. 1413ae115bc7Smrj */ 1414ae115bc7Smrj error = ETIMEDOUT; 1415a3114836SGerry Liu cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1416ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1417ae115bc7Smrj return (error); 1418ae115bc7Smrj } 1419ae115bc7Smrj 1420ae115bc7Smrj /* 1421ae115bc7Smrj * wait at least 10ms, then check again.. 1422ae115bc7Smrj */ 1423ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1424a3114836SGerry Liu tempset = *((volatile cpuset_t *)&procset_slave); 1425ae115bc7Smrj } 1426a3114836SGerry Liu CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1427ae115bc7Smrj 1428ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1429ae115bc7Smrj 1430843e1988Sjohnlev #ifndef __xpv 1431ae115bc7Smrj if (tsc_gethrtime_enable) 1432a3114836SGerry Liu tsc_sync_master(cpuid); 1433843e1988Sjohnlev #endif 1434ae115bc7Smrj 1435ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1436a3114836SGerry Liu (*dtrace_cpu_init)(cpuid); 1437a3114836SGerry Liu } 1438a3114836SGerry Liu 1439a3114836SGerry Liu /* 1440a3114836SGerry Liu * During CPU DR operations, the cpu_lock is held by current 1441a3114836SGerry Liu * (the control) thread. We can't release the cpu_lock here 1442a3114836SGerry Liu * because that will break the CPU DR logic. 1443a3114836SGerry Liu * On the other hand, CPUPM and processor group initialization 1444a3114836SGerry Liu * routines need to access the cpu_lock. So we invoke those 1445a3114836SGerry Liu * routines here on behalf of mp_startup_common(). 1446a3114836SGerry Liu * 1447a3114836SGerry Liu * CPUPM and processor group initialization routines depend 1448a3114836SGerry Liu * on the cpuid probing results. Wait for mp_startup_common() 1449a3114836SGerry Liu * to signal that cpuid probing is done. 1450a3114836SGerry Liu */ 1451a3114836SGerry Liu mp_startup_wait(&procset_slave, cpuid); 1452a3114836SGerry Liu #ifndef __xpv 1453a3114836SGerry Liu cpupm_init(cp); 1454a3114836SGerry Liu #endif 1455a3114836SGerry Liu (void) pg_cpu_init(cp, B_FALSE); 1456a3114836SGerry Liu cpu_set_state(cp); 1457a3114836SGerry Liu mp_startup_signal(&procset_master, cpuid); 1458a3114836SGerry Liu 1459a3114836SGerry Liu return (0); 1460a3114836SGerry Liu } 1461a3114836SGerry Liu 1462a3114836SGerry Liu /* 1463a3114836SGerry Liu * Start a single cpu, assuming that the kernel context is available 1464a3114836SGerry Liu * to successfully start another cpu. 1465a3114836SGerry Liu * 1466a3114836SGerry Liu * (For example, real mode code is mapped into the right place 1467a3114836SGerry Liu * in memory and is ready to be run.) 1468a3114836SGerry Liu */ 1469a3114836SGerry Liu int 1470a3114836SGerry Liu start_cpu(processorid_t who) 1471a3114836SGerry Liu { 1472a3114836SGerry Liu cpu_t *cp; 1473a3114836SGerry Liu int error = 0; 1474a3114836SGerry Liu cpuset_t tempset; 1475a3114836SGerry Liu 1476a3114836SGerry Liu ASSERT(who != 0); 1477a3114836SGerry Liu 1478a3114836SGerry Liu /* 1479a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1480a3114836SGerry Liu * before attempting to start the cpu. 1481a3114836SGerry Liu */ 1482a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1483ae115bc7Smrj /* 1484a3114836SGerry Liu * Kick off a reap in case that helps us with 1485a3114836SGerry Liu * later attempts .. 1486ae115bc7Smrj */ 1487a3114836SGerry Liu kmem_reap(); 1488a3114836SGerry Liu return (ENOMEM); 1489a3114836SGerry Liu } 1490a3114836SGerry Liu 1491a3114836SGerry Liu /* 1492a3114836SGerry Liu * First configure cpu. 1493a3114836SGerry Liu */ 1494a3114836SGerry Liu cp = mp_cpu_configure_common(who, B_TRUE); 1495a3114836SGerry Liu ASSERT(cp != NULL); 1496a3114836SGerry Liu 1497a3114836SGerry Liu /* 1498a3114836SGerry Liu * Then start cpu. 1499a3114836SGerry Liu */ 1500a3114836SGerry Liu error = mp_start_cpu_common(cp, B_TRUE); 1501a3114836SGerry Liu if (error != 0) { 1502a3114836SGerry Liu mp_cpu_unconfigure_common(cp, error); 1503a3114836SGerry Liu return (error); 1504ae115bc7Smrj } 1505ae115bc7Smrj 1506a3114836SGerry Liu mutex_exit(&cpu_lock); 1507a3114836SGerry Liu tempset = cpu_ready_set; 1508a3114836SGerry Liu while (!CPU_IN_SET(tempset, who)) { 1509a3114836SGerry Liu drv_usecwait(1); 1510a3114836SGerry Liu tempset = *((volatile cpuset_t *)&cpu_ready_set); 1511a3114836SGerry Liu } 1512a3114836SGerry Liu mutex_enter(&cpu_lock); 1513ae115bc7Smrj 1514ae115bc7Smrj return (0); 1515ae115bc7Smrj } 15167c478bd9Sstevel@tonic-gate 15177c478bd9Sstevel@tonic-gate void 15187c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 15197c478bd9Sstevel@tonic-gate { 1520a3114836SGerry Liu _NOTE(ARGUNUSED(cprboot)); 1521a3114836SGerry Liu 1522ae115bc7Smrj uint_t who; 1523ae115bc7Smrj uint_t bootcpuid = 0; 15247c478bd9Sstevel@tonic-gate 15257c478bd9Sstevel@tonic-gate /* 15267c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 15277c478bd9Sstevel@tonic-gate */ 15287c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 15297c478bd9Sstevel@tonic-gate 15302428aad8SPatrick Mooney #if !defined(__xpv) 15312428aad8SPatrick Mooney init_cpu_id_gdt(CPU); 15322428aad8SPatrick Mooney #endif 15332428aad8SPatrick Mooney 153419397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 153519397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 153619397407SSherry Moore 153739df76fbSAndy Fiddaman /* 153839df76fbSAndy Fiddaman * KPTI initialisation happens very early in boot, before logging is 153939df76fbSAndy Fiddaman * set up. Output a status message now as the boot CPU comes online. 154039df76fbSAndy Fiddaman */ 154139df76fbSAndy Fiddaman cmn_err(CE_CONT, "?KPTI %s (PCID %s, INVPCID %s)\n", 154239df76fbSAndy Fiddaman kpti_enable ? "enabled" : "disabled", 154339df76fbSAndy Fiddaman x86_use_pcid == 1 ? "in use" : 154439df76fbSAndy Fiddaman (is_x86_feature(x86_featureset, X86FSET_PCID) ? "disabled" : 154539df76fbSAndy Fiddaman "not supported"), 154639df76fbSAndy Fiddaman x86_use_pcid == 1 && x86_use_invpcid == 1 ? "in use" : 154739df76fbSAndy Fiddaman (is_x86_feature(x86_featureset, X86FSET_INVPCID) ? "disabled" : 154839df76fbSAndy Fiddaman "not supported")); 154939df76fbSAndy Fiddaman 15507c478bd9Sstevel@tonic-gate /* 15517c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 15527c478bd9Sstevel@tonic-gate */ 15537c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 15547c478bd9Sstevel@tonic-gate 1555ae115bc7Smrj /* 1556ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1557ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1558ae115bc7Smrj * precisely the same reason. 1559ae115bc7Smrj */ 1560ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1561ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1562ae115bc7Smrj 15637c478bd9Sstevel@tonic-gate /* 1564a3114836SGerry Liu * skip the rest of this if 1565a3114836SGerry Liu * . only 1 cpu dectected and system isn't hotplug-capable 1566a3114836SGerry Liu * . not using MP 15677c478bd9Sstevel@tonic-gate */ 1568a3114836SGerry Liu if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1569a3114836SGerry Liu use_mp == 0) { 15707c478bd9Sstevel@tonic-gate if (use_mp == 0) 15717c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 15727c478bd9Sstevel@tonic-gate goto done; 15737c478bd9Sstevel@tonic-gate } 15747c478bd9Sstevel@tonic-gate 15757c478bd9Sstevel@tonic-gate /* 15767c478bd9Sstevel@tonic-gate * perform such initialization as is needed 15777c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 15787c478bd9Sstevel@tonic-gate */ 15797c478bd9Sstevel@tonic-gate cpu_pause_init(); 15807c478bd9Sstevel@tonic-gate 1581f34a7178SJoe Bonasera xc_init_cpu(CPU); /* initialize processor crosscalls */ 15827c478bd9Sstevel@tonic-gate 1583ae115bc7Smrj if (mach_cpucontext_init() != 0) 15847c478bd9Sstevel@tonic-gate goto done; 15857c478bd9Sstevel@tonic-gate 15867c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 15877c478bd9Sstevel@tonic-gate 15885205ae23Snf /* 15895205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 15905205ae23Snf * do their TSC syncs with the same CPU. 15915205ae23Snf */ 15927c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 15937c478bd9Sstevel@tonic-gate 15947c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 159541791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 159641791439Sandrei continue; 1597ae115bc7Smrj ASSERT(who != bootcpuid); 1598b9e93c10SJonathan Haslam 1599b9e93c10SJonathan Haslam mutex_enter(&cpu_lock); 1600a3114836SGerry Liu if (start_cpu(who) != 0) 1601a3114836SGerry Liu CPUSET_DEL(mp_cpus, who); 1602b9e93c10SJonathan Haslam cpu_state_change_notify(who, CPU_SETUP); 1603b9e93c10SJonathan Haslam mutex_exit(&cpu_lock); 16047c478bd9Sstevel@tonic-gate } 16057c478bd9Sstevel@tonic-gate 16062449e17fSsherrym /* Free the space allocated to hold the microcode file */ 1607adc586deSMark Johnson ucode_cleanup(); 16082449e17fSsherrym 16097c478bd9Sstevel@tonic-gate affinity_clear(); 16107c478bd9Sstevel@tonic-gate 1611a3114836SGerry Liu mach_cpucontext_fini(); 1612a3114836SGerry Liu 1613a3114836SGerry Liu done: 1614a3114836SGerry Liu if (get_hwenv() == HW_NATIVE) 1615a3114836SGerry Liu workaround_errata_end(); 1616a3114836SGerry Liu cmi_post_mpstartup(); 1617a3114836SGerry Liu 1618a3114836SGerry Liu if (use_mp && ncpus != boot_max_ncpus) { 161941791439Sandrei cmn_err(CE_NOTE, 1620ae115bc7Smrj "System detected %d cpus, but " 1621ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 1622a3114836SGerry Liu boot_max_ncpus, ncpus); 162341791439Sandrei cmn_err(CE_NOTE, 162441791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 162541791439Sandrei "See eeprom(1M)."); 162641791439Sandrei } 16277c478bd9Sstevel@tonic-gate } 16287c478bd9Sstevel@tonic-gate 16297c478bd9Sstevel@tonic-gate int 16307c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 16317c478bd9Sstevel@tonic-gate { 1632a3114836SGerry Liu cpu_t *cp; 1633a3114836SGerry Liu 1634a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1635a3114836SGerry Liu return (ENOTSUP); 1636a3114836SGerry Liu } 1637a3114836SGerry Liu 1638a3114836SGerry Liu cp = cpu_get(cpuid); 1639a3114836SGerry Liu if (cp != NULL) { 1640a3114836SGerry Liu return (EALREADY); 1641a3114836SGerry Liu } 1642a3114836SGerry Liu 1643a3114836SGerry Liu /* 1644a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1645a3114836SGerry Liu * before attempting to start the cpu. 1646a3114836SGerry Liu */ 1647a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1648a3114836SGerry Liu /* 1649a3114836SGerry Liu * Kick off a reap in case that helps us with 1650a3114836SGerry Liu * later attempts .. 1651a3114836SGerry Liu */ 1652a3114836SGerry Liu kmem_reap(); 1653a3114836SGerry Liu return (ENOMEM); 1654a3114836SGerry Liu } 1655a3114836SGerry Liu 1656a3114836SGerry Liu cp = mp_cpu_configure_common(cpuid, B_FALSE); 1657a3114836SGerry Liu ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1658a3114836SGerry Liu 1659a3114836SGerry Liu return (cp != NULL ? 0 : EAGAIN); 16607c478bd9Sstevel@tonic-gate } 16617c478bd9Sstevel@tonic-gate 16627c478bd9Sstevel@tonic-gate int 16637c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 16647c478bd9Sstevel@tonic-gate { 1665a3114836SGerry Liu cpu_t *cp; 1666a3114836SGerry Liu 1667a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1668a3114836SGerry Liu return (ENOTSUP); 1669a3114836SGerry Liu } else if (cpuid < 0 || cpuid >= max_ncpus) { 1670a3114836SGerry Liu return (EINVAL); 1671a3114836SGerry Liu } 1672a3114836SGerry Liu 1673a3114836SGerry Liu cp = cpu_get(cpuid); 1674a3114836SGerry Liu if (cp == NULL) { 1675a3114836SGerry Liu return (ENODEV); 1676a3114836SGerry Liu } 1677a3114836SGerry Liu mp_cpu_unconfigure_common(cp, 0); 1678a3114836SGerry Liu 1679a3114836SGerry Liu return (0); 16807c478bd9Sstevel@tonic-gate } 16817c478bd9Sstevel@tonic-gate 16827c478bd9Sstevel@tonic-gate /* 16837c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1684498697c5Sdmick * Called from real_mode_start. 1685b4b46911Skchow * 1686a3114836SGerry Liu * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1687a3114836SGerry Liu * mp_startup_common should not call routines (e.g. kmem_free) that could call 1688b4b46911Skchow * hat_unload which requires CPU_READY to be set. 16897c478bd9Sstevel@tonic-gate */ 1690a3114836SGerry Liu static void 1691a3114836SGerry Liu mp_startup_common(boolean_t boot) 16927c478bd9Sstevel@tonic-gate { 1693a3114836SGerry Liu cpu_t *cp = CPU; 1694dfea898aSKuriakose Kuruvilla uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 1695a3114836SGerry Liu extern void cpu_event_init_cpu(cpu_t *); 16967c478bd9Sstevel@tonic-gate 169724a74e86Sdmick /* 169824a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 169924a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 170024a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 17014948216cSKeith M Wesolowski * interrupts, cmn_err, etc. Before we can do that, we want to 17024948216cSKeith M Wesolowski * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that 17034948216cSKeith M Wesolowski * right away. 170424a74e86Sdmick */ 17054948216cSKeith M Wesolowski bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES)); 17064948216cSKeith M Wesolowski cpuid_pass1(cp, new_x86_featureset); 17074948216cSKeith M Wesolowski 17084948216cSKeith M Wesolowski if (boot && get_hwenv() == HW_NATIVE && 17094948216cSKeith M Wesolowski cpuid_getvendor(CPU) == X86_VENDOR_Intel && 17104948216cSKeith M Wesolowski cpuid_getfamily(CPU) == 6 && 17114948216cSKeith M Wesolowski (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 17124948216cSKeith M Wesolowski is_x86_feature(new_x86_featureset, X86FSET_TSC)) { 17134948216cSKeith M Wesolowski (void) wrmsr(REG_TSC, 0UL); 17144948216cSKeith M Wesolowski } 171524a74e86Sdmick 1716a3114836SGerry Liu /* Let the control CPU continue into tsc_sync_master() */ 1717a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 171824a74e86Sdmick 1719843e1988Sjohnlev #ifndef __xpv 172024a74e86Sdmick if (tsc_gethrtime_enable) 172124a74e86Sdmick tsc_sync_slave(); 1722843e1988Sjohnlev #endif 172324a74e86Sdmick 1724498697c5Sdmick /* 1725498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1726498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1727498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1728498697c5Sdmick * before swtch() overwrites it. 1729498697c5Sdmick */ 1730498697c5Sdmick (void) (*ap_mlsetup)(); 1731498697c5Sdmick 1732843e1988Sjohnlev #ifndef __xpv 17337c478bd9Sstevel@tonic-gate /* 17341d03c31eSjohnlev * Program this cpu's PAT 17357c478bd9Sstevel@tonic-gate */ 173658865bb7SJosef 'Jeff' Sipek pat_sync(); 1737843e1988Sjohnlev #endif 17387c478bd9Sstevel@tonic-gate 1739ae115bc7Smrj /* 1740ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1741ae115bc7Smrj * for the rdtscp instruction. 1742ae115bc7Smrj */ 17437417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 1744ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1745ae115bc7Smrj 17467c478bd9Sstevel@tonic-gate /* 17477c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 17487c478bd9Sstevel@tonic-gate */ 17497c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 17507c478bd9Sstevel@tonic-gate 17517c478bd9Sstevel@tonic-gate /* 17527c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 17537c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 17547c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 17557c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 17567c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 17577c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 17587c478bd9Sstevel@tonic-gate */ 1759ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1760ae115bc7Smrj sti(); 17617c478bd9Sstevel@tonic-gate 1762f98fbcecSbholler /* 17634d4b4953SPatrick Mooney * There exists a small subset of systems which expose differing 17644d4b4953SPatrick Mooney * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from 17654d4b4953SPatrick Mooney * the boot CPU, but is found on a later CPU, the system continues to 17664d4b4953SPatrick Mooney * operate as if no MWAIT support is available. 17674d4b4953SPatrick Mooney * 17684d4b4953SPatrick Mooney * The reverse case, where MWAIT is available on the boot CPU but not 17694d4b4953SPatrick Mooney * on a subsequently initialized CPU, is not presently allowed and will 17704d4b4953SPatrick Mooney * result in a panic. 1771f98fbcecSbholler */ 17727417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) != 17734d4b4953SPatrick Mooney is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) { 17744d4b4953SPatrick Mooney if (!is_x86_feature(x86_featureset, X86FSET_MWAIT)) { 17754d4b4953SPatrick Mooney remove_x86_feature(new_x86_featureset, X86FSET_MWAIT); 17764d4b4953SPatrick Mooney } else { 17774d4b4953SPatrick Mooney panic("unsupported mixed cpu mwait support detected"); 17784d4b4953SPatrick Mooney } 17794d4b4953SPatrick Mooney } 1780f98fbcecSbholler 17817c478bd9Sstevel@tonic-gate /* 17827c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 17837c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 1784fb2caebeSRandy Fishel * answer of dying horribly. Provided the boot cpu is ok, 17857c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 17867c478bd9Sstevel@tonic-gate */ 17877c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 17887c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 17897c478bd9Sstevel@tonic-gate 1790a3114836SGerry Liu /* 1791a3114836SGerry Liu * We can touch cpu_flags here without acquiring the cpu_lock here 1792a3114836SGerry Liu * because the cpu_lock is held by the control CPU which is running 1793a3114836SGerry Liu * mp_start_cpu_common(). 1794a3114836SGerry Liu * Need to clear CPU_QUIESCED flag before calling any function which 1795a3114836SGerry Liu * may cause thread context switching, such as kmem_alloc() etc. 1796a3114836SGerry Liu * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1797a3114836SGerry Liu * it's set. So the startup thread may have no chance to switch back 1798a3114836SGerry Liu * again if it's switched away with CPU_QUIESCED set. 1799a3114836SGerry Liu */ 1800a3114836SGerry Liu cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1801a3114836SGerry Liu 180274ecdb51SJohn Levon enable_pcid(); 180374ecdb51SJohn Levon 18047af88ac7SKuriakose Kuruvilla /* 18057af88ac7SKuriakose Kuruvilla * Setup this processor for XSAVE. 18067af88ac7SKuriakose Kuruvilla */ 18077af88ac7SKuriakose Kuruvilla if (fp_save_mech == FP_XSAVE) { 18087af88ac7SKuriakose Kuruvilla xsave_setup_msr(cp); 18097af88ac7SKuriakose Kuruvilla } 18107af88ac7SKuriakose Kuruvilla 18117c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 18127c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 1813ebb8ac07SRobert Mustacchi cpuid_pass4(cp, NULL); 18147c478bd9Sstevel@tonic-gate 18152449e17fSsherrym /* 1816a3114836SGerry Liu * Correct cpu_idstr and cpu_brandstr on target CPU after 1817a3114836SGerry Liu * cpuid_pass1() is done. 18182449e17fSsherrym */ 1819a3114836SGerry Liu (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1820a3114836SGerry Liu (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 18212449e17fSsherrym 1822a3114836SGerry Liu cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 18237c478bd9Sstevel@tonic-gate 1824e774b42bSBill Holler post_startup_cpu_fixups(); 1825e774b42bSBill Holler 1826a3114836SGerry Liu cpu_event_init_cpu(cp); 1827a3114836SGerry Liu 1828aa7b6435Ssethg /* 1829aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1830a3114836SGerry Liu * later in mp_startup_common may be preempted if the thread owning 1831a3114836SGerry Liu * those locks is continuously executing on other CPUs (for example, 1832a3114836SGerry Liu * this CPU must be preemptible to allow other CPUs to pause it during 1833a3114836SGerry Liu * their startup phases). It's safe to enable preemption here because 1834a3114836SGerry Liu * the CPU state is pretty-much fully constructed. 1835aa7b6435Ssethg */ 1836aa7b6435Ssethg curthread->t_preempt = 0; 1837aa7b6435Ssethg 1838da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1839da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1840da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1841da43ceabSsethg 1842a3114836SGerry Liu pghw_physid_create(cp); 18430e751525SEric Saxe /* 1844a3114836SGerry Liu * Delegate initialization tasks, which need to access the cpu_lock, 1845a3114836SGerry Liu * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1846a3114836SGerry Liu * during CPU DR operations. 18470e751525SEric Saxe */ 1848a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 1849a3114836SGerry Liu mp_startup_wait(&procset_master, cp->cpu_id); 18500e751525SEric Saxe pg_cmt_cpu_startup(cp); 1851a3114836SGerry Liu 1852a3114836SGerry Liu if (boot) { 1853a3114836SGerry Liu mutex_enter(&cpu_lock); 1854a3114836SGerry Liu cp->cpu_flags &= ~CPU_OFFLINE; 1855a3114836SGerry Liu cpu_enable_intr(cp); 1856a3114836SGerry Liu cpu_add_active(cp); 1857a3114836SGerry Liu mutex_exit(&cpu_lock); 1858a3114836SGerry Liu } 18590e751525SEric Saxe 1860afbc4541Ssherrym /* Enable interrupts */ 1861afbc4541Ssherrym (void) spl0(); 18620e751525SEric Saxe 1863a3114836SGerry Liu /* 1864*e25cb0e7SJohn Levon * Fill out cpu_ucode_info. Update microcode if necessary. Note that 1865*e25cb0e7SJohn Levon * this is done after pass1 on the boot CPU, but it needs to be later on 1866*e25cb0e7SJohn Levon * for the other CPUs. 1867a3114836SGerry Liu */ 1868a3114836SGerry Liu ucode_check(cp); 186901add34aSRobert Mustacchi cpuid_pass_ucode(cp, new_x86_featureset); 187001add34aSRobert Mustacchi 187101add34aSRobert Mustacchi /* 187201add34aSRobert Mustacchi * Do a sanity check to make sure this new CPU is a sane thing 187301add34aSRobert Mustacchi * to add to the collection of processors running this system. 187401add34aSRobert Mustacchi * 187501add34aSRobert Mustacchi * XXX Clearly this needs to get more sophisticated, if x86 187601add34aSRobert Mustacchi * systems start to get built out of heterogenous CPUs; as is 187701add34aSRobert Mustacchi * likely to happen once the number of processors in a configuration 187801add34aSRobert Mustacchi * gets large enough. 187901add34aSRobert Mustacchi */ 188001add34aSRobert Mustacchi if (compare_x86_featureset(x86_featureset, new_x86_featureset) == 188101add34aSRobert Mustacchi B_FALSE) { 188201add34aSRobert Mustacchi cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id); 188301add34aSRobert Mustacchi print_x86_featureset(new_x86_featureset); 188401add34aSRobert Mustacchi cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 188501add34aSRobert Mustacchi } 1886afbc4541Ssherrym 188720c794b3Sgavinm #ifndef __xpv 188820c794b3Sgavinm { 188920c794b3Sgavinm /* 189020c794b3Sgavinm * Set up the CPU module for this CPU. This can't be done 189120c794b3Sgavinm * before this CPU is made CPU_READY, because we may (in 189220c794b3Sgavinm * heterogeneous systems) need to go load another CPU module. 189320c794b3Sgavinm * The act of attempting to load a module may trigger a 189420c794b3Sgavinm * cross-call, which will ASSERT unless this cpu is CPU_READY. 189520c794b3Sgavinm */ 189620c794b3Sgavinm cmi_hdl_t hdl; 18977aec1d6eScindi 189820c794b3Sgavinm if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1899e4b86885SCheng Sean Ye cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 19007417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MCA)) 190120c794b3Sgavinm cmi_mca_init(hdl); 1902a3114836SGerry Liu cp->cpu_m.mcpu_cmi_hdl = hdl; 190320c794b3Sgavinm } 190420c794b3Sgavinm } 190520c794b3Sgavinm #endif /* __xpv */ 19067aec1d6eScindi 19077c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1908ae115bc7Smrj kdi_cpu_init(); 19097c478bd9Sstevel@tonic-gate 1910af1da5d8SJason King (void) mach_cpu_create_device_node(cp, NULL); 1911af1da5d8SJason King 19127c478bd9Sstevel@tonic-gate /* 19137c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 19147c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 19157c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 19167c478bd9Sstevel@tonic-gate */ 19177c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 19187c478bd9Sstevel@tonic-gate 1919a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1920a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1921a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1922a3114836SGerry Liu cp->cpu_id); 1923a3114836SGerry Liu 19247c478bd9Sstevel@tonic-gate /* 19257c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 19267c478bd9Sstevel@tonic-gate */ 19277c478bd9Sstevel@tonic-gate thread_exit(); 19287c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 19297c478bd9Sstevel@tonic-gate } 19307c478bd9Sstevel@tonic-gate 1931a3114836SGerry Liu /* 1932a3114836SGerry Liu * Startup function for 'other' CPUs at boot time (besides boot cpu). 1933a3114836SGerry Liu */ 1934a3114836SGerry Liu static void 1935a3114836SGerry Liu mp_startup_boot(void) 1936a3114836SGerry Liu { 1937a3114836SGerry Liu mp_startup_common(B_TRUE); 1938a3114836SGerry Liu } 1939a3114836SGerry Liu 1940a3114836SGerry Liu /* 1941a3114836SGerry Liu * Startup function for hotplug CPUs at runtime. 1942a3114836SGerry Liu */ 1943a3114836SGerry Liu void 1944a3114836SGerry Liu mp_startup_hotplug(void) 1945a3114836SGerry Liu { 1946a3114836SGerry Liu mp_startup_common(B_FALSE); 1947a3114836SGerry Liu } 19487c478bd9Sstevel@tonic-gate 19497c478bd9Sstevel@tonic-gate /* 19507c478bd9Sstevel@tonic-gate * Start CPU on user request. 19517c478bd9Sstevel@tonic-gate */ 19527c478bd9Sstevel@tonic-gate /* ARGSUSED */ 19537c478bd9Sstevel@tonic-gate int 19547c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 19557c478bd9Sstevel@tonic-gate { 19567c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 19577c478bd9Sstevel@tonic-gate return (0); 19587c478bd9Sstevel@tonic-gate } 19597c478bd9Sstevel@tonic-gate 19607c478bd9Sstevel@tonic-gate /* 19617c478bd9Sstevel@tonic-gate * Stop CPU on user request. 19627c478bd9Sstevel@tonic-gate */ 19637c478bd9Sstevel@tonic-gate int 19647c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 19657c478bd9Sstevel@tonic-gate { 1966d90554ebSdmick extern int cbe_psm_timer_mode; 19677c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1968d90554ebSdmick 1969843e1988Sjohnlev #ifdef __xpv 1970843e1988Sjohnlev /* 1971843e1988Sjohnlev * We can't offline vcpu0. 1972843e1988Sjohnlev */ 1973843e1988Sjohnlev if (cp->cpu_id == 0) 1974843e1988Sjohnlev return (EBUSY); 1975843e1988Sjohnlev #endif 1976843e1988Sjohnlev 1977d90554ebSdmick /* 1978d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1979d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1980d90554ebSdmick */ 1981d90554ebSdmick 1982d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1983843e1988Sjohnlev return (EBUSY); 19847c478bd9Sstevel@tonic-gate 19857c478bd9Sstevel@tonic-gate return (0); 19867c478bd9Sstevel@tonic-gate } 19877c478bd9Sstevel@tonic-gate 19887c478bd9Sstevel@tonic-gate /* 19897c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 1990c3377ee9SJohn Levon * 1991c3377ee9SJohn Levon * Usually, we hold cpu_lock. But we cannot assert as such due to the 1992c3377ee9SJohn Levon * exception - i_cpr_save_context() - where we have mutual exclusion via a 1993c3377ee9SJohn Levon * separate mechanism. 19947c478bd9Sstevel@tonic-gate */ 19957c478bd9Sstevel@tonic-gate int 19967c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 19977c478bd9Sstevel@tonic-gate { 19987c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 19997c478bd9Sstevel@tonic-gate return (EBUSY); 20007c478bd9Sstevel@tonic-gate 20017c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 2002c3377ee9SJohn Levon ncpus_intr_enabled--; 20037c478bd9Sstevel@tonic-gate return (0); 20047c478bd9Sstevel@tonic-gate } 20057c478bd9Sstevel@tonic-gate 20067c478bd9Sstevel@tonic-gate /* 20077c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 20087c478bd9Sstevel@tonic-gate */ 20097c478bd9Sstevel@tonic-gate void 20107c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 20117c478bd9Sstevel@tonic-gate { 20127c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 20137c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 2014c3377ee9SJohn Levon ncpus_intr_enabled++; 20157c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 20167c478bd9Sstevel@tonic-gate } 20177c478bd9Sstevel@tonic-gate 20187c478bd9Sstevel@tonic-gate void 20197c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 20207aec1d6eScindi { 2021a3114836SGerry Liu #ifdef __xpv 2022a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 2023a3114836SGerry Liu #else 2024a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 202520c794b3Sgavinm 2026a3114836SGerry Liu if (hdl != NULL) { 2027a3114836SGerry Liu cmi_hdl_hold(hdl); 2028a3114836SGerry Liu } else { 2029a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 2030a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 2031a3114836SGerry Liu } 203220c794b3Sgavinm if (hdl != NULL) { 203320c794b3Sgavinm cmi_faulted_enter(hdl); 203420c794b3Sgavinm cmi_hdl_rele(hdl); 203520c794b3Sgavinm } 203620c794b3Sgavinm #endif 20377aec1d6eScindi } 20387c478bd9Sstevel@tonic-gate 20397c478bd9Sstevel@tonic-gate void 20407c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 20417aec1d6eScindi { 2042a3114836SGerry Liu #ifdef __xpv 2043a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 2044a3114836SGerry Liu #else 2045a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 204620c794b3Sgavinm 2047a3114836SGerry Liu if (hdl != NULL) { 2048a3114836SGerry Liu cmi_hdl_hold(hdl); 2049a3114836SGerry Liu } else { 2050a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 2051a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 2052a3114836SGerry Liu } 205320c794b3Sgavinm if (hdl != NULL) { 205420c794b3Sgavinm cmi_faulted_exit(hdl); 205520c794b3Sgavinm cmi_hdl_rele(hdl); 205620c794b3Sgavinm } 205720c794b3Sgavinm #endif 20587aec1d6eScindi } 20597c478bd9Sstevel@tonic-gate 20607c478bd9Sstevel@tonic-gate /* 20617c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 20627c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 20637c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 20647417cfdeSKuriakose Kuruvilla * organization rather than speed. We could avoid checking x86_featureset at 20657417cfdeSKuriakose Kuruvilla * every context switch by installing different context ops, depending on 20667417cfdeSKuriakose Kuruvilla * x86_featureset, at LDT creation time -- one for each combination of fast 20677417cfdeSKuriakose Kuruvilla * syscall features. 20687c478bd9Sstevel@tonic-gate */ 20697c478bd9Sstevel@tonic-gate 20707c478bd9Sstevel@tonic-gate void 2071a0955b86SJohn Levon cpu_fast_syscall_disable(void) 20727c478bd9Sstevel@tonic-gate { 20737417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20747417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 20757c478bd9Sstevel@tonic-gate cpu_sep_disable(); 20767417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20777417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 20787c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 20797c478bd9Sstevel@tonic-gate } 20807c478bd9Sstevel@tonic-gate 20817c478bd9Sstevel@tonic-gate void 2082a0955b86SJohn Levon cpu_fast_syscall_enable(void) 20837c478bd9Sstevel@tonic-gate { 20847417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20857417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 20867c478bd9Sstevel@tonic-gate cpu_sep_enable(); 20877417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20887417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 20897c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 20907c478bd9Sstevel@tonic-gate } 20917c478bd9Sstevel@tonic-gate 20927c478bd9Sstevel@tonic-gate static void 20937c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 20947c478bd9Sstevel@tonic-gate { 20957417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 20967c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20977c478bd9Sstevel@tonic-gate 20980ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 20997c478bd9Sstevel@tonic-gate } 21007c478bd9Sstevel@tonic-gate 21017c478bd9Sstevel@tonic-gate static void 21027c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 21037c478bd9Sstevel@tonic-gate { 21047417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 21057c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 21067c478bd9Sstevel@tonic-gate 21077c478bd9Sstevel@tonic-gate /* 21087c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 21097c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 21107c478bd9Sstevel@tonic-gate */ 2111ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 21127c478bd9Sstevel@tonic-gate } 21137c478bd9Sstevel@tonic-gate 21147c478bd9Sstevel@tonic-gate static void 21157c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 21167c478bd9Sstevel@tonic-gate { 21177417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 21187c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 21197c478bd9Sstevel@tonic-gate 21200ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 21210ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 21227c478bd9Sstevel@tonic-gate } 21237c478bd9Sstevel@tonic-gate 21247c478bd9Sstevel@tonic-gate static void 21257c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 21267c478bd9Sstevel@tonic-gate { 21277417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 21287c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 21297c478bd9Sstevel@tonic-gate 21307c478bd9Sstevel@tonic-gate /* 21317c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 21327c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 21337c478bd9Sstevel@tonic-gate */ 21340ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 21350ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 21367c478bd9Sstevel@tonic-gate } 2137