17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 23b9e93c10SJonathan Haslam * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 26*a3114836SGerry Liu /* 27*a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 28*a3114836SGerry Liu * All rights reserved. 29*a3114836SGerry Liu */ 307c478bd9Sstevel@tonic-gate 317c478bd9Sstevel@tonic-gate #include <sys/types.h> 327c478bd9Sstevel@tonic-gate #include <sys/thread.h> 337c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 34*a3114836SGerry Liu #include <sys/cpu.h> 357c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 367c478bd9Sstevel@tonic-gate #include <sys/param.h> 377c478bd9Sstevel@tonic-gate #include <sys/proc.h> 387c478bd9Sstevel@tonic-gate #include <sys/disp.h> 397c478bd9Sstevel@tonic-gate #include <sys/class.h> 407c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 417c478bd9Sstevel@tonic-gate #include <sys/debug.h> 42*a3114836SGerry Liu #include <sys/note.h> 437c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 447c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 457c478bd9Sstevel@tonic-gate #include <sys/systm.h> 467c478bd9Sstevel@tonic-gate #include <sys/var.h> 477c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 487c478bd9Sstevel@tonic-gate #include <vm/hat.h> 497c478bd9Sstevel@tonic-gate #include <vm/as.h> 507c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 51ae115bc7Smrj #include <vm/seg_kp.h> 527c478bd9Sstevel@tonic-gate #include <sys/segments.h> 537c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 547c478bd9Sstevel@tonic-gate #include <sys/stack.h> 557c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 567c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 577c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 587c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 597c478bd9Sstevel@tonic-gate #include <sys/clock.h> 607c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 61fb2f18f8Sesaxe #include <sys/pg.h> 62fb2f18f8Sesaxe #include <sys/cmt.h> 637c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 647c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 657c478bd9Sstevel@tonic-gate #include <sys/fp.h> 667c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 67ae115bc7Smrj #include <sys/kdi_machimpl.h> 687c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 69*a3114836SGerry Liu #include <vm/vm_dep.h> 707c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 71ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 72ae115bc7Smrj #include <sys/mach_mmu.h> 73ae115bc7Smrj #include <sys/sysmacros.h> 74843e1988Sjohnlev #if defined(__xpv) 75843e1988Sjohnlev #include <sys/hypervisor.h> 76843e1988Sjohnlev #endif 777aec1d6eScindi #include <sys/cpu_module.h> 787c478bd9Sstevel@tonic-gate 797c478bd9Sstevel@tonic-gate struct cpu cpus[1]; /* CPU data */ 807c478bd9Sstevel@tonic-gate struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 81*a3114836SGerry Liu struct cpu *cpu_free_list; /* list for released CPUs */ 827c478bd9Sstevel@tonic-gate cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 837c478bd9Sstevel@tonic-gate 84*a3114836SGerry Liu #define cpu_next_free cpu_prev 85*a3114836SGerry Liu 867c478bd9Sstevel@tonic-gate /* 87ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 887c478bd9Sstevel@tonic-gate */ 897c478bd9Sstevel@tonic-gate int use_mp = 1; 907c478bd9Sstevel@tonic-gate 9141791439Sandrei /* 92ae115bc7Smrj * to be set by a PSM to indicate what cpus 93ae115bc7Smrj * are sitting around on the system. 9441791439Sandrei */ 95ae115bc7Smrj cpuset_t mp_cpus; 967c478bd9Sstevel@tonic-gate 977c478bd9Sstevel@tonic-gate /* 987c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 997c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 1007c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 1017c478bd9Sstevel@tonic-gate * order to allow cross calls. 1027c478bd9Sstevel@tonic-gate */ 103ae115bc7Smrj int flushes_require_xcalls; 104a563a037Sbholler 105a563a037Sbholler cpuset_t cpu_ready_set; /* initialized in startup() */ 1067c478bd9Sstevel@tonic-gate 107*a3114836SGerry Liu static void mp_startup_boot(void); 108*a3114836SGerry Liu static void mp_startup_hotplug(void); 1097c478bd9Sstevel@tonic-gate 1107c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1117c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1127c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1137c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1147c478bd9Sstevel@tonic-gate 1157c478bd9Sstevel@tonic-gate /* 1167c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1177c478bd9Sstevel@tonic-gate */ 1187c478bd9Sstevel@tonic-gate void 1197c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1207c478bd9Sstevel@tonic-gate { 1217c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate /* 1247c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1257c478bd9Sstevel@tonic-gate */ 1267c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1277c478bd9Sstevel@tonic-gate 1285cff7825Smh /* 1295cff7825Smh * Current frequency in Hz. 1305cff7825Smh */ 131cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1325cff7825Smh 13337d22dc0SAnup Pemmaiah /* 13437d22dc0SAnup Pemmaiah * Supported frequencies. 13537d22dc0SAnup Pemmaiah */ 13637d22dc0SAnup Pemmaiah if (cp->cpu_supp_freqs == NULL) { 13737d22dc0SAnup Pemmaiah cpu_set_supp_freqs(cp, NULL); 13837d22dc0SAnup Pemmaiah } 13937d22dc0SAnup Pemmaiah 1407c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1417c478bd9Sstevel@tonic-gate if (fpu_exists) 1427c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1437c478bd9Sstevel@tonic-gate 144*a3114836SGerry Liu cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 145*a3114836SGerry Liu cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 1467c478bd9Sstevel@tonic-gate 147*a3114836SGerry Liu /* 148*a3114836SGerry Liu * If called for the BSP, cp is equal to current CPU. 149*a3114836SGerry Liu * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 150*a3114836SGerry Liu * of current CPU as default values for cpu_idstr and cpu_brandstr. 151*a3114836SGerry Liu * They will be corrected in mp_startup_common() after cpuid_pass1() 152*a3114836SGerry Liu * has been invoked on target CPU. 153*a3114836SGerry Liu */ 154*a3114836SGerry Liu (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 155*a3114836SGerry Liu (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 1567c478bd9Sstevel@tonic-gate } 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate /* 1597c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1607c478bd9Sstevel@tonic-gate */ 1617c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1622df1fe9cSrandyf void 1637c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1647c478bd9Sstevel@tonic-gate { 1657c478bd9Sstevel@tonic-gate kpreempt_disable(); 1667c478bd9Sstevel@tonic-gate 1677c478bd9Sstevel@tonic-gate #if defined(__amd64) 168ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 1697c478bd9Sstevel@tonic-gate 1707c478bd9Sstevel@tonic-gate #if !defined(__lint) 1717c478bd9Sstevel@tonic-gate /* 1727c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1737c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1747c478bd9Sstevel@tonic-gate * here. 1757c478bd9Sstevel@tonic-gate */ 1767c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 1777c478bd9Sstevel@tonic-gate ASSERT(UDS_SEL == U32CS_SEL + 8); 1787c478bd9Sstevel@tonic-gate ASSERT(UCS_SEL == U32CS_SEL + 16); 1797c478bd9Sstevel@tonic-gate #endif 1807c478bd9Sstevel@tonic-gate /* 1817c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1827c478bd9Sstevel@tonic-gate */ 1837c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate /* 1867c478bd9Sstevel@tonic-gate * Program the magic registers .. 1877c478bd9Sstevel@tonic-gate */ 188ae115bc7Smrj wrmsr(MSR_AMD_STAR, 189ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 1900ac7d7d8Skucharsk wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 1910ac7d7d8Skucharsk wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 1927c478bd9Sstevel@tonic-gate 1937c478bd9Sstevel@tonic-gate /* 1947c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 1957c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 1967c478bd9Sstevel@tonic-gate */ 1970ac7d7d8Skucharsk wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 1987c478bd9Sstevel@tonic-gate } 1997c478bd9Sstevel@tonic-gate #endif 2007c478bd9Sstevel@tonic-gate 2017c478bd9Sstevel@tonic-gate /* 2027c478bd9Sstevel@tonic-gate * On 32-bit kernels, we use sysenter/sysexit because it's too 2037c478bd9Sstevel@tonic-gate * hard to use syscall/sysret, and it is more portable anyway. 2047c478bd9Sstevel@tonic-gate * 2057c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 2067c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 2077c478bd9Sstevel@tonic-gate */ 208ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 2097c478bd9Sstevel@tonic-gate 2107c478bd9Sstevel@tonic-gate #if !defined(__lint) 2117c478bd9Sstevel@tonic-gate /* 2127c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 2137c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2147c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2157c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2167c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2177c478bd9Sstevel@tonic-gate */ 2187c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 2217c478bd9Sstevel@tonic-gate ASSERT32(UDS_SEL == UCS_SEL + 8); 2227c478bd9Sstevel@tonic-gate 2237c478bd9Sstevel@tonic-gate ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 2247c478bd9Sstevel@tonic-gate ASSERT64(UDS_SEL == U32CS_SEL + 8); 2257c478bd9Sstevel@tonic-gate #endif 2267c478bd9Sstevel@tonic-gate 2277c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2287c478bd9Sstevel@tonic-gate 2297c478bd9Sstevel@tonic-gate /* 2307c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2317c478bd9Sstevel@tonic-gate * via a context handler. 2327c478bd9Sstevel@tonic-gate */ 233ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 2340ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 2357c478bd9Sstevel@tonic-gate } 2367c478bd9Sstevel@tonic-gate 2377c478bd9Sstevel@tonic-gate kpreempt_enable(); 2387c478bd9Sstevel@tonic-gate } 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate /* 2417c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2427c478bd9Sstevel@tonic-gate * 2437c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2447c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 245*a3114836SGerry Liu * Parameter boot is true for boot time operations and is false for CPU 246*a3114836SGerry Liu * DR operations. 2477c478bd9Sstevel@tonic-gate */ 248*a3114836SGerry Liu static struct cpu * 249*a3114836SGerry Liu mp_cpu_configure_common(int cpun, boolean_t boot) 2507c478bd9Sstevel@tonic-gate { 2517c478bd9Sstevel@tonic-gate struct cpu *cp; 2527c478bd9Sstevel@tonic-gate kthread_id_t tp; 2537c478bd9Sstevel@tonic-gate caddr_t sp; 2547c478bd9Sstevel@tonic-gate proc_t *procp; 255843e1988Sjohnlev #if !defined(__xpv) 2565b8a6efeSbholler extern int idle_cpu_prefer_mwait; 2570e751525SEric Saxe extern void cpu_idle_mwait(); 258843e1988Sjohnlev #endif 2597c478bd9Sstevel@tonic-gate extern void idle(); 2600e751525SEric Saxe extern void cpu_idle(); 2617c478bd9Sstevel@tonic-gate 2627c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 2637c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 2647c478bd9Sstevel@tonic-gate #endif 2657c478bd9Sstevel@tonic-gate 266*a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 2677c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 2687c478bd9Sstevel@tonic-gate 269*a3114836SGerry Liu if (cpu_free_list == NULL) { 270*a3114836SGerry Liu cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 271*a3114836SGerry Liu } else { 272*a3114836SGerry Liu cp = cpu_free_list; 273*a3114836SGerry Liu cpu_free_list = cp->cpu_next_free; 274*a3114836SGerry Liu } 275f98fbcecSbholler 2763006ae82SFrank Van Der Linden cp->cpu_m.mcpu_istamp = cpun << 16; 2773006ae82SFrank Van Der Linden 278*a3114836SGerry Liu /* Create per CPU specific threads in the process p0. */ 279*a3114836SGerry Liu procp = &p0; 2807c478bd9Sstevel@tonic-gate 2817c478bd9Sstevel@tonic-gate /* 2827c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 2837c478bd9Sstevel@tonic-gate */ 2847c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 2857c478bd9Sstevel@tonic-gate 286affbd3ccSkchow cpu_vm_data_init(cp); 287affbd3ccSkchow 2887c478bd9Sstevel@tonic-gate /* 2897c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 2907c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 2917c478bd9Sstevel@tonic-gate * when the CPU starts running. 2927c478bd9Sstevel@tonic-gate */ 2937c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 2947c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 2957c478bd9Sstevel@tonic-gate 2967c478bd9Sstevel@tonic-gate /* 2977c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 2987c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 2997c478bd9Sstevel@tonic-gate * 3007c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 3017c478bd9Sstevel@tonic-gate * thread_create(). 3027c478bd9Sstevel@tonic-gate */ 3037c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 3047c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3057c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3067c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3077c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3087c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3097c478bd9Sstevel@tonic-gate 3107c478bd9Sstevel@tonic-gate /* 311*a3114836SGerry Liu * Setup thread to start in mp_startup_common. 3127c478bd9Sstevel@tonic-gate */ 3137c478bd9Sstevel@tonic-gate sp = tp->t_stk; 3147c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 315ae115bc7Smrj #if defined(__amd64) 316ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 317ae115bc7Smrj #endif 318*a3114836SGerry Liu /* 319*a3114836SGerry Liu * Setup thread start entry point for boot or hotplug. 320*a3114836SGerry Liu */ 321*a3114836SGerry Liu if (boot) { 322*a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_boot; 323*a3114836SGerry Liu } else { 324*a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_hotplug; 325*a3114836SGerry Liu } 3267c478bd9Sstevel@tonic-gate 3277c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3287c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3297c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3307c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3317c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3327c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3337c478bd9Sstevel@tonic-gate 334da43ceabSsethg /* 335da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 336*a3114836SGerry Liu * operations in mp_startup_common from causing the spl of the cpu 337*a3114836SGerry Liu * to drop to 0 (allowing device interrupts before we're ready) in 338*a3114836SGerry Liu * resume(). 339da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 340da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 341*a3114836SGerry Liu * an assertion in mp_startup_common() -- before cpu_base_spl is set 342*a3114836SGerry Liu * to its proper value. 343da43ceabSsethg */ 344da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 345da43ceabSsethg 3467c478bd9Sstevel@tonic-gate /* 3477c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3487c478bd9Sstevel@tonic-gate */ 3497c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3507c478bd9Sstevel@tonic-gate 3517c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3527c478bd9Sstevel@tonic-gate 3537c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3547c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3557c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3567c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3577c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3587c478bd9Sstevel@tonic-gate 359394b433dSesaxe /* 360fb2f18f8Sesaxe * Bootstrap the CPU's PG data 361394b433dSesaxe */ 362fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 363394b433dSesaxe 3647c478bd9Sstevel@tonic-gate /* 365ae115bc7Smrj * Perform CPC initialization on the new CPU. 3667c478bd9Sstevel@tonic-gate */ 3677c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 3687c478bd9Sstevel@tonic-gate 3697c478bd9Sstevel@tonic-gate /* 3707c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 3717c478bd9Sstevel@tonic-gate * for each CPU. 3727c478bd9Sstevel@tonic-gate */ 3737c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 3747c478bd9Sstevel@tonic-gate 3757c478bd9Sstevel@tonic-gate /* 376ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 3777c478bd9Sstevel@tonic-gate */ 378ae115bc7Smrj #if !defined(__lint) 379ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 380ae115bc7Smrj #endif 3810cfdb603Sjosephb cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 3820cfdb603Sjosephb bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 3837c478bd9Sstevel@tonic-gate 384ae115bc7Smrj #if defined(__i386) 3857c478bd9Sstevel@tonic-gate /* 3867c478bd9Sstevel@tonic-gate * setup kernel %gs. 3877c478bd9Sstevel@tonic-gate */ 3887c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 3897c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 390ae115bc7Smrj #endif 3917c478bd9Sstevel@tonic-gate 3927c478bd9Sstevel@tonic-gate /* 3937c478bd9Sstevel@tonic-gate * If we have more than one node, each cpu gets a copy of IDT 3947c478bd9Sstevel@tonic-gate * local to its node. If this is a Pentium box, we use cpu 0's 3957c478bd9Sstevel@tonic-gate * IDT. cpu 0's IDT has been made read-only to workaround the 3967c478bd9Sstevel@tonic-gate * cmpxchgl register bug 3977c478bd9Sstevel@tonic-gate */ 3987c478bd9Sstevel@tonic-gate if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 3990cfdb603Sjosephb #if !defined(__lint) 4000cfdb603Sjosephb ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 4010cfdb603Sjosephb #endif 4020cfdb603Sjosephb cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 4030cfdb603Sjosephb bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 404ae115bc7Smrj } else { 4050cfdb603Sjosephb cp->cpu_idt = CPU->cpu_idt; 4067c478bd9Sstevel@tonic-gate } 4077c478bd9Sstevel@tonic-gate 4087c478bd9Sstevel@tonic-gate /* 409ae115bc7Smrj * Get interrupt priority data from cpu 0. 4107c478bd9Sstevel@tonic-gate */ 4117c478bd9Sstevel@tonic-gate cp->cpu_pri_data = CPU->cpu_pri_data; 4127c478bd9Sstevel@tonic-gate 4137c478bd9Sstevel@tonic-gate /* 414ae115bc7Smrj * alloc space for cpuid info 4157c478bd9Sstevel@tonic-gate */ 416ae115bc7Smrj cpuid_alloc_space(cp); 417*a3114836SGerry Liu #if !defined(__xpv) 418*a3114836SGerry Liu if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) { 419*a3114836SGerry Liu cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 420*a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 421*a3114836SGerry Liu } else 422*a3114836SGerry Liu #endif 423*a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle; 424*a3114836SGerry Liu 425*a3114836SGerry Liu init_cpu_info(cp); 4267c478bd9Sstevel@tonic-gate 4272449e17fSsherrym /* 4282449e17fSsherrym * alloc space for ucode_info 4292449e17fSsherrym */ 4302449e17fSsherrym ucode_alloc_space(cp); 431f34a7178SJoe Bonasera xc_init_cpu(cp); 432ae115bc7Smrj hat_cpu_online(cp); 4337c478bd9Sstevel@tonic-gate 4347c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4357c478bd9Sstevel@tonic-gate /* 436ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4377c478bd9Sstevel@tonic-gate */ 4387c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4397c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4407c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4417c478bd9Sstevel@tonic-gate #endif 442*a3114836SGerry Liu 4437c478bd9Sstevel@tonic-gate /* 4447c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4457c478bd9Sstevel@tonic-gate */ 4467c478bd9Sstevel@tonic-gate /* 4477c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4487c478bd9Sstevel@tonic-gate */ 449100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 450*a3114836SGerry Liu 451*a3114836SGerry Liu cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 452*a3114836SGerry Liu cpu_set_state(cp); 453*a3114836SGerry Liu 4547c478bd9Sstevel@tonic-gate /* 4557c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 456*a3114836SGerry Liu * after mp_startup_common(). 4577c478bd9Sstevel@tonic-gate */ 4587c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 459ae115bc7Smrj 460ae115bc7Smrj return (cp); 461ae115bc7Smrj } 462ae115bc7Smrj 463ae115bc7Smrj /* 464*a3114836SGerry Liu * Undo what was done in mp_cpu_configure_common 465ae115bc7Smrj */ 466ae115bc7Smrj static void 467*a3114836SGerry Liu mp_cpu_unconfigure_common(struct cpu *cp, int error) 468ae115bc7Smrj { 469*a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 470ae115bc7Smrj 471ae115bc7Smrj /* 472ae115bc7Smrj * Remove the CPU from the list of available CPUs. 473ae115bc7Smrj */ 474ae115bc7Smrj cpu_del_unit(cp->cpu_id); 475ae115bc7Smrj 476ae115bc7Smrj if (error == ETIMEDOUT) { 477ae115bc7Smrj /* 478ae115bc7Smrj * The cpu was started, but never *seemed* to run any 479ae115bc7Smrj * code in the kernel; it's probably off spinning in its 480ae115bc7Smrj * own private world, though with potential references to 481ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 482ae115bc7Smrj * 483ae115bc7Smrj * Worse still, it may actually wake up some time later, 484ae115bc7Smrj * so rather than guess what it might or might not do, we 485ae115bc7Smrj * leave the fundamental data structures intact. 486ae115bc7Smrj */ 487ae115bc7Smrj cp->cpu_flags = 0; 488ae115bc7Smrj return; 489ae115bc7Smrj } 490ae115bc7Smrj 491ae115bc7Smrj /* 492ae115bc7Smrj * At this point, the only threads bound to this CPU should 493ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 494ae115bc7Smrj * and it's interrupt threads. Clean these up. 495ae115bc7Smrj */ 496ae115bc7Smrj cpu_destroy_bound_threads(cp); 497ae115bc7Smrj cp->cpu_idle_thread = NULL; 498ae115bc7Smrj 499ae115bc7Smrj /* 500ae115bc7Smrj * Free the interrupt stack. 501ae115bc7Smrj */ 502ae115bc7Smrj segkp_release(segkp, 503ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 504*a3114836SGerry Liu cp->cpu_intr_stack = NULL; 505ae115bc7Smrj 506ae115bc7Smrj #ifdef TRAPTRACE 507ae115bc7Smrj /* 508ae115bc7Smrj * Discard the trap trace buffer 509ae115bc7Smrj */ 510ae115bc7Smrj { 511ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 512ae115bc7Smrj 513ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 514ae115bc7Smrj ttc->ttc_first = NULL; 515ae115bc7Smrj } 516ae115bc7Smrj #endif 517ae115bc7Smrj 518ae115bc7Smrj hat_cpu_offline(cp); 519ae115bc7Smrj 5202449e17fSsherrym ucode_free_space(cp); 5212449e17fSsherrym 522*a3114836SGerry Liu /* Free CPU ID string and brand string. */ 523*a3114836SGerry Liu if (cp->cpu_idstr) { 524*a3114836SGerry Liu kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 525*a3114836SGerry Liu cp->cpu_idstr = NULL; 526*a3114836SGerry Liu } 527*a3114836SGerry Liu if (cp->cpu_brandstr) { 528*a3114836SGerry Liu kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 529*a3114836SGerry Liu cp->cpu_brandstr = NULL; 530*a3114836SGerry Liu } 531*a3114836SGerry Liu 532*a3114836SGerry Liu #if !defined(__xpv) 533*a3114836SGerry Liu if (cp->cpu_m.mcpu_mwait != NULL) { 534*a3114836SGerry Liu cpuid_mwait_free(cp); 535*a3114836SGerry Liu cp->cpu_m.mcpu_mwait = NULL; 536*a3114836SGerry Liu } 537*a3114836SGerry Liu #endif 538*a3114836SGerry Liu cpuid_free_space(cp); 539*a3114836SGerry Liu 5400cfdb603Sjosephb if (cp->cpu_idt != CPU->cpu_idt) 5410cfdb603Sjosephb kmem_free(cp->cpu_idt, PAGESIZE); 5420cfdb603Sjosephb cp->cpu_idt = NULL; 543ae115bc7Smrj 5440cfdb603Sjosephb kmem_free(cp->cpu_gdt, PAGESIZE); 5450cfdb603Sjosephb cp->cpu_gdt = NULL; 546ae115bc7Smrj 547*a3114836SGerry Liu if (cp->cpu_supp_freqs != NULL) { 548*a3114836SGerry Liu size_t len = strlen(cp->cpu_supp_freqs) + 1; 549*a3114836SGerry Liu kmem_free(cp->cpu_supp_freqs, len); 550*a3114836SGerry Liu cp->cpu_supp_freqs = NULL; 551*a3114836SGerry Liu } 552*a3114836SGerry Liu 553ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 554ae115bc7Smrj 555ae115bc7Smrj kcpc_hw_fini(cp); 556ae115bc7Smrj 557ae115bc7Smrj cp->cpu_dispthread = NULL; 558ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 559ae115bc7Smrj 560ae115bc7Smrj cpu_vm_data_destroy(cp); 561ae115bc7Smrj 562*a3114836SGerry Liu xc_fini_cpu(cp); 563ae115bc7Smrj disp_cpu_fini(cp); 564ae115bc7Smrj 565*a3114836SGerry Liu ASSERT(cp != CPU0); 566*a3114836SGerry Liu bzero(cp, sizeof (*cp)); 567*a3114836SGerry Liu cp->cpu_next_free = cpu_free_list; 568*a3114836SGerry Liu cpu_free_list = cp; 5697c478bd9Sstevel@tonic-gate } 5707c478bd9Sstevel@tonic-gate 5717c478bd9Sstevel@tonic-gate /* 5727c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 5737c478bd9Sstevel@tonic-gate * 5747c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 5757c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 5767c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 5777c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 5787c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 5797c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 5807c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 5817c478bd9Sstevel@tonic-gate * system. 5827c478bd9Sstevel@tonic-gate * 583ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 584*a3114836SGerry Liu * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 585*a3114836SGerry Liu * prior to acknowledging their readiness to the master, so this routine will 586ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 587ef50d8c0Sesaxe * global data safe. 588ef50d8c0Sesaxe * 5892201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 5902201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 5917c478bd9Sstevel@tonic-gate */ 5927c478bd9Sstevel@tonic-gate 593ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 594ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 595ae115bc7Smrj #endif 596ae115bc7Smrj 5977c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 5987c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 5997c478bd9Sstevel@tonic-gate #endif 6007c478bd9Sstevel@tonic-gate 6017c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 6027c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 6037c478bd9Sstevel@tonic-gate #endif 6047c478bd9Sstevel@tonic-gate 605ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 606ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 607ae115bc7Smrj #endif 608ae115bc7Smrj 6097c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 6107c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 6117c478bd9Sstevel@tonic-gate #endif 6127c478bd9Sstevel@tonic-gate 613ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 614ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 615ae115bc7Smrj #endif 616ae115bc7Smrj 6177c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 6187c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 6197c478bd9Sstevel@tonic-gate #endif 6207c478bd9Sstevel@tonic-gate 6217c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 6227c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 6237c478bd9Sstevel@tonic-gate #endif 6247c478bd9Sstevel@tonic-gate 6257c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 6267c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 6277c478bd9Sstevel@tonic-gate #endif 6287c478bd9Sstevel@tonic-gate 6297c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 6307c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 6317c478bd9Sstevel@tonic-gate #endif 6327c478bd9Sstevel@tonic-gate 6332201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 6342201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 6352201b277Skucharsk #endif 6367c478bd9Sstevel@tonic-gate 637ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 638ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 639ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 640ef50d8c0Sesaxe #endif 641ef50d8c0Sesaxe 642ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 643ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 644ee88d2b9Skchow #endif 645ee88d2b9Skchow 646512cf780Skchow #if defined(OPTERON_ERRATUM_298) 647512cf780Skchow int opteron_erratum_298; 648512cf780Skchow #endif 649512cf780Skchow 650ae115bc7Smrj static void 651ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 652ae115bc7Smrj { 653ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 654ae115bc7Smrj cp->cpu_id, erratum); 655ae115bc7Smrj } 656ae115bc7Smrj 657ae115bc7Smrj static void 658ae115bc7Smrj workaround_applied(uint_t erratum) 659ae115bc7Smrj { 660ae115bc7Smrj if (erratum > 1000000) 661ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 662ae115bc7Smrj erratum); 663ae115bc7Smrj else 664ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 665ae115bc7Smrj erratum); 666ae115bc7Smrj } 667ae115bc7Smrj 668ae115bc7Smrj static void 669ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 670ae115bc7Smrj { 671ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 672ae115bc7Smrj cp->cpu_id, rw, msr, error); 673ae115bc7Smrj } 6747c478bd9Sstevel@tonic-gate 67592564cb1Sesaxe /* 676d2aeaf66SEric Saxe * Determine the number of nodes in a Hammer / Greyhound / Griffin family 677d2aeaf66SEric Saxe * system. 67892564cb1Sesaxe */ 67992564cb1Sesaxe static uint_t 68092564cb1Sesaxe opteron_get_nnodes(void) 68192564cb1Sesaxe { 68292564cb1Sesaxe static uint_t nnodes = 0; 68392564cb1Sesaxe 684d2aeaf66SEric Saxe if (nnodes == 0) { 68592564cb1Sesaxe #ifdef DEBUG 686d2aeaf66SEric Saxe uint_t family; 68792564cb1Sesaxe 688d2aeaf66SEric Saxe /* 689d2aeaf66SEric Saxe * This routine uses a PCI config space based mechanism 690d2aeaf66SEric Saxe * for retrieving the number of nodes in the system. 691d2aeaf66SEric Saxe * Device 24, function 0, offset 0x60 as used here is not 692d2aeaf66SEric Saxe * AMD processor architectural, and may not work on processor 693d2aeaf66SEric Saxe * families other than those listed below. 694d2aeaf66SEric Saxe * 695d2aeaf66SEric Saxe * Callers of this routine must ensure that we're running on 696d2aeaf66SEric Saxe * a processor which supports this mechanism. 697d2aeaf66SEric Saxe * The assertion below is meant to catch calls on unsupported 698d2aeaf66SEric Saxe * processors. 699d2aeaf66SEric Saxe */ 700d2aeaf66SEric Saxe family = cpuid_getfamily(CPU); 701d2aeaf66SEric Saxe ASSERT(family == 0xf || family == 0x10 || family == 0x11); 70292564cb1Sesaxe #endif /* DEBUG */ 70392564cb1Sesaxe 70492564cb1Sesaxe /* 70592564cb1Sesaxe * Obtain the number of nodes in the system from 70692564cb1Sesaxe * bits [6:4] of the Node ID register on node 0. 70792564cb1Sesaxe * 70892564cb1Sesaxe * The actual node count is NodeID[6:4] + 1 70992564cb1Sesaxe * 71092564cb1Sesaxe * The Node ID register is accessed via function 0, 71192564cb1Sesaxe * offset 0x60. Node 0 is device 24. 71292564cb1Sesaxe */ 71392564cb1Sesaxe nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 71492564cb1Sesaxe } 71592564cb1Sesaxe return (nnodes); 71692564cb1Sesaxe } 71792564cb1Sesaxe 718512cf780Skchow uint_t 719512cf780Skchow do_erratum_298(struct cpu *cpu) 720512cf780Skchow { 721512cf780Skchow static int osvwrc = -3; 722512cf780Skchow extern int osvw_opteron_erratum(cpu_t *, uint_t); 723512cf780Skchow 724512cf780Skchow /* 725512cf780Skchow * L2 Eviction May Occur During Processor Operation To Set 726512cf780Skchow * Accessed or Dirty Bit. 727512cf780Skchow */ 728512cf780Skchow if (osvwrc == -3) { 729512cf780Skchow osvwrc = osvw_opteron_erratum(cpu, 298); 730512cf780Skchow } else { 731512cf780Skchow /* osvw return codes should be consistent for all cpus */ 732512cf780Skchow ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 733512cf780Skchow } 734512cf780Skchow 735512cf780Skchow switch (osvwrc) { 736512cf780Skchow case 0: /* erratum is not present: do nothing */ 737512cf780Skchow break; 738512cf780Skchow case 1: /* erratum is present: BIOS workaround applied */ 739512cf780Skchow /* 740512cf780Skchow * check if workaround is actually in place and issue warning 741512cf780Skchow * if not. 742512cf780Skchow */ 743512cf780Skchow if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 744512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 745512cf780Skchow #if defined(OPTERON_ERRATUM_298) 746512cf780Skchow opteron_erratum_298++; 747512cf780Skchow #else 748512cf780Skchow workaround_warning(cpu, 298); 749512cf780Skchow return (1); 750512cf780Skchow #endif 751512cf780Skchow } 752512cf780Skchow break; 753512cf780Skchow case -1: /* cannot determine via osvw: check cpuid */ 754512cf780Skchow if ((cpuid_opteron_erratum(cpu, 298) > 0) && 755512cf780Skchow (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 756512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 757512cf780Skchow #if defined(OPTERON_ERRATUM_298) 758512cf780Skchow opteron_erratum_298++; 759512cf780Skchow #else 760512cf780Skchow workaround_warning(cpu, 298); 761512cf780Skchow return (1); 762512cf780Skchow #endif 763512cf780Skchow } 764512cf780Skchow break; 765512cf780Skchow } 766512cf780Skchow return (0); 767512cf780Skchow } 768512cf780Skchow 7697c478bd9Sstevel@tonic-gate uint_t 7707c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 7717c478bd9Sstevel@tonic-gate { 7727c478bd9Sstevel@tonic-gate uint_t missing = 0; 7737c478bd9Sstevel@tonic-gate 7747c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 7757c478bd9Sstevel@tonic-gate 7767c478bd9Sstevel@tonic-gate /*LINTED*/ 7777c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 7787c478bd9Sstevel@tonic-gate /* 7797c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 7807c478bd9Sstevel@tonic-gate */ 7817c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 7827c478bd9Sstevel@tonic-gate /* 7837c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 7847c478bd9Sstevel@tonic-gate */ 785ae115bc7Smrj opteron_erratum_88++; 7867c478bd9Sstevel@tonic-gate #else 787ae115bc7Smrj workaround_warning(cpu, 88); 7887c478bd9Sstevel@tonic-gate missing++; 7897c478bd9Sstevel@tonic-gate #endif 7907c478bd9Sstevel@tonic-gate } 7917c478bd9Sstevel@tonic-gate 7927c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 7937c478bd9Sstevel@tonic-gate /* 7947c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 7957c478bd9Sstevel@tonic-gate */ 7967c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 7977c478bd9Sstevel@tonic-gate /* 7987c478bd9Sstevel@tonic-gate * fix is in trap.c 7997c478bd9Sstevel@tonic-gate */ 8007c478bd9Sstevel@tonic-gate opteron_erratum_91++; 8017c478bd9Sstevel@tonic-gate #else 802ae115bc7Smrj workaround_warning(cpu, 91); 8037c478bd9Sstevel@tonic-gate missing++; 8047c478bd9Sstevel@tonic-gate #endif 8057c478bd9Sstevel@tonic-gate } 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 8087c478bd9Sstevel@tonic-gate /* 8097c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 8107c478bd9Sstevel@tonic-gate */ 8117c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 8127c478bd9Sstevel@tonic-gate /* 8137c478bd9Sstevel@tonic-gate * fix is in trap.c 8147c478bd9Sstevel@tonic-gate */ 8157c478bd9Sstevel@tonic-gate opteron_erratum_93++; 8167c478bd9Sstevel@tonic-gate #else 817ae115bc7Smrj workaround_warning(cpu, 93); 8187c478bd9Sstevel@tonic-gate missing++; 8197c478bd9Sstevel@tonic-gate #endif 8207c478bd9Sstevel@tonic-gate } 8217c478bd9Sstevel@tonic-gate 8227c478bd9Sstevel@tonic-gate /*LINTED*/ 8237c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 8247c478bd9Sstevel@tonic-gate /* 8257c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 8267c478bd9Sstevel@tonic-gate */ 8277c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 8287c478bd9Sstevel@tonic-gate #if defined(_LP64) 8297c478bd9Sstevel@tonic-gate /* 8307c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 8317c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 8327c478bd9Sstevel@tonic-gate * range mod 4G. 8337c478bd9Sstevel@tonic-gate */ 8347c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 8357c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 8367c478bd9Sstevel@tonic-gate 8377c478bd9Sstevel@tonic-gate /*LINTED*/ 8387c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 839ae115bc7Smrj opteron_erratum_95++; 8407c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 8417c478bd9Sstevel@tonic-gate #else 842ae115bc7Smrj workaround_warning(cpu, 95); 8437c478bd9Sstevel@tonic-gate missing++; 844ae115bc7Smrj #endif 8457c478bd9Sstevel@tonic-gate } 8467c478bd9Sstevel@tonic-gate 8477c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 8487c478bd9Sstevel@tonic-gate /* 8497c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 8507c478bd9Sstevel@tonic-gate */ 8517c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8527c478bd9Sstevel@tonic-gate /* 8537c478bd9Sstevel@tonic-gate * fix is in trap.c 8547c478bd9Sstevel@tonic-gate */ 8557c478bd9Sstevel@tonic-gate opteron_erratum_100++; 8567c478bd9Sstevel@tonic-gate #else 857ae115bc7Smrj workaround_warning(cpu, 100); 8587c478bd9Sstevel@tonic-gate missing++; 8597c478bd9Sstevel@tonic-gate #endif 8607c478bd9Sstevel@tonic-gate } 8617c478bd9Sstevel@tonic-gate 8627c478bd9Sstevel@tonic-gate /*LINTED*/ 8637c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 8647c478bd9Sstevel@tonic-gate /* 8657c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 8667c478bd9Sstevel@tonic-gate * Some Processors 8677c478bd9Sstevel@tonic-gate */ 8687c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 8697c478bd9Sstevel@tonic-gate /* 8707c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 8717c478bd9Sstevel@tonic-gate * those processors) 8727c478bd9Sstevel@tonic-gate */ 8737c478bd9Sstevel@tonic-gate #else 874ae115bc7Smrj workaround_warning(cpu, 108); 8757c478bd9Sstevel@tonic-gate missing++; 8767c478bd9Sstevel@tonic-gate #endif 8777c478bd9Sstevel@tonic-gate } 8787c478bd9Sstevel@tonic-gate 8797c478bd9Sstevel@tonic-gate /*LINTED*/ 880ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 8817c478bd9Sstevel@tonic-gate /* 882fb2caebeSRandy Fishel * Certain Reverse REP MOVS May Produce Unpredictable Behavior 8837c478bd9Sstevel@tonic-gate */ 8847c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 885ae115bc7Smrj /* 886ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 887ae115bc7Smrj */ 888ae115bc7Smrj uint64_t value; 889ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 890ae115bc7Smrj int err; 891ae115bc7Smrj 892ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 893ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 894ae115bc7Smrj workaround_warning(cpu, 109); 895ae115bc7Smrj missing++; 896ae115bc7Smrj } 897ae115bc7Smrj if (value == 0) 8987c478bd9Sstevel@tonic-gate opteron_erratum_109++; 8997c478bd9Sstevel@tonic-gate #else 900ae115bc7Smrj workaround_warning(cpu, 109); 9017c478bd9Sstevel@tonic-gate missing++; 9027c478bd9Sstevel@tonic-gate #endif 903ae115bc7Smrj /*CONSTANTCONDITION*/ 904ae115bc7Smrj } while (0); 905ae115bc7Smrj 9067c478bd9Sstevel@tonic-gate /*LINTED*/ 9077c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 9087c478bd9Sstevel@tonic-gate /* 9097c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 9107c478bd9Sstevel@tonic-gate * Processor Hang 9117c478bd9Sstevel@tonic-gate */ 9127c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 913ae115bc7Smrj #if defined(_LP64) 9147c478bd9Sstevel@tonic-gate /* 9157c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 9167c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 9177c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 9187c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 9197c478bd9Sstevel@tonic-gate */ 920ae115bc7Smrj if (opteron_erratum_121) 921ae115bc7Smrj opteron_erratum_121++; 922ae115bc7Smrj else { 923ae115bc7Smrj if (hole_start) { 924ae115bc7Smrj hole_start -= PAGESIZE; 925ae115bc7Smrj } else { 926ae115bc7Smrj /* 927ae115bc7Smrj * hole_start not yet initialized by 928ae115bc7Smrj * mmu_init. Initialize hole_start 929ae115bc7Smrj * with value to be subtracted. 930ae115bc7Smrj */ 931ae115bc7Smrj hole_start = PAGESIZE; 9327c478bd9Sstevel@tonic-gate } 933ae115bc7Smrj opteron_erratum_121++; 9347c478bd9Sstevel@tonic-gate } 935ae115bc7Smrj #endif /* _LP64 */ 9367c478bd9Sstevel@tonic-gate #else 937ae115bc7Smrj workaround_warning(cpu, 121); 9387c478bd9Sstevel@tonic-gate missing++; 9397c478bd9Sstevel@tonic-gate #endif 9407c478bd9Sstevel@tonic-gate } 9417c478bd9Sstevel@tonic-gate 9427c478bd9Sstevel@tonic-gate /*LINTED*/ 943ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 9447c478bd9Sstevel@tonic-gate /* 945ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 9467c478bd9Sstevel@tonic-gate * Multiprocessor Systems 9477c478bd9Sstevel@tonic-gate */ 9487c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 949ae115bc7Smrj uint64_t value; 950ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 951ae115bc7Smrj int error; 952ae115bc7Smrj 9537c478bd9Sstevel@tonic-gate /* 9547c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 9557c478bd9Sstevel@tonic-gate * or multi-processor). 9567c478bd9Sstevel@tonic-gate */ 957843e1988Sjohnlev #if defined(__xpv) 958843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 959843e1988Sjohnlev break; 960349b53ddSStuart Maybee if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 961843e1988Sjohnlev break; 962843e1988Sjohnlev #else 96392564cb1Sesaxe if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 964ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 965ae115bc7Smrj break; 966843e1988Sjohnlev #endif 967ae115bc7Smrj /* disable TLB Flush Filter */ 968ae115bc7Smrj 969ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 970ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 971ae115bc7Smrj workaround_warning(cpu, 122); 972ae115bc7Smrj missing++; 973ae115bc7Smrj } else { 974ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 975ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 976ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 977ae115bc7Smrj workaround_warning(cpu, 122); 978ae115bc7Smrj missing++; 979ae115bc7Smrj } 9807c478bd9Sstevel@tonic-gate } 981ae115bc7Smrj opteron_erratum_122++; 9827c478bd9Sstevel@tonic-gate #else 983ae115bc7Smrj workaround_warning(cpu, 122); 9847c478bd9Sstevel@tonic-gate missing++; 9857c478bd9Sstevel@tonic-gate #endif 986ae115bc7Smrj /*CONSTANTCONDITION*/ 987ae115bc7Smrj } while (0); 988403c216aSkchow 9897c478bd9Sstevel@tonic-gate /*LINTED*/ 990ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 9917c478bd9Sstevel@tonic-gate /* 9927c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 9937c478bd9Sstevel@tonic-gate * Dual Core Processors 9947c478bd9Sstevel@tonic-gate */ 995ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 996ae115bc7Smrj uint64_t value; 997ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 998ae115bc7Smrj int err; 999ae115bc7Smrj 10007c478bd9Sstevel@tonic-gate /* 10017c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 10027c478bd9Sstevel@tonic-gate */ 1003ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 1004ae115bc7Smrj break; 1005843e1988Sjohnlev #if defined(__xpv) 1006843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1007843e1988Sjohnlev break; 1008843e1988Sjohnlev #endif 1009ae115bc7Smrj /* 1010ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 1011ae115bc7Smrj */ 1012ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 1013ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 1014ae115bc7Smrj workaround_warning(cpu, 123); 1015ae115bc7Smrj missing++; 10167c478bd9Sstevel@tonic-gate } 1017ae115bc7Smrj if (value == 0) 1018ae115bc7Smrj opteron_erratum_123++; 1019ae115bc7Smrj #else 1020ae115bc7Smrj workaround_warning(cpu, 123); 1021ae115bc7Smrj missing++; 1022ae115bc7Smrj 1023403c216aSkchow #endif 1024ae115bc7Smrj /*CONSTANTCONDITION*/ 1025ae115bc7Smrj } while (0); 10262201b277Skucharsk 10272201b277Skucharsk /*LINTED*/ 1028ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 10292201b277Skucharsk /* 10302201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 10312201b277Skucharsk * Waiting for a Probe Response 10322201b277Skucharsk */ 1033ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 1034ae115bc7Smrj uint64_t nbcfg; 1035ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 1036ae115bc7Smrj const uint64_t wabits = 1037ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1038ae115bc7Smrj int error; 1039ae115bc7Smrj 10402201b277Skucharsk /* 10412201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 10422201b277Skucharsk */ 1043ae115bc7Smrj if (opteron_erratum_131) 1044ae115bc7Smrj break; 1045843e1988Sjohnlev #if defined(__xpv) 1046843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1047843e1988Sjohnlev break; 1048349b53ddSStuart Maybee if (xpv_nr_phys_cpus() < 4) 1049843e1988Sjohnlev break; 1050843e1988Sjohnlev #else 105192564cb1Sesaxe if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1052ae115bc7Smrj break; 1053843e1988Sjohnlev #endif 1054ae115bc7Smrj /* 1055ae115bc7Smrj * Print a warning if neither of the workarounds for 1056ae115bc7Smrj * erratum 131 is present. 1057ae115bc7Smrj */ 1058ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1059ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1060ae115bc7Smrj workaround_warning(cpu, 131); 1061ae115bc7Smrj missing++; 1062ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 1063ae115bc7Smrj opteron_erratum_131++; 1064ae115bc7Smrj } else { 1065ae115bc7Smrj /* cannot have both workarounds set */ 1066ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 10672201b277Skucharsk } 1068ae115bc7Smrj #else 1069ae115bc7Smrj workaround_warning(cpu, 131); 1070ae115bc7Smrj missing++; 10712201b277Skucharsk #endif 1072ae115bc7Smrj /*CONSTANTCONDITION*/ 1073ae115bc7Smrj } while (0); 1074ef50d8c0Sesaxe 1075ef50d8c0Sesaxe /* 1076ae115bc7Smrj * This isn't really an erratum, but for convenience the 1077ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 1078ef50d8c0Sesaxe */ 1079ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1080ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1081ef50d8c0Sesaxe /* 1082ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 1083ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 1084ef50d8c0Sesaxe */ 1085ef50d8c0Sesaxe if (opteron_workaround_6336786) { 1086ef50d8c0Sesaxe opteron_workaround_6336786++; 1087843e1988Sjohnlev #if defined(__xpv) 1088843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1089349b53ddSStuart Maybee xpv_nr_phys_cpus() > 1) || 1090843e1988Sjohnlev opteron_workaround_6336786_UP) { 1091843e1988Sjohnlev /* 109292564cb1Sesaxe * XXPV Hmm. We can't walk the Northbridges on 1093843e1988Sjohnlev * the hypervisor; so just complain and drive 1094843e1988Sjohnlev * on. This probably needs to be fixed in 1095843e1988Sjohnlev * the hypervisor itself. 1096843e1988Sjohnlev */ 1097843e1988Sjohnlev opteron_workaround_6336786++; 1098843e1988Sjohnlev workaround_warning(cpu, 6336786); 1099843e1988Sjohnlev #else /* __xpv */ 110092564cb1Sesaxe } else if ((opteron_get_nnodes() * 1101d38257c4Sesaxe cpuid_get_ncpu_per_chip(cpu) > 1) || 1102ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 110392564cb1Sesaxe 110492564cb1Sesaxe uint_t node, nnodes; 1105ae115bc7Smrj uint8_t data; 1106ae115bc7Smrj 110792564cb1Sesaxe nnodes = opteron_get_nnodes(); 110892564cb1Sesaxe for (node = 0; node < nnodes; node++) { 1109ef50d8c0Sesaxe /* 1110ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 1111ef50d8c0Sesaxe * Northbridge device is the node id + 24. 1112ef50d8c0Sesaxe */ 1113ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 1114ef50d8c0Sesaxe data &= 0xFC; 1115ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 1116ef50d8c0Sesaxe } 1117ef50d8c0Sesaxe opteron_workaround_6336786++; 1118843e1988Sjohnlev #endif /* __xpv */ 1119ef50d8c0Sesaxe } 1120ae115bc7Smrj #else 1121ae115bc7Smrj workaround_warning(cpu, 6336786); 1122ae115bc7Smrj missing++; 1123ef50d8c0Sesaxe #endif 1124ae115bc7Smrj } 1125ee88d2b9Skchow 1126ee88d2b9Skchow /*LINTED*/ 1127ee88d2b9Skchow /* 1128ee88d2b9Skchow * Mutex primitives don't work as expected. 1129ee88d2b9Skchow */ 1130ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1131ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1132ee88d2b9Skchow /* 1133ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1134512cf780Skchow * MSR_AMD_BU_CFG set, then not applicable. The workaround 1135ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1136ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1137ee88d2b9Skchow * possible subsequent read-modify-write ops. 1138ee88d2b9Skchow * 1139ee88d2b9Skchow * It is too early in boot to call the patch routine so 1140ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1141ee88d2b9Skchow */ 1142ee88d2b9Skchow if (opteron_workaround_6323525) { 1143ee88d2b9Skchow opteron_workaround_6323525++; 1144843e1988Sjohnlev #if defined(__xpv) 1145843e1988Sjohnlev } else if (x86_feature & X86_SSE2) { 1146843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1147843e1988Sjohnlev /* 1148843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1149843e1988Sjohnlev * operations are supported? 1150843e1988Sjohnlev */ 1151349b53ddSStuart Maybee if (xpv_nr_phys_cpus() > 1) 1152843e1988Sjohnlev opteron_workaround_6323525++; 1153843e1988Sjohnlev } else { 1154843e1988Sjohnlev /* 1155843e1988Sjohnlev * We have no way to tell how many physical 1156843e1988Sjohnlev * cpus there are, or even if this processor 1157843e1988Sjohnlev * has the problem, so enable the workaround 1158843e1988Sjohnlev * unconditionally (at some performance cost). 1159843e1988Sjohnlev */ 1160843e1988Sjohnlev opteron_workaround_6323525++; 1161843e1988Sjohnlev } 1162843e1988Sjohnlev #else /* __xpv */ 116392564cb1Sesaxe } else if ((x86_feature & X86_SSE2) && ((opteron_get_nnodes() * 1164ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 116548b2bf45SKit Chow if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1166ee88d2b9Skchow opteron_workaround_6323525++; 1167843e1988Sjohnlev #endif /* __xpv */ 1168ee88d2b9Skchow } 1169ae115bc7Smrj #else 1170ae115bc7Smrj workaround_warning(cpu, 6323525); 1171ae115bc7Smrj missing++; 1172ee88d2b9Skchow #endif 1173ae115bc7Smrj } 1174ae115bc7Smrj 1175512cf780Skchow missing += do_erratum_298(cpu); 1176512cf780Skchow 1177843e1988Sjohnlev #ifdef __xpv 1178843e1988Sjohnlev return (0); 1179843e1988Sjohnlev #else 11807c478bd9Sstevel@tonic-gate return (missing); 1181843e1988Sjohnlev #endif 11827c478bd9Sstevel@tonic-gate } 11837c478bd9Sstevel@tonic-gate 11847c478bd9Sstevel@tonic-gate void 11857c478bd9Sstevel@tonic-gate workaround_errata_end() 11867c478bd9Sstevel@tonic-gate { 1187ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1188ae115bc7Smrj if (opteron_erratum_88) 1189ae115bc7Smrj workaround_applied(88); 1190ae115bc7Smrj #endif 1191ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1192ae115bc7Smrj if (opteron_erratum_91) 1193ae115bc7Smrj workaround_applied(91); 1194ae115bc7Smrj #endif 1195ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1196ae115bc7Smrj if (opteron_erratum_93) 1197ae115bc7Smrj workaround_applied(93); 1198ae115bc7Smrj #endif 1199ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1200ae115bc7Smrj if (opteron_erratum_95) 1201ae115bc7Smrj workaround_applied(95); 1202ae115bc7Smrj #endif 1203ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1204ae115bc7Smrj if (opteron_erratum_100) 1205ae115bc7Smrj workaround_applied(100); 1206ae115bc7Smrj #endif 1207ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1208ae115bc7Smrj if (opteron_erratum_108) 1209ae115bc7Smrj workaround_applied(108); 1210ae115bc7Smrj #endif 12117c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 12127c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 12132201b277Skucharsk cmn_err(CE_WARN, 12142201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12152201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 12162201b277Skucharsk " system's BIOS to a version\ncontaining this" 12172201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12182201b277Skucharsk " system\noperation may occur.\n"); 12197c478bd9Sstevel@tonic-gate } 1220ae115bc7Smrj #endif 1221ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1222ae115bc7Smrj if (opteron_erratum_121) 1223ae115bc7Smrj workaround_applied(121); 1224ae115bc7Smrj #endif 1225ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1226ae115bc7Smrj if (opteron_erratum_122) 1227ae115bc7Smrj workaround_applied(122); 1228ae115bc7Smrj #endif 12297c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 12307c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 12312201b277Skucharsk cmn_err(CE_WARN, 12322201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12332201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 12342201b277Skucharsk " system's BIOS to a version\ncontaining this" 12352201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12362201b277Skucharsk " system\noperation may occur.\n"); 12377c478bd9Sstevel@tonic-gate } 1238ae115bc7Smrj #endif 12392201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 12402201b277Skucharsk if (opteron_erratum_131) { 12412201b277Skucharsk cmn_err(CE_WARN, 12422201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12432201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 12442201b277Skucharsk " system's BIOS to a version\ncontaining this" 12452201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12462201b277Skucharsk " system\noperation may occur.\n"); 12472201b277Skucharsk } 1248ae115bc7Smrj #endif 1249ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1250ae115bc7Smrj if (opteron_workaround_6336786) 1251ae115bc7Smrj workaround_applied(6336786); 1252ae115bc7Smrj #endif 1253ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1254ae115bc7Smrj if (opteron_workaround_6323525) 1255ae115bc7Smrj workaround_applied(6323525); 1256ae115bc7Smrj #endif 1257512cf780Skchow #if defined(OPTERON_ERRATUM_298) 1258512cf780Skchow if (opteron_erratum_298) { 1259512cf780Skchow cmn_err(CE_WARN, 1260512cf780Skchow "BIOS microcode patch for AMD 64/Opteron(tm)" 1261512cf780Skchow " processor\nerratum 298 was not detected; updating your" 1262512cf780Skchow " system's BIOS to a version\ncontaining this" 1263512cf780Skchow " microcode patch is HIGHLY recommended or erroneous" 1264512cf780Skchow " system\noperation may occur.\n"); 1265512cf780Skchow } 1266512cf780Skchow #endif 12677c478bd9Sstevel@tonic-gate } 12687c478bd9Sstevel@tonic-gate 1269ae115bc7Smrj /* 1270*a3114836SGerry Liu * The procset_slave and procset_master are used to synchronize 1271*a3114836SGerry Liu * between the control CPU and the target CPU when starting CPUs. 1272ae115bc7Smrj */ 1273*a3114836SGerry Liu static cpuset_t procset_slave, procset_master; 1274*a3114836SGerry Liu 1275*a3114836SGerry Liu static void 1276*a3114836SGerry Liu mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1277*a3114836SGerry Liu { 1278*a3114836SGerry Liu cpuset_t tempset; 1279*a3114836SGerry Liu 1280*a3114836SGerry Liu for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1281*a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1282*a3114836SGerry Liu SMT_PAUSE(); 1283*a3114836SGerry Liu } 1284*a3114836SGerry Liu CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1285*a3114836SGerry Liu } 1286*a3114836SGerry Liu 1287*a3114836SGerry Liu static void 1288*a3114836SGerry Liu mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1289*a3114836SGerry Liu { 1290*a3114836SGerry Liu cpuset_t tempset; 1291*a3114836SGerry Liu 1292*a3114836SGerry Liu CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1293*a3114836SGerry Liu for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1294*a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1295*a3114836SGerry Liu SMT_PAUSE(); 1296*a3114836SGerry Liu } 1297*a3114836SGerry Liu } 1298*a3114836SGerry Liu 1299ae115bc7Smrj int 1300*a3114836SGerry Liu mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1301ae115bc7Smrj { 1302*a3114836SGerry Liu _NOTE(ARGUNUSED(boot)); 1303*a3114836SGerry Liu 1304ae115bc7Smrj void *ctx; 1305ae115bc7Smrj int delays; 1306ae115bc7Smrj int error = 0; 1307*a3114836SGerry Liu cpuset_t tempset; 1308*a3114836SGerry Liu processorid_t cpuid; 1309*a3114836SGerry Liu #ifndef __xpv 1310*a3114836SGerry Liu extern void cpupm_init(cpu_t *); 1311*a3114836SGerry Liu #endif 1312ae115bc7Smrj 1313*a3114836SGerry Liu ASSERT(cp != NULL); 1314*a3114836SGerry Liu cpuid = cp->cpu_id; 1315*a3114836SGerry Liu ctx = mach_cpucontext_alloc(cp); 1316*a3114836SGerry Liu if (ctx == NULL) { 1317*a3114836SGerry Liu cmn_err(CE_WARN, 1318*a3114836SGerry Liu "cpu%d: failed to allocate context", cp->cpu_id); 1319*a3114836SGerry Liu return (EAGAIN); 1320ae115bc7Smrj } 1321*a3114836SGerry Liu error = mach_cpu_start(cp, ctx); 1322*a3114836SGerry Liu if (error != 0) { 1323*a3114836SGerry Liu cmn_err(CE_WARN, 1324*a3114836SGerry Liu "cpu%d: failed to start, error %d", cp->cpu_id, error); 1325*a3114836SGerry Liu mach_cpucontext_free(cp, ctx, error); 1326ae115bc7Smrj return (error); 1327ae115bc7Smrj } 1328ae115bc7Smrj 1329*a3114836SGerry Liu for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1330*a3114836SGerry Liu delays++) { 1331ae115bc7Smrj if (delays == 500) { 1332ae115bc7Smrj /* 1333ae115bc7Smrj * After five seconds, things are probably looking 1334ae115bc7Smrj * a bit bleak - explain the hang. 1335ae115bc7Smrj */ 1336ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1337*a3114836SGerry Liu "but not running in the kernel yet", cpuid); 1338ae115bc7Smrj } else if (delays > 2000) { 1339ae115bc7Smrj /* 1340ae115bc7Smrj * We waited at least 20 seconds, bail .. 1341ae115bc7Smrj */ 1342ae115bc7Smrj error = ETIMEDOUT; 1343*a3114836SGerry Liu cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1344ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1345ae115bc7Smrj return (error); 1346ae115bc7Smrj } 1347ae115bc7Smrj 1348ae115bc7Smrj /* 1349ae115bc7Smrj * wait at least 10ms, then check again.. 1350ae115bc7Smrj */ 1351ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1352*a3114836SGerry Liu tempset = *((volatile cpuset_t *)&procset_slave); 1353ae115bc7Smrj } 1354*a3114836SGerry Liu CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1355ae115bc7Smrj 1356ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1357ae115bc7Smrj 1358843e1988Sjohnlev #ifndef __xpv 1359ae115bc7Smrj if (tsc_gethrtime_enable) 1360*a3114836SGerry Liu tsc_sync_master(cpuid); 1361843e1988Sjohnlev #endif 1362ae115bc7Smrj 1363ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1364*a3114836SGerry Liu (*dtrace_cpu_init)(cpuid); 1365*a3114836SGerry Liu } 1366*a3114836SGerry Liu 1367*a3114836SGerry Liu /* 1368*a3114836SGerry Liu * During CPU DR operations, the cpu_lock is held by current 1369*a3114836SGerry Liu * (the control) thread. We can't release the cpu_lock here 1370*a3114836SGerry Liu * because that will break the CPU DR logic. 1371*a3114836SGerry Liu * On the other hand, CPUPM and processor group initialization 1372*a3114836SGerry Liu * routines need to access the cpu_lock. So we invoke those 1373*a3114836SGerry Liu * routines here on behalf of mp_startup_common(). 1374*a3114836SGerry Liu * 1375*a3114836SGerry Liu * CPUPM and processor group initialization routines depend 1376*a3114836SGerry Liu * on the cpuid probing results. Wait for mp_startup_common() 1377*a3114836SGerry Liu * to signal that cpuid probing is done. 1378*a3114836SGerry Liu */ 1379*a3114836SGerry Liu mp_startup_wait(&procset_slave, cpuid); 1380*a3114836SGerry Liu #ifndef __xpv 1381*a3114836SGerry Liu cpupm_init(cp); 1382*a3114836SGerry Liu #endif 1383*a3114836SGerry Liu (void) pg_cpu_init(cp, B_FALSE); 1384*a3114836SGerry Liu cpu_set_state(cp); 1385*a3114836SGerry Liu mp_startup_signal(&procset_master, cpuid); 1386*a3114836SGerry Liu 1387*a3114836SGerry Liu return (0); 1388*a3114836SGerry Liu } 1389*a3114836SGerry Liu 1390*a3114836SGerry Liu /* 1391*a3114836SGerry Liu * Start a single cpu, assuming that the kernel context is available 1392*a3114836SGerry Liu * to successfully start another cpu. 1393*a3114836SGerry Liu * 1394*a3114836SGerry Liu * (For example, real mode code is mapped into the right place 1395*a3114836SGerry Liu * in memory and is ready to be run.) 1396*a3114836SGerry Liu */ 1397*a3114836SGerry Liu int 1398*a3114836SGerry Liu start_cpu(processorid_t who) 1399*a3114836SGerry Liu { 1400*a3114836SGerry Liu cpu_t *cp; 1401*a3114836SGerry Liu int error = 0; 1402*a3114836SGerry Liu cpuset_t tempset; 1403*a3114836SGerry Liu 1404*a3114836SGerry Liu ASSERT(who != 0); 1405*a3114836SGerry Liu 1406*a3114836SGerry Liu /* 1407*a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1408*a3114836SGerry Liu * before attempting to start the cpu. 1409*a3114836SGerry Liu */ 1410*a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1411ae115bc7Smrj /* 1412*a3114836SGerry Liu * Kick off a reap in case that helps us with 1413*a3114836SGerry Liu * later attempts .. 1414ae115bc7Smrj */ 1415*a3114836SGerry Liu kmem_reap(); 1416*a3114836SGerry Liu return (ENOMEM); 1417*a3114836SGerry Liu } 1418*a3114836SGerry Liu 1419*a3114836SGerry Liu /* 1420*a3114836SGerry Liu * First configure cpu. 1421*a3114836SGerry Liu */ 1422*a3114836SGerry Liu cp = mp_cpu_configure_common(who, B_TRUE); 1423*a3114836SGerry Liu ASSERT(cp != NULL); 1424*a3114836SGerry Liu 1425*a3114836SGerry Liu /* 1426*a3114836SGerry Liu * Then start cpu. 1427*a3114836SGerry Liu */ 1428*a3114836SGerry Liu error = mp_start_cpu_common(cp, B_TRUE); 1429*a3114836SGerry Liu if (error != 0) { 1430*a3114836SGerry Liu mp_cpu_unconfigure_common(cp, error); 1431*a3114836SGerry Liu return (error); 1432ae115bc7Smrj } 1433ae115bc7Smrj 1434*a3114836SGerry Liu mutex_exit(&cpu_lock); 1435*a3114836SGerry Liu tempset = cpu_ready_set; 1436*a3114836SGerry Liu while (!CPU_IN_SET(tempset, who)) { 1437*a3114836SGerry Liu drv_usecwait(1); 1438*a3114836SGerry Liu tempset = *((volatile cpuset_t *)&cpu_ready_set); 1439*a3114836SGerry Liu } 1440*a3114836SGerry Liu mutex_enter(&cpu_lock); 1441ae115bc7Smrj 1442ae115bc7Smrj return (0); 1443ae115bc7Smrj } 14447c478bd9Sstevel@tonic-gate 14457c478bd9Sstevel@tonic-gate void 14467c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 14477c478bd9Sstevel@tonic-gate { 1448*a3114836SGerry Liu _NOTE(ARGUNUSED(cprboot)); 1449*a3114836SGerry Liu 1450ae115bc7Smrj uint_t who; 1451ae115bc7Smrj uint_t bootcpuid = 0; 14527c478bd9Sstevel@tonic-gate 14537c478bd9Sstevel@tonic-gate /* 14547c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 14557c478bd9Sstevel@tonic-gate */ 14567c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 14577c478bd9Sstevel@tonic-gate 145819397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 145919397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 146019397407SSherry Moore 14617c478bd9Sstevel@tonic-gate /* 14627c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 14637c478bd9Sstevel@tonic-gate */ 14647c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 14657c478bd9Sstevel@tonic-gate 1466ae115bc7Smrj /* 1467ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1468ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1469ae115bc7Smrj * precisely the same reason. 1470ae115bc7Smrj */ 1471ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1472ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1473ae115bc7Smrj 14747c478bd9Sstevel@tonic-gate /* 1475*a3114836SGerry Liu * skip the rest of this if 1476*a3114836SGerry Liu * . only 1 cpu dectected and system isn't hotplug-capable 1477*a3114836SGerry Liu * . not using MP 14787c478bd9Sstevel@tonic-gate */ 1479*a3114836SGerry Liu if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1480*a3114836SGerry Liu use_mp == 0) { 14817c478bd9Sstevel@tonic-gate if (use_mp == 0) 14827c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 14837c478bd9Sstevel@tonic-gate goto done; 14847c478bd9Sstevel@tonic-gate } 14857c478bd9Sstevel@tonic-gate 14867c478bd9Sstevel@tonic-gate /* 14877c478bd9Sstevel@tonic-gate * perform such initialization as is needed 14887c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 14897c478bd9Sstevel@tonic-gate */ 14907c478bd9Sstevel@tonic-gate cpu_pause_init(); 14917c478bd9Sstevel@tonic-gate 1492f34a7178SJoe Bonasera xc_init_cpu(CPU); /* initialize processor crosscalls */ 14937c478bd9Sstevel@tonic-gate 1494ae115bc7Smrj if (mach_cpucontext_init() != 0) 14957c478bd9Sstevel@tonic-gate goto done; 14967c478bd9Sstevel@tonic-gate 14977c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 14987c478bd9Sstevel@tonic-gate 14995205ae23Snf /* 15005205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 15015205ae23Snf * do their TSC syncs with the same CPU. 15025205ae23Snf */ 15037c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 15047c478bd9Sstevel@tonic-gate 15057c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 150641791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 150741791439Sandrei continue; 1508ae115bc7Smrj ASSERT(who != bootcpuid); 1509b9e93c10SJonathan Haslam 1510b9e93c10SJonathan Haslam mutex_enter(&cpu_lock); 1511*a3114836SGerry Liu if (start_cpu(who) != 0) 1512*a3114836SGerry Liu CPUSET_DEL(mp_cpus, who); 1513b9e93c10SJonathan Haslam cpu_state_change_notify(who, CPU_SETUP); 1514b9e93c10SJonathan Haslam mutex_exit(&cpu_lock); 15157c478bd9Sstevel@tonic-gate } 15167c478bd9Sstevel@tonic-gate 15172449e17fSsherrym /* Free the space allocated to hold the microcode file */ 1518adc586deSMark Johnson ucode_cleanup(); 15192449e17fSsherrym 15207c478bd9Sstevel@tonic-gate affinity_clear(); 15217c478bd9Sstevel@tonic-gate 1522*a3114836SGerry Liu mach_cpucontext_fini(); 1523*a3114836SGerry Liu 1524*a3114836SGerry Liu done: 1525*a3114836SGerry Liu if (get_hwenv() == HW_NATIVE) 1526*a3114836SGerry Liu workaround_errata_end(); 1527*a3114836SGerry Liu cmi_post_mpstartup(); 1528*a3114836SGerry Liu 1529*a3114836SGerry Liu if (use_mp && ncpus != boot_max_ncpus) { 153041791439Sandrei cmn_err(CE_NOTE, 1531ae115bc7Smrj "System detected %d cpus, but " 1532ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 1533*a3114836SGerry Liu boot_max_ncpus, ncpus); 153441791439Sandrei cmn_err(CE_NOTE, 153541791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 153641791439Sandrei "See eeprom(1M)."); 153741791439Sandrei } 15387c478bd9Sstevel@tonic-gate } 15397c478bd9Sstevel@tonic-gate 15407c478bd9Sstevel@tonic-gate int 15417c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 15427c478bd9Sstevel@tonic-gate { 1543*a3114836SGerry Liu cpu_t *cp; 1544*a3114836SGerry Liu 1545*a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1546*a3114836SGerry Liu return (ENOTSUP); 1547*a3114836SGerry Liu } 1548*a3114836SGerry Liu 1549*a3114836SGerry Liu cp = cpu_get(cpuid); 1550*a3114836SGerry Liu if (cp != NULL) { 1551*a3114836SGerry Liu return (EALREADY); 1552*a3114836SGerry Liu } 1553*a3114836SGerry Liu 1554*a3114836SGerry Liu /* 1555*a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1556*a3114836SGerry Liu * before attempting to start the cpu. 1557*a3114836SGerry Liu */ 1558*a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1559*a3114836SGerry Liu /* 1560*a3114836SGerry Liu * Kick off a reap in case that helps us with 1561*a3114836SGerry Liu * later attempts .. 1562*a3114836SGerry Liu */ 1563*a3114836SGerry Liu kmem_reap(); 1564*a3114836SGerry Liu return (ENOMEM); 1565*a3114836SGerry Liu } 1566*a3114836SGerry Liu 1567*a3114836SGerry Liu cp = mp_cpu_configure_common(cpuid, B_FALSE); 1568*a3114836SGerry Liu ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1569*a3114836SGerry Liu 1570*a3114836SGerry Liu return (cp != NULL ? 0 : EAGAIN); 15717c478bd9Sstevel@tonic-gate } 15727c478bd9Sstevel@tonic-gate 15737c478bd9Sstevel@tonic-gate int 15747c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 15757c478bd9Sstevel@tonic-gate { 1576*a3114836SGerry Liu cpu_t *cp; 1577*a3114836SGerry Liu 1578*a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1579*a3114836SGerry Liu return (ENOTSUP); 1580*a3114836SGerry Liu } else if (cpuid < 0 || cpuid >= max_ncpus) { 1581*a3114836SGerry Liu return (EINVAL); 1582*a3114836SGerry Liu } 1583*a3114836SGerry Liu 1584*a3114836SGerry Liu cp = cpu_get(cpuid); 1585*a3114836SGerry Liu if (cp == NULL) { 1586*a3114836SGerry Liu return (ENODEV); 1587*a3114836SGerry Liu } 1588*a3114836SGerry Liu mp_cpu_unconfigure_common(cp, 0); 1589*a3114836SGerry Liu 1590*a3114836SGerry Liu return (0); 15917c478bd9Sstevel@tonic-gate } 15927c478bd9Sstevel@tonic-gate 15937c478bd9Sstevel@tonic-gate /* 15947c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1595498697c5Sdmick * Called from real_mode_start. 1596b4b46911Skchow * 1597*a3114836SGerry Liu * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1598*a3114836SGerry Liu * mp_startup_common should not call routines (e.g. kmem_free) that could call 1599b4b46911Skchow * hat_unload which requires CPU_READY to be set. 16007c478bd9Sstevel@tonic-gate */ 1601*a3114836SGerry Liu static void 1602*a3114836SGerry Liu mp_startup_common(boolean_t boot) 16037c478bd9Sstevel@tonic-gate { 1604*a3114836SGerry Liu cpu_t *cp = CPU; 16057c478bd9Sstevel@tonic-gate uint_t new_x86_feature; 1606a50a8b93SKuriakose Kuruvilla const char *fmt = "?cpu%d: %b\n"; 1607*a3114836SGerry Liu extern void cpu_event_init_cpu(cpu_t *); 16087c478bd9Sstevel@tonic-gate 160924a74e86Sdmick /* 161024a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 161124a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 161224a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 161324a74e86Sdmick * interrupts, cmn_err, etc. 161424a74e86Sdmick */ 161524a74e86Sdmick 1616*a3114836SGerry Liu /* Let the control CPU continue into tsc_sync_master() */ 1617*a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 161824a74e86Sdmick 1619843e1988Sjohnlev #ifndef __xpv 162024a74e86Sdmick if (tsc_gethrtime_enable) 162124a74e86Sdmick tsc_sync_slave(); 1622843e1988Sjohnlev #endif 162324a74e86Sdmick 1624498697c5Sdmick /* 1625498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1626498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1627498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1628498697c5Sdmick * before swtch() overwrites it. 1629498697c5Sdmick */ 1630498697c5Sdmick (void) (*ap_mlsetup)(); 1631498697c5Sdmick 16327c478bd9Sstevel@tonic-gate new_x86_feature = cpuid_pass1(cp); 16337c478bd9Sstevel@tonic-gate 1634843e1988Sjohnlev #ifndef __xpv 16357c478bd9Sstevel@tonic-gate /* 16361d03c31eSjohnlev * Program this cpu's PAT 16377c478bd9Sstevel@tonic-gate */ 16381d03c31eSjohnlev if (x86_feature & X86_PAT) 16391d03c31eSjohnlev pat_sync(); 1640843e1988Sjohnlev #endif 16417c478bd9Sstevel@tonic-gate 1642ae115bc7Smrj /* 1643ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1644ae115bc7Smrj * for the rdtscp instruction. 1645ae115bc7Smrj */ 1646ae115bc7Smrj if (x86_feature & X86_TSCP) 1647ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1648ae115bc7Smrj 16497c478bd9Sstevel@tonic-gate /* 16507c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 16517c478bd9Sstevel@tonic-gate */ 16527c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 16537c478bd9Sstevel@tonic-gate 16547c478bd9Sstevel@tonic-gate /* 16557c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 16567c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 16577c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 16587c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 16597c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 16607c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 16617c478bd9Sstevel@tonic-gate */ 1662ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1663ae115bc7Smrj sti(); 16647c478bd9Sstevel@tonic-gate 16657c478bd9Sstevel@tonic-gate /* 16667c478bd9Sstevel@tonic-gate * Do a sanity check to make sure this new CPU is a sane thing 16677c478bd9Sstevel@tonic-gate * to add to the collection of processors running this system. 16687c478bd9Sstevel@tonic-gate * 16697c478bd9Sstevel@tonic-gate * XXX Clearly this needs to get more sophisticated, if x86 16707c478bd9Sstevel@tonic-gate * systems start to get built out of heterogenous CPUs; as is 16717c478bd9Sstevel@tonic-gate * likely to happen once the number of processors in a configuration 16727c478bd9Sstevel@tonic-gate * gets large enough. 16737c478bd9Sstevel@tonic-gate */ 16747c478bd9Sstevel@tonic-gate if ((x86_feature & new_x86_feature) != x86_feature) { 1675a50a8b93SKuriakose Kuruvilla cmn_err(CE_CONT, fmt, cp->cpu_id, new_x86_feature, 1676a50a8b93SKuriakose Kuruvilla FMT_X86_FEATURE); 16777c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 16787c478bd9Sstevel@tonic-gate } 16797c478bd9Sstevel@tonic-gate 1680f98fbcecSbholler /* 1681f98fbcecSbholler * We do not support cpus with mixed monitor/mwait support if the 1682f98fbcecSbholler * boot cpu supports monitor/mwait. 1683f98fbcecSbholler */ 1684f98fbcecSbholler if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1685f98fbcecSbholler panic("unsupported mixed cpu monitor/mwait support detected"); 1686f98fbcecSbholler 16877c478bd9Sstevel@tonic-gate /* 16887c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 16897c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 1690fb2caebeSRandy Fishel * answer of dying horribly. Provided the boot cpu is ok, 16917c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 16927c478bd9Sstevel@tonic-gate */ 16937c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 16947c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 16957c478bd9Sstevel@tonic-gate 1696*a3114836SGerry Liu /* 1697*a3114836SGerry Liu * We can touch cpu_flags here without acquiring the cpu_lock here 1698*a3114836SGerry Liu * because the cpu_lock is held by the control CPU which is running 1699*a3114836SGerry Liu * mp_start_cpu_common(). 1700*a3114836SGerry Liu * Need to clear CPU_QUIESCED flag before calling any function which 1701*a3114836SGerry Liu * may cause thread context switching, such as kmem_alloc() etc. 1702*a3114836SGerry Liu * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1703*a3114836SGerry Liu * it's set. So the startup thread may have no chance to switch back 1704*a3114836SGerry Liu * again if it's switched away with CPU_QUIESCED set. 1705*a3114836SGerry Liu */ 1706*a3114836SGerry Liu cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1707*a3114836SGerry Liu 17087c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 17097c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 17107c478bd9Sstevel@tonic-gate (void) cpuid_pass4(cp); 17117c478bd9Sstevel@tonic-gate 17122449e17fSsherrym /* 1713*a3114836SGerry Liu * Correct cpu_idstr and cpu_brandstr on target CPU after 1714*a3114836SGerry Liu * cpuid_pass1() is done. 17152449e17fSsherrym */ 1716*a3114836SGerry Liu (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1717*a3114836SGerry Liu (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 17182449e17fSsherrym 1719*a3114836SGerry Liu cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 17207c478bd9Sstevel@tonic-gate 1721e774b42bSBill Holler post_startup_cpu_fixups(); 1722e774b42bSBill Holler 1723*a3114836SGerry Liu cpu_event_init_cpu(cp); 1724*a3114836SGerry Liu 1725aa7b6435Ssethg /* 1726aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1727*a3114836SGerry Liu * later in mp_startup_common may be preempted if the thread owning 1728*a3114836SGerry Liu * those locks is continuously executing on other CPUs (for example, 1729*a3114836SGerry Liu * this CPU must be preemptible to allow other CPUs to pause it during 1730*a3114836SGerry Liu * their startup phases). It's safe to enable preemption here because 1731*a3114836SGerry Liu * the CPU state is pretty-much fully constructed. 1732aa7b6435Ssethg */ 1733aa7b6435Ssethg curthread->t_preempt = 0; 1734aa7b6435Ssethg 1735da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1736da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1737da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1738da43ceabSsethg 1739*a3114836SGerry Liu pghw_physid_create(cp); 17400e751525SEric Saxe /* 1741*a3114836SGerry Liu * Delegate initialization tasks, which need to access the cpu_lock, 1742*a3114836SGerry Liu * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1743*a3114836SGerry Liu * during CPU DR operations. 17440e751525SEric Saxe */ 1745*a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 1746*a3114836SGerry Liu mp_startup_wait(&procset_master, cp->cpu_id); 17470e751525SEric Saxe pg_cmt_cpu_startup(cp); 1748*a3114836SGerry Liu 1749*a3114836SGerry Liu if (boot) { 1750*a3114836SGerry Liu mutex_enter(&cpu_lock); 1751*a3114836SGerry Liu cp->cpu_flags &= ~CPU_OFFLINE; 1752*a3114836SGerry Liu cpu_enable_intr(cp); 1753*a3114836SGerry Liu cpu_add_active(cp); 1754*a3114836SGerry Liu mutex_exit(&cpu_lock); 1755*a3114836SGerry Liu } 17560e751525SEric Saxe 1757afbc4541Ssherrym /* Enable interrupts */ 1758afbc4541Ssherrym (void) spl0(); 17590e751525SEric Saxe 1760*a3114836SGerry Liu /* 1761*a3114836SGerry Liu * Fill out cpu_ucode_info. Update microcode if necessary. 1762*a3114836SGerry Liu */ 1763*a3114836SGerry Liu ucode_check(cp); 1764afbc4541Ssherrym 176520c794b3Sgavinm #ifndef __xpv 176620c794b3Sgavinm { 176720c794b3Sgavinm /* 176820c794b3Sgavinm * Set up the CPU module for this CPU. This can't be done 176920c794b3Sgavinm * before this CPU is made CPU_READY, because we may (in 177020c794b3Sgavinm * heterogeneous systems) need to go load another CPU module. 177120c794b3Sgavinm * The act of attempting to load a module may trigger a 177220c794b3Sgavinm * cross-call, which will ASSERT unless this cpu is CPU_READY. 177320c794b3Sgavinm */ 177420c794b3Sgavinm cmi_hdl_t hdl; 17757aec1d6eScindi 177620c794b3Sgavinm if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1777e4b86885SCheng Sean Ye cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 177820c794b3Sgavinm if (x86_feature & X86_MCA) 177920c794b3Sgavinm cmi_mca_init(hdl); 1780*a3114836SGerry Liu cp->cpu_m.mcpu_cmi_hdl = hdl; 178120c794b3Sgavinm } 178220c794b3Sgavinm } 178320c794b3Sgavinm #endif /* __xpv */ 17847aec1d6eScindi 17857c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1786ae115bc7Smrj kdi_cpu_init(); 17877c478bd9Sstevel@tonic-gate 17887c478bd9Sstevel@tonic-gate /* 17897c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 17907c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 17917c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 17927c478bd9Sstevel@tonic-gate */ 17937c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 17947c478bd9Sstevel@tonic-gate 1795fa96bd91SMichael Corcoran (void) mach_cpu_create_device_node(cp, NULL); 1796fa96bd91SMichael Corcoran 1797*a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1798*a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1799*a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1800*a3114836SGerry Liu cp->cpu_id); 1801*a3114836SGerry Liu 18027c478bd9Sstevel@tonic-gate /* 18037c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 18047c478bd9Sstevel@tonic-gate */ 18057c478bd9Sstevel@tonic-gate thread_exit(); 18067c478bd9Sstevel@tonic-gate panic("mp_startup: cannot return"); 18077c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 18087c478bd9Sstevel@tonic-gate } 18097c478bd9Sstevel@tonic-gate 1810*a3114836SGerry Liu /* 1811*a3114836SGerry Liu * Startup function for 'other' CPUs at boot time (besides boot cpu). 1812*a3114836SGerry Liu */ 1813*a3114836SGerry Liu static void 1814*a3114836SGerry Liu mp_startup_boot(void) 1815*a3114836SGerry Liu { 1816*a3114836SGerry Liu mp_startup_common(B_TRUE); 1817*a3114836SGerry Liu } 1818*a3114836SGerry Liu 1819*a3114836SGerry Liu /* 1820*a3114836SGerry Liu * Startup function for hotplug CPUs at runtime. 1821*a3114836SGerry Liu */ 1822*a3114836SGerry Liu void 1823*a3114836SGerry Liu mp_startup_hotplug(void) 1824*a3114836SGerry Liu { 1825*a3114836SGerry Liu mp_startup_common(B_FALSE); 1826*a3114836SGerry Liu } 18277c478bd9Sstevel@tonic-gate 18287c478bd9Sstevel@tonic-gate /* 18297c478bd9Sstevel@tonic-gate * Start CPU on user request. 18307c478bd9Sstevel@tonic-gate */ 18317c478bd9Sstevel@tonic-gate /* ARGSUSED */ 18327c478bd9Sstevel@tonic-gate int 18337c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 18347c478bd9Sstevel@tonic-gate { 18357c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 18367c478bd9Sstevel@tonic-gate return (0); 18377c478bd9Sstevel@tonic-gate } 18387c478bd9Sstevel@tonic-gate 18397c478bd9Sstevel@tonic-gate /* 18407c478bd9Sstevel@tonic-gate * Stop CPU on user request. 18417c478bd9Sstevel@tonic-gate */ 18427c478bd9Sstevel@tonic-gate int 18437c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 18447c478bd9Sstevel@tonic-gate { 1845d90554ebSdmick extern int cbe_psm_timer_mode; 18467c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1847d90554ebSdmick 1848843e1988Sjohnlev #ifdef __xpv 1849843e1988Sjohnlev /* 1850843e1988Sjohnlev * We can't offline vcpu0. 1851843e1988Sjohnlev */ 1852843e1988Sjohnlev if (cp->cpu_id == 0) 1853843e1988Sjohnlev return (EBUSY); 1854843e1988Sjohnlev #endif 1855843e1988Sjohnlev 1856d90554ebSdmick /* 1857d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1858d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1859d90554ebSdmick */ 1860d90554ebSdmick 1861d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1862843e1988Sjohnlev return (EBUSY); 18637c478bd9Sstevel@tonic-gate 18647c478bd9Sstevel@tonic-gate return (0); 18657c478bd9Sstevel@tonic-gate } 18667c478bd9Sstevel@tonic-gate 18677c478bd9Sstevel@tonic-gate /* 18687c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 18697c478bd9Sstevel@tonic-gate */ 18707c478bd9Sstevel@tonic-gate int 18717c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 18727c478bd9Sstevel@tonic-gate { 18737c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 18747c478bd9Sstevel@tonic-gate return (EBUSY); 18757c478bd9Sstevel@tonic-gate 18767c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 18777c478bd9Sstevel@tonic-gate return (0); 18787c478bd9Sstevel@tonic-gate } 18797c478bd9Sstevel@tonic-gate 18807c478bd9Sstevel@tonic-gate /* 18817c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 18827c478bd9Sstevel@tonic-gate */ 18837c478bd9Sstevel@tonic-gate void 18847c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 18857c478bd9Sstevel@tonic-gate { 18867c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 18877c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 18887c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 18897c478bd9Sstevel@tonic-gate } 18907c478bd9Sstevel@tonic-gate 18917c478bd9Sstevel@tonic-gate void 18927c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 18937aec1d6eScindi { 1894*a3114836SGerry Liu #ifdef __xpv 1895*a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1896*a3114836SGerry Liu #else 1897*a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 189820c794b3Sgavinm 1899*a3114836SGerry Liu if (hdl != NULL) { 1900*a3114836SGerry Liu cmi_hdl_hold(hdl); 1901*a3114836SGerry Liu } else { 1902*a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1903*a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1904*a3114836SGerry Liu } 190520c794b3Sgavinm if (hdl != NULL) { 190620c794b3Sgavinm cmi_faulted_enter(hdl); 190720c794b3Sgavinm cmi_hdl_rele(hdl); 190820c794b3Sgavinm } 190920c794b3Sgavinm #endif 19107aec1d6eScindi } 19117c478bd9Sstevel@tonic-gate 19127c478bd9Sstevel@tonic-gate void 19137c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 19147aec1d6eScindi { 1915*a3114836SGerry Liu #ifdef __xpv 1916*a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1917*a3114836SGerry Liu #else 1918*a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 191920c794b3Sgavinm 1920*a3114836SGerry Liu if (hdl != NULL) { 1921*a3114836SGerry Liu cmi_hdl_hold(hdl); 1922*a3114836SGerry Liu } else { 1923*a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1924*a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1925*a3114836SGerry Liu } 192620c794b3Sgavinm if (hdl != NULL) { 192720c794b3Sgavinm cmi_faulted_exit(hdl); 192820c794b3Sgavinm cmi_hdl_rele(hdl); 192920c794b3Sgavinm } 193020c794b3Sgavinm #endif 19317aec1d6eScindi } 19327c478bd9Sstevel@tonic-gate 19337c478bd9Sstevel@tonic-gate /* 19347c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 19357c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 19367c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 19377c478bd9Sstevel@tonic-gate * organization rather than speed. We could avoid checking x86_feature at every 19387c478bd9Sstevel@tonic-gate * context switch by installing different context ops, depending on the 19397c478bd9Sstevel@tonic-gate * x86_feature flags, at LDT creation time -- one for each combination of fast 19407c478bd9Sstevel@tonic-gate * syscall feature flags. 19417c478bd9Sstevel@tonic-gate */ 19427c478bd9Sstevel@tonic-gate 19437c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 19447c478bd9Sstevel@tonic-gate void 19457c478bd9Sstevel@tonic-gate cpu_fast_syscall_disable(void *arg) 19467c478bd9Sstevel@tonic-gate { 1947ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 19487c478bd9Sstevel@tonic-gate cpu_sep_disable(); 1949ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 19507c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 19517c478bd9Sstevel@tonic-gate } 19527c478bd9Sstevel@tonic-gate 19537c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 19547c478bd9Sstevel@tonic-gate void 19557c478bd9Sstevel@tonic-gate cpu_fast_syscall_enable(void *arg) 19567c478bd9Sstevel@tonic-gate { 1957ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 19587c478bd9Sstevel@tonic-gate cpu_sep_enable(); 1959ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 19607c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 19617c478bd9Sstevel@tonic-gate } 19627c478bd9Sstevel@tonic-gate 19637c478bd9Sstevel@tonic-gate static void 19647c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 19657c478bd9Sstevel@tonic-gate { 19667c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 19677c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 19687c478bd9Sstevel@tonic-gate 19690ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 19707c478bd9Sstevel@tonic-gate } 19717c478bd9Sstevel@tonic-gate 19727c478bd9Sstevel@tonic-gate static void 19737c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 19747c478bd9Sstevel@tonic-gate { 19757c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 19767c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 19777c478bd9Sstevel@tonic-gate 19787c478bd9Sstevel@tonic-gate /* 19797c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 19807c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 19817c478bd9Sstevel@tonic-gate */ 1982ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 19837c478bd9Sstevel@tonic-gate } 19847c478bd9Sstevel@tonic-gate 19857c478bd9Sstevel@tonic-gate static void 19867c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 19877c478bd9Sstevel@tonic-gate { 19887c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 19897c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 19907c478bd9Sstevel@tonic-gate 19910ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 19920ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 19937c478bd9Sstevel@tonic-gate } 19947c478bd9Sstevel@tonic-gate 19957c478bd9Sstevel@tonic-gate static void 19967c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 19977c478bd9Sstevel@tonic-gate { 19987c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 19997c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20007c478bd9Sstevel@tonic-gate 20017c478bd9Sstevel@tonic-gate /* 20027c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 20037c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 20047c478bd9Sstevel@tonic-gate */ 20050ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 20060ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 20077c478bd9Sstevel@tonic-gate } 2008