17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 23fb2f18f8Sesaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/thread.h> 317c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 327c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 337c478bd9Sstevel@tonic-gate #include <sys/param.h> 347c478bd9Sstevel@tonic-gate #include <sys/proc.h> 357c478bd9Sstevel@tonic-gate #include <sys/disp.h> 367c478bd9Sstevel@tonic-gate #include <sys/class.h> 377c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 387c478bd9Sstevel@tonic-gate #include <sys/debug.h> 397c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 407c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 417c478bd9Sstevel@tonic-gate #include <sys/systm.h> 427c478bd9Sstevel@tonic-gate #include <sys/var.h> 437c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 447c478bd9Sstevel@tonic-gate #include <vm/hat.h> 457c478bd9Sstevel@tonic-gate #include <vm/as.h> 467c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 47ae115bc7Smrj #include <vm/seg_kp.h> 487c478bd9Sstevel@tonic-gate #include <sys/segments.h> 497c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 507c478bd9Sstevel@tonic-gate #include <sys/stack.h> 517c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 527c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 537c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 547c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 557c478bd9Sstevel@tonic-gate #include <sys/clock.h> 567c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 57fb2f18f8Sesaxe #include <sys/pg.h> 58fb2f18f8Sesaxe #include <sys/cmt.h> 597c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 607c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 617c478bd9Sstevel@tonic-gate #include <sys/fp.h> 627c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 63ae115bc7Smrj #include <sys/kdi_machimpl.h> 647c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 657c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 66ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 67ae115bc7Smrj #include <sys/mach_mmu.h> 68ae115bc7Smrj #include <sys/sysmacros.h> 69*843e1988Sjohnlev #if defined(__xpv) 70*843e1988Sjohnlev #include <sys/hypervisor.h> 71*843e1988Sjohnlev #endif 727aec1d6eScindi #include <sys/cpu_module.h> 737c478bd9Sstevel@tonic-gate 747c478bd9Sstevel@tonic-gate struct cpu cpus[1]; /* CPU data */ 757c478bd9Sstevel@tonic-gate struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 767c478bd9Sstevel@tonic-gate cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate /* 79ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 807c478bd9Sstevel@tonic-gate */ 817c478bd9Sstevel@tonic-gate int use_mp = 1; 827c478bd9Sstevel@tonic-gate 8341791439Sandrei /* 84ae115bc7Smrj * to be set by a PSM to indicate what cpus 85ae115bc7Smrj * are sitting around on the system. 8641791439Sandrei */ 87ae115bc7Smrj cpuset_t mp_cpus; 887c478bd9Sstevel@tonic-gate 897c478bd9Sstevel@tonic-gate /* 907c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 917c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 927c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 937c478bd9Sstevel@tonic-gate * order to allow cross calls. 947c478bd9Sstevel@tonic-gate */ 95ae115bc7Smrj int flushes_require_xcalls; 96ae115bc7Smrj cpuset_t cpu_ready_set = 1; 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate static void mp_startup(void); 997c478bd9Sstevel@tonic-gate 1007c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1017c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1027c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1037c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate /* 1067c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1077c478bd9Sstevel@tonic-gate */ 1087c478bd9Sstevel@tonic-gate void 1097c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1107c478bd9Sstevel@tonic-gate { 1117c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1127c478bd9Sstevel@tonic-gate char buf[CPU_IDSTRLEN]; 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate /* 1157c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1167c478bd9Sstevel@tonic-gate */ 1177c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1187c478bd9Sstevel@tonic-gate 1195cff7825Smh /* 1205cff7825Smh * Current frequency in Hz. 1215cff7825Smh */ 122cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1235cff7825Smh 12468afbec1Smh /* 12568afbec1Smh * Supported frequencies. 12668afbec1Smh */ 12768afbec1Smh cpu_set_supp_freqs(cp, NULL); 12868afbec1Smh 1297c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1307c478bd9Sstevel@tonic-gate if (fpu_exists) 1317c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate (void) cpuid_getidstr(cp, buf, sizeof (buf)); 1347c478bd9Sstevel@tonic-gate 1357c478bd9Sstevel@tonic-gate cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 1367c478bd9Sstevel@tonic-gate (void) strcpy(cp->cpu_idstr, buf); 1377c478bd9Sstevel@tonic-gate 1387c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 1417c478bd9Sstevel@tonic-gate cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 1427c478bd9Sstevel@tonic-gate (void) strcpy(cp->cpu_brandstr, buf); 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1457c478bd9Sstevel@tonic-gate } 1467c478bd9Sstevel@tonic-gate 1477c478bd9Sstevel@tonic-gate /* 1487c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1497c478bd9Sstevel@tonic-gate */ 1507c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1517c478bd9Sstevel@tonic-gate static void 1527c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1537c478bd9Sstevel@tonic-gate { 1547c478bd9Sstevel@tonic-gate kpreempt_disable(); 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate #if defined(__amd64) 157ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 1587c478bd9Sstevel@tonic-gate 1597c478bd9Sstevel@tonic-gate #if !defined(__lint) 1607c478bd9Sstevel@tonic-gate /* 1617c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1627c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1637c478bd9Sstevel@tonic-gate * here. 1647c478bd9Sstevel@tonic-gate */ 1657c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 1667c478bd9Sstevel@tonic-gate ASSERT(UDS_SEL == U32CS_SEL + 8); 1677c478bd9Sstevel@tonic-gate ASSERT(UCS_SEL == U32CS_SEL + 16); 1687c478bd9Sstevel@tonic-gate #endif 1697c478bd9Sstevel@tonic-gate /* 1707c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1717c478bd9Sstevel@tonic-gate */ 1727c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1737c478bd9Sstevel@tonic-gate 1747c478bd9Sstevel@tonic-gate /* 1757c478bd9Sstevel@tonic-gate * Program the magic registers .. 1767c478bd9Sstevel@tonic-gate */ 177ae115bc7Smrj wrmsr(MSR_AMD_STAR, 178ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 1790ac7d7d8Skucharsk wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 1800ac7d7d8Skucharsk wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 1817c478bd9Sstevel@tonic-gate 1827c478bd9Sstevel@tonic-gate /* 1837c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 1847c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 1857c478bd9Sstevel@tonic-gate */ 1860ac7d7d8Skucharsk wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 1877c478bd9Sstevel@tonic-gate } 1887c478bd9Sstevel@tonic-gate #endif 1897c478bd9Sstevel@tonic-gate 1907c478bd9Sstevel@tonic-gate /* 1917c478bd9Sstevel@tonic-gate * On 32-bit kernels, we use sysenter/sysexit because it's too 1927c478bd9Sstevel@tonic-gate * hard to use syscall/sysret, and it is more portable anyway. 1937c478bd9Sstevel@tonic-gate * 1947c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 1957c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 1967c478bd9Sstevel@tonic-gate */ 197ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 1987c478bd9Sstevel@tonic-gate 1997c478bd9Sstevel@tonic-gate #if !defined(__lint) 2007c478bd9Sstevel@tonic-gate /* 2017c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 2027c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2037c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2047c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2057c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2067c478bd9Sstevel@tonic-gate */ 2077c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 2087c478bd9Sstevel@tonic-gate 2097c478bd9Sstevel@tonic-gate ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 2107c478bd9Sstevel@tonic-gate ASSERT32(UDS_SEL == UCS_SEL + 8); 2117c478bd9Sstevel@tonic-gate 2127c478bd9Sstevel@tonic-gate ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 2137c478bd9Sstevel@tonic-gate ASSERT64(UDS_SEL == U32CS_SEL + 8); 2147c478bd9Sstevel@tonic-gate #endif 2157c478bd9Sstevel@tonic-gate 2167c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2177c478bd9Sstevel@tonic-gate 2187c478bd9Sstevel@tonic-gate /* 2197c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2207c478bd9Sstevel@tonic-gate * via a context handler. 2217c478bd9Sstevel@tonic-gate */ 222ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 2230ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 2247c478bd9Sstevel@tonic-gate } 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate kpreempt_enable(); 2277c478bd9Sstevel@tonic-gate } 2287c478bd9Sstevel@tonic-gate 2297c478bd9Sstevel@tonic-gate /* 2307c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2317c478bd9Sstevel@tonic-gate * 2327c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2337c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 2347c478bd9Sstevel@tonic-gate */ 235ae115bc7Smrj struct cpu * 2367c478bd9Sstevel@tonic-gate mp_startup_init(int cpun) 2377c478bd9Sstevel@tonic-gate { 2387c478bd9Sstevel@tonic-gate struct cpu *cp; 2397c478bd9Sstevel@tonic-gate kthread_id_t tp; 2407c478bd9Sstevel@tonic-gate caddr_t sp; 2417c478bd9Sstevel@tonic-gate proc_t *procp; 242*843e1988Sjohnlev #if !defined(__xpv) 2435b8a6efeSbholler extern int idle_cpu_prefer_mwait; 244*843e1988Sjohnlev #endif 2457c478bd9Sstevel@tonic-gate extern void idle(); 2467c478bd9Sstevel@tonic-gate 2477c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 2487c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 2497c478bd9Sstevel@tonic-gate #endif 2507c478bd9Sstevel@tonic-gate 2517c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 2527c478bd9Sstevel@tonic-gate 253ae115bc7Smrj cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 254*843e1988Sjohnlev #if !defined(__xpv) 2555b8a6efeSbholler if ((x86_feature & X86_MWAIT) && idle_cpu_prefer_mwait) 2565b8a6efeSbholler cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(CPU); 257*843e1988Sjohnlev #endif 258f98fbcecSbholler 2597c478bd9Sstevel@tonic-gate procp = curthread->t_procp; 2607c478bd9Sstevel@tonic-gate 2617c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 2627c478bd9Sstevel@tonic-gate /* 2637c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 2647c478bd9Sstevel@tonic-gate */ 2657c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 2667c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 2677c478bd9Sstevel@tonic-gate 268affbd3ccSkchow cpu_vm_data_init(cp); 269affbd3ccSkchow 2707c478bd9Sstevel@tonic-gate /* 2717c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 2727c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 2737c478bd9Sstevel@tonic-gate * when the CPU starts running. 2747c478bd9Sstevel@tonic-gate */ 2757c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 2767c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 2777c478bd9Sstevel@tonic-gate 2787c478bd9Sstevel@tonic-gate /* 2797c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 2807c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 2817c478bd9Sstevel@tonic-gate * 2827c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 2837c478bd9Sstevel@tonic-gate * thread_create(). 2847c478bd9Sstevel@tonic-gate */ 2857c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 2867c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 2877c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 2887c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 2897c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 2907c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 2917c478bd9Sstevel@tonic-gate 2927c478bd9Sstevel@tonic-gate /* 2937c478bd9Sstevel@tonic-gate * Setup thread to start in mp_startup. 2947c478bd9Sstevel@tonic-gate */ 2957c478bd9Sstevel@tonic-gate sp = tp->t_stk; 2967c478bd9Sstevel@tonic-gate tp->t_pc = (uintptr_t)mp_startup; 2977c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 298ae115bc7Smrj #if defined(__amd64) 299ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 300ae115bc7Smrj #endif 3017c478bd9Sstevel@tonic-gate 3027c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3037c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3047c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3057c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3067c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3077c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3087c478bd9Sstevel@tonic-gate 309da43ceabSsethg /* 310da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 311da43ceabSsethg * operations in mp_startup from causing the spl of the cpu to drop 312da43ceabSsethg * to 0 (allowing device interrupts before we're ready) in resume(). 313da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 314da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 315da43ceabSsethg * an assertion in mp_startup() -- before cpu_base_spl is set to its 316da43ceabSsethg * proper value. 317da43ceabSsethg */ 318da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 319da43ceabSsethg 3207c478bd9Sstevel@tonic-gate /* 3217c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3227c478bd9Sstevel@tonic-gate */ 3237c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3247c478bd9Sstevel@tonic-gate 3257c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3267c478bd9Sstevel@tonic-gate 3277c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3287c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3297c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3307c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3317c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3327c478bd9Sstevel@tonic-gate 333394b433dSesaxe /* 334fb2f18f8Sesaxe * Bootstrap the CPU's PG data 335394b433dSesaxe */ 336fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 337394b433dSesaxe 3387c478bd9Sstevel@tonic-gate /* 339ae115bc7Smrj * Perform CPC initialization on the new CPU. 3407c478bd9Sstevel@tonic-gate */ 3417c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate /* 3447c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 3457c478bd9Sstevel@tonic-gate * for each CPU. 3467c478bd9Sstevel@tonic-gate */ 3477c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 3487c478bd9Sstevel@tonic-gate 3497c478bd9Sstevel@tonic-gate /* 350ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 3517c478bd9Sstevel@tonic-gate */ 352ae115bc7Smrj #if !defined(__lint) 353ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 354ae115bc7Smrj #endif 355ae115bc7Smrj cp->cpu_m.mcpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 356ae115bc7Smrj bcopy(CPU->cpu_m.mcpu_gdt, cp->cpu_m.mcpu_gdt, 357ae115bc7Smrj (sizeof (*cp->cpu_m.mcpu_gdt) * NGDT)); 3587c478bd9Sstevel@tonic-gate 359ae115bc7Smrj #if defined(__i386) 3607c478bd9Sstevel@tonic-gate /* 3617c478bd9Sstevel@tonic-gate * setup kernel %gs. 3627c478bd9Sstevel@tonic-gate */ 3637c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 3647c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 365ae115bc7Smrj #endif 3667c478bd9Sstevel@tonic-gate 3677c478bd9Sstevel@tonic-gate /* 3687c478bd9Sstevel@tonic-gate * If we have more than one node, each cpu gets a copy of IDT 3697c478bd9Sstevel@tonic-gate * local to its node. If this is a Pentium box, we use cpu 0's 3707c478bd9Sstevel@tonic-gate * IDT. cpu 0's IDT has been made read-only to workaround the 3717c478bd9Sstevel@tonic-gate * cmpxchgl register bug 3727c478bd9Sstevel@tonic-gate */ 3737c478bd9Sstevel@tonic-gate if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 374ae115bc7Smrj struct machcpu *mcpu = &cp->cpu_m; 375ae115bc7Smrj 376ae115bc7Smrj mcpu->mcpu_idt = kmem_alloc(sizeof (idt0), KM_SLEEP); 377ae115bc7Smrj bcopy(idt0, mcpu->mcpu_idt, sizeof (idt0)); 378ae115bc7Smrj } else { 379ae115bc7Smrj cp->cpu_m.mcpu_idt = CPU->cpu_m.mcpu_idt; 3807c478bd9Sstevel@tonic-gate } 3817c478bd9Sstevel@tonic-gate 3827c478bd9Sstevel@tonic-gate /* 383ae115bc7Smrj * Get interrupt priority data from cpu 0. 3847c478bd9Sstevel@tonic-gate */ 3857c478bd9Sstevel@tonic-gate cp->cpu_pri_data = CPU->cpu_pri_data; 3867c478bd9Sstevel@tonic-gate 3877c478bd9Sstevel@tonic-gate /* 388ae115bc7Smrj * alloc space for cpuid info 3897c478bd9Sstevel@tonic-gate */ 390ae115bc7Smrj cpuid_alloc_space(cp); 3917c478bd9Sstevel@tonic-gate 392*843e1988Sjohnlev #if !defined(__xpv) 3932449e17fSsherrym /* 3942449e17fSsherrym * alloc space for ucode_info 3952449e17fSsherrym */ 3962449e17fSsherrym ucode_alloc_space(cp); 397*843e1988Sjohnlev #endif 3982449e17fSsherrym 399ae115bc7Smrj hat_cpu_online(cp); 4007c478bd9Sstevel@tonic-gate 4017c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4027c478bd9Sstevel@tonic-gate /* 403ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4047c478bd9Sstevel@tonic-gate */ 4057c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4067c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4077c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4087c478bd9Sstevel@tonic-gate #endif 4097c478bd9Sstevel@tonic-gate /* 4107c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4117c478bd9Sstevel@tonic-gate */ 4127c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 4137c478bd9Sstevel@tonic-gate /* 4147c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4157c478bd9Sstevel@tonic-gate */ 416100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 4177c478bd9Sstevel@tonic-gate /* 4187c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 4197c478bd9Sstevel@tonic-gate * after mp_startup(). 4207c478bd9Sstevel@tonic-gate */ 4217c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 4227c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 423ae115bc7Smrj 424ae115bc7Smrj return (cp); 425ae115bc7Smrj } 426ae115bc7Smrj 427ae115bc7Smrj /* 428ae115bc7Smrj * Undo what was done in mp_startup_init 429ae115bc7Smrj */ 430ae115bc7Smrj static void 431ae115bc7Smrj mp_startup_fini(struct cpu *cp, int error) 432ae115bc7Smrj { 433ae115bc7Smrj mutex_enter(&cpu_lock); 434ae115bc7Smrj 435ae115bc7Smrj /* 436ae115bc7Smrj * Remove the CPU from the list of available CPUs. 437ae115bc7Smrj */ 438ae115bc7Smrj cpu_del_unit(cp->cpu_id); 439ae115bc7Smrj 440ae115bc7Smrj if (error == ETIMEDOUT) { 441ae115bc7Smrj /* 442ae115bc7Smrj * The cpu was started, but never *seemed* to run any 443ae115bc7Smrj * code in the kernel; it's probably off spinning in its 444ae115bc7Smrj * own private world, though with potential references to 445ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 446ae115bc7Smrj * 447ae115bc7Smrj * Worse still, it may actually wake up some time later, 448ae115bc7Smrj * so rather than guess what it might or might not do, we 449ae115bc7Smrj * leave the fundamental data structures intact. 450ae115bc7Smrj */ 451ae115bc7Smrj cp->cpu_flags = 0; 452ae115bc7Smrj mutex_exit(&cpu_lock); 453ae115bc7Smrj return; 454ae115bc7Smrj } 455ae115bc7Smrj 456ae115bc7Smrj /* 457ae115bc7Smrj * At this point, the only threads bound to this CPU should 458ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 459ae115bc7Smrj * and it's interrupt threads. Clean these up. 460ae115bc7Smrj */ 461ae115bc7Smrj cpu_destroy_bound_threads(cp); 462ae115bc7Smrj cp->cpu_idle_thread = NULL; 463ae115bc7Smrj 464ae115bc7Smrj /* 465ae115bc7Smrj * Free the interrupt stack. 466ae115bc7Smrj */ 467ae115bc7Smrj segkp_release(segkp, 468ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 469ae115bc7Smrj 470ae115bc7Smrj mutex_exit(&cpu_lock); 471ae115bc7Smrj 472ae115bc7Smrj #ifdef TRAPTRACE 473ae115bc7Smrj /* 474ae115bc7Smrj * Discard the trap trace buffer 475ae115bc7Smrj */ 476ae115bc7Smrj { 477ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 478ae115bc7Smrj 479ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 480ae115bc7Smrj ttc->ttc_first = NULL; 481ae115bc7Smrj } 482ae115bc7Smrj #endif 483ae115bc7Smrj 484ae115bc7Smrj hat_cpu_offline(cp); 485ae115bc7Smrj 486ae115bc7Smrj cpuid_free_space(cp); 487ae115bc7Smrj 488*843e1988Sjohnlev #if !defined(__xpv) 4892449e17fSsherrym ucode_free_space(cp); 490*843e1988Sjohnlev #endif 4912449e17fSsherrym 492ae115bc7Smrj if (cp->cpu_m.mcpu_idt != CPU->cpu_m.mcpu_idt) 493ae115bc7Smrj kmem_free(cp->cpu_m.mcpu_idt, sizeof (idt0)); 494ae115bc7Smrj cp->cpu_m.mcpu_idt = NULL; 495ae115bc7Smrj 496ae115bc7Smrj kmem_free(cp->cpu_m.mcpu_gdt, PAGESIZE); 497ae115bc7Smrj cp->cpu_m.mcpu_gdt = NULL; 498ae115bc7Smrj 499ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 500ae115bc7Smrj 501ae115bc7Smrj kcpc_hw_fini(cp); 502ae115bc7Smrj 503ae115bc7Smrj cp->cpu_dispthread = NULL; 504ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 505ae115bc7Smrj 506ae115bc7Smrj cpu_vm_data_destroy(cp); 507ae115bc7Smrj 508ae115bc7Smrj mutex_enter(&cpu_lock); 509ae115bc7Smrj disp_cpu_fini(cp); 510ae115bc7Smrj mutex_exit(&cpu_lock); 511ae115bc7Smrj 512*843e1988Sjohnlev #if !defined(__xpv) 5135b8a6efeSbholler if (cp->cpu_m.mcpu_mwait != NULL) 5145b8a6efeSbholler cpuid_mwait_free(cp); 515*843e1988Sjohnlev #endif 516ae115bc7Smrj kmem_free(cp, sizeof (*cp)); 5177c478bd9Sstevel@tonic-gate } 5187c478bd9Sstevel@tonic-gate 5197c478bd9Sstevel@tonic-gate /* 5207c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 5217c478bd9Sstevel@tonic-gate * 5227c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 5237c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 5247c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 5257c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 5267c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 5277c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 5287c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 5297c478bd9Sstevel@tonic-gate * system. 5307c478bd9Sstevel@tonic-gate * 531ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 532ef50d8c0Sesaxe * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 533ef50d8c0Sesaxe * to acknowledging their readiness to the master, so this routine will 534ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 535ef50d8c0Sesaxe * global data safe. 536ef50d8c0Sesaxe * 5372201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 5382201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 5397c478bd9Sstevel@tonic-gate */ 5407c478bd9Sstevel@tonic-gate 541ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 542ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 543ae115bc7Smrj #endif 544ae115bc7Smrj 5457c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 5467c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 5477c478bd9Sstevel@tonic-gate #endif 5487c478bd9Sstevel@tonic-gate 5497c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 5507c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 5517c478bd9Sstevel@tonic-gate #endif 5527c478bd9Sstevel@tonic-gate 553ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 554ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 555ae115bc7Smrj #endif 556ae115bc7Smrj 5577c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 5587c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 5597c478bd9Sstevel@tonic-gate #endif 5607c478bd9Sstevel@tonic-gate 561ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 562ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 563ae115bc7Smrj #endif 564ae115bc7Smrj 5657c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 5667c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 5677c478bd9Sstevel@tonic-gate #endif 5687c478bd9Sstevel@tonic-gate 5697c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 5707c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 5717c478bd9Sstevel@tonic-gate #endif 5727c478bd9Sstevel@tonic-gate 5737c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 5747c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 5757c478bd9Sstevel@tonic-gate #endif 5767c478bd9Sstevel@tonic-gate 5777c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 5787c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 5797c478bd9Sstevel@tonic-gate #endif 5807c478bd9Sstevel@tonic-gate 5812201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 5822201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 5832201b277Skucharsk #endif 5847c478bd9Sstevel@tonic-gate 585ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 586ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 587ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 588ef50d8c0Sesaxe #endif 589ef50d8c0Sesaxe 590ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 591ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 592ee88d2b9Skchow #endif 593ee88d2b9Skchow 594ae115bc7Smrj static void 595ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 596ae115bc7Smrj { 597ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 598ae115bc7Smrj cp->cpu_id, erratum); 599ae115bc7Smrj } 600ae115bc7Smrj 601ae115bc7Smrj static void 602ae115bc7Smrj workaround_applied(uint_t erratum) 603ae115bc7Smrj { 604ae115bc7Smrj if (erratum > 1000000) 605ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 606ae115bc7Smrj erratum); 607ae115bc7Smrj else 608ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 609ae115bc7Smrj erratum); 610ae115bc7Smrj } 611ae115bc7Smrj 612ae115bc7Smrj static void 613ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 614ae115bc7Smrj { 615ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 616ae115bc7Smrj cp->cpu_id, rw, msr, error); 617ae115bc7Smrj } 6187c478bd9Sstevel@tonic-gate 619*843e1988Sjohnlev #if defined(__xpv) 620*843e1988Sjohnlev 621*843e1988Sjohnlev /* 622*843e1988Sjohnlev * On dom0, we can determine the number of physical cpus on the machine. 623*843e1988Sjohnlev * This number is important when figuring out what workarounds are 624*843e1988Sjohnlev * appropriate, so compute it now. 625*843e1988Sjohnlev */ 626*843e1988Sjohnlev static uint_t 627*843e1988Sjohnlev xen_get_nphyscpus(void) 628*843e1988Sjohnlev { 629*843e1988Sjohnlev static uint_t nphyscpus = 0; 630*843e1988Sjohnlev 631*843e1988Sjohnlev ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 632*843e1988Sjohnlev 633*843e1988Sjohnlev if (nphyscpus == 0) { 634*843e1988Sjohnlev xen_sysctl_t op; 635*843e1988Sjohnlev xen_sysctl_physinfo_t *pi = &op.u.physinfo; 636*843e1988Sjohnlev 637*843e1988Sjohnlev op.cmd = XEN_SYSCTL_physinfo; 638*843e1988Sjohnlev op.interface_version = XEN_SYSCTL_INTERFACE_VERSION; 639*843e1988Sjohnlev if (HYPERVISOR_sysctl(&op) == 0) 640*843e1988Sjohnlev nphyscpus = pi->threads_per_core * 641*843e1988Sjohnlev pi->cores_per_socket * pi->sockets_per_node * 642*843e1988Sjohnlev pi->nr_nodes; 643*843e1988Sjohnlev } 644*843e1988Sjohnlev return (nphyscpus); 645*843e1988Sjohnlev } 646*843e1988Sjohnlev #endif 647*843e1988Sjohnlev 6487c478bd9Sstevel@tonic-gate uint_t 6497c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 6507c478bd9Sstevel@tonic-gate { 6517c478bd9Sstevel@tonic-gate uint_t missing = 0; 6527c478bd9Sstevel@tonic-gate 6537c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 6547c478bd9Sstevel@tonic-gate 6557c478bd9Sstevel@tonic-gate /*LINTED*/ 6567c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 6577c478bd9Sstevel@tonic-gate /* 6587c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 6597c478bd9Sstevel@tonic-gate */ 6607c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 6617c478bd9Sstevel@tonic-gate /* 6627c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 6637c478bd9Sstevel@tonic-gate */ 664ae115bc7Smrj opteron_erratum_88++; 6657c478bd9Sstevel@tonic-gate #else 666ae115bc7Smrj workaround_warning(cpu, 88); 6677c478bd9Sstevel@tonic-gate missing++; 6687c478bd9Sstevel@tonic-gate #endif 6697c478bd9Sstevel@tonic-gate } 6707c478bd9Sstevel@tonic-gate 6717c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 6727c478bd9Sstevel@tonic-gate /* 6737c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 6747c478bd9Sstevel@tonic-gate */ 6757c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 6767c478bd9Sstevel@tonic-gate /* 6777c478bd9Sstevel@tonic-gate * fix is in trap.c 6787c478bd9Sstevel@tonic-gate */ 6797c478bd9Sstevel@tonic-gate opteron_erratum_91++; 6807c478bd9Sstevel@tonic-gate #else 681ae115bc7Smrj workaround_warning(cpu, 91); 6827c478bd9Sstevel@tonic-gate missing++; 6837c478bd9Sstevel@tonic-gate #endif 6847c478bd9Sstevel@tonic-gate } 6857c478bd9Sstevel@tonic-gate 6867c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 6877c478bd9Sstevel@tonic-gate /* 6887c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 6897c478bd9Sstevel@tonic-gate */ 6907c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 6917c478bd9Sstevel@tonic-gate /* 6927c478bd9Sstevel@tonic-gate * fix is in trap.c 6937c478bd9Sstevel@tonic-gate */ 6947c478bd9Sstevel@tonic-gate opteron_erratum_93++; 6957c478bd9Sstevel@tonic-gate #else 696ae115bc7Smrj workaround_warning(cpu, 93); 6977c478bd9Sstevel@tonic-gate missing++; 6987c478bd9Sstevel@tonic-gate #endif 6997c478bd9Sstevel@tonic-gate } 7007c478bd9Sstevel@tonic-gate 7017c478bd9Sstevel@tonic-gate /*LINTED*/ 7027c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 7037c478bd9Sstevel@tonic-gate /* 7047c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 7057c478bd9Sstevel@tonic-gate */ 7067c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 7077c478bd9Sstevel@tonic-gate #if defined(_LP64) 7087c478bd9Sstevel@tonic-gate /* 7097c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 7107c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 7117c478bd9Sstevel@tonic-gate * range mod 4G. 7127c478bd9Sstevel@tonic-gate */ 7137c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 7147c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 7157c478bd9Sstevel@tonic-gate 7167c478bd9Sstevel@tonic-gate /*LINTED*/ 7177c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 718ae115bc7Smrj opteron_erratum_95++; 7197c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 7207c478bd9Sstevel@tonic-gate #else 721ae115bc7Smrj workaround_warning(cpu, 95); 7227c478bd9Sstevel@tonic-gate missing++; 723ae115bc7Smrj #endif 7247c478bd9Sstevel@tonic-gate } 7257c478bd9Sstevel@tonic-gate 7267c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 7277c478bd9Sstevel@tonic-gate /* 7287c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 7297c478bd9Sstevel@tonic-gate */ 7307c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 7317c478bd9Sstevel@tonic-gate /* 7327c478bd9Sstevel@tonic-gate * fix is in trap.c 7337c478bd9Sstevel@tonic-gate */ 7347c478bd9Sstevel@tonic-gate opteron_erratum_100++; 7357c478bd9Sstevel@tonic-gate #else 736ae115bc7Smrj workaround_warning(cpu, 100); 7377c478bd9Sstevel@tonic-gate missing++; 7387c478bd9Sstevel@tonic-gate #endif 7397c478bd9Sstevel@tonic-gate } 7407c478bd9Sstevel@tonic-gate 7417c478bd9Sstevel@tonic-gate /*LINTED*/ 7427c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 7437c478bd9Sstevel@tonic-gate /* 7447c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 7457c478bd9Sstevel@tonic-gate * Some Processors 7467c478bd9Sstevel@tonic-gate */ 7477c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 7487c478bd9Sstevel@tonic-gate /* 7497c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 7507c478bd9Sstevel@tonic-gate * those processors) 7517c478bd9Sstevel@tonic-gate */ 7527c478bd9Sstevel@tonic-gate #else 753ae115bc7Smrj workaround_warning(cpu, 108); 7547c478bd9Sstevel@tonic-gate missing++; 7557c478bd9Sstevel@tonic-gate #endif 7567c478bd9Sstevel@tonic-gate } 7577c478bd9Sstevel@tonic-gate 7587c478bd9Sstevel@tonic-gate /*LINTED*/ 759ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 7607c478bd9Sstevel@tonic-gate /* 7617c478bd9Sstevel@tonic-gate * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 7627c478bd9Sstevel@tonic-gate */ 7637c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 764ae115bc7Smrj /* 765ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 766ae115bc7Smrj */ 767ae115bc7Smrj uint64_t value; 768ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 769ae115bc7Smrj int err; 770ae115bc7Smrj 771ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 772ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 773ae115bc7Smrj workaround_warning(cpu, 109); 774ae115bc7Smrj missing++; 775ae115bc7Smrj } 776ae115bc7Smrj if (value == 0) 7777c478bd9Sstevel@tonic-gate opteron_erratum_109++; 7787c478bd9Sstevel@tonic-gate #else 779ae115bc7Smrj workaround_warning(cpu, 109); 7807c478bd9Sstevel@tonic-gate missing++; 7817c478bd9Sstevel@tonic-gate #endif 782ae115bc7Smrj /*CONSTANTCONDITION*/ 783ae115bc7Smrj } while (0); 784ae115bc7Smrj 7857c478bd9Sstevel@tonic-gate /*LINTED*/ 7867c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 7877c478bd9Sstevel@tonic-gate /* 7887c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 7897c478bd9Sstevel@tonic-gate * Processor Hang 7907c478bd9Sstevel@tonic-gate */ 7917c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 792ae115bc7Smrj #if defined(_LP64) 7937c478bd9Sstevel@tonic-gate /* 7947c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 7957c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 7967c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 7977c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 7987c478bd9Sstevel@tonic-gate */ 799ae115bc7Smrj if (opteron_erratum_121) 800ae115bc7Smrj opteron_erratum_121++; 801ae115bc7Smrj else { 802ae115bc7Smrj if (hole_start) { 803ae115bc7Smrj hole_start -= PAGESIZE; 804ae115bc7Smrj } else { 805ae115bc7Smrj /* 806ae115bc7Smrj * hole_start not yet initialized by 807ae115bc7Smrj * mmu_init. Initialize hole_start 808ae115bc7Smrj * with value to be subtracted. 809ae115bc7Smrj */ 810ae115bc7Smrj hole_start = PAGESIZE; 8117c478bd9Sstevel@tonic-gate } 812ae115bc7Smrj opteron_erratum_121++; 8137c478bd9Sstevel@tonic-gate } 814ae115bc7Smrj #endif /* _LP64 */ 8157c478bd9Sstevel@tonic-gate #else 816ae115bc7Smrj workaround_warning(cpu, 121); 8177c478bd9Sstevel@tonic-gate missing++; 8187c478bd9Sstevel@tonic-gate #endif 8197c478bd9Sstevel@tonic-gate } 8207c478bd9Sstevel@tonic-gate 8217c478bd9Sstevel@tonic-gate /*LINTED*/ 822ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 8237c478bd9Sstevel@tonic-gate /* 824ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 8257c478bd9Sstevel@tonic-gate * Multiprocessor Systems 8267c478bd9Sstevel@tonic-gate */ 8277c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 828ae115bc7Smrj uint64_t value; 829ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 830ae115bc7Smrj int error; 831ae115bc7Smrj 8327c478bd9Sstevel@tonic-gate /* 8337c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 8347c478bd9Sstevel@tonic-gate * or multi-processor). 8357c478bd9Sstevel@tonic-gate */ 836*843e1988Sjohnlev #if defined(__xpv) 837*843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 838*843e1988Sjohnlev break; 839*843e1988Sjohnlev if (!opteron_erratum_122 && xen_get_nphyscpus() == 1) 840*843e1988Sjohnlev break; 841*843e1988Sjohnlev #else 842ae115bc7Smrj if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 843ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 844ae115bc7Smrj break; 845*843e1988Sjohnlev #endif 846ae115bc7Smrj /* disable TLB Flush Filter */ 847ae115bc7Smrj 848ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 849ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 850ae115bc7Smrj workaround_warning(cpu, 122); 851ae115bc7Smrj missing++; 852ae115bc7Smrj } else { 853ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 854ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 855ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 856ae115bc7Smrj workaround_warning(cpu, 122); 857ae115bc7Smrj missing++; 858ae115bc7Smrj } 8597c478bd9Sstevel@tonic-gate } 860ae115bc7Smrj opteron_erratum_122++; 8617c478bd9Sstevel@tonic-gate #else 862ae115bc7Smrj workaround_warning(cpu, 122); 8637c478bd9Sstevel@tonic-gate missing++; 8647c478bd9Sstevel@tonic-gate #endif 865ae115bc7Smrj /*CONSTANTCONDITION*/ 866ae115bc7Smrj } while (0); 867403c216aSkchow 8687c478bd9Sstevel@tonic-gate /*LINTED*/ 869ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 8707c478bd9Sstevel@tonic-gate /* 8717c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 8727c478bd9Sstevel@tonic-gate * Dual Core Processors 8737c478bd9Sstevel@tonic-gate */ 874ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 875ae115bc7Smrj uint64_t value; 876ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 877ae115bc7Smrj int err; 878ae115bc7Smrj 8797c478bd9Sstevel@tonic-gate /* 8807c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 8817c478bd9Sstevel@tonic-gate */ 882ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 883ae115bc7Smrj break; 884*843e1988Sjohnlev #if defined(__xpv) 885*843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 886*843e1988Sjohnlev break; 887*843e1988Sjohnlev #endif 888ae115bc7Smrj /* 889ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 890ae115bc7Smrj */ 891ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 892ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 893ae115bc7Smrj workaround_warning(cpu, 123); 894ae115bc7Smrj missing++; 8957c478bd9Sstevel@tonic-gate } 896ae115bc7Smrj if (value == 0) 897ae115bc7Smrj opteron_erratum_123++; 898ae115bc7Smrj #else 899ae115bc7Smrj workaround_warning(cpu, 123); 900ae115bc7Smrj missing++; 901ae115bc7Smrj 902403c216aSkchow #endif 903ae115bc7Smrj /*CONSTANTCONDITION*/ 904ae115bc7Smrj } while (0); 9052201b277Skucharsk 9062201b277Skucharsk /*LINTED*/ 907ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 9082201b277Skucharsk /* 9092201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 9102201b277Skucharsk * Waiting for a Probe Response 9112201b277Skucharsk */ 912ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 913ae115bc7Smrj uint64_t nbcfg; 914ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 915ae115bc7Smrj const uint64_t wabits = 916ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 917ae115bc7Smrj int error; 918ae115bc7Smrj 9192201b277Skucharsk /* 9202201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 9212201b277Skucharsk */ 922ae115bc7Smrj if (opteron_erratum_131) 923ae115bc7Smrj break; 924*843e1988Sjohnlev #if defined(__xpv) 925*843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 926*843e1988Sjohnlev break; 927*843e1988Sjohnlev if (xen_get_nphyscpus() < 4) 928*843e1988Sjohnlev break; 929*843e1988Sjohnlev #else 930ae115bc7Smrj if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 931ae115bc7Smrj break; 932*843e1988Sjohnlev #endif 933ae115bc7Smrj /* 934ae115bc7Smrj * Print a warning if neither of the workarounds for 935ae115bc7Smrj * erratum 131 is present. 936ae115bc7Smrj */ 937ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 938ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 939ae115bc7Smrj workaround_warning(cpu, 131); 940ae115bc7Smrj missing++; 941ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 942ae115bc7Smrj opteron_erratum_131++; 943ae115bc7Smrj } else { 944ae115bc7Smrj /* cannot have both workarounds set */ 945ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 9462201b277Skucharsk } 947ae115bc7Smrj #else 948ae115bc7Smrj workaround_warning(cpu, 131); 949ae115bc7Smrj missing++; 9502201b277Skucharsk #endif 951ae115bc7Smrj /*CONSTANTCONDITION*/ 952ae115bc7Smrj } while (0); 953ef50d8c0Sesaxe 954ef50d8c0Sesaxe /* 955ae115bc7Smrj * This isn't really an erratum, but for convenience the 956ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 957ef50d8c0Sesaxe */ 958ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 959ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 960ef50d8c0Sesaxe /* 961ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 962ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 963ef50d8c0Sesaxe */ 964ef50d8c0Sesaxe if (opteron_workaround_6336786) { 965ef50d8c0Sesaxe opteron_workaround_6336786++; 966*843e1988Sjohnlev #if defined(__xpv) 967*843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 968*843e1988Sjohnlev xen_get_nphyscpus() > 1) || 969*843e1988Sjohnlev opteron_workaround_6336786_UP) { 970*843e1988Sjohnlev /* 971*843e1988Sjohnlev * XXPV Hmm. We can't walk the set of lgrps on 972*843e1988Sjohnlev * the hypervisor; so just complain and drive 973*843e1988Sjohnlev * on. This probably needs to be fixed in 974*843e1988Sjohnlev * the hypervisor itself. 975*843e1988Sjohnlev */ 976*843e1988Sjohnlev opteron_workaround_6336786++; 977*843e1988Sjohnlev workaround_warning(cpu, 6336786); 978*843e1988Sjohnlev #else /* __xpv */ 979ef50d8c0Sesaxe } else if ((lgrp_plat_node_cnt * 980ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) > 1) || 981ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 982ae115bc7Smrj int node; 983ae115bc7Smrj uint8_t data; 984ae115bc7Smrj 985ef50d8c0Sesaxe for (node = 0; node < lgrp_plat_node_cnt; node++) { 986ef50d8c0Sesaxe /* 987ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 988ef50d8c0Sesaxe * Northbridge device is the node id + 24. 989ef50d8c0Sesaxe */ 990ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 991ef50d8c0Sesaxe data &= 0xFC; 992ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 993ef50d8c0Sesaxe } 994ef50d8c0Sesaxe opteron_workaround_6336786++; 995*843e1988Sjohnlev #endif /* __xpv */ 996ef50d8c0Sesaxe } 997ae115bc7Smrj #else 998ae115bc7Smrj workaround_warning(cpu, 6336786); 999ae115bc7Smrj missing++; 1000ef50d8c0Sesaxe #endif 1001ae115bc7Smrj } 1002ee88d2b9Skchow 1003ee88d2b9Skchow /*LINTED*/ 1004ee88d2b9Skchow /* 1005ee88d2b9Skchow * Mutex primitives don't work as expected. 1006ee88d2b9Skchow */ 1007ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1008ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1009ee88d2b9Skchow /* 1010ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1011ee88d2b9Skchow * MSR_BU_CFG set, then not applicable. The workaround 1012ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1013ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1014ee88d2b9Skchow * possible subsequent read-modify-write ops. 1015ee88d2b9Skchow * 1016ee88d2b9Skchow * It is too early in boot to call the patch routine so 1017ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1018ee88d2b9Skchow */ 1019ee88d2b9Skchow if (opteron_workaround_6323525) { 1020ee88d2b9Skchow opteron_workaround_6323525++; 1021*843e1988Sjohnlev #if defined(__xpv) 1022*843e1988Sjohnlev } else if (x86_feature & X86_SSE2) { 1023*843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1024*843e1988Sjohnlev /* 1025*843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1026*843e1988Sjohnlev * operations are supported? 1027*843e1988Sjohnlev */ 1028*843e1988Sjohnlev if (xen_get_nphyscpus() > 1) 1029*843e1988Sjohnlev opteron_workaround_6323525++; 1030*843e1988Sjohnlev } else { 1031*843e1988Sjohnlev /* 1032*843e1988Sjohnlev * We have no way to tell how many physical 1033*843e1988Sjohnlev * cpus there are, or even if this processor 1034*843e1988Sjohnlev * has the problem, so enable the workaround 1035*843e1988Sjohnlev * unconditionally (at some performance cost). 1036*843e1988Sjohnlev */ 1037*843e1988Sjohnlev opteron_workaround_6323525++; 1038*843e1988Sjohnlev } 1039*843e1988Sjohnlev #else /* __xpv */ 1040ee88d2b9Skchow } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 1041ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 1042ee88d2b9Skchow if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 1043ee88d2b9Skchow opteron_workaround_6323525++; 1044*843e1988Sjohnlev #endif /* __xpv */ 1045ee88d2b9Skchow } 1046ae115bc7Smrj #else 1047ae115bc7Smrj workaround_warning(cpu, 6323525); 1048ae115bc7Smrj missing++; 1049ee88d2b9Skchow #endif 1050ae115bc7Smrj } 1051ae115bc7Smrj 1052*843e1988Sjohnlev #ifdef __xpv 1053*843e1988Sjohnlev return (0); 1054*843e1988Sjohnlev #else 10557c478bd9Sstevel@tonic-gate return (missing); 1056*843e1988Sjohnlev #endif 10577c478bd9Sstevel@tonic-gate } 10587c478bd9Sstevel@tonic-gate 10597c478bd9Sstevel@tonic-gate void 10607c478bd9Sstevel@tonic-gate workaround_errata_end() 10617c478bd9Sstevel@tonic-gate { 1062ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1063ae115bc7Smrj if (opteron_erratum_88) 1064ae115bc7Smrj workaround_applied(88); 1065ae115bc7Smrj #endif 1066ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1067ae115bc7Smrj if (opteron_erratum_91) 1068ae115bc7Smrj workaround_applied(91); 1069ae115bc7Smrj #endif 1070ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1071ae115bc7Smrj if (opteron_erratum_93) 1072ae115bc7Smrj workaround_applied(93); 1073ae115bc7Smrj #endif 1074ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1075ae115bc7Smrj if (opteron_erratum_95) 1076ae115bc7Smrj workaround_applied(95); 1077ae115bc7Smrj #endif 1078ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1079ae115bc7Smrj if (opteron_erratum_100) 1080ae115bc7Smrj workaround_applied(100); 1081ae115bc7Smrj #endif 1082ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1083ae115bc7Smrj if (opteron_erratum_108) 1084ae115bc7Smrj workaround_applied(108); 1085ae115bc7Smrj #endif 10867c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 10877c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 10882201b277Skucharsk cmn_err(CE_WARN, 10892201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 10902201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 10912201b277Skucharsk " system's BIOS to a version\ncontaining this" 10922201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 10932201b277Skucharsk " system\noperation may occur.\n"); 10947c478bd9Sstevel@tonic-gate } 1095ae115bc7Smrj #endif 1096ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1097ae115bc7Smrj if (opteron_erratum_121) 1098ae115bc7Smrj workaround_applied(121); 1099ae115bc7Smrj #endif 1100ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1101ae115bc7Smrj if (opteron_erratum_122) 1102ae115bc7Smrj workaround_applied(122); 1103ae115bc7Smrj #endif 11047c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 11057c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 11062201b277Skucharsk cmn_err(CE_WARN, 11072201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 11082201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 11092201b277Skucharsk " system's BIOS to a version\ncontaining this" 11102201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 11112201b277Skucharsk " system\noperation may occur.\n"); 11127c478bd9Sstevel@tonic-gate } 1113ae115bc7Smrj #endif 11142201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 11152201b277Skucharsk if (opteron_erratum_131) { 11162201b277Skucharsk cmn_err(CE_WARN, 11172201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 11182201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 11192201b277Skucharsk " system's BIOS to a version\ncontaining this" 11202201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 11212201b277Skucharsk " system\noperation may occur.\n"); 11222201b277Skucharsk } 1123ae115bc7Smrj #endif 1124ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1125ae115bc7Smrj if (opteron_workaround_6336786) 1126ae115bc7Smrj workaround_applied(6336786); 1127ae115bc7Smrj #endif 1128ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1129ae115bc7Smrj if (opteron_workaround_6323525) 1130ae115bc7Smrj workaround_applied(6323525); 1131ae115bc7Smrj #endif 11327c478bd9Sstevel@tonic-gate } 11337c478bd9Sstevel@tonic-gate 1134ae115bc7Smrj static cpuset_t procset; 1135ae115bc7Smrj 1136ae115bc7Smrj /* 1137ae115bc7Smrj * Start a single cpu, assuming that the kernel context is available 1138ae115bc7Smrj * to successfully start another cpu. 1139ae115bc7Smrj * 1140ae115bc7Smrj * (For example, real mode code is mapped into the right place 1141ae115bc7Smrj * in memory and is ready to be run.) 1142ae115bc7Smrj */ 1143ae115bc7Smrj int 1144ae115bc7Smrj start_cpu(processorid_t who) 1145ae115bc7Smrj { 1146ae115bc7Smrj void *ctx; 1147ae115bc7Smrj cpu_t *cp; 1148ae115bc7Smrj int delays; 1149ae115bc7Smrj int error = 0; 1150ae115bc7Smrj 1151ae115bc7Smrj ASSERT(who != 0); 1152ae115bc7Smrj 1153ae115bc7Smrj /* 1154ae115bc7Smrj * Check if there's at least a Mbyte of kmem available 1155ae115bc7Smrj * before attempting to start the cpu. 1156ae115bc7Smrj */ 1157ae115bc7Smrj if (kmem_avail() < 1024 * 1024) { 1158ae115bc7Smrj /* 1159ae115bc7Smrj * Kick off a reap in case that helps us with 1160ae115bc7Smrj * later attempts .. 1161ae115bc7Smrj */ 1162ae115bc7Smrj kmem_reap(); 1163ae115bc7Smrj return (ENOMEM); 1164ae115bc7Smrj } 1165ae115bc7Smrj 1166ae115bc7Smrj cp = mp_startup_init(who); 1167ae115bc7Smrj if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1168ae115bc7Smrj (error = mach_cpu_start(cp, ctx)) != 0) { 1169ae115bc7Smrj 1170ae115bc7Smrj /* 1171ae115bc7Smrj * Something went wrong before we even started it 1172ae115bc7Smrj */ 1173ae115bc7Smrj if (ctx) 1174ae115bc7Smrj cmn_err(CE_WARN, 1175ae115bc7Smrj "cpu%d: failed to start error %d", 1176ae115bc7Smrj cp->cpu_id, error); 1177ae115bc7Smrj else 1178ae115bc7Smrj cmn_err(CE_WARN, 1179ae115bc7Smrj "cpu%d: failed to allocate context", cp->cpu_id); 1180ae115bc7Smrj 1181ae115bc7Smrj if (ctx) 1182ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1183ae115bc7Smrj else 1184ae115bc7Smrj error = EAGAIN; /* hmm. */ 1185ae115bc7Smrj mp_startup_fini(cp, error); 1186ae115bc7Smrj return (error); 1187ae115bc7Smrj } 1188ae115bc7Smrj 1189ae115bc7Smrj for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1190ae115bc7Smrj if (delays == 500) { 1191ae115bc7Smrj /* 1192ae115bc7Smrj * After five seconds, things are probably looking 1193ae115bc7Smrj * a bit bleak - explain the hang. 1194ae115bc7Smrj */ 1195ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1196ae115bc7Smrj "but not running in the kernel yet", who); 1197ae115bc7Smrj } else if (delays > 2000) { 1198ae115bc7Smrj /* 1199ae115bc7Smrj * We waited at least 20 seconds, bail .. 1200ae115bc7Smrj */ 1201ae115bc7Smrj error = ETIMEDOUT; 1202ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: timed out", who); 1203ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1204ae115bc7Smrj mp_startup_fini(cp, error); 1205ae115bc7Smrj return (error); 1206ae115bc7Smrj } 1207ae115bc7Smrj 1208ae115bc7Smrj /* 1209ae115bc7Smrj * wait at least 10ms, then check again.. 1210ae115bc7Smrj */ 1211ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1212ae115bc7Smrj } 1213ae115bc7Smrj 1214ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1215ae115bc7Smrj 1216*843e1988Sjohnlev #ifndef __xpv 1217ae115bc7Smrj if (tsc_gethrtime_enable) 1218ae115bc7Smrj tsc_sync_master(who); 1219*843e1988Sjohnlev #endif 1220ae115bc7Smrj 1221ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1222ae115bc7Smrj /* 1223ae115bc7Smrj * DTrace CPU initialization expects cpu_lock to be held. 1224ae115bc7Smrj */ 1225ae115bc7Smrj mutex_enter(&cpu_lock); 1226ae115bc7Smrj (*dtrace_cpu_init)(who); 1227ae115bc7Smrj mutex_exit(&cpu_lock); 1228ae115bc7Smrj } 1229ae115bc7Smrj 1230ae115bc7Smrj while (!CPU_IN_SET(cpu_ready_set, who)) 1231ae115bc7Smrj delay(1); 1232ae115bc7Smrj 1233ae115bc7Smrj return (0); 1234ae115bc7Smrj } 12357c478bd9Sstevel@tonic-gate 123641791439Sandrei 12377c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 12387c478bd9Sstevel@tonic-gate void 12397c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 12407c478bd9Sstevel@tonic-gate { 1241ae115bc7Smrj uint_t who; 1242ae115bc7Smrj uint_t skipped = 0; 1243ae115bc7Smrj uint_t bootcpuid = 0; 12447c478bd9Sstevel@tonic-gate 12457c478bd9Sstevel@tonic-gate /* 12467c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 12477c478bd9Sstevel@tonic-gate */ 12487c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 12497c478bd9Sstevel@tonic-gate 12507c478bd9Sstevel@tonic-gate /* 12517c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 12527c478bd9Sstevel@tonic-gate */ 12537c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 12547c478bd9Sstevel@tonic-gate 1255ae115bc7Smrj /* 1256ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1257ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1258ae115bc7Smrj * precisely the same reason. 1259ae115bc7Smrj */ 1260ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1261ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1262ae115bc7Smrj 12637c478bd9Sstevel@tonic-gate /* 12647c478bd9Sstevel@tonic-gate * if only 1 cpu or not using MP, skip the rest of this 12657c478bd9Sstevel@tonic-gate */ 1266ae115bc7Smrj if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 12677c478bd9Sstevel@tonic-gate if (use_mp == 0) 12687c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 12697c478bd9Sstevel@tonic-gate goto done; 12707c478bd9Sstevel@tonic-gate } 12717c478bd9Sstevel@tonic-gate 12727c478bd9Sstevel@tonic-gate /* 12737c478bd9Sstevel@tonic-gate * perform such initialization as is needed 12747c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 12757c478bd9Sstevel@tonic-gate */ 12767c478bd9Sstevel@tonic-gate cpu_pause_init(); 12777c478bd9Sstevel@tonic-gate 12787c478bd9Sstevel@tonic-gate xc_init(); /* initialize processor crosscalls */ 12797c478bd9Sstevel@tonic-gate 1280ae115bc7Smrj if (mach_cpucontext_init() != 0) 12817c478bd9Sstevel@tonic-gate goto done; 12827c478bd9Sstevel@tonic-gate 12837c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 12847c478bd9Sstevel@tonic-gate 12855205ae23Snf /* 12865205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 12875205ae23Snf * do their TSC syncs with the same CPU. 12885205ae23Snf */ 12897c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 12907c478bd9Sstevel@tonic-gate 12917c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 12925205ae23Snf 129341791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 129441791439Sandrei continue; 1295ae115bc7Smrj ASSERT(who != bootcpuid); 129641791439Sandrei if (ncpus >= max_ncpus) { 129741791439Sandrei skipped = who; 12987c478bd9Sstevel@tonic-gate continue; 129941791439Sandrei } 1300ae115bc7Smrj if (start_cpu(who) != 0) 1301ae115bc7Smrj CPUSET_DEL(mp_cpus, who); 13027c478bd9Sstevel@tonic-gate } 13037c478bd9Sstevel@tonic-gate 1304*843e1988Sjohnlev #if !defined(__xpv) 13052449e17fSsherrym /* Free the space allocated to hold the microcode file */ 13062449e17fSsherrym ucode_free(); 1307*843e1988Sjohnlev #endif 13082449e17fSsherrym 13097c478bd9Sstevel@tonic-gate affinity_clear(); 13107c478bd9Sstevel@tonic-gate 131141791439Sandrei if (skipped) { 131241791439Sandrei cmn_err(CE_NOTE, 1313ae115bc7Smrj "System detected %d cpus, but " 1314ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 131541791439Sandrei skipped + 1, ncpus); 131641791439Sandrei cmn_err(CE_NOTE, 131741791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 131841791439Sandrei "See eeprom(1M)."); 131941791439Sandrei } 132041791439Sandrei 13217c478bd9Sstevel@tonic-gate done: 13227c478bd9Sstevel@tonic-gate workaround_errata_end(); 1323ae115bc7Smrj mach_cpucontext_fini(); 13243ad553a7Sgavinm 13253ad553a7Sgavinm cmi_post_mpstartup(); 13267c478bd9Sstevel@tonic-gate } 13277c478bd9Sstevel@tonic-gate 13287c478bd9Sstevel@tonic-gate /* 13297c478bd9Sstevel@tonic-gate * Dummy functions - no i86pc platforms support dynamic cpu allocation. 13307c478bd9Sstevel@tonic-gate */ 13317c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 13327c478bd9Sstevel@tonic-gate int 13337c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 13347c478bd9Sstevel@tonic-gate { 13357c478bd9Sstevel@tonic-gate return (ENOTSUP); /* not supported */ 13367c478bd9Sstevel@tonic-gate } 13377c478bd9Sstevel@tonic-gate 13387c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 13397c478bd9Sstevel@tonic-gate int 13407c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 13417c478bd9Sstevel@tonic-gate { 13427c478bd9Sstevel@tonic-gate return (ENOTSUP); /* not supported */ 13437c478bd9Sstevel@tonic-gate } 13447c478bd9Sstevel@tonic-gate 13457c478bd9Sstevel@tonic-gate /* 13467c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1347498697c5Sdmick * Called from real_mode_start. 1348b4b46911Skchow * 1349b4b46911Skchow * WARNING: until CPU_READY is set, mp_startup and routines called by 1350b4b46911Skchow * mp_startup should not call routines (e.g. kmem_free) that could call 1351b4b46911Skchow * hat_unload which requires CPU_READY to be set. 13527c478bd9Sstevel@tonic-gate */ 13537c478bd9Sstevel@tonic-gate void 13547c478bd9Sstevel@tonic-gate mp_startup(void) 13557c478bd9Sstevel@tonic-gate { 13567c478bd9Sstevel@tonic-gate struct cpu *cp = CPU; 13577c478bd9Sstevel@tonic-gate uint_t new_x86_feature; 13587c478bd9Sstevel@tonic-gate 135924a74e86Sdmick /* 136024a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 136124a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 136224a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 136324a74e86Sdmick * interrupts, cmn_err, etc. 136424a74e86Sdmick */ 136524a74e86Sdmick 136624a74e86Sdmick /* Let cpu0 continue into tsc_sync_master() */ 136724a74e86Sdmick CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 136824a74e86Sdmick 1369*843e1988Sjohnlev #ifndef __xpv 137024a74e86Sdmick if (tsc_gethrtime_enable) 137124a74e86Sdmick tsc_sync_slave(); 1372*843e1988Sjohnlev #endif 137324a74e86Sdmick 1374498697c5Sdmick /* 1375498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1376498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1377498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1378498697c5Sdmick * before swtch() overwrites it. 1379498697c5Sdmick */ 1380498697c5Sdmick 1381498697c5Sdmick (void) (*ap_mlsetup)(); 1382498697c5Sdmick 13837c478bd9Sstevel@tonic-gate new_x86_feature = cpuid_pass1(cp); 13847c478bd9Sstevel@tonic-gate 1385*843e1988Sjohnlev #ifndef __xpv 13867c478bd9Sstevel@tonic-gate /* 13877c478bd9Sstevel@tonic-gate * We need to Sync MTRR with cpu0's MTRR. We have to do 13887c478bd9Sstevel@tonic-gate * this with interrupts disabled. 13897c478bd9Sstevel@tonic-gate */ 13907c478bd9Sstevel@tonic-gate if (x86_feature & X86_MTRR) 13917c478bd9Sstevel@tonic-gate mtrr_sync(); 1392*843e1988Sjohnlev #endif 13937c478bd9Sstevel@tonic-gate 1394ae115bc7Smrj /* 1395ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1396ae115bc7Smrj * for the rdtscp instruction. 1397ae115bc7Smrj */ 1398ae115bc7Smrj if (x86_feature & X86_TSCP) 1399ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1400ae115bc7Smrj 14017c478bd9Sstevel@tonic-gate /* 14027c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 14037c478bd9Sstevel@tonic-gate */ 14047c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 14057c478bd9Sstevel@tonic-gate 14067c478bd9Sstevel@tonic-gate /* 14077c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 14087c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 14097c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 14107c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 14117c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 14127c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 14137c478bd9Sstevel@tonic-gate */ 1414ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1415ae115bc7Smrj sti(); 14167c478bd9Sstevel@tonic-gate 14177c478bd9Sstevel@tonic-gate /* 14187c478bd9Sstevel@tonic-gate * Do a sanity check to make sure this new CPU is a sane thing 14197c478bd9Sstevel@tonic-gate * to add to the collection of processors running this system. 14207c478bd9Sstevel@tonic-gate * 14217c478bd9Sstevel@tonic-gate * XXX Clearly this needs to get more sophisticated, if x86 14227c478bd9Sstevel@tonic-gate * systems start to get built out of heterogenous CPUs; as is 14237c478bd9Sstevel@tonic-gate * likely to happen once the number of processors in a configuration 14247c478bd9Sstevel@tonic-gate * gets large enough. 14257c478bd9Sstevel@tonic-gate */ 14267c478bd9Sstevel@tonic-gate if ((x86_feature & new_x86_feature) != x86_feature) { 14277c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?cpu%d: %b\n", 14287c478bd9Sstevel@tonic-gate cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 14297c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 14307c478bd9Sstevel@tonic-gate } 14317c478bd9Sstevel@tonic-gate 1432f98fbcecSbholler /* 1433f98fbcecSbholler * We do not support cpus with mixed monitor/mwait support if the 1434f98fbcecSbholler * boot cpu supports monitor/mwait. 1435f98fbcecSbholler */ 1436f98fbcecSbholler if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1437f98fbcecSbholler panic("unsupported mixed cpu monitor/mwait support detected"); 1438f98fbcecSbholler 14397c478bd9Sstevel@tonic-gate /* 14407c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 14417c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 14427c478bd9Sstevel@tonic-gate * answer of dieing horribly. Provided the boot cpu is ok, 14437c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 14447c478bd9Sstevel@tonic-gate */ 14457c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 14467c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 14477c478bd9Sstevel@tonic-gate 14487c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 14497c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 14507c478bd9Sstevel@tonic-gate (void) cpuid_pass4(cp); 14517c478bd9Sstevel@tonic-gate 14527c478bd9Sstevel@tonic-gate init_cpu_info(cp); 14537c478bd9Sstevel@tonic-gate 14547c478bd9Sstevel@tonic-gate mutex_enter(&cpu_lock); 14557c478bd9Sstevel@tonic-gate /* 1456fb2f18f8Sesaxe * Processor group initialization for this CPU is dependent on the 1457fb2f18f8Sesaxe * cpuid probing, which must be done in the context of the current 1458fb2f18f8Sesaxe * CPU. 14597c478bd9Sstevel@tonic-gate */ 1460fb2f18f8Sesaxe pghw_physid_create(cp); 1461fb2f18f8Sesaxe pg_cpu_init(cp); 1462fb2f18f8Sesaxe pg_cmt_cpu_startup(cp); 14637c478bd9Sstevel@tonic-gate 14647c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 14657c478bd9Sstevel@tonic-gate cpu_add_active(cp); 14665205ae23Snf 14675205ae23Snf if (dtrace_cpu_init != NULL) { 14685205ae23Snf (*dtrace_cpu_init)(cp->cpu_id); 14695205ae23Snf } 14705205ae23Snf 1471*843e1988Sjohnlev #if !defined(__xpv) 14722449e17fSsherrym /* 14732449e17fSsherrym * Fill out cpu_ucode_info. Update microcode if necessary. 14742449e17fSsherrym */ 14752449e17fSsherrym ucode_check(cp); 1476*843e1988Sjohnlev #endif 14772449e17fSsherrym 14787c478bd9Sstevel@tonic-gate mutex_exit(&cpu_lock); 14797c478bd9Sstevel@tonic-gate 1480aa7b6435Ssethg /* 1481aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1482aa7b6435Ssethg * later in mp_startup may be preempted if the thread owning those 1483aa7b6435Ssethg * locks is continously executing on other CPUs (for example, this 1484aa7b6435Ssethg * CPU must be preemptible to allow other CPUs to pause it during their 1485aa7b6435Ssethg * startup phases). It's safe to enable preemption here because the 1486aa7b6435Ssethg * CPU state is pretty-much fully constructed. 1487aa7b6435Ssethg */ 1488aa7b6435Ssethg curthread->t_preempt = 0; 1489aa7b6435Ssethg 1490b4b46911Skchow add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1491b4b46911Skchow 1492da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1493da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1494da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1495da43ceabSsethg 14967c478bd9Sstevel@tonic-gate (void) spl0(); /* enable interrupts */ 14977c478bd9Sstevel@tonic-gate 14987aec1d6eScindi /* 14997aec1d6eScindi * Set up the CPU module for this CPU. This can't be done before 15007aec1d6eScindi * this CPU is made CPU_READY, because we may (in heterogeneous systems) 15017aec1d6eScindi * need to go load another CPU module. The act of attempting to load 15027aec1d6eScindi * a module may trigger a cross-call, which will ASSERT unless this 15037aec1d6eScindi * cpu is CPU_READY. 15047aec1d6eScindi */ 15057aec1d6eScindi cmi_init(); 15067aec1d6eScindi 15077aec1d6eScindi if (x86_feature & X86_MCA) 15087aec1d6eScindi cmi_mca_init(); 15097aec1d6eScindi 15107c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1511ae115bc7Smrj kdi_cpu_init(); 15127c478bd9Sstevel@tonic-gate 15137c478bd9Sstevel@tonic-gate /* 15147c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 15157c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 15167c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 15177c478bd9Sstevel@tonic-gate */ 15187c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 15197c478bd9Sstevel@tonic-gate 15207c478bd9Sstevel@tonic-gate /* 15217c478bd9Sstevel@tonic-gate * Because mp_startup() gets fired off after init() starts, we 15227c478bd9Sstevel@tonic-gate * can't use the '?' trick to do 'boot -v' printing - so we 15237c478bd9Sstevel@tonic-gate * always direct the 'cpu .. online' messages to the log. 15247c478bd9Sstevel@tonic-gate */ 15257c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 15267c478bd9Sstevel@tonic-gate cp->cpu_id); 15277c478bd9Sstevel@tonic-gate 15287c478bd9Sstevel@tonic-gate /* 15297c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 15307c478bd9Sstevel@tonic-gate */ 15317c478bd9Sstevel@tonic-gate thread_exit(); 15327c478bd9Sstevel@tonic-gate panic("mp_startup: cannot return"); 15337c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 15347c478bd9Sstevel@tonic-gate } 15357c478bd9Sstevel@tonic-gate 15367c478bd9Sstevel@tonic-gate 15377c478bd9Sstevel@tonic-gate /* 15387c478bd9Sstevel@tonic-gate * Start CPU on user request. 15397c478bd9Sstevel@tonic-gate */ 15407c478bd9Sstevel@tonic-gate /* ARGSUSED */ 15417c478bd9Sstevel@tonic-gate int 15427c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 15437c478bd9Sstevel@tonic-gate { 15447c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 15457c478bd9Sstevel@tonic-gate return (0); 15467c478bd9Sstevel@tonic-gate } 15477c478bd9Sstevel@tonic-gate 15487c478bd9Sstevel@tonic-gate /* 15497c478bd9Sstevel@tonic-gate * Stop CPU on user request. 15507c478bd9Sstevel@tonic-gate */ 15517c478bd9Sstevel@tonic-gate /* ARGSUSED */ 15527c478bd9Sstevel@tonic-gate int 15537c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 15547c478bd9Sstevel@tonic-gate { 1555d90554ebSdmick extern int cbe_psm_timer_mode; 15567c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1557d90554ebSdmick 1558*843e1988Sjohnlev #ifdef __xpv 1559*843e1988Sjohnlev /* 1560*843e1988Sjohnlev * We can't offline vcpu0. 1561*843e1988Sjohnlev */ 1562*843e1988Sjohnlev if (cp->cpu_id == 0) 1563*843e1988Sjohnlev return (EBUSY); 1564*843e1988Sjohnlev #endif 1565*843e1988Sjohnlev 1566d90554ebSdmick /* 1567d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1568d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1569d90554ebSdmick */ 1570d90554ebSdmick 1571d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1572*843e1988Sjohnlev return (EBUSY); 15737c478bd9Sstevel@tonic-gate 15747c478bd9Sstevel@tonic-gate return (0); 15757c478bd9Sstevel@tonic-gate } 15767c478bd9Sstevel@tonic-gate 15777c478bd9Sstevel@tonic-gate /* 15787c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 15797c478bd9Sstevel@tonic-gate */ 15807c478bd9Sstevel@tonic-gate int 15817c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 15827c478bd9Sstevel@tonic-gate { 15837c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 15847c478bd9Sstevel@tonic-gate return (EBUSY); 15857c478bd9Sstevel@tonic-gate 15867c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 15877c478bd9Sstevel@tonic-gate return (0); 15887c478bd9Sstevel@tonic-gate } 15897c478bd9Sstevel@tonic-gate 15907c478bd9Sstevel@tonic-gate /* 15917c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 15927c478bd9Sstevel@tonic-gate */ 15937c478bd9Sstevel@tonic-gate void 15947c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 15957c478bd9Sstevel@tonic-gate { 15967c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 15977c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 15987c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 15997c478bd9Sstevel@tonic-gate } 16007c478bd9Sstevel@tonic-gate 16017c478bd9Sstevel@tonic-gate 16027c478bd9Sstevel@tonic-gate 16037c478bd9Sstevel@tonic-gate void 16047c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 16057aec1d6eScindi { 16067aec1d6eScindi cmi_faulted_enter(cp); 16077aec1d6eScindi } 16087c478bd9Sstevel@tonic-gate 16097c478bd9Sstevel@tonic-gate void 16107c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 16117aec1d6eScindi { 16127aec1d6eScindi cmi_faulted_exit(cp); 16137aec1d6eScindi } 16147c478bd9Sstevel@tonic-gate 16157c478bd9Sstevel@tonic-gate /* 16167c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 16177c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 16187c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 16197c478bd9Sstevel@tonic-gate * organization rather than speed. We could avoid checking x86_feature at every 16207c478bd9Sstevel@tonic-gate * context switch by installing different context ops, depending on the 16217c478bd9Sstevel@tonic-gate * x86_feature flags, at LDT creation time -- one for each combination of fast 16227c478bd9Sstevel@tonic-gate * syscall feature flags. 16237c478bd9Sstevel@tonic-gate */ 16247c478bd9Sstevel@tonic-gate 16257c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 16267c478bd9Sstevel@tonic-gate void 16277c478bd9Sstevel@tonic-gate cpu_fast_syscall_disable(void *arg) 16287c478bd9Sstevel@tonic-gate { 1629ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 16307c478bd9Sstevel@tonic-gate cpu_sep_disable(); 1631ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 16327c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 16337c478bd9Sstevel@tonic-gate } 16347c478bd9Sstevel@tonic-gate 16357c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 16367c478bd9Sstevel@tonic-gate void 16377c478bd9Sstevel@tonic-gate cpu_fast_syscall_enable(void *arg) 16387c478bd9Sstevel@tonic-gate { 1639ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 16407c478bd9Sstevel@tonic-gate cpu_sep_enable(); 1641ae115bc7Smrj if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 16427c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 16437c478bd9Sstevel@tonic-gate } 16447c478bd9Sstevel@tonic-gate 16457c478bd9Sstevel@tonic-gate static void 16467c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 16477c478bd9Sstevel@tonic-gate { 16487c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 16497c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 16507c478bd9Sstevel@tonic-gate 16510ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 16527c478bd9Sstevel@tonic-gate } 16537c478bd9Sstevel@tonic-gate 16547c478bd9Sstevel@tonic-gate static void 16557c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 16567c478bd9Sstevel@tonic-gate { 16577c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_SEP); 16587c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 16597c478bd9Sstevel@tonic-gate 16607c478bd9Sstevel@tonic-gate /* 16617c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 16627c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 16637c478bd9Sstevel@tonic-gate */ 1664ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 16657c478bd9Sstevel@tonic-gate } 16667c478bd9Sstevel@tonic-gate 16677c478bd9Sstevel@tonic-gate static void 16687c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 16697c478bd9Sstevel@tonic-gate { 16707c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 16717c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 16727c478bd9Sstevel@tonic-gate 16730ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 16740ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 16757c478bd9Sstevel@tonic-gate } 16767c478bd9Sstevel@tonic-gate 16777c478bd9Sstevel@tonic-gate static void 16787c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 16797c478bd9Sstevel@tonic-gate { 16807c478bd9Sstevel@tonic-gate ASSERT(x86_feature & X86_ASYSC); 16817c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 16827c478bd9Sstevel@tonic-gate 16837c478bd9Sstevel@tonic-gate /* 16847c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 16857c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 16867c478bd9Sstevel@tonic-gate */ 16870ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 16880ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 16897c478bd9Sstevel@tonic-gate } 1690