17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 23*7417cfdeSKuriakose Kuruvilla * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 25a3114836SGerry Liu /* 26a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 27a3114836SGerry Liu * All rights reserved. 28a3114836SGerry Liu */ 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #include <sys/types.h> 317c478bd9Sstevel@tonic-gate #include <sys/thread.h> 327c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 33a3114836SGerry Liu #include <sys/cpu.h> 347c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 357c478bd9Sstevel@tonic-gate #include <sys/param.h> 367c478bd9Sstevel@tonic-gate #include <sys/proc.h> 377c478bd9Sstevel@tonic-gate #include <sys/disp.h> 387c478bd9Sstevel@tonic-gate #include <sys/class.h> 397c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 407c478bd9Sstevel@tonic-gate #include <sys/debug.h> 41a3114836SGerry Liu #include <sys/note.h> 427c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 437c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 447c478bd9Sstevel@tonic-gate #include <sys/systm.h> 457c478bd9Sstevel@tonic-gate #include <sys/var.h> 467c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 477c478bd9Sstevel@tonic-gate #include <vm/hat.h> 487c478bd9Sstevel@tonic-gate #include <vm/as.h> 497c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 50ae115bc7Smrj #include <vm/seg_kp.h> 517c478bd9Sstevel@tonic-gate #include <sys/segments.h> 527c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 537c478bd9Sstevel@tonic-gate #include <sys/stack.h> 547c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 557c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 567c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 577c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 587c478bd9Sstevel@tonic-gate #include <sys/clock.h> 597c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 60fb2f18f8Sesaxe #include <sys/pg.h> 61fb2f18f8Sesaxe #include <sys/cmt.h> 627c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 637c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 647c478bd9Sstevel@tonic-gate #include <sys/fp.h> 657c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 66ae115bc7Smrj #include <sys/kdi_machimpl.h> 677c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 68a3114836SGerry Liu #include <vm/vm_dep.h> 697c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 70ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 71ae115bc7Smrj #include <sys/mach_mmu.h> 72ae115bc7Smrj #include <sys/sysmacros.h> 73843e1988Sjohnlev #if defined(__xpv) 74843e1988Sjohnlev #include <sys/hypervisor.h> 75843e1988Sjohnlev #endif 767aec1d6eScindi #include <sys/cpu_module.h> 777c478bd9Sstevel@tonic-gate 787c478bd9Sstevel@tonic-gate struct cpu cpus[1]; /* CPU data */ 797c478bd9Sstevel@tonic-gate struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 80a3114836SGerry Liu struct cpu *cpu_free_list; /* list for released CPUs */ 817c478bd9Sstevel@tonic-gate cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 827c478bd9Sstevel@tonic-gate 83a3114836SGerry Liu #define cpu_next_free cpu_prev 84a3114836SGerry Liu 857c478bd9Sstevel@tonic-gate /* 86ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 877c478bd9Sstevel@tonic-gate */ 887c478bd9Sstevel@tonic-gate int use_mp = 1; 897c478bd9Sstevel@tonic-gate 9041791439Sandrei /* 91ae115bc7Smrj * to be set by a PSM to indicate what cpus 92ae115bc7Smrj * are sitting around on the system. 9341791439Sandrei */ 94ae115bc7Smrj cpuset_t mp_cpus; 957c478bd9Sstevel@tonic-gate 967c478bd9Sstevel@tonic-gate /* 977c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 987c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 997c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 1007c478bd9Sstevel@tonic-gate * order to allow cross calls. 1017c478bd9Sstevel@tonic-gate */ 102ae115bc7Smrj int flushes_require_xcalls; 103a563a037Sbholler 104a563a037Sbholler cpuset_t cpu_ready_set; /* initialized in startup() */ 1057c478bd9Sstevel@tonic-gate 106a3114836SGerry Liu static void mp_startup_boot(void); 107a3114836SGerry Liu static void mp_startup_hotplug(void); 1087c478bd9Sstevel@tonic-gate 1097c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1107c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1117c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1127c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate /* 1157c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1167c478bd9Sstevel@tonic-gate */ 1177c478bd9Sstevel@tonic-gate void 1187c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1197c478bd9Sstevel@tonic-gate { 1207c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1217c478bd9Sstevel@tonic-gate 1227c478bd9Sstevel@tonic-gate /* 1237c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1247c478bd9Sstevel@tonic-gate */ 1257c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1267c478bd9Sstevel@tonic-gate 1275cff7825Smh /* 1285cff7825Smh * Current frequency in Hz. 1295cff7825Smh */ 130cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1315cff7825Smh 13237d22dc0SAnup Pemmaiah /* 13337d22dc0SAnup Pemmaiah * Supported frequencies. 13437d22dc0SAnup Pemmaiah */ 13537d22dc0SAnup Pemmaiah if (cp->cpu_supp_freqs == NULL) { 13637d22dc0SAnup Pemmaiah cpu_set_supp_freqs(cp, NULL); 13737d22dc0SAnup Pemmaiah } 13837d22dc0SAnup Pemmaiah 1397c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1407c478bd9Sstevel@tonic-gate if (fpu_exists) 1417c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1427c478bd9Sstevel@tonic-gate 143a3114836SGerry Liu cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 144a3114836SGerry Liu cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 1457c478bd9Sstevel@tonic-gate 146a3114836SGerry Liu /* 147a3114836SGerry Liu * If called for the BSP, cp is equal to current CPU. 148a3114836SGerry Liu * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 149a3114836SGerry Liu * of current CPU as default values for cpu_idstr and cpu_brandstr. 150a3114836SGerry Liu * They will be corrected in mp_startup_common() after cpuid_pass1() 151a3114836SGerry Liu * has been invoked on target CPU. 152a3114836SGerry Liu */ 153a3114836SGerry Liu (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 154a3114836SGerry Liu (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 1557c478bd9Sstevel@tonic-gate } 1567c478bd9Sstevel@tonic-gate 1577c478bd9Sstevel@tonic-gate /* 1587c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1597c478bd9Sstevel@tonic-gate */ 1607c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1612df1fe9cSrandyf void 1627c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1637c478bd9Sstevel@tonic-gate { 1647c478bd9Sstevel@tonic-gate kpreempt_disable(); 1657c478bd9Sstevel@tonic-gate 1667c478bd9Sstevel@tonic-gate #if defined(__amd64) 167*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 168*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) { 1697c478bd9Sstevel@tonic-gate 1707c478bd9Sstevel@tonic-gate #if !defined(__lint) 1717c478bd9Sstevel@tonic-gate /* 1727c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1737c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1747c478bd9Sstevel@tonic-gate * here. 1757c478bd9Sstevel@tonic-gate */ 1767c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 1777c478bd9Sstevel@tonic-gate ASSERT(UDS_SEL == U32CS_SEL + 8); 1787c478bd9Sstevel@tonic-gate ASSERT(UCS_SEL == U32CS_SEL + 16); 1797c478bd9Sstevel@tonic-gate #endif 1807c478bd9Sstevel@tonic-gate /* 1817c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1827c478bd9Sstevel@tonic-gate */ 1837c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate /* 1867c478bd9Sstevel@tonic-gate * Program the magic registers .. 1877c478bd9Sstevel@tonic-gate */ 188ae115bc7Smrj wrmsr(MSR_AMD_STAR, 189ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 1900ac7d7d8Skucharsk wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 1910ac7d7d8Skucharsk wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 1927c478bd9Sstevel@tonic-gate 1937c478bd9Sstevel@tonic-gate /* 1947c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 1957c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 1967c478bd9Sstevel@tonic-gate */ 1970ac7d7d8Skucharsk wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 1987c478bd9Sstevel@tonic-gate } 1997c478bd9Sstevel@tonic-gate #endif 2007c478bd9Sstevel@tonic-gate 2017c478bd9Sstevel@tonic-gate /* 2027c478bd9Sstevel@tonic-gate * On 32-bit kernels, we use sysenter/sysexit because it's too 2037c478bd9Sstevel@tonic-gate * hard to use syscall/sysret, and it is more portable anyway. 2047c478bd9Sstevel@tonic-gate * 2057c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 2067c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 2077c478bd9Sstevel@tonic-gate */ 208*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 209*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) { 2107c478bd9Sstevel@tonic-gate 2117c478bd9Sstevel@tonic-gate #if !defined(__lint) 2127c478bd9Sstevel@tonic-gate /* 2137c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 2147c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2157c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2167c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2177c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2187c478bd9Sstevel@tonic-gate */ 2197c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 2207c478bd9Sstevel@tonic-gate 2217c478bd9Sstevel@tonic-gate ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 2227c478bd9Sstevel@tonic-gate ASSERT32(UDS_SEL == UCS_SEL + 8); 2237c478bd9Sstevel@tonic-gate 2247c478bd9Sstevel@tonic-gate ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 2257c478bd9Sstevel@tonic-gate ASSERT64(UDS_SEL == U32CS_SEL + 8); 2267c478bd9Sstevel@tonic-gate #endif 2277c478bd9Sstevel@tonic-gate 2287c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate /* 2317c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2327c478bd9Sstevel@tonic-gate * via a context handler. 2337c478bd9Sstevel@tonic-gate */ 234ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 2350ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 2367c478bd9Sstevel@tonic-gate } 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate kpreempt_enable(); 2397c478bd9Sstevel@tonic-gate } 2407c478bd9Sstevel@tonic-gate 2417c478bd9Sstevel@tonic-gate /* 2427c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2437c478bd9Sstevel@tonic-gate * 2447c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2457c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 246a3114836SGerry Liu * Parameter boot is true for boot time operations and is false for CPU 247a3114836SGerry Liu * DR operations. 2487c478bd9Sstevel@tonic-gate */ 249a3114836SGerry Liu static struct cpu * 250a3114836SGerry Liu mp_cpu_configure_common(int cpun, boolean_t boot) 2517c478bd9Sstevel@tonic-gate { 2527c478bd9Sstevel@tonic-gate struct cpu *cp; 2537c478bd9Sstevel@tonic-gate kthread_id_t tp; 2547c478bd9Sstevel@tonic-gate caddr_t sp; 2557c478bd9Sstevel@tonic-gate proc_t *procp; 256843e1988Sjohnlev #if !defined(__xpv) 2575b8a6efeSbholler extern int idle_cpu_prefer_mwait; 2580e751525SEric Saxe extern void cpu_idle_mwait(); 259843e1988Sjohnlev #endif 2607c478bd9Sstevel@tonic-gate extern void idle(); 2610e751525SEric Saxe extern void cpu_idle(); 2627c478bd9Sstevel@tonic-gate 2637c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 2647c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 2657c478bd9Sstevel@tonic-gate #endif 2667c478bd9Sstevel@tonic-gate 267a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 2687c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 2697c478bd9Sstevel@tonic-gate 270a3114836SGerry Liu if (cpu_free_list == NULL) { 271a3114836SGerry Liu cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 272a3114836SGerry Liu } else { 273a3114836SGerry Liu cp = cpu_free_list; 274a3114836SGerry Liu cpu_free_list = cp->cpu_next_free; 275a3114836SGerry Liu } 276f98fbcecSbholler 2773006ae82SFrank Van Der Linden cp->cpu_m.mcpu_istamp = cpun << 16; 2783006ae82SFrank Van Der Linden 279a3114836SGerry Liu /* Create per CPU specific threads in the process p0. */ 280a3114836SGerry Liu procp = &p0; 2817c478bd9Sstevel@tonic-gate 2827c478bd9Sstevel@tonic-gate /* 2837c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 2847c478bd9Sstevel@tonic-gate */ 2857c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 2867c478bd9Sstevel@tonic-gate 287affbd3ccSkchow cpu_vm_data_init(cp); 288affbd3ccSkchow 2897c478bd9Sstevel@tonic-gate /* 2907c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 2917c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 2927c478bd9Sstevel@tonic-gate * when the CPU starts running. 2937c478bd9Sstevel@tonic-gate */ 2947c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 2957c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 2967c478bd9Sstevel@tonic-gate 2977c478bd9Sstevel@tonic-gate /* 2987c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 2997c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 3007c478bd9Sstevel@tonic-gate * 3017c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 3027c478bd9Sstevel@tonic-gate * thread_create(). 3037c478bd9Sstevel@tonic-gate */ 3047c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 3057c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3067c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3077c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3087c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3097c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3107c478bd9Sstevel@tonic-gate 3117c478bd9Sstevel@tonic-gate /* 312a3114836SGerry Liu * Setup thread to start in mp_startup_common. 3137c478bd9Sstevel@tonic-gate */ 3147c478bd9Sstevel@tonic-gate sp = tp->t_stk; 3157c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 316ae115bc7Smrj #if defined(__amd64) 317ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 318ae115bc7Smrj #endif 319a3114836SGerry Liu /* 320a3114836SGerry Liu * Setup thread start entry point for boot or hotplug. 321a3114836SGerry Liu */ 322a3114836SGerry Liu if (boot) { 323a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_boot; 324a3114836SGerry Liu } else { 325a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_hotplug; 326a3114836SGerry Liu } 3277c478bd9Sstevel@tonic-gate 3287c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3297c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3307c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3317c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3327c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3337c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3347c478bd9Sstevel@tonic-gate 335da43ceabSsethg /* 336da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 337a3114836SGerry Liu * operations in mp_startup_common from causing the spl of the cpu 338a3114836SGerry Liu * to drop to 0 (allowing device interrupts before we're ready) in 339a3114836SGerry Liu * resume(). 340da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 341da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 342a3114836SGerry Liu * an assertion in mp_startup_common() -- before cpu_base_spl is set 343a3114836SGerry Liu * to its proper value. 344da43ceabSsethg */ 345da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 346da43ceabSsethg 3477c478bd9Sstevel@tonic-gate /* 3487c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3497c478bd9Sstevel@tonic-gate */ 3507c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3517c478bd9Sstevel@tonic-gate 3527c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3557c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3567c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3577c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3587c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3597c478bd9Sstevel@tonic-gate 360394b433dSesaxe /* 361fb2f18f8Sesaxe * Bootstrap the CPU's PG data 362394b433dSesaxe */ 363fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 364394b433dSesaxe 3657c478bd9Sstevel@tonic-gate /* 366ae115bc7Smrj * Perform CPC initialization on the new CPU. 3677c478bd9Sstevel@tonic-gate */ 3687c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 3697c478bd9Sstevel@tonic-gate 3707c478bd9Sstevel@tonic-gate /* 3717c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 3727c478bd9Sstevel@tonic-gate * for each CPU. 3737c478bd9Sstevel@tonic-gate */ 3747c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 3757c478bd9Sstevel@tonic-gate 3767c478bd9Sstevel@tonic-gate /* 377ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 3787c478bd9Sstevel@tonic-gate */ 379ae115bc7Smrj #if !defined(__lint) 380ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 381ae115bc7Smrj #endif 3820cfdb603Sjosephb cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 3830cfdb603Sjosephb bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 3847c478bd9Sstevel@tonic-gate 385ae115bc7Smrj #if defined(__i386) 3867c478bd9Sstevel@tonic-gate /* 3877c478bd9Sstevel@tonic-gate * setup kernel %gs. 3887c478bd9Sstevel@tonic-gate */ 3897c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 3907c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 391ae115bc7Smrj #endif 3927c478bd9Sstevel@tonic-gate 3937c478bd9Sstevel@tonic-gate /* 3947c478bd9Sstevel@tonic-gate * If we have more than one node, each cpu gets a copy of IDT 3957c478bd9Sstevel@tonic-gate * local to its node. If this is a Pentium box, we use cpu 0's 3967c478bd9Sstevel@tonic-gate * IDT. cpu 0's IDT has been made read-only to workaround the 3977c478bd9Sstevel@tonic-gate * cmpxchgl register bug 3987c478bd9Sstevel@tonic-gate */ 3997c478bd9Sstevel@tonic-gate if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 4000cfdb603Sjosephb #if !defined(__lint) 4010cfdb603Sjosephb ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 4020cfdb603Sjosephb #endif 4030cfdb603Sjosephb cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 4040cfdb603Sjosephb bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 405ae115bc7Smrj } else { 4060cfdb603Sjosephb cp->cpu_idt = CPU->cpu_idt; 4077c478bd9Sstevel@tonic-gate } 4087c478bd9Sstevel@tonic-gate 4097c478bd9Sstevel@tonic-gate /* 410ae115bc7Smrj * Get interrupt priority data from cpu 0. 4117c478bd9Sstevel@tonic-gate */ 4127c478bd9Sstevel@tonic-gate cp->cpu_pri_data = CPU->cpu_pri_data; 4137c478bd9Sstevel@tonic-gate 4147c478bd9Sstevel@tonic-gate /* 415ae115bc7Smrj * alloc space for cpuid info 4167c478bd9Sstevel@tonic-gate */ 417ae115bc7Smrj cpuid_alloc_space(cp); 418a3114836SGerry Liu #if !defined(__xpv) 419*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) && 420*7417cfdeSKuriakose Kuruvilla idle_cpu_prefer_mwait) { 421a3114836SGerry Liu cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 422a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 423a3114836SGerry Liu } else 424a3114836SGerry Liu #endif 425a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle; 426a3114836SGerry Liu 427a3114836SGerry Liu init_cpu_info(cp); 4287c478bd9Sstevel@tonic-gate 4292449e17fSsherrym /* 4302449e17fSsherrym * alloc space for ucode_info 4312449e17fSsherrym */ 4322449e17fSsherrym ucode_alloc_space(cp); 433f34a7178SJoe Bonasera xc_init_cpu(cp); 434ae115bc7Smrj hat_cpu_online(cp); 4357c478bd9Sstevel@tonic-gate 4367c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4377c478bd9Sstevel@tonic-gate /* 438ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4397c478bd9Sstevel@tonic-gate */ 4407c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4417c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4427c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4437c478bd9Sstevel@tonic-gate #endif 444a3114836SGerry Liu 4457c478bd9Sstevel@tonic-gate /* 4467c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4477c478bd9Sstevel@tonic-gate */ 4487c478bd9Sstevel@tonic-gate /* 4497c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4507c478bd9Sstevel@tonic-gate */ 451100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 452a3114836SGerry Liu 453a3114836SGerry Liu cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 454a3114836SGerry Liu cpu_set_state(cp); 455a3114836SGerry Liu 4567c478bd9Sstevel@tonic-gate /* 4577c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 458a3114836SGerry Liu * after mp_startup_common(). 4597c478bd9Sstevel@tonic-gate */ 4607c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 461ae115bc7Smrj 462ae115bc7Smrj return (cp); 463ae115bc7Smrj } 464ae115bc7Smrj 465ae115bc7Smrj /* 466a3114836SGerry Liu * Undo what was done in mp_cpu_configure_common 467ae115bc7Smrj */ 468ae115bc7Smrj static void 469a3114836SGerry Liu mp_cpu_unconfigure_common(struct cpu *cp, int error) 470ae115bc7Smrj { 471a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 472ae115bc7Smrj 473ae115bc7Smrj /* 474ae115bc7Smrj * Remove the CPU from the list of available CPUs. 475ae115bc7Smrj */ 476ae115bc7Smrj cpu_del_unit(cp->cpu_id); 477ae115bc7Smrj 478ae115bc7Smrj if (error == ETIMEDOUT) { 479ae115bc7Smrj /* 480ae115bc7Smrj * The cpu was started, but never *seemed* to run any 481ae115bc7Smrj * code in the kernel; it's probably off spinning in its 482ae115bc7Smrj * own private world, though with potential references to 483ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 484ae115bc7Smrj * 485ae115bc7Smrj * Worse still, it may actually wake up some time later, 486ae115bc7Smrj * so rather than guess what it might or might not do, we 487ae115bc7Smrj * leave the fundamental data structures intact. 488ae115bc7Smrj */ 489ae115bc7Smrj cp->cpu_flags = 0; 490ae115bc7Smrj return; 491ae115bc7Smrj } 492ae115bc7Smrj 493ae115bc7Smrj /* 494ae115bc7Smrj * At this point, the only threads bound to this CPU should 495ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 496ae115bc7Smrj * and it's interrupt threads. Clean these up. 497ae115bc7Smrj */ 498ae115bc7Smrj cpu_destroy_bound_threads(cp); 499ae115bc7Smrj cp->cpu_idle_thread = NULL; 500ae115bc7Smrj 501ae115bc7Smrj /* 502ae115bc7Smrj * Free the interrupt stack. 503ae115bc7Smrj */ 504ae115bc7Smrj segkp_release(segkp, 505ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 506a3114836SGerry Liu cp->cpu_intr_stack = NULL; 507ae115bc7Smrj 508ae115bc7Smrj #ifdef TRAPTRACE 509ae115bc7Smrj /* 510ae115bc7Smrj * Discard the trap trace buffer 511ae115bc7Smrj */ 512ae115bc7Smrj { 513ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 514ae115bc7Smrj 515ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 516ae115bc7Smrj ttc->ttc_first = NULL; 517ae115bc7Smrj } 518ae115bc7Smrj #endif 519ae115bc7Smrj 520ae115bc7Smrj hat_cpu_offline(cp); 521ae115bc7Smrj 5222449e17fSsherrym ucode_free_space(cp); 5232449e17fSsherrym 524a3114836SGerry Liu /* Free CPU ID string and brand string. */ 525a3114836SGerry Liu if (cp->cpu_idstr) { 526a3114836SGerry Liu kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 527a3114836SGerry Liu cp->cpu_idstr = NULL; 528a3114836SGerry Liu } 529a3114836SGerry Liu if (cp->cpu_brandstr) { 530a3114836SGerry Liu kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 531a3114836SGerry Liu cp->cpu_brandstr = NULL; 532a3114836SGerry Liu } 533a3114836SGerry Liu 534a3114836SGerry Liu #if !defined(__xpv) 535a3114836SGerry Liu if (cp->cpu_m.mcpu_mwait != NULL) { 536a3114836SGerry Liu cpuid_mwait_free(cp); 537a3114836SGerry Liu cp->cpu_m.mcpu_mwait = NULL; 538a3114836SGerry Liu } 539a3114836SGerry Liu #endif 540a3114836SGerry Liu cpuid_free_space(cp); 541a3114836SGerry Liu 5420cfdb603Sjosephb if (cp->cpu_idt != CPU->cpu_idt) 5430cfdb603Sjosephb kmem_free(cp->cpu_idt, PAGESIZE); 5440cfdb603Sjosephb cp->cpu_idt = NULL; 545ae115bc7Smrj 5460cfdb603Sjosephb kmem_free(cp->cpu_gdt, PAGESIZE); 5470cfdb603Sjosephb cp->cpu_gdt = NULL; 548ae115bc7Smrj 549a3114836SGerry Liu if (cp->cpu_supp_freqs != NULL) { 550a3114836SGerry Liu size_t len = strlen(cp->cpu_supp_freqs) + 1; 551a3114836SGerry Liu kmem_free(cp->cpu_supp_freqs, len); 552a3114836SGerry Liu cp->cpu_supp_freqs = NULL; 553a3114836SGerry Liu } 554a3114836SGerry Liu 555ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 556ae115bc7Smrj 557ae115bc7Smrj kcpc_hw_fini(cp); 558ae115bc7Smrj 559ae115bc7Smrj cp->cpu_dispthread = NULL; 560ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 561ae115bc7Smrj 562ae115bc7Smrj cpu_vm_data_destroy(cp); 563ae115bc7Smrj 564a3114836SGerry Liu xc_fini_cpu(cp); 565ae115bc7Smrj disp_cpu_fini(cp); 566ae115bc7Smrj 567a3114836SGerry Liu ASSERT(cp != CPU0); 568a3114836SGerry Liu bzero(cp, sizeof (*cp)); 569a3114836SGerry Liu cp->cpu_next_free = cpu_free_list; 570a3114836SGerry Liu cpu_free_list = cp; 5717c478bd9Sstevel@tonic-gate } 5727c478bd9Sstevel@tonic-gate 5737c478bd9Sstevel@tonic-gate /* 5747c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 5757c478bd9Sstevel@tonic-gate * 5767c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 5777c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 5787c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 5797c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 5807c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 5817c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 5827c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 5837c478bd9Sstevel@tonic-gate * system. 5847c478bd9Sstevel@tonic-gate * 585ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 586a3114836SGerry Liu * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 587a3114836SGerry Liu * prior to acknowledging their readiness to the master, so this routine will 588ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 589ef50d8c0Sesaxe * global data safe. 590ef50d8c0Sesaxe * 5912201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 5922201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 5937c478bd9Sstevel@tonic-gate */ 5947c478bd9Sstevel@tonic-gate 595ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 596ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 597ae115bc7Smrj #endif 598ae115bc7Smrj 5997c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 6007c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 6017c478bd9Sstevel@tonic-gate #endif 6027c478bd9Sstevel@tonic-gate 6037c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 6047c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 6057c478bd9Sstevel@tonic-gate #endif 6067c478bd9Sstevel@tonic-gate 607ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 608ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 609ae115bc7Smrj #endif 610ae115bc7Smrj 6117c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 6127c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 6137c478bd9Sstevel@tonic-gate #endif 6147c478bd9Sstevel@tonic-gate 615ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 616ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 617ae115bc7Smrj #endif 618ae115bc7Smrj 6197c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 6207c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 6217c478bd9Sstevel@tonic-gate #endif 6227c478bd9Sstevel@tonic-gate 6237c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 6247c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 6257c478bd9Sstevel@tonic-gate #endif 6267c478bd9Sstevel@tonic-gate 6277c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 6287c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 6297c478bd9Sstevel@tonic-gate #endif 6307c478bd9Sstevel@tonic-gate 6317c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 6327c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 6337c478bd9Sstevel@tonic-gate #endif 6347c478bd9Sstevel@tonic-gate 6352201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 6362201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 6372201b277Skucharsk #endif 6387c478bd9Sstevel@tonic-gate 639ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 640ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 641ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 642ef50d8c0Sesaxe #endif 643ef50d8c0Sesaxe 644ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 645ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 646ee88d2b9Skchow #endif 647ee88d2b9Skchow 648512cf780Skchow #if defined(OPTERON_ERRATUM_298) 649512cf780Skchow int opteron_erratum_298; 650512cf780Skchow #endif 651512cf780Skchow 652ae115bc7Smrj static void 653ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 654ae115bc7Smrj { 655ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 656ae115bc7Smrj cp->cpu_id, erratum); 657ae115bc7Smrj } 658ae115bc7Smrj 659ae115bc7Smrj static void 660ae115bc7Smrj workaround_applied(uint_t erratum) 661ae115bc7Smrj { 662ae115bc7Smrj if (erratum > 1000000) 663ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 664ae115bc7Smrj erratum); 665ae115bc7Smrj else 666ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 667ae115bc7Smrj erratum); 668ae115bc7Smrj } 669ae115bc7Smrj 670ae115bc7Smrj static void 671ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 672ae115bc7Smrj { 673ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 674ae115bc7Smrj cp->cpu_id, rw, msr, error); 675ae115bc7Smrj } 6767c478bd9Sstevel@tonic-gate 67792564cb1Sesaxe /* 678d2aeaf66SEric Saxe * Determine the number of nodes in a Hammer / Greyhound / Griffin family 679d2aeaf66SEric Saxe * system. 68092564cb1Sesaxe */ 68192564cb1Sesaxe static uint_t 68292564cb1Sesaxe opteron_get_nnodes(void) 68392564cb1Sesaxe { 68492564cb1Sesaxe static uint_t nnodes = 0; 68592564cb1Sesaxe 686d2aeaf66SEric Saxe if (nnodes == 0) { 68792564cb1Sesaxe #ifdef DEBUG 688d2aeaf66SEric Saxe uint_t family; 68992564cb1Sesaxe 690d2aeaf66SEric Saxe /* 691d2aeaf66SEric Saxe * This routine uses a PCI config space based mechanism 692d2aeaf66SEric Saxe * for retrieving the number of nodes in the system. 693d2aeaf66SEric Saxe * Device 24, function 0, offset 0x60 as used here is not 694d2aeaf66SEric Saxe * AMD processor architectural, and may not work on processor 695d2aeaf66SEric Saxe * families other than those listed below. 696d2aeaf66SEric Saxe * 697d2aeaf66SEric Saxe * Callers of this routine must ensure that we're running on 698d2aeaf66SEric Saxe * a processor which supports this mechanism. 699d2aeaf66SEric Saxe * The assertion below is meant to catch calls on unsupported 700d2aeaf66SEric Saxe * processors. 701d2aeaf66SEric Saxe */ 702d2aeaf66SEric Saxe family = cpuid_getfamily(CPU); 703d2aeaf66SEric Saxe ASSERT(family == 0xf || family == 0x10 || family == 0x11); 70492564cb1Sesaxe #endif /* DEBUG */ 70592564cb1Sesaxe 70692564cb1Sesaxe /* 70792564cb1Sesaxe * Obtain the number of nodes in the system from 70892564cb1Sesaxe * bits [6:4] of the Node ID register on node 0. 70992564cb1Sesaxe * 71092564cb1Sesaxe * The actual node count is NodeID[6:4] + 1 71192564cb1Sesaxe * 71292564cb1Sesaxe * The Node ID register is accessed via function 0, 71392564cb1Sesaxe * offset 0x60. Node 0 is device 24. 71492564cb1Sesaxe */ 71592564cb1Sesaxe nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 71692564cb1Sesaxe } 71792564cb1Sesaxe return (nnodes); 71892564cb1Sesaxe } 71992564cb1Sesaxe 720512cf780Skchow uint_t 721512cf780Skchow do_erratum_298(struct cpu *cpu) 722512cf780Skchow { 723512cf780Skchow static int osvwrc = -3; 724512cf780Skchow extern int osvw_opteron_erratum(cpu_t *, uint_t); 725512cf780Skchow 726512cf780Skchow /* 727512cf780Skchow * L2 Eviction May Occur During Processor Operation To Set 728512cf780Skchow * Accessed or Dirty Bit. 729512cf780Skchow */ 730512cf780Skchow if (osvwrc == -3) { 731512cf780Skchow osvwrc = osvw_opteron_erratum(cpu, 298); 732512cf780Skchow } else { 733512cf780Skchow /* osvw return codes should be consistent for all cpus */ 734512cf780Skchow ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 735512cf780Skchow } 736512cf780Skchow 737512cf780Skchow switch (osvwrc) { 738512cf780Skchow case 0: /* erratum is not present: do nothing */ 739512cf780Skchow break; 740512cf780Skchow case 1: /* erratum is present: BIOS workaround applied */ 741512cf780Skchow /* 742512cf780Skchow * check if workaround is actually in place and issue warning 743512cf780Skchow * if not. 744512cf780Skchow */ 745512cf780Skchow if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 746512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 747512cf780Skchow #if defined(OPTERON_ERRATUM_298) 748512cf780Skchow opteron_erratum_298++; 749512cf780Skchow #else 750512cf780Skchow workaround_warning(cpu, 298); 751512cf780Skchow return (1); 752512cf780Skchow #endif 753512cf780Skchow } 754512cf780Skchow break; 755512cf780Skchow case -1: /* cannot determine via osvw: check cpuid */ 756512cf780Skchow if ((cpuid_opteron_erratum(cpu, 298) > 0) && 757512cf780Skchow (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 758512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 759512cf780Skchow #if defined(OPTERON_ERRATUM_298) 760512cf780Skchow opteron_erratum_298++; 761512cf780Skchow #else 762512cf780Skchow workaround_warning(cpu, 298); 763512cf780Skchow return (1); 764512cf780Skchow #endif 765512cf780Skchow } 766512cf780Skchow break; 767512cf780Skchow } 768512cf780Skchow return (0); 769512cf780Skchow } 770512cf780Skchow 7717c478bd9Sstevel@tonic-gate uint_t 7727c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 7737c478bd9Sstevel@tonic-gate { 7747c478bd9Sstevel@tonic-gate uint_t missing = 0; 7757c478bd9Sstevel@tonic-gate 7767c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 7777c478bd9Sstevel@tonic-gate 7787c478bd9Sstevel@tonic-gate /*LINTED*/ 7797c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 7807c478bd9Sstevel@tonic-gate /* 7817c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 7827c478bd9Sstevel@tonic-gate */ 7837c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 7847c478bd9Sstevel@tonic-gate /* 7857c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 7867c478bd9Sstevel@tonic-gate */ 787ae115bc7Smrj opteron_erratum_88++; 7887c478bd9Sstevel@tonic-gate #else 789ae115bc7Smrj workaround_warning(cpu, 88); 7907c478bd9Sstevel@tonic-gate missing++; 7917c478bd9Sstevel@tonic-gate #endif 7927c478bd9Sstevel@tonic-gate } 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 7957c478bd9Sstevel@tonic-gate /* 7967c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 7977c478bd9Sstevel@tonic-gate */ 7987c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 7997c478bd9Sstevel@tonic-gate /* 8007c478bd9Sstevel@tonic-gate * fix is in trap.c 8017c478bd9Sstevel@tonic-gate */ 8027c478bd9Sstevel@tonic-gate opteron_erratum_91++; 8037c478bd9Sstevel@tonic-gate #else 804ae115bc7Smrj workaround_warning(cpu, 91); 8057c478bd9Sstevel@tonic-gate missing++; 8067c478bd9Sstevel@tonic-gate #endif 8077c478bd9Sstevel@tonic-gate } 8087c478bd9Sstevel@tonic-gate 8097c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 8107c478bd9Sstevel@tonic-gate /* 8117c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 8127c478bd9Sstevel@tonic-gate */ 8137c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 8147c478bd9Sstevel@tonic-gate /* 8157c478bd9Sstevel@tonic-gate * fix is in trap.c 8167c478bd9Sstevel@tonic-gate */ 8177c478bd9Sstevel@tonic-gate opteron_erratum_93++; 8187c478bd9Sstevel@tonic-gate #else 819ae115bc7Smrj workaround_warning(cpu, 93); 8207c478bd9Sstevel@tonic-gate missing++; 8217c478bd9Sstevel@tonic-gate #endif 8227c478bd9Sstevel@tonic-gate } 8237c478bd9Sstevel@tonic-gate 8247c478bd9Sstevel@tonic-gate /*LINTED*/ 8257c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 8267c478bd9Sstevel@tonic-gate /* 8277c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 8287c478bd9Sstevel@tonic-gate */ 8297c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 8307c478bd9Sstevel@tonic-gate #if defined(_LP64) 8317c478bd9Sstevel@tonic-gate /* 8327c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 8337c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 8347c478bd9Sstevel@tonic-gate * range mod 4G. 8357c478bd9Sstevel@tonic-gate */ 8367c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 8377c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 8387c478bd9Sstevel@tonic-gate 8397c478bd9Sstevel@tonic-gate /*LINTED*/ 8407c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 841ae115bc7Smrj opteron_erratum_95++; 8427c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 8437c478bd9Sstevel@tonic-gate #else 844ae115bc7Smrj workaround_warning(cpu, 95); 8457c478bd9Sstevel@tonic-gate missing++; 846ae115bc7Smrj #endif 8477c478bd9Sstevel@tonic-gate } 8487c478bd9Sstevel@tonic-gate 8497c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 8507c478bd9Sstevel@tonic-gate /* 8517c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 8527c478bd9Sstevel@tonic-gate */ 8537c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8547c478bd9Sstevel@tonic-gate /* 8557c478bd9Sstevel@tonic-gate * fix is in trap.c 8567c478bd9Sstevel@tonic-gate */ 8577c478bd9Sstevel@tonic-gate opteron_erratum_100++; 8587c478bd9Sstevel@tonic-gate #else 859ae115bc7Smrj workaround_warning(cpu, 100); 8607c478bd9Sstevel@tonic-gate missing++; 8617c478bd9Sstevel@tonic-gate #endif 8627c478bd9Sstevel@tonic-gate } 8637c478bd9Sstevel@tonic-gate 8647c478bd9Sstevel@tonic-gate /*LINTED*/ 8657c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 8667c478bd9Sstevel@tonic-gate /* 8677c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 8687c478bd9Sstevel@tonic-gate * Some Processors 8697c478bd9Sstevel@tonic-gate */ 8707c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 8717c478bd9Sstevel@tonic-gate /* 8727c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 8737c478bd9Sstevel@tonic-gate * those processors) 8747c478bd9Sstevel@tonic-gate */ 8757c478bd9Sstevel@tonic-gate #else 876ae115bc7Smrj workaround_warning(cpu, 108); 8777c478bd9Sstevel@tonic-gate missing++; 8787c478bd9Sstevel@tonic-gate #endif 8797c478bd9Sstevel@tonic-gate } 8807c478bd9Sstevel@tonic-gate 8817c478bd9Sstevel@tonic-gate /*LINTED*/ 882ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 8837c478bd9Sstevel@tonic-gate /* 884fb2caebeSRandy Fishel * Certain Reverse REP MOVS May Produce Unpredictable Behavior 8857c478bd9Sstevel@tonic-gate */ 8867c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 887ae115bc7Smrj /* 888ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 889ae115bc7Smrj */ 890ae115bc7Smrj uint64_t value; 891ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 892ae115bc7Smrj int err; 893ae115bc7Smrj 894ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 895ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 896ae115bc7Smrj workaround_warning(cpu, 109); 897ae115bc7Smrj missing++; 898ae115bc7Smrj } 899ae115bc7Smrj if (value == 0) 9007c478bd9Sstevel@tonic-gate opteron_erratum_109++; 9017c478bd9Sstevel@tonic-gate #else 902ae115bc7Smrj workaround_warning(cpu, 109); 9037c478bd9Sstevel@tonic-gate missing++; 9047c478bd9Sstevel@tonic-gate #endif 905ae115bc7Smrj /*CONSTANTCONDITION*/ 906ae115bc7Smrj } while (0); 907ae115bc7Smrj 9087c478bd9Sstevel@tonic-gate /*LINTED*/ 9097c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 9107c478bd9Sstevel@tonic-gate /* 9117c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 9127c478bd9Sstevel@tonic-gate * Processor Hang 9137c478bd9Sstevel@tonic-gate */ 9147c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 915ae115bc7Smrj #if defined(_LP64) 9167c478bd9Sstevel@tonic-gate /* 9177c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 9187c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 9197c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 9207c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 9217c478bd9Sstevel@tonic-gate */ 922ae115bc7Smrj if (opteron_erratum_121) 923ae115bc7Smrj opteron_erratum_121++; 924ae115bc7Smrj else { 925ae115bc7Smrj if (hole_start) { 926ae115bc7Smrj hole_start -= PAGESIZE; 927ae115bc7Smrj } else { 928ae115bc7Smrj /* 929ae115bc7Smrj * hole_start not yet initialized by 930ae115bc7Smrj * mmu_init. Initialize hole_start 931ae115bc7Smrj * with value to be subtracted. 932ae115bc7Smrj */ 933ae115bc7Smrj hole_start = PAGESIZE; 9347c478bd9Sstevel@tonic-gate } 935ae115bc7Smrj opteron_erratum_121++; 9367c478bd9Sstevel@tonic-gate } 937ae115bc7Smrj #endif /* _LP64 */ 9387c478bd9Sstevel@tonic-gate #else 939ae115bc7Smrj workaround_warning(cpu, 121); 9407c478bd9Sstevel@tonic-gate missing++; 9417c478bd9Sstevel@tonic-gate #endif 9427c478bd9Sstevel@tonic-gate } 9437c478bd9Sstevel@tonic-gate 9447c478bd9Sstevel@tonic-gate /*LINTED*/ 945ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 9467c478bd9Sstevel@tonic-gate /* 947ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 9487c478bd9Sstevel@tonic-gate * Multiprocessor Systems 9497c478bd9Sstevel@tonic-gate */ 9507c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 951ae115bc7Smrj uint64_t value; 952ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 953ae115bc7Smrj int error; 954ae115bc7Smrj 9557c478bd9Sstevel@tonic-gate /* 9567c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 9577c478bd9Sstevel@tonic-gate * or multi-processor). 9587c478bd9Sstevel@tonic-gate */ 959843e1988Sjohnlev #if defined(__xpv) 960843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 961843e1988Sjohnlev break; 962349b53ddSStuart Maybee if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 963843e1988Sjohnlev break; 964843e1988Sjohnlev #else 96592564cb1Sesaxe if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 966ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 967ae115bc7Smrj break; 968843e1988Sjohnlev #endif 969ae115bc7Smrj /* disable TLB Flush Filter */ 970ae115bc7Smrj 971ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 972ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 973ae115bc7Smrj workaround_warning(cpu, 122); 974ae115bc7Smrj missing++; 975ae115bc7Smrj } else { 976ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 977ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 978ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 979ae115bc7Smrj workaround_warning(cpu, 122); 980ae115bc7Smrj missing++; 981ae115bc7Smrj } 9827c478bd9Sstevel@tonic-gate } 983ae115bc7Smrj opteron_erratum_122++; 9847c478bd9Sstevel@tonic-gate #else 985ae115bc7Smrj workaround_warning(cpu, 122); 9867c478bd9Sstevel@tonic-gate missing++; 9877c478bd9Sstevel@tonic-gate #endif 988ae115bc7Smrj /*CONSTANTCONDITION*/ 989ae115bc7Smrj } while (0); 990403c216aSkchow 9917c478bd9Sstevel@tonic-gate /*LINTED*/ 992ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 9937c478bd9Sstevel@tonic-gate /* 9947c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 9957c478bd9Sstevel@tonic-gate * Dual Core Processors 9967c478bd9Sstevel@tonic-gate */ 997ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 998ae115bc7Smrj uint64_t value; 999ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 1000ae115bc7Smrj int err; 1001ae115bc7Smrj 10027c478bd9Sstevel@tonic-gate /* 10037c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 10047c478bd9Sstevel@tonic-gate */ 1005ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 1006ae115bc7Smrj break; 1007843e1988Sjohnlev #if defined(__xpv) 1008843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1009843e1988Sjohnlev break; 1010843e1988Sjohnlev #endif 1011ae115bc7Smrj /* 1012ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 1013ae115bc7Smrj */ 1014ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 1015ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 1016ae115bc7Smrj workaround_warning(cpu, 123); 1017ae115bc7Smrj missing++; 10187c478bd9Sstevel@tonic-gate } 1019ae115bc7Smrj if (value == 0) 1020ae115bc7Smrj opteron_erratum_123++; 1021ae115bc7Smrj #else 1022ae115bc7Smrj workaround_warning(cpu, 123); 1023ae115bc7Smrj missing++; 1024ae115bc7Smrj 1025403c216aSkchow #endif 1026ae115bc7Smrj /*CONSTANTCONDITION*/ 1027ae115bc7Smrj } while (0); 10282201b277Skucharsk 10292201b277Skucharsk /*LINTED*/ 1030ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 10312201b277Skucharsk /* 10322201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 10332201b277Skucharsk * Waiting for a Probe Response 10342201b277Skucharsk */ 1035ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 1036ae115bc7Smrj uint64_t nbcfg; 1037ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 1038ae115bc7Smrj const uint64_t wabits = 1039ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1040ae115bc7Smrj int error; 1041ae115bc7Smrj 10422201b277Skucharsk /* 10432201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 10442201b277Skucharsk */ 1045ae115bc7Smrj if (opteron_erratum_131) 1046ae115bc7Smrj break; 1047843e1988Sjohnlev #if defined(__xpv) 1048843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1049843e1988Sjohnlev break; 1050349b53ddSStuart Maybee if (xpv_nr_phys_cpus() < 4) 1051843e1988Sjohnlev break; 1052843e1988Sjohnlev #else 105392564cb1Sesaxe if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1054ae115bc7Smrj break; 1055843e1988Sjohnlev #endif 1056ae115bc7Smrj /* 1057ae115bc7Smrj * Print a warning if neither of the workarounds for 1058ae115bc7Smrj * erratum 131 is present. 1059ae115bc7Smrj */ 1060ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1061ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1062ae115bc7Smrj workaround_warning(cpu, 131); 1063ae115bc7Smrj missing++; 1064ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 1065ae115bc7Smrj opteron_erratum_131++; 1066ae115bc7Smrj } else { 1067ae115bc7Smrj /* cannot have both workarounds set */ 1068ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 10692201b277Skucharsk } 1070ae115bc7Smrj #else 1071ae115bc7Smrj workaround_warning(cpu, 131); 1072ae115bc7Smrj missing++; 10732201b277Skucharsk #endif 1074ae115bc7Smrj /*CONSTANTCONDITION*/ 1075ae115bc7Smrj } while (0); 1076ef50d8c0Sesaxe 1077ef50d8c0Sesaxe /* 1078ae115bc7Smrj * This isn't really an erratum, but for convenience the 1079ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 1080ef50d8c0Sesaxe */ 1081ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1082ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1083ef50d8c0Sesaxe /* 1084ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 1085ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 1086ef50d8c0Sesaxe */ 1087ef50d8c0Sesaxe if (opteron_workaround_6336786) { 1088ef50d8c0Sesaxe opteron_workaround_6336786++; 1089843e1988Sjohnlev #if defined(__xpv) 1090843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1091349b53ddSStuart Maybee xpv_nr_phys_cpus() > 1) || 1092843e1988Sjohnlev opteron_workaround_6336786_UP) { 1093843e1988Sjohnlev /* 109492564cb1Sesaxe * XXPV Hmm. We can't walk the Northbridges on 1095843e1988Sjohnlev * the hypervisor; so just complain and drive 1096843e1988Sjohnlev * on. This probably needs to be fixed in 1097843e1988Sjohnlev * the hypervisor itself. 1098843e1988Sjohnlev */ 1099843e1988Sjohnlev opteron_workaround_6336786++; 1100843e1988Sjohnlev workaround_warning(cpu, 6336786); 1101843e1988Sjohnlev #else /* __xpv */ 110292564cb1Sesaxe } else if ((opteron_get_nnodes() * 1103d38257c4Sesaxe cpuid_get_ncpu_per_chip(cpu) > 1) || 1104ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 110592564cb1Sesaxe 110692564cb1Sesaxe uint_t node, nnodes; 1107ae115bc7Smrj uint8_t data; 1108ae115bc7Smrj 110992564cb1Sesaxe nnodes = opteron_get_nnodes(); 111092564cb1Sesaxe for (node = 0; node < nnodes; node++) { 1111ef50d8c0Sesaxe /* 1112ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 1113ef50d8c0Sesaxe * Northbridge device is the node id + 24. 1114ef50d8c0Sesaxe */ 1115ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 1116ef50d8c0Sesaxe data &= 0xFC; 1117ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 1118ef50d8c0Sesaxe } 1119ef50d8c0Sesaxe opteron_workaround_6336786++; 1120843e1988Sjohnlev #endif /* __xpv */ 1121ef50d8c0Sesaxe } 1122ae115bc7Smrj #else 1123ae115bc7Smrj workaround_warning(cpu, 6336786); 1124ae115bc7Smrj missing++; 1125ef50d8c0Sesaxe #endif 1126ae115bc7Smrj } 1127ee88d2b9Skchow 1128ee88d2b9Skchow /*LINTED*/ 1129ee88d2b9Skchow /* 1130ee88d2b9Skchow * Mutex primitives don't work as expected. 1131ee88d2b9Skchow */ 1132ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1133ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1134ee88d2b9Skchow /* 1135ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1136512cf780Skchow * MSR_AMD_BU_CFG set, then not applicable. The workaround 1137ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1138ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1139ee88d2b9Skchow * possible subsequent read-modify-write ops. 1140ee88d2b9Skchow * 1141ee88d2b9Skchow * It is too early in boot to call the patch routine so 1142ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1143ee88d2b9Skchow */ 1144ee88d2b9Skchow if (opteron_workaround_6323525) { 1145ee88d2b9Skchow opteron_workaround_6323525++; 1146843e1988Sjohnlev #if defined(__xpv) 1147*7417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1148843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1149843e1988Sjohnlev /* 1150843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1151843e1988Sjohnlev * operations are supported? 1152843e1988Sjohnlev */ 1153349b53ddSStuart Maybee if (xpv_nr_phys_cpus() > 1) 1154843e1988Sjohnlev opteron_workaround_6323525++; 1155843e1988Sjohnlev } else { 1156843e1988Sjohnlev /* 1157843e1988Sjohnlev * We have no way to tell how many physical 1158843e1988Sjohnlev * cpus there are, or even if this processor 1159843e1988Sjohnlev * has the problem, so enable the workaround 1160843e1988Sjohnlev * unconditionally (at some performance cost). 1161843e1988Sjohnlev */ 1162843e1988Sjohnlev opteron_workaround_6323525++; 1163843e1988Sjohnlev } 1164843e1988Sjohnlev #else /* __xpv */ 1165*7417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) && 1166*7417cfdeSKuriakose Kuruvilla ((opteron_get_nnodes() * 1167ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 116848b2bf45SKit Chow if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1169ee88d2b9Skchow opteron_workaround_6323525++; 1170843e1988Sjohnlev #endif /* __xpv */ 1171ee88d2b9Skchow } 1172ae115bc7Smrj #else 1173ae115bc7Smrj workaround_warning(cpu, 6323525); 1174ae115bc7Smrj missing++; 1175ee88d2b9Skchow #endif 1176ae115bc7Smrj } 1177ae115bc7Smrj 1178512cf780Skchow missing += do_erratum_298(cpu); 1179512cf780Skchow 1180843e1988Sjohnlev #ifdef __xpv 1181843e1988Sjohnlev return (0); 1182843e1988Sjohnlev #else 11837c478bd9Sstevel@tonic-gate return (missing); 1184843e1988Sjohnlev #endif 11857c478bd9Sstevel@tonic-gate } 11867c478bd9Sstevel@tonic-gate 11877c478bd9Sstevel@tonic-gate void 11887c478bd9Sstevel@tonic-gate workaround_errata_end() 11897c478bd9Sstevel@tonic-gate { 1190ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1191ae115bc7Smrj if (opteron_erratum_88) 1192ae115bc7Smrj workaround_applied(88); 1193ae115bc7Smrj #endif 1194ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1195ae115bc7Smrj if (opteron_erratum_91) 1196ae115bc7Smrj workaround_applied(91); 1197ae115bc7Smrj #endif 1198ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1199ae115bc7Smrj if (opteron_erratum_93) 1200ae115bc7Smrj workaround_applied(93); 1201ae115bc7Smrj #endif 1202ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1203ae115bc7Smrj if (opteron_erratum_95) 1204ae115bc7Smrj workaround_applied(95); 1205ae115bc7Smrj #endif 1206ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1207ae115bc7Smrj if (opteron_erratum_100) 1208ae115bc7Smrj workaround_applied(100); 1209ae115bc7Smrj #endif 1210ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1211ae115bc7Smrj if (opteron_erratum_108) 1212ae115bc7Smrj workaround_applied(108); 1213ae115bc7Smrj #endif 12147c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 12157c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 12162201b277Skucharsk cmn_err(CE_WARN, 12172201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12182201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 12192201b277Skucharsk " system's BIOS to a version\ncontaining this" 12202201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12212201b277Skucharsk " system\noperation may occur.\n"); 12227c478bd9Sstevel@tonic-gate } 1223ae115bc7Smrj #endif 1224ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1225ae115bc7Smrj if (opteron_erratum_121) 1226ae115bc7Smrj workaround_applied(121); 1227ae115bc7Smrj #endif 1228ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1229ae115bc7Smrj if (opteron_erratum_122) 1230ae115bc7Smrj workaround_applied(122); 1231ae115bc7Smrj #endif 12327c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 12337c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 12342201b277Skucharsk cmn_err(CE_WARN, 12352201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12362201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 12372201b277Skucharsk " system's BIOS to a version\ncontaining this" 12382201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12392201b277Skucharsk " system\noperation may occur.\n"); 12407c478bd9Sstevel@tonic-gate } 1241ae115bc7Smrj #endif 12422201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 12432201b277Skucharsk if (opteron_erratum_131) { 12442201b277Skucharsk cmn_err(CE_WARN, 12452201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12462201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 12472201b277Skucharsk " system's BIOS to a version\ncontaining this" 12482201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12492201b277Skucharsk " system\noperation may occur.\n"); 12502201b277Skucharsk } 1251ae115bc7Smrj #endif 1252ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1253ae115bc7Smrj if (opteron_workaround_6336786) 1254ae115bc7Smrj workaround_applied(6336786); 1255ae115bc7Smrj #endif 1256ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1257ae115bc7Smrj if (opteron_workaround_6323525) 1258ae115bc7Smrj workaround_applied(6323525); 1259ae115bc7Smrj #endif 1260512cf780Skchow #if defined(OPTERON_ERRATUM_298) 1261512cf780Skchow if (opteron_erratum_298) { 1262512cf780Skchow cmn_err(CE_WARN, 1263512cf780Skchow "BIOS microcode patch for AMD 64/Opteron(tm)" 1264512cf780Skchow " processor\nerratum 298 was not detected; updating your" 1265512cf780Skchow " system's BIOS to a version\ncontaining this" 1266512cf780Skchow " microcode patch is HIGHLY recommended or erroneous" 1267512cf780Skchow " system\noperation may occur.\n"); 1268512cf780Skchow } 1269512cf780Skchow #endif 12707c478bd9Sstevel@tonic-gate } 12717c478bd9Sstevel@tonic-gate 1272ae115bc7Smrj /* 1273a3114836SGerry Liu * The procset_slave and procset_master are used to synchronize 1274a3114836SGerry Liu * between the control CPU and the target CPU when starting CPUs. 1275ae115bc7Smrj */ 1276a3114836SGerry Liu static cpuset_t procset_slave, procset_master; 1277a3114836SGerry Liu 1278a3114836SGerry Liu static void 1279a3114836SGerry Liu mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1280a3114836SGerry Liu { 1281a3114836SGerry Liu cpuset_t tempset; 1282a3114836SGerry Liu 1283a3114836SGerry Liu for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1284a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1285a3114836SGerry Liu SMT_PAUSE(); 1286a3114836SGerry Liu } 1287a3114836SGerry Liu CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1288a3114836SGerry Liu } 1289a3114836SGerry Liu 1290a3114836SGerry Liu static void 1291a3114836SGerry Liu mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1292a3114836SGerry Liu { 1293a3114836SGerry Liu cpuset_t tempset; 1294a3114836SGerry Liu 1295a3114836SGerry Liu CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1296a3114836SGerry Liu for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1297a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1298a3114836SGerry Liu SMT_PAUSE(); 1299a3114836SGerry Liu } 1300a3114836SGerry Liu } 1301a3114836SGerry Liu 1302ae115bc7Smrj int 1303a3114836SGerry Liu mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1304ae115bc7Smrj { 1305a3114836SGerry Liu _NOTE(ARGUNUSED(boot)); 1306a3114836SGerry Liu 1307ae115bc7Smrj void *ctx; 1308ae115bc7Smrj int delays; 1309ae115bc7Smrj int error = 0; 1310a3114836SGerry Liu cpuset_t tempset; 1311a3114836SGerry Liu processorid_t cpuid; 1312a3114836SGerry Liu #ifndef __xpv 1313a3114836SGerry Liu extern void cpupm_init(cpu_t *); 1314a3114836SGerry Liu #endif 1315ae115bc7Smrj 1316a3114836SGerry Liu ASSERT(cp != NULL); 1317a3114836SGerry Liu cpuid = cp->cpu_id; 1318a3114836SGerry Liu ctx = mach_cpucontext_alloc(cp); 1319a3114836SGerry Liu if (ctx == NULL) { 1320a3114836SGerry Liu cmn_err(CE_WARN, 1321a3114836SGerry Liu "cpu%d: failed to allocate context", cp->cpu_id); 1322a3114836SGerry Liu return (EAGAIN); 1323ae115bc7Smrj } 1324a3114836SGerry Liu error = mach_cpu_start(cp, ctx); 1325a3114836SGerry Liu if (error != 0) { 1326a3114836SGerry Liu cmn_err(CE_WARN, 1327a3114836SGerry Liu "cpu%d: failed to start, error %d", cp->cpu_id, error); 1328a3114836SGerry Liu mach_cpucontext_free(cp, ctx, error); 1329ae115bc7Smrj return (error); 1330ae115bc7Smrj } 1331ae115bc7Smrj 1332a3114836SGerry Liu for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1333a3114836SGerry Liu delays++) { 1334ae115bc7Smrj if (delays == 500) { 1335ae115bc7Smrj /* 1336ae115bc7Smrj * After five seconds, things are probably looking 1337ae115bc7Smrj * a bit bleak - explain the hang. 1338ae115bc7Smrj */ 1339ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1340a3114836SGerry Liu "but not running in the kernel yet", cpuid); 1341ae115bc7Smrj } else if (delays > 2000) { 1342ae115bc7Smrj /* 1343ae115bc7Smrj * We waited at least 20 seconds, bail .. 1344ae115bc7Smrj */ 1345ae115bc7Smrj error = ETIMEDOUT; 1346a3114836SGerry Liu cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1347ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1348ae115bc7Smrj return (error); 1349ae115bc7Smrj } 1350ae115bc7Smrj 1351ae115bc7Smrj /* 1352ae115bc7Smrj * wait at least 10ms, then check again.. 1353ae115bc7Smrj */ 1354ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1355a3114836SGerry Liu tempset = *((volatile cpuset_t *)&procset_slave); 1356ae115bc7Smrj } 1357a3114836SGerry Liu CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1358ae115bc7Smrj 1359ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1360ae115bc7Smrj 1361843e1988Sjohnlev #ifndef __xpv 1362ae115bc7Smrj if (tsc_gethrtime_enable) 1363a3114836SGerry Liu tsc_sync_master(cpuid); 1364843e1988Sjohnlev #endif 1365ae115bc7Smrj 1366ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1367a3114836SGerry Liu (*dtrace_cpu_init)(cpuid); 1368a3114836SGerry Liu } 1369a3114836SGerry Liu 1370a3114836SGerry Liu /* 1371a3114836SGerry Liu * During CPU DR operations, the cpu_lock is held by current 1372a3114836SGerry Liu * (the control) thread. We can't release the cpu_lock here 1373a3114836SGerry Liu * because that will break the CPU DR logic. 1374a3114836SGerry Liu * On the other hand, CPUPM and processor group initialization 1375a3114836SGerry Liu * routines need to access the cpu_lock. So we invoke those 1376a3114836SGerry Liu * routines here on behalf of mp_startup_common(). 1377a3114836SGerry Liu * 1378a3114836SGerry Liu * CPUPM and processor group initialization routines depend 1379a3114836SGerry Liu * on the cpuid probing results. Wait for mp_startup_common() 1380a3114836SGerry Liu * to signal that cpuid probing is done. 1381a3114836SGerry Liu */ 1382a3114836SGerry Liu mp_startup_wait(&procset_slave, cpuid); 1383a3114836SGerry Liu #ifndef __xpv 1384a3114836SGerry Liu cpupm_init(cp); 1385a3114836SGerry Liu #endif 1386a3114836SGerry Liu (void) pg_cpu_init(cp, B_FALSE); 1387a3114836SGerry Liu cpu_set_state(cp); 1388a3114836SGerry Liu mp_startup_signal(&procset_master, cpuid); 1389a3114836SGerry Liu 1390a3114836SGerry Liu return (0); 1391a3114836SGerry Liu } 1392a3114836SGerry Liu 1393a3114836SGerry Liu /* 1394a3114836SGerry Liu * Start a single cpu, assuming that the kernel context is available 1395a3114836SGerry Liu * to successfully start another cpu. 1396a3114836SGerry Liu * 1397a3114836SGerry Liu * (For example, real mode code is mapped into the right place 1398a3114836SGerry Liu * in memory and is ready to be run.) 1399a3114836SGerry Liu */ 1400a3114836SGerry Liu int 1401a3114836SGerry Liu start_cpu(processorid_t who) 1402a3114836SGerry Liu { 1403a3114836SGerry Liu cpu_t *cp; 1404a3114836SGerry Liu int error = 0; 1405a3114836SGerry Liu cpuset_t tempset; 1406a3114836SGerry Liu 1407a3114836SGerry Liu ASSERT(who != 0); 1408a3114836SGerry Liu 1409a3114836SGerry Liu /* 1410a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1411a3114836SGerry Liu * before attempting to start the cpu. 1412a3114836SGerry Liu */ 1413a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1414ae115bc7Smrj /* 1415a3114836SGerry Liu * Kick off a reap in case that helps us with 1416a3114836SGerry Liu * later attempts .. 1417ae115bc7Smrj */ 1418a3114836SGerry Liu kmem_reap(); 1419a3114836SGerry Liu return (ENOMEM); 1420a3114836SGerry Liu } 1421a3114836SGerry Liu 1422a3114836SGerry Liu /* 1423a3114836SGerry Liu * First configure cpu. 1424a3114836SGerry Liu */ 1425a3114836SGerry Liu cp = mp_cpu_configure_common(who, B_TRUE); 1426a3114836SGerry Liu ASSERT(cp != NULL); 1427a3114836SGerry Liu 1428a3114836SGerry Liu /* 1429a3114836SGerry Liu * Then start cpu. 1430a3114836SGerry Liu */ 1431a3114836SGerry Liu error = mp_start_cpu_common(cp, B_TRUE); 1432a3114836SGerry Liu if (error != 0) { 1433a3114836SGerry Liu mp_cpu_unconfigure_common(cp, error); 1434a3114836SGerry Liu return (error); 1435ae115bc7Smrj } 1436ae115bc7Smrj 1437a3114836SGerry Liu mutex_exit(&cpu_lock); 1438a3114836SGerry Liu tempset = cpu_ready_set; 1439a3114836SGerry Liu while (!CPU_IN_SET(tempset, who)) { 1440a3114836SGerry Liu drv_usecwait(1); 1441a3114836SGerry Liu tempset = *((volatile cpuset_t *)&cpu_ready_set); 1442a3114836SGerry Liu } 1443a3114836SGerry Liu mutex_enter(&cpu_lock); 1444ae115bc7Smrj 1445ae115bc7Smrj return (0); 1446ae115bc7Smrj } 14477c478bd9Sstevel@tonic-gate 14487c478bd9Sstevel@tonic-gate void 14497c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 14507c478bd9Sstevel@tonic-gate { 1451a3114836SGerry Liu _NOTE(ARGUNUSED(cprboot)); 1452a3114836SGerry Liu 1453ae115bc7Smrj uint_t who; 1454ae115bc7Smrj uint_t bootcpuid = 0; 14557c478bd9Sstevel@tonic-gate 14567c478bd9Sstevel@tonic-gate /* 14577c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 14587c478bd9Sstevel@tonic-gate */ 14597c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 14607c478bd9Sstevel@tonic-gate 146119397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 146219397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 146319397407SSherry Moore 14647c478bd9Sstevel@tonic-gate /* 14657c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 14667c478bd9Sstevel@tonic-gate */ 14677c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 14687c478bd9Sstevel@tonic-gate 1469ae115bc7Smrj /* 1470ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1471ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1472ae115bc7Smrj * precisely the same reason. 1473ae115bc7Smrj */ 1474ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1475ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1476ae115bc7Smrj 14777c478bd9Sstevel@tonic-gate /* 1478a3114836SGerry Liu * skip the rest of this if 1479a3114836SGerry Liu * . only 1 cpu dectected and system isn't hotplug-capable 1480a3114836SGerry Liu * . not using MP 14817c478bd9Sstevel@tonic-gate */ 1482a3114836SGerry Liu if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1483a3114836SGerry Liu use_mp == 0) { 14847c478bd9Sstevel@tonic-gate if (use_mp == 0) 14857c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 14867c478bd9Sstevel@tonic-gate goto done; 14877c478bd9Sstevel@tonic-gate } 14887c478bd9Sstevel@tonic-gate 14897c478bd9Sstevel@tonic-gate /* 14907c478bd9Sstevel@tonic-gate * perform such initialization as is needed 14917c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 14927c478bd9Sstevel@tonic-gate */ 14937c478bd9Sstevel@tonic-gate cpu_pause_init(); 14947c478bd9Sstevel@tonic-gate 1495f34a7178SJoe Bonasera xc_init_cpu(CPU); /* initialize processor crosscalls */ 14967c478bd9Sstevel@tonic-gate 1497ae115bc7Smrj if (mach_cpucontext_init() != 0) 14987c478bd9Sstevel@tonic-gate goto done; 14997c478bd9Sstevel@tonic-gate 15007c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 15017c478bd9Sstevel@tonic-gate 15025205ae23Snf /* 15035205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 15045205ae23Snf * do their TSC syncs with the same CPU. 15055205ae23Snf */ 15067c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 15077c478bd9Sstevel@tonic-gate 15087c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 150941791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 151041791439Sandrei continue; 1511ae115bc7Smrj ASSERT(who != bootcpuid); 1512b9e93c10SJonathan Haslam 1513b9e93c10SJonathan Haslam mutex_enter(&cpu_lock); 1514a3114836SGerry Liu if (start_cpu(who) != 0) 1515a3114836SGerry Liu CPUSET_DEL(mp_cpus, who); 1516b9e93c10SJonathan Haslam cpu_state_change_notify(who, CPU_SETUP); 1517b9e93c10SJonathan Haslam mutex_exit(&cpu_lock); 15187c478bd9Sstevel@tonic-gate } 15197c478bd9Sstevel@tonic-gate 15202449e17fSsherrym /* Free the space allocated to hold the microcode file */ 1521adc586deSMark Johnson ucode_cleanup(); 15222449e17fSsherrym 15237c478bd9Sstevel@tonic-gate affinity_clear(); 15247c478bd9Sstevel@tonic-gate 1525a3114836SGerry Liu mach_cpucontext_fini(); 1526a3114836SGerry Liu 1527a3114836SGerry Liu done: 1528a3114836SGerry Liu if (get_hwenv() == HW_NATIVE) 1529a3114836SGerry Liu workaround_errata_end(); 1530a3114836SGerry Liu cmi_post_mpstartup(); 1531a3114836SGerry Liu 1532a3114836SGerry Liu if (use_mp && ncpus != boot_max_ncpus) { 153341791439Sandrei cmn_err(CE_NOTE, 1534ae115bc7Smrj "System detected %d cpus, but " 1535ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 1536a3114836SGerry Liu boot_max_ncpus, ncpus); 153741791439Sandrei cmn_err(CE_NOTE, 153841791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 153941791439Sandrei "See eeprom(1M)."); 154041791439Sandrei } 15417c478bd9Sstevel@tonic-gate } 15427c478bd9Sstevel@tonic-gate 15437c478bd9Sstevel@tonic-gate int 15447c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 15457c478bd9Sstevel@tonic-gate { 1546a3114836SGerry Liu cpu_t *cp; 1547a3114836SGerry Liu 1548a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1549a3114836SGerry Liu return (ENOTSUP); 1550a3114836SGerry Liu } 1551a3114836SGerry Liu 1552a3114836SGerry Liu cp = cpu_get(cpuid); 1553a3114836SGerry Liu if (cp != NULL) { 1554a3114836SGerry Liu return (EALREADY); 1555a3114836SGerry Liu } 1556a3114836SGerry Liu 1557a3114836SGerry Liu /* 1558a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1559a3114836SGerry Liu * before attempting to start the cpu. 1560a3114836SGerry Liu */ 1561a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1562a3114836SGerry Liu /* 1563a3114836SGerry Liu * Kick off a reap in case that helps us with 1564a3114836SGerry Liu * later attempts .. 1565a3114836SGerry Liu */ 1566a3114836SGerry Liu kmem_reap(); 1567a3114836SGerry Liu return (ENOMEM); 1568a3114836SGerry Liu } 1569a3114836SGerry Liu 1570a3114836SGerry Liu cp = mp_cpu_configure_common(cpuid, B_FALSE); 1571a3114836SGerry Liu ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1572a3114836SGerry Liu 1573a3114836SGerry Liu return (cp != NULL ? 0 : EAGAIN); 15747c478bd9Sstevel@tonic-gate } 15757c478bd9Sstevel@tonic-gate 15767c478bd9Sstevel@tonic-gate int 15777c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 15787c478bd9Sstevel@tonic-gate { 1579a3114836SGerry Liu cpu_t *cp; 1580a3114836SGerry Liu 1581a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1582a3114836SGerry Liu return (ENOTSUP); 1583a3114836SGerry Liu } else if (cpuid < 0 || cpuid >= max_ncpus) { 1584a3114836SGerry Liu return (EINVAL); 1585a3114836SGerry Liu } 1586a3114836SGerry Liu 1587a3114836SGerry Liu cp = cpu_get(cpuid); 1588a3114836SGerry Liu if (cp == NULL) { 1589a3114836SGerry Liu return (ENODEV); 1590a3114836SGerry Liu } 1591a3114836SGerry Liu mp_cpu_unconfigure_common(cp, 0); 1592a3114836SGerry Liu 1593a3114836SGerry Liu return (0); 15947c478bd9Sstevel@tonic-gate } 15957c478bd9Sstevel@tonic-gate 15967c478bd9Sstevel@tonic-gate /* 15977c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1598498697c5Sdmick * Called from real_mode_start. 1599b4b46911Skchow * 1600a3114836SGerry Liu * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1601a3114836SGerry Liu * mp_startup_common should not call routines (e.g. kmem_free) that could call 1602b4b46911Skchow * hat_unload which requires CPU_READY to be set. 16037c478bd9Sstevel@tonic-gate */ 1604a3114836SGerry Liu static void 1605a3114836SGerry Liu mp_startup_common(boolean_t boot) 16067c478bd9Sstevel@tonic-gate { 1607a3114836SGerry Liu cpu_t *cp = CPU; 1608*7417cfdeSKuriakose Kuruvilla void *new_x86_featureset; 1609a3114836SGerry Liu extern void cpu_event_init_cpu(cpu_t *); 16107c478bd9Sstevel@tonic-gate 161124a74e86Sdmick /* 161224a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 161324a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 161424a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 161524a74e86Sdmick * interrupts, cmn_err, etc. 161624a74e86Sdmick */ 161724a74e86Sdmick 1618a3114836SGerry Liu /* Let the control CPU continue into tsc_sync_master() */ 1619a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 162024a74e86Sdmick 1621843e1988Sjohnlev #ifndef __xpv 162224a74e86Sdmick if (tsc_gethrtime_enable) 162324a74e86Sdmick tsc_sync_slave(); 1624843e1988Sjohnlev #endif 162524a74e86Sdmick 1626498697c5Sdmick /* 1627498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1628498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1629498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1630498697c5Sdmick * before swtch() overwrites it. 1631498697c5Sdmick */ 1632498697c5Sdmick (void) (*ap_mlsetup)(); 1633498697c5Sdmick 1634*7417cfdeSKuriakose Kuruvilla new_x86_featureset = cpuid_pass1(cp); 16357c478bd9Sstevel@tonic-gate 1636843e1988Sjohnlev #ifndef __xpv 16377c478bd9Sstevel@tonic-gate /* 16381d03c31eSjohnlev * Program this cpu's PAT 16397c478bd9Sstevel@tonic-gate */ 1640*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_PAT)) 16411d03c31eSjohnlev pat_sync(); 1642843e1988Sjohnlev #endif 16437c478bd9Sstevel@tonic-gate 1644ae115bc7Smrj /* 1645ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1646ae115bc7Smrj * for the rdtscp instruction. 1647ae115bc7Smrj */ 1648*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 1649ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1650ae115bc7Smrj 16517c478bd9Sstevel@tonic-gate /* 16527c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 16537c478bd9Sstevel@tonic-gate */ 16547c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 16557c478bd9Sstevel@tonic-gate 16567c478bd9Sstevel@tonic-gate /* 16577c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 16587c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 16597c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 16607c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 16617c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 16627c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 16637c478bd9Sstevel@tonic-gate */ 1664ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1665ae115bc7Smrj sti(); 16667c478bd9Sstevel@tonic-gate 16677c478bd9Sstevel@tonic-gate /* 16687c478bd9Sstevel@tonic-gate * Do a sanity check to make sure this new CPU is a sane thing 16697c478bd9Sstevel@tonic-gate * to add to the collection of processors running this system. 16707c478bd9Sstevel@tonic-gate * 16717c478bd9Sstevel@tonic-gate * XXX Clearly this needs to get more sophisticated, if x86 16727c478bd9Sstevel@tonic-gate * systems start to get built out of heterogenous CPUs; as is 16737c478bd9Sstevel@tonic-gate * likely to happen once the number of processors in a configuration 16747c478bd9Sstevel@tonic-gate * gets large enough. 16757c478bd9Sstevel@tonic-gate */ 1676*7417cfdeSKuriakose Kuruvilla if (compare_x86_featureset(x86_featureset, new_x86_featureset) == 1677*7417cfdeSKuriakose Kuruvilla B_FALSE) { 1678*7417cfdeSKuriakose Kuruvilla cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id); 1679*7417cfdeSKuriakose Kuruvilla print_x86_featureset(new_x86_featureset); 16807c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 16817c478bd9Sstevel@tonic-gate } 16827c478bd9Sstevel@tonic-gate 1683f98fbcecSbholler /* 1684f98fbcecSbholler * We do not support cpus with mixed monitor/mwait support if the 1685f98fbcecSbholler * boot cpu supports monitor/mwait. 1686f98fbcecSbholler */ 1687*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) != 1688*7417cfdeSKuriakose Kuruvilla is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) 1689f98fbcecSbholler panic("unsupported mixed cpu monitor/mwait support detected"); 1690f98fbcecSbholler 1691*7417cfdeSKuriakose Kuruvilla free_x86_featureset(new_x86_featureset); 1692*7417cfdeSKuriakose Kuruvilla 16937c478bd9Sstevel@tonic-gate /* 16947c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 16957c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 1696fb2caebeSRandy Fishel * answer of dying horribly. Provided the boot cpu is ok, 16977c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 16987c478bd9Sstevel@tonic-gate */ 16997c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 17007c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 17017c478bd9Sstevel@tonic-gate 1702a3114836SGerry Liu /* 1703a3114836SGerry Liu * We can touch cpu_flags here without acquiring the cpu_lock here 1704a3114836SGerry Liu * because the cpu_lock is held by the control CPU which is running 1705a3114836SGerry Liu * mp_start_cpu_common(). 1706a3114836SGerry Liu * Need to clear CPU_QUIESCED flag before calling any function which 1707a3114836SGerry Liu * may cause thread context switching, such as kmem_alloc() etc. 1708a3114836SGerry Liu * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1709a3114836SGerry Liu * it's set. So the startup thread may have no chance to switch back 1710a3114836SGerry Liu * again if it's switched away with CPU_QUIESCED set. 1711a3114836SGerry Liu */ 1712a3114836SGerry Liu cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1713a3114836SGerry Liu 17147c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 17157c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 17167c478bd9Sstevel@tonic-gate (void) cpuid_pass4(cp); 17177c478bd9Sstevel@tonic-gate 17182449e17fSsherrym /* 1719a3114836SGerry Liu * Correct cpu_idstr and cpu_brandstr on target CPU after 1720a3114836SGerry Liu * cpuid_pass1() is done. 17212449e17fSsherrym */ 1722a3114836SGerry Liu (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1723a3114836SGerry Liu (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 17242449e17fSsherrym 1725a3114836SGerry Liu cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 17267c478bd9Sstevel@tonic-gate 1727e774b42bSBill Holler post_startup_cpu_fixups(); 1728e774b42bSBill Holler 1729a3114836SGerry Liu cpu_event_init_cpu(cp); 1730a3114836SGerry Liu 1731aa7b6435Ssethg /* 1732aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1733a3114836SGerry Liu * later in mp_startup_common may be preempted if the thread owning 1734a3114836SGerry Liu * those locks is continuously executing on other CPUs (for example, 1735a3114836SGerry Liu * this CPU must be preemptible to allow other CPUs to pause it during 1736a3114836SGerry Liu * their startup phases). It's safe to enable preemption here because 1737a3114836SGerry Liu * the CPU state is pretty-much fully constructed. 1738aa7b6435Ssethg */ 1739aa7b6435Ssethg curthread->t_preempt = 0; 1740aa7b6435Ssethg 1741da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1742da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1743da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1744da43ceabSsethg 1745a3114836SGerry Liu pghw_physid_create(cp); 17460e751525SEric Saxe /* 1747a3114836SGerry Liu * Delegate initialization tasks, which need to access the cpu_lock, 1748a3114836SGerry Liu * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1749a3114836SGerry Liu * during CPU DR operations. 17500e751525SEric Saxe */ 1751a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 1752a3114836SGerry Liu mp_startup_wait(&procset_master, cp->cpu_id); 17530e751525SEric Saxe pg_cmt_cpu_startup(cp); 1754a3114836SGerry Liu 1755a3114836SGerry Liu if (boot) { 1756a3114836SGerry Liu mutex_enter(&cpu_lock); 1757a3114836SGerry Liu cp->cpu_flags &= ~CPU_OFFLINE; 1758a3114836SGerry Liu cpu_enable_intr(cp); 1759a3114836SGerry Liu cpu_add_active(cp); 1760a3114836SGerry Liu mutex_exit(&cpu_lock); 1761a3114836SGerry Liu } 17620e751525SEric Saxe 1763afbc4541Ssherrym /* Enable interrupts */ 1764afbc4541Ssherrym (void) spl0(); 17650e751525SEric Saxe 1766a3114836SGerry Liu /* 1767a3114836SGerry Liu * Fill out cpu_ucode_info. Update microcode if necessary. 1768a3114836SGerry Liu */ 1769a3114836SGerry Liu ucode_check(cp); 1770afbc4541Ssherrym 177120c794b3Sgavinm #ifndef __xpv 177220c794b3Sgavinm { 177320c794b3Sgavinm /* 177420c794b3Sgavinm * Set up the CPU module for this CPU. This can't be done 177520c794b3Sgavinm * before this CPU is made CPU_READY, because we may (in 177620c794b3Sgavinm * heterogeneous systems) need to go load another CPU module. 177720c794b3Sgavinm * The act of attempting to load a module may trigger a 177820c794b3Sgavinm * cross-call, which will ASSERT unless this cpu is CPU_READY. 177920c794b3Sgavinm */ 178020c794b3Sgavinm cmi_hdl_t hdl; 17817aec1d6eScindi 178220c794b3Sgavinm if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1783e4b86885SCheng Sean Ye cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 1784*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MCA)) 178520c794b3Sgavinm cmi_mca_init(hdl); 1786a3114836SGerry Liu cp->cpu_m.mcpu_cmi_hdl = hdl; 178720c794b3Sgavinm } 178820c794b3Sgavinm } 178920c794b3Sgavinm #endif /* __xpv */ 17907aec1d6eScindi 17917c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1792ae115bc7Smrj kdi_cpu_init(); 17937c478bd9Sstevel@tonic-gate 17947c478bd9Sstevel@tonic-gate /* 17957c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 17967c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 17977c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 17987c478bd9Sstevel@tonic-gate */ 17997c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 18007c478bd9Sstevel@tonic-gate 1801fa96bd91SMichael Corcoran (void) mach_cpu_create_device_node(cp, NULL); 1802fa96bd91SMichael Corcoran 1803a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1804a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1805a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1806a3114836SGerry Liu cp->cpu_id); 1807a3114836SGerry Liu 18087c478bd9Sstevel@tonic-gate /* 18097c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 18107c478bd9Sstevel@tonic-gate */ 18117c478bd9Sstevel@tonic-gate thread_exit(); 18127c478bd9Sstevel@tonic-gate panic("mp_startup: cannot return"); 18137c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 18147c478bd9Sstevel@tonic-gate } 18157c478bd9Sstevel@tonic-gate 1816a3114836SGerry Liu /* 1817a3114836SGerry Liu * Startup function for 'other' CPUs at boot time (besides boot cpu). 1818a3114836SGerry Liu */ 1819a3114836SGerry Liu static void 1820a3114836SGerry Liu mp_startup_boot(void) 1821a3114836SGerry Liu { 1822a3114836SGerry Liu mp_startup_common(B_TRUE); 1823a3114836SGerry Liu } 1824a3114836SGerry Liu 1825a3114836SGerry Liu /* 1826a3114836SGerry Liu * Startup function for hotplug CPUs at runtime. 1827a3114836SGerry Liu */ 1828a3114836SGerry Liu void 1829a3114836SGerry Liu mp_startup_hotplug(void) 1830a3114836SGerry Liu { 1831a3114836SGerry Liu mp_startup_common(B_FALSE); 1832a3114836SGerry Liu } 18337c478bd9Sstevel@tonic-gate 18347c478bd9Sstevel@tonic-gate /* 18357c478bd9Sstevel@tonic-gate * Start CPU on user request. 18367c478bd9Sstevel@tonic-gate */ 18377c478bd9Sstevel@tonic-gate /* ARGSUSED */ 18387c478bd9Sstevel@tonic-gate int 18397c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 18407c478bd9Sstevel@tonic-gate { 18417c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 18427c478bd9Sstevel@tonic-gate return (0); 18437c478bd9Sstevel@tonic-gate } 18447c478bd9Sstevel@tonic-gate 18457c478bd9Sstevel@tonic-gate /* 18467c478bd9Sstevel@tonic-gate * Stop CPU on user request. 18477c478bd9Sstevel@tonic-gate */ 18487c478bd9Sstevel@tonic-gate int 18497c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 18507c478bd9Sstevel@tonic-gate { 1851d90554ebSdmick extern int cbe_psm_timer_mode; 18527c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1853d90554ebSdmick 1854843e1988Sjohnlev #ifdef __xpv 1855843e1988Sjohnlev /* 1856843e1988Sjohnlev * We can't offline vcpu0. 1857843e1988Sjohnlev */ 1858843e1988Sjohnlev if (cp->cpu_id == 0) 1859843e1988Sjohnlev return (EBUSY); 1860843e1988Sjohnlev #endif 1861843e1988Sjohnlev 1862d90554ebSdmick /* 1863d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1864d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1865d90554ebSdmick */ 1866d90554ebSdmick 1867d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1868843e1988Sjohnlev return (EBUSY); 18697c478bd9Sstevel@tonic-gate 18707c478bd9Sstevel@tonic-gate return (0); 18717c478bd9Sstevel@tonic-gate } 18727c478bd9Sstevel@tonic-gate 18737c478bd9Sstevel@tonic-gate /* 18747c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 18757c478bd9Sstevel@tonic-gate */ 18767c478bd9Sstevel@tonic-gate int 18777c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 18787c478bd9Sstevel@tonic-gate { 18797c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 18807c478bd9Sstevel@tonic-gate return (EBUSY); 18817c478bd9Sstevel@tonic-gate 18827c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 18837c478bd9Sstevel@tonic-gate return (0); 18847c478bd9Sstevel@tonic-gate } 18857c478bd9Sstevel@tonic-gate 18867c478bd9Sstevel@tonic-gate /* 18877c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 18887c478bd9Sstevel@tonic-gate */ 18897c478bd9Sstevel@tonic-gate void 18907c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 18917c478bd9Sstevel@tonic-gate { 18927c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 18937c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 18947c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 18957c478bd9Sstevel@tonic-gate } 18967c478bd9Sstevel@tonic-gate 18977c478bd9Sstevel@tonic-gate void 18987c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 18997aec1d6eScindi { 1900a3114836SGerry Liu #ifdef __xpv 1901a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1902a3114836SGerry Liu #else 1903a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 190420c794b3Sgavinm 1905a3114836SGerry Liu if (hdl != NULL) { 1906a3114836SGerry Liu cmi_hdl_hold(hdl); 1907a3114836SGerry Liu } else { 1908a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1909a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1910a3114836SGerry Liu } 191120c794b3Sgavinm if (hdl != NULL) { 191220c794b3Sgavinm cmi_faulted_enter(hdl); 191320c794b3Sgavinm cmi_hdl_rele(hdl); 191420c794b3Sgavinm } 191520c794b3Sgavinm #endif 19167aec1d6eScindi } 19177c478bd9Sstevel@tonic-gate 19187c478bd9Sstevel@tonic-gate void 19197c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 19207aec1d6eScindi { 1921a3114836SGerry Liu #ifdef __xpv 1922a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1923a3114836SGerry Liu #else 1924a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 192520c794b3Sgavinm 1926a3114836SGerry Liu if (hdl != NULL) { 1927a3114836SGerry Liu cmi_hdl_hold(hdl); 1928a3114836SGerry Liu } else { 1929a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1930a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1931a3114836SGerry Liu } 193220c794b3Sgavinm if (hdl != NULL) { 193320c794b3Sgavinm cmi_faulted_exit(hdl); 193420c794b3Sgavinm cmi_hdl_rele(hdl); 193520c794b3Sgavinm } 193620c794b3Sgavinm #endif 19377aec1d6eScindi } 19387c478bd9Sstevel@tonic-gate 19397c478bd9Sstevel@tonic-gate /* 19407c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 19417c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 19427c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 1943*7417cfdeSKuriakose Kuruvilla * organization rather than speed. We could avoid checking x86_featureset at 1944*7417cfdeSKuriakose Kuruvilla * every context switch by installing different context ops, depending on 1945*7417cfdeSKuriakose Kuruvilla * x86_featureset, at LDT creation time -- one for each combination of fast 1946*7417cfdeSKuriakose Kuruvilla * syscall features. 19477c478bd9Sstevel@tonic-gate */ 19487c478bd9Sstevel@tonic-gate 19497c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 19507c478bd9Sstevel@tonic-gate void 19517c478bd9Sstevel@tonic-gate cpu_fast_syscall_disable(void *arg) 19527c478bd9Sstevel@tonic-gate { 1953*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1954*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 19557c478bd9Sstevel@tonic-gate cpu_sep_disable(); 1956*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1957*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 19587c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 19597c478bd9Sstevel@tonic-gate } 19607c478bd9Sstevel@tonic-gate 19617c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 19627c478bd9Sstevel@tonic-gate void 19637c478bd9Sstevel@tonic-gate cpu_fast_syscall_enable(void *arg) 19647c478bd9Sstevel@tonic-gate { 1965*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1966*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 19677c478bd9Sstevel@tonic-gate cpu_sep_enable(); 1968*7417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1969*7417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 19707c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 19717c478bd9Sstevel@tonic-gate } 19727c478bd9Sstevel@tonic-gate 19737c478bd9Sstevel@tonic-gate static void 19747c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 19757c478bd9Sstevel@tonic-gate { 1976*7417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 19777c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 19787c478bd9Sstevel@tonic-gate 19790ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 19807c478bd9Sstevel@tonic-gate } 19817c478bd9Sstevel@tonic-gate 19827c478bd9Sstevel@tonic-gate static void 19837c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 19847c478bd9Sstevel@tonic-gate { 1985*7417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 19867c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 19877c478bd9Sstevel@tonic-gate 19887c478bd9Sstevel@tonic-gate /* 19897c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 19907c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 19917c478bd9Sstevel@tonic-gate */ 1992ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 19937c478bd9Sstevel@tonic-gate } 19947c478bd9Sstevel@tonic-gate 19957c478bd9Sstevel@tonic-gate static void 19967c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 19977c478bd9Sstevel@tonic-gate { 1998*7417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 19997c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20007c478bd9Sstevel@tonic-gate 20010ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 20020ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 20037c478bd9Sstevel@tonic-gate } 20047c478bd9Sstevel@tonic-gate 20057c478bd9Sstevel@tonic-gate static void 20067c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 20077c478bd9Sstevel@tonic-gate { 2008*7417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 20097c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20107c478bd9Sstevel@tonic-gate 20117c478bd9Sstevel@tonic-gate /* 20127c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 20137c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 20147c478bd9Sstevel@tonic-gate */ 20150ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 20160ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 20177c478bd9Sstevel@tonic-gate } 2018