17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5100b72f4Sandrei * Common Development and Distribution License (the "License"). 6100b72f4Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 21ae115bc7Smrj 227c478bd9Sstevel@tonic-gate /* 237417cfdeSKuriakose Kuruvilla * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. 247c478bd9Sstevel@tonic-gate */ 25a3114836SGerry Liu /* 26a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 27a3114836SGerry Liu * All rights reserved. 28a3114836SGerry Liu */ 29ebb8ac07SRobert Mustacchi /* 30*3ce2fcdcSRobert Mustacchi * Copyright 2015 Joyent, Inc. 31850ad55aSHans Rosenfeld * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 32ebb8ac07SRobert Mustacchi */ 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate #include <sys/types.h> 357c478bd9Sstevel@tonic-gate #include <sys/thread.h> 367c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 37a3114836SGerry Liu #include <sys/cpu.h> 387c478bd9Sstevel@tonic-gate #include <sys/t_lock.h> 397c478bd9Sstevel@tonic-gate #include <sys/param.h> 407c478bd9Sstevel@tonic-gate #include <sys/proc.h> 417c478bd9Sstevel@tonic-gate #include <sys/disp.h> 427c478bd9Sstevel@tonic-gate #include <sys/class.h> 437c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 447c478bd9Sstevel@tonic-gate #include <sys/debug.h> 45a3114836SGerry Liu #include <sys/note.h> 467c478bd9Sstevel@tonic-gate #include <sys/asm_linkage.h> 477c478bd9Sstevel@tonic-gate #include <sys/x_call.h> 487c478bd9Sstevel@tonic-gate #include <sys/systm.h> 497c478bd9Sstevel@tonic-gate #include <sys/var.h> 507c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 517c478bd9Sstevel@tonic-gate #include <vm/hat.h> 527c478bd9Sstevel@tonic-gate #include <vm/as.h> 537c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 54ae115bc7Smrj #include <vm/seg_kp.h> 557c478bd9Sstevel@tonic-gate #include <sys/segments.h> 567c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 577c478bd9Sstevel@tonic-gate #include <sys/stack.h> 587c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h> 597c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 607c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 617c478bd9Sstevel@tonic-gate #include <sys/traptrace.h> 627c478bd9Sstevel@tonic-gate #include <sys/clock.h> 637c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h> 64fb2f18f8Sesaxe #include <sys/pg.h> 65fb2f18f8Sesaxe #include <sys/cmt.h> 667c478bd9Sstevel@tonic-gate #include <sys/dtrace.h> 677c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 687c478bd9Sstevel@tonic-gate #include <sys/fp.h> 697c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 70ae115bc7Smrj #include <sys/kdi_machimpl.h> 717c478bd9Sstevel@tonic-gate #include <vm/hat_i86.h> 72a3114836SGerry Liu #include <vm/vm_dep.h> 737c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 74ef50d8c0Sesaxe #include <sys/pci_cfgspace.h> 75ae115bc7Smrj #include <sys/mach_mmu.h> 76ae115bc7Smrj #include <sys/sysmacros.h> 77843e1988Sjohnlev #if defined(__xpv) 78843e1988Sjohnlev #include <sys/hypervisor.h> 79843e1988Sjohnlev #endif 807aec1d6eScindi #include <sys/cpu_module.h> 81850ad55aSHans Rosenfeld #include <sys/ontrap.h> 827c478bd9Sstevel@tonic-gate 837c478bd9Sstevel@tonic-gate struct cpu cpus[1]; /* CPU data */ 847c478bd9Sstevel@tonic-gate struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 85a3114836SGerry Liu struct cpu *cpu_free_list; /* list for released CPUs */ 867c478bd9Sstevel@tonic-gate cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 877c478bd9Sstevel@tonic-gate 88a3114836SGerry Liu #define cpu_next_free cpu_prev 89a3114836SGerry Liu 907c478bd9Sstevel@tonic-gate /* 91ae115bc7Smrj * Useful for disabling MP bring-up on a MP capable system. 927c478bd9Sstevel@tonic-gate */ 937c478bd9Sstevel@tonic-gate int use_mp = 1; 947c478bd9Sstevel@tonic-gate 9541791439Sandrei /* 96ae115bc7Smrj * to be set by a PSM to indicate what cpus 97ae115bc7Smrj * are sitting around on the system. 9841791439Sandrei */ 99ae115bc7Smrj cpuset_t mp_cpus; 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate /* 1027c478bd9Sstevel@tonic-gate * This variable is used by the hat layer to decide whether or not 1037c478bd9Sstevel@tonic-gate * critical sections are needed to prevent race conditions. For sun4m, 1047c478bd9Sstevel@tonic-gate * this variable is set once enough MP initialization has been done in 1057c478bd9Sstevel@tonic-gate * order to allow cross calls. 1067c478bd9Sstevel@tonic-gate */ 107ae115bc7Smrj int flushes_require_xcalls; 108a563a037Sbholler 109a563a037Sbholler cpuset_t cpu_ready_set; /* initialized in startup() */ 1107c478bd9Sstevel@tonic-gate 111a3114836SGerry Liu static void mp_startup_boot(void); 112a3114836SGerry Liu static void mp_startup_hotplug(void); 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate static void cpu_sep_enable(void); 1157c478bd9Sstevel@tonic-gate static void cpu_sep_disable(void); 1167c478bd9Sstevel@tonic-gate static void cpu_asysc_enable(void); 1177c478bd9Sstevel@tonic-gate static void cpu_asysc_disable(void); 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate /* 1207c478bd9Sstevel@tonic-gate * Init CPU info - get CPU type info for processor_info system call. 1217c478bd9Sstevel@tonic-gate */ 1227c478bd9Sstevel@tonic-gate void 1237c478bd9Sstevel@tonic-gate init_cpu_info(struct cpu *cp) 1247c478bd9Sstevel@tonic-gate { 1257c478bd9Sstevel@tonic-gate processor_info_t *pi = &cp->cpu_type_info; 1267c478bd9Sstevel@tonic-gate 1277c478bd9Sstevel@tonic-gate /* 1287c478bd9Sstevel@tonic-gate * Get clock-frequency property for the CPU. 1297c478bd9Sstevel@tonic-gate */ 1307c478bd9Sstevel@tonic-gate pi->pi_clock = cpu_freq; 1317c478bd9Sstevel@tonic-gate 1325cff7825Smh /* 1335cff7825Smh * Current frequency in Hz. 1345cff7825Smh */ 135cf74e62bSmh cp->cpu_curr_clock = cpu_freq_hz; 1365cff7825Smh 13737d22dc0SAnup Pemmaiah /* 13837d22dc0SAnup Pemmaiah * Supported frequencies. 13937d22dc0SAnup Pemmaiah */ 14037d22dc0SAnup Pemmaiah if (cp->cpu_supp_freqs == NULL) { 14137d22dc0SAnup Pemmaiah cpu_set_supp_freqs(cp, NULL); 14237d22dc0SAnup Pemmaiah } 14337d22dc0SAnup Pemmaiah 1447c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_processor_type, "i386"); 1457c478bd9Sstevel@tonic-gate if (fpu_exists) 1467c478bd9Sstevel@tonic-gate (void) strcpy(pi->pi_fputypes, "i387 compatible"); 1477c478bd9Sstevel@tonic-gate 148a3114836SGerry Liu cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 149a3114836SGerry Liu cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP); 1507c478bd9Sstevel@tonic-gate 151a3114836SGerry Liu /* 152a3114836SGerry Liu * If called for the BSP, cp is equal to current CPU. 153a3114836SGerry Liu * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info 154a3114836SGerry Liu * of current CPU as default values for cpu_idstr and cpu_brandstr. 155a3114836SGerry Liu * They will be corrected in mp_startup_common() after cpuid_pass1() 156a3114836SGerry Liu * has been invoked on target CPU. 157a3114836SGerry Liu */ 158a3114836SGerry Liu (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN); 159a3114836SGerry Liu (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN); 1607c478bd9Sstevel@tonic-gate } 1617c478bd9Sstevel@tonic-gate 1627c478bd9Sstevel@tonic-gate /* 1637c478bd9Sstevel@tonic-gate * Configure syscall support on this CPU. 1647c478bd9Sstevel@tonic-gate */ 1657c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1662df1fe9cSrandyf void 1677c478bd9Sstevel@tonic-gate init_cpu_syscall(struct cpu *cp) 1687c478bd9Sstevel@tonic-gate { 1697c478bd9Sstevel@tonic-gate kpreempt_disable(); 1707c478bd9Sstevel@tonic-gate 1717c478bd9Sstevel@tonic-gate #if defined(__amd64) 1727417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 1737417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) { 174*3ce2fcdcSRobert Mustacchi uint64_t flags; 1757c478bd9Sstevel@tonic-gate 1767c478bd9Sstevel@tonic-gate #if !defined(__lint) 1777c478bd9Sstevel@tonic-gate /* 1787c478bd9Sstevel@tonic-gate * The syscall instruction imposes a certain ordering on 1797c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 1807c478bd9Sstevel@tonic-gate * here. 1817c478bd9Sstevel@tonic-gate */ 1827c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 1837c478bd9Sstevel@tonic-gate ASSERT(UDS_SEL == U32CS_SEL + 8); 1847c478bd9Sstevel@tonic-gate ASSERT(UCS_SEL == U32CS_SEL + 16); 1857c478bd9Sstevel@tonic-gate #endif 1867c478bd9Sstevel@tonic-gate /* 1877c478bd9Sstevel@tonic-gate * Turn syscall/sysret extensions on. 1887c478bd9Sstevel@tonic-gate */ 1897c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 1907c478bd9Sstevel@tonic-gate 1917c478bd9Sstevel@tonic-gate /* 1927c478bd9Sstevel@tonic-gate * Program the magic registers .. 1937c478bd9Sstevel@tonic-gate */ 194ae115bc7Smrj wrmsr(MSR_AMD_STAR, 195ae115bc7Smrj ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 1960ac7d7d8Skucharsk wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 1970ac7d7d8Skucharsk wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 1987c478bd9Sstevel@tonic-gate 1997c478bd9Sstevel@tonic-gate /* 2007c478bd9Sstevel@tonic-gate * This list of flags is masked off the incoming 2017c478bd9Sstevel@tonic-gate * %rfl when we enter the kernel. 2027c478bd9Sstevel@tonic-gate */ 203*3ce2fcdcSRobert Mustacchi flags = PS_IE | PS_T; 204*3ce2fcdcSRobert Mustacchi if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE) 205*3ce2fcdcSRobert Mustacchi flags |= PS_ACHK; 206*3ce2fcdcSRobert Mustacchi wrmsr(MSR_AMD_SFMASK, flags); 2077c478bd9Sstevel@tonic-gate } 2087c478bd9Sstevel@tonic-gate #endif 2097c478bd9Sstevel@tonic-gate 2107c478bd9Sstevel@tonic-gate /* 2117c478bd9Sstevel@tonic-gate * On 32-bit kernels, we use sysenter/sysexit because it's too 2127c478bd9Sstevel@tonic-gate * hard to use syscall/sysret, and it is more portable anyway. 2137c478bd9Sstevel@tonic-gate * 2147c478bd9Sstevel@tonic-gate * On 64-bit kernels on Nocona machines, the 32-bit syscall 2157c478bd9Sstevel@tonic-gate * variant isn't available to 32-bit applications, but sysenter is. 2167c478bd9Sstevel@tonic-gate */ 2177417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 2187417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) { 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate #if !defined(__lint) 2217c478bd9Sstevel@tonic-gate /* 2227c478bd9Sstevel@tonic-gate * The sysenter instruction imposes a certain ordering on 2237c478bd9Sstevel@tonic-gate * segment selectors, so we double-check that ordering 2247c478bd9Sstevel@tonic-gate * here. See "sysenter" in Intel document 245471-012, "IA-32 2257c478bd9Sstevel@tonic-gate * Intel Architecture Software Developer's Manual Volume 2: 2267c478bd9Sstevel@tonic-gate * Instruction Set Reference" 2277c478bd9Sstevel@tonic-gate */ 2287c478bd9Sstevel@tonic-gate ASSERT(KDS_SEL == KCS_SEL + 8); 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 2317c478bd9Sstevel@tonic-gate ASSERT32(UDS_SEL == UCS_SEL + 8); 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 2347c478bd9Sstevel@tonic-gate ASSERT64(UDS_SEL == U32CS_SEL + 8); 2357c478bd9Sstevel@tonic-gate #endif 2367c478bd9Sstevel@tonic-gate 2377c478bd9Sstevel@tonic-gate cpu_sep_enable(); 2387c478bd9Sstevel@tonic-gate 2397c478bd9Sstevel@tonic-gate /* 2407c478bd9Sstevel@tonic-gate * resume() sets this value to the base of the threads stack 2417c478bd9Sstevel@tonic-gate * via a context handler. 2427c478bd9Sstevel@tonic-gate */ 243ae115bc7Smrj wrmsr(MSR_INTC_SEP_ESP, 0); 2440ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 2457c478bd9Sstevel@tonic-gate } 2467c478bd9Sstevel@tonic-gate 2477c478bd9Sstevel@tonic-gate kpreempt_enable(); 2487c478bd9Sstevel@tonic-gate } 2497c478bd9Sstevel@tonic-gate 2507c478bd9Sstevel@tonic-gate /* 2517c478bd9Sstevel@tonic-gate * Multiprocessor initialization. 2527c478bd9Sstevel@tonic-gate * 2537c478bd9Sstevel@tonic-gate * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 2547c478bd9Sstevel@tonic-gate * startup and idle threads for the specified CPU. 255a3114836SGerry Liu * Parameter boot is true for boot time operations and is false for CPU 256a3114836SGerry Liu * DR operations. 2577c478bd9Sstevel@tonic-gate */ 258a3114836SGerry Liu static struct cpu * 259a3114836SGerry Liu mp_cpu_configure_common(int cpun, boolean_t boot) 2607c478bd9Sstevel@tonic-gate { 2617c478bd9Sstevel@tonic-gate struct cpu *cp; 2627c478bd9Sstevel@tonic-gate kthread_id_t tp; 2637c478bd9Sstevel@tonic-gate caddr_t sp; 2647c478bd9Sstevel@tonic-gate proc_t *procp; 265843e1988Sjohnlev #if !defined(__xpv) 2665b8a6efeSbholler extern int idle_cpu_prefer_mwait; 2670e751525SEric Saxe extern void cpu_idle_mwait(); 268843e1988Sjohnlev #endif 2697c478bd9Sstevel@tonic-gate extern void idle(); 2700e751525SEric Saxe extern void cpu_idle(); 2717c478bd9Sstevel@tonic-gate 2727c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 2737c478bd9Sstevel@tonic-gate trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 2747c478bd9Sstevel@tonic-gate #endif 2757c478bd9Sstevel@tonic-gate 276a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 2777c478bd9Sstevel@tonic-gate ASSERT(cpun < NCPU && cpu[cpun] == NULL); 2787c478bd9Sstevel@tonic-gate 279a3114836SGerry Liu if (cpu_free_list == NULL) { 280a3114836SGerry Liu cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 281a3114836SGerry Liu } else { 282a3114836SGerry Liu cp = cpu_free_list; 283a3114836SGerry Liu cpu_free_list = cp->cpu_next_free; 284a3114836SGerry Liu } 285f98fbcecSbholler 2863006ae82SFrank Van Der Linden cp->cpu_m.mcpu_istamp = cpun << 16; 2873006ae82SFrank Van Der Linden 288a3114836SGerry Liu /* Create per CPU specific threads in the process p0. */ 289a3114836SGerry Liu procp = &p0; 2907c478bd9Sstevel@tonic-gate 2917c478bd9Sstevel@tonic-gate /* 2927c478bd9Sstevel@tonic-gate * Initialize the dispatcher first. 2937c478bd9Sstevel@tonic-gate */ 2947c478bd9Sstevel@tonic-gate disp_cpu_init(cp); 2957c478bd9Sstevel@tonic-gate 296affbd3ccSkchow cpu_vm_data_init(cp); 297affbd3ccSkchow 2987c478bd9Sstevel@tonic-gate /* 2997c478bd9Sstevel@tonic-gate * Allocate and initialize the startup thread for this CPU. 3007c478bd9Sstevel@tonic-gate * Interrupt and process switch stacks get allocated later 3017c478bd9Sstevel@tonic-gate * when the CPU starts running. 3027c478bd9Sstevel@tonic-gate */ 3037c478bd9Sstevel@tonic-gate tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 3047c478bd9Sstevel@tonic-gate TS_STOPPED, maxclsyspri); 3057c478bd9Sstevel@tonic-gate 3067c478bd9Sstevel@tonic-gate /* 3077c478bd9Sstevel@tonic-gate * Set state to TS_ONPROC since this thread will start running 3087c478bd9Sstevel@tonic-gate * as soon as the CPU comes online. 3097c478bd9Sstevel@tonic-gate * 3107c478bd9Sstevel@tonic-gate * All the other fields of the thread structure are setup by 3117c478bd9Sstevel@tonic-gate * thread_create(). 3127c478bd9Sstevel@tonic-gate */ 3137c478bd9Sstevel@tonic-gate THREAD_ONPROC(tp, cp); 3147c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3157c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3167c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3177c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3187c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3197c478bd9Sstevel@tonic-gate 3207c478bd9Sstevel@tonic-gate /* 321a3114836SGerry Liu * Setup thread to start in mp_startup_common. 3227c478bd9Sstevel@tonic-gate */ 3237c478bd9Sstevel@tonic-gate sp = tp->t_stk; 3247c478bd9Sstevel@tonic-gate tp->t_sp = (uintptr_t)(sp - MINFRAME); 325ae115bc7Smrj #if defined(__amd64) 326ae115bc7Smrj tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 327ae115bc7Smrj #endif 328a3114836SGerry Liu /* 329a3114836SGerry Liu * Setup thread start entry point for boot or hotplug. 330a3114836SGerry Liu */ 331a3114836SGerry Liu if (boot) { 332a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_boot; 333a3114836SGerry Liu } else { 334a3114836SGerry Liu tp->t_pc = (uintptr_t)mp_startup_hotplug; 335a3114836SGerry Liu } 3367c478bd9Sstevel@tonic-gate 3377c478bd9Sstevel@tonic-gate cp->cpu_id = cpun; 3387c478bd9Sstevel@tonic-gate cp->cpu_self = cp; 3397c478bd9Sstevel@tonic-gate cp->cpu_thread = tp; 3407c478bd9Sstevel@tonic-gate cp->cpu_lwp = NULL; 3417c478bd9Sstevel@tonic-gate cp->cpu_dispthread = tp; 3427c478bd9Sstevel@tonic-gate cp->cpu_dispatch_pri = DISP_PRIO(tp); 3437c478bd9Sstevel@tonic-gate 344da43ceabSsethg /* 345da43ceabSsethg * cpu_base_spl must be set explicitly here to prevent any blocking 346a3114836SGerry Liu * operations in mp_startup_common from causing the spl of the cpu 347a3114836SGerry Liu * to drop to 0 (allowing device interrupts before we're ready) in 348a3114836SGerry Liu * resume(). 349da43ceabSsethg * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 350da43ceabSsethg * As an extra bit of security on DEBUG kernels, this is enforced with 351a3114836SGerry Liu * an assertion in mp_startup_common() -- before cpu_base_spl is set 352a3114836SGerry Liu * to its proper value. 353da43ceabSsethg */ 354da43ceabSsethg cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 355da43ceabSsethg 3567c478bd9Sstevel@tonic-gate /* 3577c478bd9Sstevel@tonic-gate * Now, initialize per-CPU idle thread for this CPU. 3587c478bd9Sstevel@tonic-gate */ 3597c478bd9Sstevel@tonic-gate tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 3607c478bd9Sstevel@tonic-gate 3617c478bd9Sstevel@tonic-gate cp->cpu_idle_thread = tp; 3627c478bd9Sstevel@tonic-gate 3637c478bd9Sstevel@tonic-gate tp->t_preempt = 1; 3647c478bd9Sstevel@tonic-gate tp->t_bound_cpu = cp; 3657c478bd9Sstevel@tonic-gate tp->t_affinitycnt = 1; 3667c478bd9Sstevel@tonic-gate tp->t_cpu = cp; 3677c478bd9Sstevel@tonic-gate tp->t_disp_queue = cp->cpu_disp; 3687c478bd9Sstevel@tonic-gate 369394b433dSesaxe /* 370fb2f18f8Sesaxe * Bootstrap the CPU's PG data 371394b433dSesaxe */ 372fb2f18f8Sesaxe pg_cpu_bootstrap(cp); 373394b433dSesaxe 3747c478bd9Sstevel@tonic-gate /* 375ae115bc7Smrj * Perform CPC initialization on the new CPU. 3767c478bd9Sstevel@tonic-gate */ 3777c478bd9Sstevel@tonic-gate kcpc_hw_init(cp); 3787c478bd9Sstevel@tonic-gate 3797c478bd9Sstevel@tonic-gate /* 3807c478bd9Sstevel@tonic-gate * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 3817c478bd9Sstevel@tonic-gate * for each CPU. 3827c478bd9Sstevel@tonic-gate */ 3837c478bd9Sstevel@tonic-gate setup_vaddr_for_ppcopy(cp); 3847c478bd9Sstevel@tonic-gate 3857c478bd9Sstevel@tonic-gate /* 386ae115bc7Smrj * Allocate page for new GDT and initialize from current GDT. 3877c478bd9Sstevel@tonic-gate */ 388ae115bc7Smrj #if !defined(__lint) 389ae115bc7Smrj ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 390ae115bc7Smrj #endif 3910cfdb603Sjosephb cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 3920cfdb603Sjosephb bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT)); 3937c478bd9Sstevel@tonic-gate 394ae115bc7Smrj #if defined(__i386) 3957c478bd9Sstevel@tonic-gate /* 3967c478bd9Sstevel@tonic-gate * setup kernel %gs. 3977c478bd9Sstevel@tonic-gate */ 3987c478bd9Sstevel@tonic-gate set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 3997c478bd9Sstevel@tonic-gate SEL_KPL, 0, 1); 400ae115bc7Smrj #endif 4017c478bd9Sstevel@tonic-gate 4027c478bd9Sstevel@tonic-gate /* 4037c478bd9Sstevel@tonic-gate * If we have more than one node, each cpu gets a copy of IDT 4047c478bd9Sstevel@tonic-gate * local to its node. If this is a Pentium box, we use cpu 0's 4057c478bd9Sstevel@tonic-gate * IDT. cpu 0's IDT has been made read-only to workaround the 4067c478bd9Sstevel@tonic-gate * cmpxchgl register bug 4077c478bd9Sstevel@tonic-gate */ 4087c478bd9Sstevel@tonic-gate if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 4090cfdb603Sjosephb #if !defined(__lint) 4100cfdb603Sjosephb ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE); 4110cfdb603Sjosephb #endif 4120cfdb603Sjosephb cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP); 4130cfdb603Sjosephb bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE); 414ae115bc7Smrj } else { 4150cfdb603Sjosephb cp->cpu_idt = CPU->cpu_idt; 4167c478bd9Sstevel@tonic-gate } 4177c478bd9Sstevel@tonic-gate 4187c478bd9Sstevel@tonic-gate /* 419ae115bc7Smrj * alloc space for cpuid info 4207c478bd9Sstevel@tonic-gate */ 421ae115bc7Smrj cpuid_alloc_space(cp); 422a3114836SGerry Liu #if !defined(__xpv) 4237417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) && 4247417cfdeSKuriakose Kuruvilla idle_cpu_prefer_mwait) { 425a3114836SGerry Liu cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp); 426a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait; 427a3114836SGerry Liu } else 428a3114836SGerry Liu #endif 429a3114836SGerry Liu cp->cpu_m.mcpu_idle_cpu = cpu_idle; 430a3114836SGerry Liu 431a3114836SGerry Liu init_cpu_info(cp); 4327c478bd9Sstevel@tonic-gate 4332449e17fSsherrym /* 4342449e17fSsherrym * alloc space for ucode_info 4352449e17fSsherrym */ 4362449e17fSsherrym ucode_alloc_space(cp); 437f34a7178SJoe Bonasera xc_init_cpu(cp); 438ae115bc7Smrj hat_cpu_online(cp); 4397c478bd9Sstevel@tonic-gate 4407c478bd9Sstevel@tonic-gate #ifdef TRAPTRACE 4417c478bd9Sstevel@tonic-gate /* 442ae115bc7Smrj * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 4437c478bd9Sstevel@tonic-gate */ 4447c478bd9Sstevel@tonic-gate ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 4457c478bd9Sstevel@tonic-gate ttc->ttc_next = ttc->ttc_first; 4467c478bd9Sstevel@tonic-gate ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 4477c478bd9Sstevel@tonic-gate #endif 448a3114836SGerry Liu 4497c478bd9Sstevel@tonic-gate /* 4507c478bd9Sstevel@tonic-gate * Record that we have another CPU. 4517c478bd9Sstevel@tonic-gate */ 4527c478bd9Sstevel@tonic-gate /* 4537c478bd9Sstevel@tonic-gate * Initialize the interrupt threads for this CPU 4547c478bd9Sstevel@tonic-gate */ 455100b72f4Sandrei cpu_intr_alloc(cp, NINTR_THREADS); 456a3114836SGerry Liu 457a3114836SGerry Liu cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF; 458a3114836SGerry Liu cpu_set_state(cp); 459a3114836SGerry Liu 4607c478bd9Sstevel@tonic-gate /* 4617c478bd9Sstevel@tonic-gate * Add CPU to list of available CPUs. It'll be on the active list 462a3114836SGerry Liu * after mp_startup_common(). 4637c478bd9Sstevel@tonic-gate */ 4647c478bd9Sstevel@tonic-gate cpu_add_unit(cp); 465ae115bc7Smrj 466ae115bc7Smrj return (cp); 467ae115bc7Smrj } 468ae115bc7Smrj 469ae115bc7Smrj /* 470a3114836SGerry Liu * Undo what was done in mp_cpu_configure_common 471ae115bc7Smrj */ 472ae115bc7Smrj static void 473a3114836SGerry Liu mp_cpu_unconfigure_common(struct cpu *cp, int error) 474ae115bc7Smrj { 475a3114836SGerry Liu ASSERT(MUTEX_HELD(&cpu_lock)); 476ae115bc7Smrj 477ae115bc7Smrj /* 478ae115bc7Smrj * Remove the CPU from the list of available CPUs. 479ae115bc7Smrj */ 480ae115bc7Smrj cpu_del_unit(cp->cpu_id); 481ae115bc7Smrj 482ae115bc7Smrj if (error == ETIMEDOUT) { 483ae115bc7Smrj /* 484ae115bc7Smrj * The cpu was started, but never *seemed* to run any 485ae115bc7Smrj * code in the kernel; it's probably off spinning in its 486ae115bc7Smrj * own private world, though with potential references to 487ae115bc7Smrj * our kmem-allocated IDTs and GDTs (for example). 488ae115bc7Smrj * 489ae115bc7Smrj * Worse still, it may actually wake up some time later, 490ae115bc7Smrj * so rather than guess what it might or might not do, we 491ae115bc7Smrj * leave the fundamental data structures intact. 492ae115bc7Smrj */ 493ae115bc7Smrj cp->cpu_flags = 0; 494ae115bc7Smrj return; 495ae115bc7Smrj } 496ae115bc7Smrj 497ae115bc7Smrj /* 498ae115bc7Smrj * At this point, the only threads bound to this CPU should 499ae115bc7Smrj * special per-cpu threads: it's idle thread, it's pause threads, 500ae115bc7Smrj * and it's interrupt threads. Clean these up. 501ae115bc7Smrj */ 502ae115bc7Smrj cpu_destroy_bound_threads(cp); 503ae115bc7Smrj cp->cpu_idle_thread = NULL; 504ae115bc7Smrj 505ae115bc7Smrj /* 506ae115bc7Smrj * Free the interrupt stack. 507ae115bc7Smrj */ 508ae115bc7Smrj segkp_release(segkp, 509ae115bc7Smrj cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 510a3114836SGerry Liu cp->cpu_intr_stack = NULL; 511ae115bc7Smrj 512ae115bc7Smrj #ifdef TRAPTRACE 513ae115bc7Smrj /* 514ae115bc7Smrj * Discard the trap trace buffer 515ae115bc7Smrj */ 516ae115bc7Smrj { 517ae115bc7Smrj trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 518ae115bc7Smrj 519ae115bc7Smrj kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 520ae115bc7Smrj ttc->ttc_first = NULL; 521ae115bc7Smrj } 522ae115bc7Smrj #endif 523ae115bc7Smrj 524ae115bc7Smrj hat_cpu_offline(cp); 525ae115bc7Smrj 5262449e17fSsherrym ucode_free_space(cp); 5272449e17fSsherrym 528a3114836SGerry Liu /* Free CPU ID string and brand string. */ 529a3114836SGerry Liu if (cp->cpu_idstr) { 530a3114836SGerry Liu kmem_free(cp->cpu_idstr, CPU_IDSTRLEN); 531a3114836SGerry Liu cp->cpu_idstr = NULL; 532a3114836SGerry Liu } 533a3114836SGerry Liu if (cp->cpu_brandstr) { 534a3114836SGerry Liu kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN); 535a3114836SGerry Liu cp->cpu_brandstr = NULL; 536a3114836SGerry Liu } 537a3114836SGerry Liu 538a3114836SGerry Liu #if !defined(__xpv) 539a3114836SGerry Liu if (cp->cpu_m.mcpu_mwait != NULL) { 540a3114836SGerry Liu cpuid_mwait_free(cp); 541a3114836SGerry Liu cp->cpu_m.mcpu_mwait = NULL; 542a3114836SGerry Liu } 543a3114836SGerry Liu #endif 544a3114836SGerry Liu cpuid_free_space(cp); 545a3114836SGerry Liu 5460cfdb603Sjosephb if (cp->cpu_idt != CPU->cpu_idt) 5470cfdb603Sjosephb kmem_free(cp->cpu_idt, PAGESIZE); 5480cfdb603Sjosephb cp->cpu_idt = NULL; 549ae115bc7Smrj 5500cfdb603Sjosephb kmem_free(cp->cpu_gdt, PAGESIZE); 5510cfdb603Sjosephb cp->cpu_gdt = NULL; 552ae115bc7Smrj 553a3114836SGerry Liu if (cp->cpu_supp_freqs != NULL) { 554a3114836SGerry Liu size_t len = strlen(cp->cpu_supp_freqs) + 1; 555a3114836SGerry Liu kmem_free(cp->cpu_supp_freqs, len); 556a3114836SGerry Liu cp->cpu_supp_freqs = NULL; 557a3114836SGerry Liu } 558a3114836SGerry Liu 559ae115bc7Smrj teardown_vaddr_for_ppcopy(cp); 560ae115bc7Smrj 561ae115bc7Smrj kcpc_hw_fini(cp); 562ae115bc7Smrj 563ae115bc7Smrj cp->cpu_dispthread = NULL; 564ae115bc7Smrj cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 565ae115bc7Smrj 566ae115bc7Smrj cpu_vm_data_destroy(cp); 567ae115bc7Smrj 568a3114836SGerry Liu xc_fini_cpu(cp); 569ae115bc7Smrj disp_cpu_fini(cp); 570ae115bc7Smrj 571a3114836SGerry Liu ASSERT(cp != CPU0); 572a3114836SGerry Liu bzero(cp, sizeof (*cp)); 573a3114836SGerry Liu cp->cpu_next_free = cpu_free_list; 574a3114836SGerry Liu cpu_free_list = cp; 5757c478bd9Sstevel@tonic-gate } 5767c478bd9Sstevel@tonic-gate 5777c478bd9Sstevel@tonic-gate /* 5787c478bd9Sstevel@tonic-gate * Apply workarounds for known errata, and warn about those that are absent. 5797c478bd9Sstevel@tonic-gate * 5807c478bd9Sstevel@tonic-gate * System vendors occasionally create configurations which contain different 5817c478bd9Sstevel@tonic-gate * revisions of the CPUs that are almost but not exactly the same. At the 5827c478bd9Sstevel@tonic-gate * time of writing, this meant that their clock rates were the same, their 5837c478bd9Sstevel@tonic-gate * feature sets were the same, but the required workaround were -not- 5847c478bd9Sstevel@tonic-gate * necessarily the same. So, this routine is invoked on -every- CPU soon 5857c478bd9Sstevel@tonic-gate * after starting to make sure that the resulting system contains the most 5867c478bd9Sstevel@tonic-gate * pessimal set of workarounds needed to cope with *any* of the CPUs in the 5877c478bd9Sstevel@tonic-gate * system. 5887c478bd9Sstevel@tonic-gate * 589ef50d8c0Sesaxe * workaround_errata is invoked early in mlsetup() for CPU 0, and in 590a3114836SGerry Liu * mp_startup_common() for all slave CPUs. Slaves process workaround_errata 591a3114836SGerry Liu * prior to acknowledging their readiness to the master, so this routine will 592ef50d8c0Sesaxe * never be executed by multiple CPUs in parallel, thus making updates to 593ef50d8c0Sesaxe * global data safe. 594ef50d8c0Sesaxe * 5952201b277Skucharsk * These workarounds are based on Rev 3.57 of the Revision Guide for 5962201b277Skucharsk * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 5977c478bd9Sstevel@tonic-gate */ 5987c478bd9Sstevel@tonic-gate 599ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 600ae115bc7Smrj int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 601ae115bc7Smrj #endif 602ae115bc7Smrj 6037c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 6047c478bd9Sstevel@tonic-gate int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 6057c478bd9Sstevel@tonic-gate #endif 6067c478bd9Sstevel@tonic-gate 6077c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 6087c478bd9Sstevel@tonic-gate int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 6097c478bd9Sstevel@tonic-gate #endif 6107c478bd9Sstevel@tonic-gate 611ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 612ae115bc7Smrj int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 613ae115bc7Smrj #endif 614ae115bc7Smrj 6157c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 6167c478bd9Sstevel@tonic-gate int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 6177c478bd9Sstevel@tonic-gate #endif 6187c478bd9Sstevel@tonic-gate 619ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 620ae115bc7Smrj int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 621ae115bc7Smrj #endif 622ae115bc7Smrj 6237c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 6247c478bd9Sstevel@tonic-gate int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 6257c478bd9Sstevel@tonic-gate #endif 6267c478bd9Sstevel@tonic-gate 6277c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 6287c478bd9Sstevel@tonic-gate int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 6297c478bd9Sstevel@tonic-gate #endif 6307c478bd9Sstevel@tonic-gate 6317c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 6327c478bd9Sstevel@tonic-gate int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 6337c478bd9Sstevel@tonic-gate #endif 6347c478bd9Sstevel@tonic-gate 6357c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 6367c478bd9Sstevel@tonic-gate int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 6377c478bd9Sstevel@tonic-gate #endif 6387c478bd9Sstevel@tonic-gate 6392201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 6402201b277Skucharsk int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 6412201b277Skucharsk #endif 6427c478bd9Sstevel@tonic-gate 643ef50d8c0Sesaxe #if defined(OPTERON_WORKAROUND_6336786) 644ef50d8c0Sesaxe int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 645ef50d8c0Sesaxe int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 646ef50d8c0Sesaxe #endif 647ef50d8c0Sesaxe 648ee88d2b9Skchow #if defined(OPTERON_WORKAROUND_6323525) 649ee88d2b9Skchow int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 650ee88d2b9Skchow #endif 651ee88d2b9Skchow 652512cf780Skchow #if defined(OPTERON_ERRATUM_298) 653512cf780Skchow int opteron_erratum_298; 654512cf780Skchow #endif 655512cf780Skchow 6565e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 6575e54b56dSHans Rosenfeld int opteron_erratum_721; 6585e54b56dSHans Rosenfeld #endif 6595e54b56dSHans Rosenfeld 660ae115bc7Smrj static void 661ae115bc7Smrj workaround_warning(cpu_t *cp, uint_t erratum) 662ae115bc7Smrj { 663ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 664ae115bc7Smrj cp->cpu_id, erratum); 665ae115bc7Smrj } 666ae115bc7Smrj 667ae115bc7Smrj static void 668ae115bc7Smrj workaround_applied(uint_t erratum) 669ae115bc7Smrj { 670ae115bc7Smrj if (erratum > 1000000) 671ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 672ae115bc7Smrj erratum); 673ae115bc7Smrj else 674ae115bc7Smrj cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 675ae115bc7Smrj erratum); 676ae115bc7Smrj } 677ae115bc7Smrj 678ae115bc7Smrj static void 679ae115bc7Smrj msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 680ae115bc7Smrj { 681ae115bc7Smrj cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 682ae115bc7Smrj cp->cpu_id, rw, msr, error); 683ae115bc7Smrj } 6847c478bd9Sstevel@tonic-gate 68592564cb1Sesaxe /* 686d2aeaf66SEric Saxe * Determine the number of nodes in a Hammer / Greyhound / Griffin family 687d2aeaf66SEric Saxe * system. 68892564cb1Sesaxe */ 68992564cb1Sesaxe static uint_t 69092564cb1Sesaxe opteron_get_nnodes(void) 69192564cb1Sesaxe { 69292564cb1Sesaxe static uint_t nnodes = 0; 69392564cb1Sesaxe 694d2aeaf66SEric Saxe if (nnodes == 0) { 69592564cb1Sesaxe #ifdef DEBUG 696d2aeaf66SEric Saxe uint_t family; 69792564cb1Sesaxe 698d2aeaf66SEric Saxe /* 699d2aeaf66SEric Saxe * This routine uses a PCI config space based mechanism 700d2aeaf66SEric Saxe * for retrieving the number of nodes in the system. 701d2aeaf66SEric Saxe * Device 24, function 0, offset 0x60 as used here is not 702d2aeaf66SEric Saxe * AMD processor architectural, and may not work on processor 703d2aeaf66SEric Saxe * families other than those listed below. 704d2aeaf66SEric Saxe * 705d2aeaf66SEric Saxe * Callers of this routine must ensure that we're running on 706d2aeaf66SEric Saxe * a processor which supports this mechanism. 707d2aeaf66SEric Saxe * The assertion below is meant to catch calls on unsupported 708d2aeaf66SEric Saxe * processors. 709d2aeaf66SEric Saxe */ 710d2aeaf66SEric Saxe family = cpuid_getfamily(CPU); 711d2aeaf66SEric Saxe ASSERT(family == 0xf || family == 0x10 || family == 0x11); 71292564cb1Sesaxe #endif /* DEBUG */ 71392564cb1Sesaxe 71492564cb1Sesaxe /* 71592564cb1Sesaxe * Obtain the number of nodes in the system from 71692564cb1Sesaxe * bits [6:4] of the Node ID register on node 0. 71792564cb1Sesaxe * 71892564cb1Sesaxe * The actual node count is NodeID[6:4] + 1 71992564cb1Sesaxe * 72092564cb1Sesaxe * The Node ID register is accessed via function 0, 72192564cb1Sesaxe * offset 0x60. Node 0 is device 24. 72292564cb1Sesaxe */ 72392564cb1Sesaxe nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1; 72492564cb1Sesaxe } 72592564cb1Sesaxe return (nnodes); 72692564cb1Sesaxe } 72792564cb1Sesaxe 728512cf780Skchow uint_t 729512cf780Skchow do_erratum_298(struct cpu *cpu) 730512cf780Skchow { 731512cf780Skchow static int osvwrc = -3; 732512cf780Skchow extern int osvw_opteron_erratum(cpu_t *, uint_t); 733512cf780Skchow 734512cf780Skchow /* 735512cf780Skchow * L2 Eviction May Occur During Processor Operation To Set 736512cf780Skchow * Accessed or Dirty Bit. 737512cf780Skchow */ 738512cf780Skchow if (osvwrc == -3) { 739512cf780Skchow osvwrc = osvw_opteron_erratum(cpu, 298); 740512cf780Skchow } else { 741512cf780Skchow /* osvw return codes should be consistent for all cpus */ 742512cf780Skchow ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298)); 743512cf780Skchow } 744512cf780Skchow 745512cf780Skchow switch (osvwrc) { 746512cf780Skchow case 0: /* erratum is not present: do nothing */ 747512cf780Skchow break; 748512cf780Skchow case 1: /* erratum is present: BIOS workaround applied */ 749512cf780Skchow /* 750512cf780Skchow * check if workaround is actually in place and issue warning 751512cf780Skchow * if not. 752512cf780Skchow */ 753512cf780Skchow if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 754512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) { 755512cf780Skchow #if defined(OPTERON_ERRATUM_298) 756512cf780Skchow opteron_erratum_298++; 757512cf780Skchow #else 758512cf780Skchow workaround_warning(cpu, 298); 759512cf780Skchow return (1); 760512cf780Skchow #endif 761512cf780Skchow } 762512cf780Skchow break; 763512cf780Skchow case -1: /* cannot determine via osvw: check cpuid */ 764512cf780Skchow if ((cpuid_opteron_erratum(cpu, 298) > 0) && 765512cf780Skchow (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) || 766512cf780Skchow ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) { 767512cf780Skchow #if defined(OPTERON_ERRATUM_298) 768512cf780Skchow opteron_erratum_298++; 769512cf780Skchow #else 770512cf780Skchow workaround_warning(cpu, 298); 771512cf780Skchow return (1); 772512cf780Skchow #endif 773512cf780Skchow } 774512cf780Skchow break; 775512cf780Skchow } 776512cf780Skchow return (0); 777512cf780Skchow } 778512cf780Skchow 7797c478bd9Sstevel@tonic-gate uint_t 7807c478bd9Sstevel@tonic-gate workaround_errata(struct cpu *cpu) 7817c478bd9Sstevel@tonic-gate { 7827c478bd9Sstevel@tonic-gate uint_t missing = 0; 7837c478bd9Sstevel@tonic-gate 7847c478bd9Sstevel@tonic-gate ASSERT(cpu == CPU); 7857c478bd9Sstevel@tonic-gate 7867c478bd9Sstevel@tonic-gate /*LINTED*/ 7877c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 88) > 0) { 7887c478bd9Sstevel@tonic-gate /* 7897c478bd9Sstevel@tonic-gate * SWAPGS May Fail To Read Correct GS Base 7907c478bd9Sstevel@tonic-gate */ 7917c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_88) 7927c478bd9Sstevel@tonic-gate /* 7937c478bd9Sstevel@tonic-gate * The workaround is an mfence in the relevant assembler code 7947c478bd9Sstevel@tonic-gate */ 795ae115bc7Smrj opteron_erratum_88++; 7967c478bd9Sstevel@tonic-gate #else 797ae115bc7Smrj workaround_warning(cpu, 88); 7987c478bd9Sstevel@tonic-gate missing++; 7997c478bd9Sstevel@tonic-gate #endif 8007c478bd9Sstevel@tonic-gate } 8017c478bd9Sstevel@tonic-gate 8027c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 91) > 0) { 8037c478bd9Sstevel@tonic-gate /* 8047c478bd9Sstevel@tonic-gate * Software Prefetches May Report A Page Fault 8057c478bd9Sstevel@tonic-gate */ 8067c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_91) 8077c478bd9Sstevel@tonic-gate /* 8087c478bd9Sstevel@tonic-gate * fix is in trap.c 8097c478bd9Sstevel@tonic-gate */ 8107c478bd9Sstevel@tonic-gate opteron_erratum_91++; 8117c478bd9Sstevel@tonic-gate #else 812ae115bc7Smrj workaround_warning(cpu, 91); 8137c478bd9Sstevel@tonic-gate missing++; 8147c478bd9Sstevel@tonic-gate #endif 8157c478bd9Sstevel@tonic-gate } 8167c478bd9Sstevel@tonic-gate 8177c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 93) > 0) { 8187c478bd9Sstevel@tonic-gate /* 8197c478bd9Sstevel@tonic-gate * RSM Auto-Halt Restart Returns to Incorrect RIP 8207c478bd9Sstevel@tonic-gate */ 8217c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_93) 8227c478bd9Sstevel@tonic-gate /* 8237c478bd9Sstevel@tonic-gate * fix is in trap.c 8247c478bd9Sstevel@tonic-gate */ 8257c478bd9Sstevel@tonic-gate opteron_erratum_93++; 8267c478bd9Sstevel@tonic-gate #else 827ae115bc7Smrj workaround_warning(cpu, 93); 8287c478bd9Sstevel@tonic-gate missing++; 8297c478bd9Sstevel@tonic-gate #endif 8307c478bd9Sstevel@tonic-gate } 8317c478bd9Sstevel@tonic-gate 8327c478bd9Sstevel@tonic-gate /*LINTED*/ 8337c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 95) > 0) { 8347c478bd9Sstevel@tonic-gate /* 8357c478bd9Sstevel@tonic-gate * RET Instruction May Return to Incorrect EIP 8367c478bd9Sstevel@tonic-gate */ 8377c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_95) 8387c478bd9Sstevel@tonic-gate #if defined(_LP64) 8397c478bd9Sstevel@tonic-gate /* 8407c478bd9Sstevel@tonic-gate * Workaround this by ensuring that 32-bit user code and 8417c478bd9Sstevel@tonic-gate * 64-bit kernel code never occupy the same address 8427c478bd9Sstevel@tonic-gate * range mod 4G. 8437c478bd9Sstevel@tonic-gate */ 8447c478bd9Sstevel@tonic-gate if (_userlimit32 > 0xc0000000ul) 8457c478bd9Sstevel@tonic-gate *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 8467c478bd9Sstevel@tonic-gate 8477c478bd9Sstevel@tonic-gate /*LINTED*/ 8487c478bd9Sstevel@tonic-gate ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 849ae115bc7Smrj opteron_erratum_95++; 8507c478bd9Sstevel@tonic-gate #endif /* _LP64 */ 8517c478bd9Sstevel@tonic-gate #else 852ae115bc7Smrj workaround_warning(cpu, 95); 8537c478bd9Sstevel@tonic-gate missing++; 854ae115bc7Smrj #endif 8557c478bd9Sstevel@tonic-gate } 8567c478bd9Sstevel@tonic-gate 8577c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 100) > 0) { 8587c478bd9Sstevel@tonic-gate /* 8597c478bd9Sstevel@tonic-gate * Compatibility Mode Branches Transfer to Illegal Address 8607c478bd9Sstevel@tonic-gate */ 8617c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_100) 8627c478bd9Sstevel@tonic-gate /* 8637c478bd9Sstevel@tonic-gate * fix is in trap.c 8647c478bd9Sstevel@tonic-gate */ 8657c478bd9Sstevel@tonic-gate opteron_erratum_100++; 8667c478bd9Sstevel@tonic-gate #else 867ae115bc7Smrj workaround_warning(cpu, 100); 8687c478bd9Sstevel@tonic-gate missing++; 8697c478bd9Sstevel@tonic-gate #endif 8707c478bd9Sstevel@tonic-gate } 8717c478bd9Sstevel@tonic-gate 8727c478bd9Sstevel@tonic-gate /*LINTED*/ 8737c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 108) > 0) { 8747c478bd9Sstevel@tonic-gate /* 8757c478bd9Sstevel@tonic-gate * CPUID Instruction May Return Incorrect Model Number In 8767c478bd9Sstevel@tonic-gate * Some Processors 8777c478bd9Sstevel@tonic-gate */ 8787c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 8797c478bd9Sstevel@tonic-gate /* 8807c478bd9Sstevel@tonic-gate * (Our cpuid-handling code corrects the model number on 8817c478bd9Sstevel@tonic-gate * those processors) 8827c478bd9Sstevel@tonic-gate */ 8837c478bd9Sstevel@tonic-gate #else 884ae115bc7Smrj workaround_warning(cpu, 108); 8857c478bd9Sstevel@tonic-gate missing++; 8867c478bd9Sstevel@tonic-gate #endif 8877c478bd9Sstevel@tonic-gate } 8887c478bd9Sstevel@tonic-gate 8897c478bd9Sstevel@tonic-gate /*LINTED*/ 890ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 109) > 0) do { 8917c478bd9Sstevel@tonic-gate /* 892fb2caebeSRandy Fishel * Certain Reverse REP MOVS May Produce Unpredictable Behavior 8937c478bd9Sstevel@tonic-gate */ 8947c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 895ae115bc7Smrj /* 896ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 897ae115bc7Smrj */ 898ae115bc7Smrj uint64_t value; 899ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 900ae115bc7Smrj int err; 901ae115bc7Smrj 902ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 903ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 904ae115bc7Smrj workaround_warning(cpu, 109); 905ae115bc7Smrj missing++; 906ae115bc7Smrj } 907ae115bc7Smrj if (value == 0) 9087c478bd9Sstevel@tonic-gate opteron_erratum_109++; 9097c478bd9Sstevel@tonic-gate #else 910ae115bc7Smrj workaround_warning(cpu, 109); 9117c478bd9Sstevel@tonic-gate missing++; 9127c478bd9Sstevel@tonic-gate #endif 913ae115bc7Smrj /*CONSTANTCONDITION*/ 914ae115bc7Smrj } while (0); 915ae115bc7Smrj 9167c478bd9Sstevel@tonic-gate /*LINTED*/ 9177c478bd9Sstevel@tonic-gate if (cpuid_opteron_erratum(cpu, 121) > 0) { 9187c478bd9Sstevel@tonic-gate /* 9197c478bd9Sstevel@tonic-gate * Sequential Execution Across Non_Canonical Boundary Caused 9207c478bd9Sstevel@tonic-gate * Processor Hang 9217c478bd9Sstevel@tonic-gate */ 9227c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_121) 923ae115bc7Smrj #if defined(_LP64) 9247c478bd9Sstevel@tonic-gate /* 9257c478bd9Sstevel@tonic-gate * Erratum 121 is only present in long (64 bit) mode. 9267c478bd9Sstevel@tonic-gate * Workaround is to include the page immediately before the 9277c478bd9Sstevel@tonic-gate * va hole to eliminate the possibility of system hangs due to 9287c478bd9Sstevel@tonic-gate * sequential execution across the va hole boundary. 9297c478bd9Sstevel@tonic-gate */ 930ae115bc7Smrj if (opteron_erratum_121) 931ae115bc7Smrj opteron_erratum_121++; 932ae115bc7Smrj else { 933ae115bc7Smrj if (hole_start) { 934ae115bc7Smrj hole_start -= PAGESIZE; 935ae115bc7Smrj } else { 936ae115bc7Smrj /* 937ae115bc7Smrj * hole_start not yet initialized by 938ae115bc7Smrj * mmu_init. Initialize hole_start 939ae115bc7Smrj * with value to be subtracted. 940ae115bc7Smrj */ 941ae115bc7Smrj hole_start = PAGESIZE; 9427c478bd9Sstevel@tonic-gate } 943ae115bc7Smrj opteron_erratum_121++; 9447c478bd9Sstevel@tonic-gate } 945ae115bc7Smrj #endif /* _LP64 */ 9467c478bd9Sstevel@tonic-gate #else 947ae115bc7Smrj workaround_warning(cpu, 121); 9487c478bd9Sstevel@tonic-gate missing++; 9497c478bd9Sstevel@tonic-gate #endif 9507c478bd9Sstevel@tonic-gate } 9517c478bd9Sstevel@tonic-gate 9527c478bd9Sstevel@tonic-gate /*LINTED*/ 953ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 122) > 0) do { 9547c478bd9Sstevel@tonic-gate /* 955ae115bc7Smrj * TLB Flush Filter May Cause Coherency Problem in 9567c478bd9Sstevel@tonic-gate * Multiprocessor Systems 9577c478bd9Sstevel@tonic-gate */ 9587c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_122) 959ae115bc7Smrj uint64_t value; 960ae115bc7Smrj const uint_t msr = MSR_AMD_HWCR; 961ae115bc7Smrj int error; 962ae115bc7Smrj 9637c478bd9Sstevel@tonic-gate /* 9647c478bd9Sstevel@tonic-gate * Erratum 122 is only present in MP configurations (multi-core 9657c478bd9Sstevel@tonic-gate * or multi-processor). 9667c478bd9Sstevel@tonic-gate */ 967843e1988Sjohnlev #if defined(__xpv) 968843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 969843e1988Sjohnlev break; 970349b53ddSStuart Maybee if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1) 971843e1988Sjohnlev break; 972843e1988Sjohnlev #else 97392564cb1Sesaxe if (!opteron_erratum_122 && opteron_get_nnodes() == 1 && 974ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu) == 1) 975ae115bc7Smrj break; 976843e1988Sjohnlev #endif 977ae115bc7Smrj /* disable TLB Flush Filter */ 978ae115bc7Smrj 979ae115bc7Smrj if ((error = checked_rdmsr(msr, &value)) != 0) { 980ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 981ae115bc7Smrj workaround_warning(cpu, 122); 982ae115bc7Smrj missing++; 983ae115bc7Smrj } else { 984ae115bc7Smrj value |= (uint64_t)AMD_HWCR_FFDIS; 985ae115bc7Smrj if ((error = checked_wrmsr(msr, value)) != 0) { 986ae115bc7Smrj msr_warning(cpu, "wr", msr, error); 987ae115bc7Smrj workaround_warning(cpu, 122); 988ae115bc7Smrj missing++; 989ae115bc7Smrj } 9907c478bd9Sstevel@tonic-gate } 991ae115bc7Smrj opteron_erratum_122++; 9927c478bd9Sstevel@tonic-gate #else 993ae115bc7Smrj workaround_warning(cpu, 122); 9947c478bd9Sstevel@tonic-gate missing++; 9957c478bd9Sstevel@tonic-gate #endif 996ae115bc7Smrj /*CONSTANTCONDITION*/ 997ae115bc7Smrj } while (0); 998403c216aSkchow 9997c478bd9Sstevel@tonic-gate /*LINTED*/ 1000ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 123) > 0) do { 10017c478bd9Sstevel@tonic-gate /* 10027c478bd9Sstevel@tonic-gate * Bypassed Reads May Cause Data Corruption of System Hang in 10037c478bd9Sstevel@tonic-gate * Dual Core Processors 10047c478bd9Sstevel@tonic-gate */ 1005ae115bc7Smrj #if defined(OPTERON_ERRATUM_123) 1006ae115bc7Smrj uint64_t value; 1007ae115bc7Smrj const uint_t msr = MSR_AMD_PATCHLEVEL; 1008ae115bc7Smrj int err; 1009ae115bc7Smrj 10107c478bd9Sstevel@tonic-gate /* 10117c478bd9Sstevel@tonic-gate * Erratum 123 applies only to multi-core cpus. 10127c478bd9Sstevel@tonic-gate */ 1013ae115bc7Smrj if (cpuid_get_ncpu_per_chip(cpu) < 2) 1014ae115bc7Smrj break; 1015843e1988Sjohnlev #if defined(__xpv) 1016843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1017843e1988Sjohnlev break; 1018843e1988Sjohnlev #endif 1019ae115bc7Smrj /* 1020ae115bc7Smrj * The "workaround" is to print a warning to upgrade the BIOS 1021ae115bc7Smrj */ 1022ae115bc7Smrj if ((err = checked_rdmsr(msr, &value)) != 0) { 1023ae115bc7Smrj msr_warning(cpu, "rd", msr, err); 1024ae115bc7Smrj workaround_warning(cpu, 123); 1025ae115bc7Smrj missing++; 10267c478bd9Sstevel@tonic-gate } 1027ae115bc7Smrj if (value == 0) 1028ae115bc7Smrj opteron_erratum_123++; 1029ae115bc7Smrj #else 1030ae115bc7Smrj workaround_warning(cpu, 123); 1031ae115bc7Smrj missing++; 1032ae115bc7Smrj 1033403c216aSkchow #endif 1034ae115bc7Smrj /*CONSTANTCONDITION*/ 1035ae115bc7Smrj } while (0); 10362201b277Skucharsk 10372201b277Skucharsk /*LINTED*/ 1038ae115bc7Smrj if (cpuid_opteron_erratum(cpu, 131) > 0) do { 10392201b277Skucharsk /* 10402201b277Skucharsk * Multiprocessor Systems with Four or More Cores May Deadlock 10412201b277Skucharsk * Waiting for a Probe Response 10422201b277Skucharsk */ 1043ae115bc7Smrj #if defined(OPTERON_ERRATUM_131) 1044ae115bc7Smrj uint64_t nbcfg; 1045ae115bc7Smrj const uint_t msr = MSR_AMD_NB_CFG; 1046ae115bc7Smrj const uint64_t wabits = 1047ae115bc7Smrj AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 1048ae115bc7Smrj int error; 1049ae115bc7Smrj 10502201b277Skucharsk /* 10512201b277Skucharsk * Erratum 131 applies to any system with four or more cores. 10522201b277Skucharsk */ 1053ae115bc7Smrj if (opteron_erratum_131) 1054ae115bc7Smrj break; 1055843e1988Sjohnlev #if defined(__xpv) 1056843e1988Sjohnlev if (!DOMAIN_IS_INITDOMAIN(xen_info)) 1057843e1988Sjohnlev break; 1058349b53ddSStuart Maybee if (xpv_nr_phys_cpus() < 4) 1059843e1988Sjohnlev break; 1060843e1988Sjohnlev #else 106192564cb1Sesaxe if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4) 1062ae115bc7Smrj break; 1063843e1988Sjohnlev #endif 1064ae115bc7Smrj /* 1065ae115bc7Smrj * Print a warning if neither of the workarounds for 1066ae115bc7Smrj * erratum 131 is present. 1067ae115bc7Smrj */ 1068ae115bc7Smrj if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 1069ae115bc7Smrj msr_warning(cpu, "rd", msr, error); 1070ae115bc7Smrj workaround_warning(cpu, 131); 1071ae115bc7Smrj missing++; 1072ae115bc7Smrj } else if ((nbcfg & wabits) == 0) { 1073ae115bc7Smrj opteron_erratum_131++; 1074ae115bc7Smrj } else { 1075ae115bc7Smrj /* cannot have both workarounds set */ 1076ae115bc7Smrj ASSERT((nbcfg & wabits) != wabits); 10772201b277Skucharsk } 1078ae115bc7Smrj #else 1079ae115bc7Smrj workaround_warning(cpu, 131); 1080ae115bc7Smrj missing++; 10812201b277Skucharsk #endif 1082ae115bc7Smrj /*CONSTANTCONDITION*/ 1083ae115bc7Smrj } while (0); 1084ef50d8c0Sesaxe 1085ef50d8c0Sesaxe /* 1086ae115bc7Smrj * This isn't really an erratum, but for convenience the 1087ef50d8c0Sesaxe * detection/workaround code lives here and in cpuid_opteron_erratum. 1088ef50d8c0Sesaxe */ 1089ef50d8c0Sesaxe if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 1090ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1091ef50d8c0Sesaxe /* 1092ef50d8c0Sesaxe * Disable C1-Clock ramping on multi-core/multi-processor 1093ef50d8c0Sesaxe * K8 platforms to guard against TSC drift. 1094ef50d8c0Sesaxe */ 1095ef50d8c0Sesaxe if (opteron_workaround_6336786) { 1096ef50d8c0Sesaxe opteron_workaround_6336786++; 1097843e1988Sjohnlev #if defined(__xpv) 1098843e1988Sjohnlev } else if ((DOMAIN_IS_INITDOMAIN(xen_info) && 1099349b53ddSStuart Maybee xpv_nr_phys_cpus() > 1) || 1100843e1988Sjohnlev opteron_workaround_6336786_UP) { 1101843e1988Sjohnlev /* 110292564cb1Sesaxe * XXPV Hmm. We can't walk the Northbridges on 1103843e1988Sjohnlev * the hypervisor; so just complain and drive 1104843e1988Sjohnlev * on. This probably needs to be fixed in 1105843e1988Sjohnlev * the hypervisor itself. 1106843e1988Sjohnlev */ 1107843e1988Sjohnlev opteron_workaround_6336786++; 1108843e1988Sjohnlev workaround_warning(cpu, 6336786); 1109843e1988Sjohnlev #else /* __xpv */ 111092564cb1Sesaxe } else if ((opteron_get_nnodes() * 1111d38257c4Sesaxe cpuid_get_ncpu_per_chip(cpu) > 1) || 1112ef50d8c0Sesaxe opteron_workaround_6336786_UP) { 111392564cb1Sesaxe 111492564cb1Sesaxe uint_t node, nnodes; 1115ae115bc7Smrj uint8_t data; 1116ae115bc7Smrj 111792564cb1Sesaxe nnodes = opteron_get_nnodes(); 111892564cb1Sesaxe for (node = 0; node < nnodes; node++) { 1119ef50d8c0Sesaxe /* 1120ef50d8c0Sesaxe * Clear PMM7[1:0] (function 3, offset 0x87) 1121ef50d8c0Sesaxe * Northbridge device is the node id + 24. 1122ef50d8c0Sesaxe */ 1123ef50d8c0Sesaxe data = pci_getb_func(0, node + 24, 3, 0x87); 1124ef50d8c0Sesaxe data &= 0xFC; 1125ef50d8c0Sesaxe pci_putb_func(0, node + 24, 3, 0x87, data); 1126ef50d8c0Sesaxe } 1127ef50d8c0Sesaxe opteron_workaround_6336786++; 1128843e1988Sjohnlev #endif /* __xpv */ 1129ef50d8c0Sesaxe } 1130ae115bc7Smrj #else 1131ae115bc7Smrj workaround_warning(cpu, 6336786); 1132ae115bc7Smrj missing++; 1133ef50d8c0Sesaxe #endif 1134ae115bc7Smrj } 1135ee88d2b9Skchow 1136ee88d2b9Skchow /*LINTED*/ 1137ee88d2b9Skchow /* 1138ee88d2b9Skchow * Mutex primitives don't work as expected. 1139ee88d2b9Skchow */ 1140ee88d2b9Skchow if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 1141ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1142ee88d2b9Skchow /* 1143ae115bc7Smrj * This problem only occurs with 2 or more cores. If bit in 1144512cf780Skchow * MSR_AMD_BU_CFG set, then not applicable. The workaround 1145ee88d2b9Skchow * is to patch the semaphone routines with the lfence 1146ee88d2b9Skchow * instruction to provide necessary load memory barrier with 1147ee88d2b9Skchow * possible subsequent read-modify-write ops. 1148ee88d2b9Skchow * 1149ee88d2b9Skchow * It is too early in boot to call the patch routine so 1150ee88d2b9Skchow * set erratum variable to be done in startup_end(). 1151ee88d2b9Skchow */ 1152ee88d2b9Skchow if (opteron_workaround_6323525) { 1153ee88d2b9Skchow opteron_workaround_6323525++; 1154843e1988Sjohnlev #if defined(__xpv) 11557417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) { 1156843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1157843e1988Sjohnlev /* 1158843e1988Sjohnlev * XXPV Use dom0_msr here when extended 1159843e1988Sjohnlev * operations are supported? 1160843e1988Sjohnlev */ 1161349b53ddSStuart Maybee if (xpv_nr_phys_cpus() > 1) 1162843e1988Sjohnlev opteron_workaround_6323525++; 1163843e1988Sjohnlev } else { 1164843e1988Sjohnlev /* 1165843e1988Sjohnlev * We have no way to tell how many physical 1166843e1988Sjohnlev * cpus there are, or even if this processor 1167843e1988Sjohnlev * has the problem, so enable the workaround 1168843e1988Sjohnlev * unconditionally (at some performance cost). 1169843e1988Sjohnlev */ 1170843e1988Sjohnlev opteron_workaround_6323525++; 1171843e1988Sjohnlev } 1172843e1988Sjohnlev #else /* __xpv */ 11737417cfdeSKuriakose Kuruvilla } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) && 11747417cfdeSKuriakose Kuruvilla ((opteron_get_nnodes() * 1175ae115bc7Smrj cpuid_get_ncpu_per_chip(cpu)) > 1)) { 117648b2bf45SKit Chow if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0) 1177ee88d2b9Skchow opteron_workaround_6323525++; 1178843e1988Sjohnlev #endif /* __xpv */ 1179ee88d2b9Skchow } 1180ae115bc7Smrj #else 1181ae115bc7Smrj workaround_warning(cpu, 6323525); 1182ae115bc7Smrj missing++; 1183ee88d2b9Skchow #endif 1184ae115bc7Smrj } 1185ae115bc7Smrj 1186512cf780Skchow missing += do_erratum_298(cpu); 1187512cf780Skchow 11885e54b56dSHans Rosenfeld if (cpuid_opteron_erratum(cpu, 721) > 0) { 11895e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 1190850ad55aSHans Rosenfeld on_trap_data_t otd; 1191850ad55aSHans Rosenfeld 1192850ad55aSHans Rosenfeld if (!on_trap(&otd, OT_DATA_ACCESS)) 1193850ad55aSHans Rosenfeld wrmsr(MSR_AMD_DE_CFG, 1194850ad55aSHans Rosenfeld rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721); 1195850ad55aSHans Rosenfeld no_trap(); 1196850ad55aSHans Rosenfeld 11975e54b56dSHans Rosenfeld opteron_erratum_721++; 11985e54b56dSHans Rosenfeld #else 11995e54b56dSHans Rosenfeld workaround_warning(cpu, 721); 12005e54b56dSHans Rosenfeld missing++; 12015e54b56dSHans Rosenfeld #endif 12025e54b56dSHans Rosenfeld } 12035e54b56dSHans Rosenfeld 1204843e1988Sjohnlev #ifdef __xpv 1205843e1988Sjohnlev return (0); 1206843e1988Sjohnlev #else 12077c478bd9Sstevel@tonic-gate return (missing); 1208843e1988Sjohnlev #endif 12097c478bd9Sstevel@tonic-gate } 12107c478bd9Sstevel@tonic-gate 12117c478bd9Sstevel@tonic-gate void 12127c478bd9Sstevel@tonic-gate workaround_errata_end() 12137c478bd9Sstevel@tonic-gate { 1214ae115bc7Smrj #if defined(OPTERON_ERRATUM_88) 1215ae115bc7Smrj if (opteron_erratum_88) 1216ae115bc7Smrj workaround_applied(88); 1217ae115bc7Smrj #endif 1218ae115bc7Smrj #if defined(OPTERON_ERRATUM_91) 1219ae115bc7Smrj if (opteron_erratum_91) 1220ae115bc7Smrj workaround_applied(91); 1221ae115bc7Smrj #endif 1222ae115bc7Smrj #if defined(OPTERON_ERRATUM_93) 1223ae115bc7Smrj if (opteron_erratum_93) 1224ae115bc7Smrj workaround_applied(93); 1225ae115bc7Smrj #endif 1226ae115bc7Smrj #if defined(OPTERON_ERRATUM_95) 1227ae115bc7Smrj if (opteron_erratum_95) 1228ae115bc7Smrj workaround_applied(95); 1229ae115bc7Smrj #endif 1230ae115bc7Smrj #if defined(OPTERON_ERRATUM_100) 1231ae115bc7Smrj if (opteron_erratum_100) 1232ae115bc7Smrj workaround_applied(100); 1233ae115bc7Smrj #endif 1234ae115bc7Smrj #if defined(OPTERON_ERRATUM_108) 1235ae115bc7Smrj if (opteron_erratum_108) 1236ae115bc7Smrj workaround_applied(108); 1237ae115bc7Smrj #endif 12387c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_109) 12397c478bd9Sstevel@tonic-gate if (opteron_erratum_109) { 12402201b277Skucharsk cmn_err(CE_WARN, 12412201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12422201b277Skucharsk " processor\nerratum 109 was not detected; updating your" 12432201b277Skucharsk " system's BIOS to a version\ncontaining this" 12442201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12452201b277Skucharsk " system\noperation may occur.\n"); 12467c478bd9Sstevel@tonic-gate } 1247ae115bc7Smrj #endif 1248ae115bc7Smrj #if defined(OPTERON_ERRATUM_121) 1249ae115bc7Smrj if (opteron_erratum_121) 1250ae115bc7Smrj workaround_applied(121); 1251ae115bc7Smrj #endif 1252ae115bc7Smrj #if defined(OPTERON_ERRATUM_122) 1253ae115bc7Smrj if (opteron_erratum_122) 1254ae115bc7Smrj workaround_applied(122); 1255ae115bc7Smrj #endif 12567c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_123) 12577c478bd9Sstevel@tonic-gate if (opteron_erratum_123) { 12582201b277Skucharsk cmn_err(CE_WARN, 12592201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12602201b277Skucharsk " processor\nerratum 123 was not detected; updating your" 12612201b277Skucharsk " system's BIOS to a version\ncontaining this" 12622201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12632201b277Skucharsk " system\noperation may occur.\n"); 12647c478bd9Sstevel@tonic-gate } 1265ae115bc7Smrj #endif 12662201b277Skucharsk #if defined(OPTERON_ERRATUM_131) 12672201b277Skucharsk if (opteron_erratum_131) { 12682201b277Skucharsk cmn_err(CE_WARN, 12692201b277Skucharsk "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 12702201b277Skucharsk " processor\nerratum 131 was not detected; updating your" 12712201b277Skucharsk " system's BIOS to a version\ncontaining this" 12722201b277Skucharsk " microcode patch is HIGHLY recommended or erroneous" 12732201b277Skucharsk " system\noperation may occur.\n"); 12742201b277Skucharsk } 1275ae115bc7Smrj #endif 1276ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6336786) 1277ae115bc7Smrj if (opteron_workaround_6336786) 1278ae115bc7Smrj workaround_applied(6336786); 1279ae115bc7Smrj #endif 1280ae115bc7Smrj #if defined(OPTERON_WORKAROUND_6323525) 1281ae115bc7Smrj if (opteron_workaround_6323525) 1282ae115bc7Smrj workaround_applied(6323525); 1283ae115bc7Smrj #endif 1284512cf780Skchow #if defined(OPTERON_ERRATUM_298) 1285512cf780Skchow if (opteron_erratum_298) { 1286512cf780Skchow cmn_err(CE_WARN, 1287512cf780Skchow "BIOS microcode patch for AMD 64/Opteron(tm)" 1288512cf780Skchow " processor\nerratum 298 was not detected; updating your" 1289512cf780Skchow " system's BIOS to a version\ncontaining this" 1290512cf780Skchow " microcode patch is HIGHLY recommended or erroneous" 1291512cf780Skchow " system\noperation may occur.\n"); 1292512cf780Skchow } 1293512cf780Skchow #endif 12945e54b56dSHans Rosenfeld #if defined(OPTERON_ERRATUM_721) 12955e54b56dSHans Rosenfeld if (opteron_erratum_721) 12965e54b56dSHans Rosenfeld workaround_applied(721); 12975e54b56dSHans Rosenfeld #endif 12987c478bd9Sstevel@tonic-gate } 12997c478bd9Sstevel@tonic-gate 1300ae115bc7Smrj /* 1301a3114836SGerry Liu * The procset_slave and procset_master are used to synchronize 1302a3114836SGerry Liu * between the control CPU and the target CPU when starting CPUs. 1303ae115bc7Smrj */ 1304a3114836SGerry Liu static cpuset_t procset_slave, procset_master; 1305a3114836SGerry Liu 1306a3114836SGerry Liu static void 1307a3114836SGerry Liu mp_startup_wait(cpuset_t *sp, processorid_t cpuid) 1308a3114836SGerry Liu { 1309a3114836SGerry Liu cpuset_t tempset; 1310a3114836SGerry Liu 1311a3114836SGerry Liu for (tempset = *sp; !CPU_IN_SET(tempset, cpuid); 1312a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1313a3114836SGerry Liu SMT_PAUSE(); 1314a3114836SGerry Liu } 1315a3114836SGerry Liu CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid); 1316a3114836SGerry Liu } 1317a3114836SGerry Liu 1318a3114836SGerry Liu static void 1319a3114836SGerry Liu mp_startup_signal(cpuset_t *sp, processorid_t cpuid) 1320a3114836SGerry Liu { 1321a3114836SGerry Liu cpuset_t tempset; 1322a3114836SGerry Liu 1323a3114836SGerry Liu CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid); 1324a3114836SGerry Liu for (tempset = *sp; CPU_IN_SET(tempset, cpuid); 1325a3114836SGerry Liu tempset = *(volatile cpuset_t *)sp) { 1326a3114836SGerry Liu SMT_PAUSE(); 1327a3114836SGerry Liu } 1328a3114836SGerry Liu } 1329a3114836SGerry Liu 1330ae115bc7Smrj int 1331a3114836SGerry Liu mp_start_cpu_common(cpu_t *cp, boolean_t boot) 1332ae115bc7Smrj { 1333a3114836SGerry Liu _NOTE(ARGUNUSED(boot)); 1334a3114836SGerry Liu 1335ae115bc7Smrj void *ctx; 1336ae115bc7Smrj int delays; 1337ae115bc7Smrj int error = 0; 1338a3114836SGerry Liu cpuset_t tempset; 1339a3114836SGerry Liu processorid_t cpuid; 1340a3114836SGerry Liu #ifndef __xpv 1341a3114836SGerry Liu extern void cpupm_init(cpu_t *); 1342a3114836SGerry Liu #endif 1343ae115bc7Smrj 1344a3114836SGerry Liu ASSERT(cp != NULL); 1345a3114836SGerry Liu cpuid = cp->cpu_id; 1346a3114836SGerry Liu ctx = mach_cpucontext_alloc(cp); 1347a3114836SGerry Liu if (ctx == NULL) { 1348a3114836SGerry Liu cmn_err(CE_WARN, 1349a3114836SGerry Liu "cpu%d: failed to allocate context", cp->cpu_id); 1350a3114836SGerry Liu return (EAGAIN); 1351ae115bc7Smrj } 1352a3114836SGerry Liu error = mach_cpu_start(cp, ctx); 1353a3114836SGerry Liu if (error != 0) { 1354a3114836SGerry Liu cmn_err(CE_WARN, 1355a3114836SGerry Liu "cpu%d: failed to start, error %d", cp->cpu_id, error); 1356a3114836SGerry Liu mach_cpucontext_free(cp, ctx, error); 1357ae115bc7Smrj return (error); 1358ae115bc7Smrj } 1359ae115bc7Smrj 1360a3114836SGerry Liu for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid); 1361a3114836SGerry Liu delays++) { 1362ae115bc7Smrj if (delays == 500) { 1363ae115bc7Smrj /* 1364ae115bc7Smrj * After five seconds, things are probably looking 1365ae115bc7Smrj * a bit bleak - explain the hang. 1366ae115bc7Smrj */ 1367ae115bc7Smrj cmn_err(CE_NOTE, "cpu%d: started, " 1368a3114836SGerry Liu "but not running in the kernel yet", cpuid); 1369ae115bc7Smrj } else if (delays > 2000) { 1370ae115bc7Smrj /* 1371ae115bc7Smrj * We waited at least 20 seconds, bail .. 1372ae115bc7Smrj */ 1373ae115bc7Smrj error = ETIMEDOUT; 1374a3114836SGerry Liu cmn_err(CE_WARN, "cpu%d: timed out", cpuid); 1375ae115bc7Smrj mach_cpucontext_free(cp, ctx, error); 1376ae115bc7Smrj return (error); 1377ae115bc7Smrj } 1378ae115bc7Smrj 1379ae115bc7Smrj /* 1380ae115bc7Smrj * wait at least 10ms, then check again.. 1381ae115bc7Smrj */ 1382ae115bc7Smrj delay(USEC_TO_TICK_ROUNDUP(10000)); 1383a3114836SGerry Liu tempset = *((volatile cpuset_t *)&procset_slave); 1384ae115bc7Smrj } 1385a3114836SGerry Liu CPUSET_ATOMIC_DEL(procset_slave, cpuid); 1386ae115bc7Smrj 1387ae115bc7Smrj mach_cpucontext_free(cp, ctx, 0); 1388ae115bc7Smrj 1389843e1988Sjohnlev #ifndef __xpv 1390ae115bc7Smrj if (tsc_gethrtime_enable) 1391a3114836SGerry Liu tsc_sync_master(cpuid); 1392843e1988Sjohnlev #endif 1393ae115bc7Smrj 1394ae115bc7Smrj if (dtrace_cpu_init != NULL) { 1395a3114836SGerry Liu (*dtrace_cpu_init)(cpuid); 1396a3114836SGerry Liu } 1397a3114836SGerry Liu 1398a3114836SGerry Liu /* 1399a3114836SGerry Liu * During CPU DR operations, the cpu_lock is held by current 1400a3114836SGerry Liu * (the control) thread. We can't release the cpu_lock here 1401a3114836SGerry Liu * because that will break the CPU DR logic. 1402a3114836SGerry Liu * On the other hand, CPUPM and processor group initialization 1403a3114836SGerry Liu * routines need to access the cpu_lock. So we invoke those 1404a3114836SGerry Liu * routines here on behalf of mp_startup_common(). 1405a3114836SGerry Liu * 1406a3114836SGerry Liu * CPUPM and processor group initialization routines depend 1407a3114836SGerry Liu * on the cpuid probing results. Wait for mp_startup_common() 1408a3114836SGerry Liu * to signal that cpuid probing is done. 1409a3114836SGerry Liu */ 1410a3114836SGerry Liu mp_startup_wait(&procset_slave, cpuid); 1411a3114836SGerry Liu #ifndef __xpv 1412a3114836SGerry Liu cpupm_init(cp); 1413a3114836SGerry Liu #endif 1414a3114836SGerry Liu (void) pg_cpu_init(cp, B_FALSE); 1415a3114836SGerry Liu cpu_set_state(cp); 1416a3114836SGerry Liu mp_startup_signal(&procset_master, cpuid); 1417a3114836SGerry Liu 1418a3114836SGerry Liu return (0); 1419a3114836SGerry Liu } 1420a3114836SGerry Liu 1421a3114836SGerry Liu /* 1422a3114836SGerry Liu * Start a single cpu, assuming that the kernel context is available 1423a3114836SGerry Liu * to successfully start another cpu. 1424a3114836SGerry Liu * 1425a3114836SGerry Liu * (For example, real mode code is mapped into the right place 1426a3114836SGerry Liu * in memory and is ready to be run.) 1427a3114836SGerry Liu */ 1428a3114836SGerry Liu int 1429a3114836SGerry Liu start_cpu(processorid_t who) 1430a3114836SGerry Liu { 1431a3114836SGerry Liu cpu_t *cp; 1432a3114836SGerry Liu int error = 0; 1433a3114836SGerry Liu cpuset_t tempset; 1434a3114836SGerry Liu 1435a3114836SGerry Liu ASSERT(who != 0); 1436a3114836SGerry Liu 1437a3114836SGerry Liu /* 1438a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1439a3114836SGerry Liu * before attempting to start the cpu. 1440a3114836SGerry Liu */ 1441a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1442ae115bc7Smrj /* 1443a3114836SGerry Liu * Kick off a reap in case that helps us with 1444a3114836SGerry Liu * later attempts .. 1445ae115bc7Smrj */ 1446a3114836SGerry Liu kmem_reap(); 1447a3114836SGerry Liu return (ENOMEM); 1448a3114836SGerry Liu } 1449a3114836SGerry Liu 1450a3114836SGerry Liu /* 1451a3114836SGerry Liu * First configure cpu. 1452a3114836SGerry Liu */ 1453a3114836SGerry Liu cp = mp_cpu_configure_common(who, B_TRUE); 1454a3114836SGerry Liu ASSERT(cp != NULL); 1455a3114836SGerry Liu 1456a3114836SGerry Liu /* 1457a3114836SGerry Liu * Then start cpu. 1458a3114836SGerry Liu */ 1459a3114836SGerry Liu error = mp_start_cpu_common(cp, B_TRUE); 1460a3114836SGerry Liu if (error != 0) { 1461a3114836SGerry Liu mp_cpu_unconfigure_common(cp, error); 1462a3114836SGerry Liu return (error); 1463ae115bc7Smrj } 1464ae115bc7Smrj 1465a3114836SGerry Liu mutex_exit(&cpu_lock); 1466a3114836SGerry Liu tempset = cpu_ready_set; 1467a3114836SGerry Liu while (!CPU_IN_SET(tempset, who)) { 1468a3114836SGerry Liu drv_usecwait(1); 1469a3114836SGerry Liu tempset = *((volatile cpuset_t *)&cpu_ready_set); 1470a3114836SGerry Liu } 1471a3114836SGerry Liu mutex_enter(&cpu_lock); 1472ae115bc7Smrj 1473ae115bc7Smrj return (0); 1474ae115bc7Smrj } 14757c478bd9Sstevel@tonic-gate 14767c478bd9Sstevel@tonic-gate void 14777c478bd9Sstevel@tonic-gate start_other_cpus(int cprboot) 14787c478bd9Sstevel@tonic-gate { 1479a3114836SGerry Liu _NOTE(ARGUNUSED(cprboot)); 1480a3114836SGerry Liu 1481ae115bc7Smrj uint_t who; 1482ae115bc7Smrj uint_t bootcpuid = 0; 14837c478bd9Sstevel@tonic-gate 14847c478bd9Sstevel@tonic-gate /* 14857c478bd9Sstevel@tonic-gate * Initialize our own cpu_info. 14867c478bd9Sstevel@tonic-gate */ 14877c478bd9Sstevel@tonic-gate init_cpu_info(CPU); 14887c478bd9Sstevel@tonic-gate 148919397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr); 149019397407SSherry Moore cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr); 149119397407SSherry Moore 14927c478bd9Sstevel@tonic-gate /* 14937c478bd9Sstevel@tonic-gate * Initialize our syscall handlers 14947c478bd9Sstevel@tonic-gate */ 14957c478bd9Sstevel@tonic-gate init_cpu_syscall(CPU); 14967c478bd9Sstevel@tonic-gate 1497ae115bc7Smrj /* 1498ae115bc7Smrj * Take the boot cpu out of the mp_cpus set because we know 1499ae115bc7Smrj * it's already running. Add it to the cpu_ready_set for 1500ae115bc7Smrj * precisely the same reason. 1501ae115bc7Smrj */ 1502ae115bc7Smrj CPUSET_DEL(mp_cpus, bootcpuid); 1503ae115bc7Smrj CPUSET_ADD(cpu_ready_set, bootcpuid); 1504ae115bc7Smrj 15057c478bd9Sstevel@tonic-gate /* 1506a3114836SGerry Liu * skip the rest of this if 1507a3114836SGerry Liu * . only 1 cpu dectected and system isn't hotplug-capable 1508a3114836SGerry Liu * . not using MP 15097c478bd9Sstevel@tonic-gate */ 1510a3114836SGerry Liu if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) || 1511a3114836SGerry Liu use_mp == 0) { 15127c478bd9Sstevel@tonic-gate if (use_mp == 0) 15137c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "?***** Not in MP mode\n"); 15147c478bd9Sstevel@tonic-gate goto done; 15157c478bd9Sstevel@tonic-gate } 15167c478bd9Sstevel@tonic-gate 15177c478bd9Sstevel@tonic-gate /* 15187c478bd9Sstevel@tonic-gate * perform such initialization as is needed 15197c478bd9Sstevel@tonic-gate * to be able to take CPUs on- and off-line. 15207c478bd9Sstevel@tonic-gate */ 15217c478bd9Sstevel@tonic-gate cpu_pause_init(); 15227c478bd9Sstevel@tonic-gate 1523f34a7178SJoe Bonasera xc_init_cpu(CPU); /* initialize processor crosscalls */ 15247c478bd9Sstevel@tonic-gate 1525ae115bc7Smrj if (mach_cpucontext_init() != 0) 15267c478bd9Sstevel@tonic-gate goto done; 15277c478bd9Sstevel@tonic-gate 15287c478bd9Sstevel@tonic-gate flushes_require_xcalls = 1; 15297c478bd9Sstevel@tonic-gate 15305205ae23Snf /* 15315205ae23Snf * We lock our affinity to the master CPU to ensure that all slave CPUs 15325205ae23Snf * do their TSC syncs with the same CPU. 15335205ae23Snf */ 15347c478bd9Sstevel@tonic-gate affinity_set(CPU_CURRENT); 15357c478bd9Sstevel@tonic-gate 15367c478bd9Sstevel@tonic-gate for (who = 0; who < NCPU; who++) { 153741791439Sandrei if (!CPU_IN_SET(mp_cpus, who)) 153841791439Sandrei continue; 1539ae115bc7Smrj ASSERT(who != bootcpuid); 1540b9e93c10SJonathan Haslam 1541b9e93c10SJonathan Haslam mutex_enter(&cpu_lock); 1542a3114836SGerry Liu if (start_cpu(who) != 0) 1543a3114836SGerry Liu CPUSET_DEL(mp_cpus, who); 1544b9e93c10SJonathan Haslam cpu_state_change_notify(who, CPU_SETUP); 1545b9e93c10SJonathan Haslam mutex_exit(&cpu_lock); 15467c478bd9Sstevel@tonic-gate } 15477c478bd9Sstevel@tonic-gate 15482449e17fSsherrym /* Free the space allocated to hold the microcode file */ 1549adc586deSMark Johnson ucode_cleanup(); 15502449e17fSsherrym 15517c478bd9Sstevel@tonic-gate affinity_clear(); 15527c478bd9Sstevel@tonic-gate 1553a3114836SGerry Liu mach_cpucontext_fini(); 1554a3114836SGerry Liu 1555a3114836SGerry Liu done: 1556a3114836SGerry Liu if (get_hwenv() == HW_NATIVE) 1557a3114836SGerry Liu workaround_errata_end(); 1558a3114836SGerry Liu cmi_post_mpstartup(); 1559a3114836SGerry Liu 1560a3114836SGerry Liu if (use_mp && ncpus != boot_max_ncpus) { 156141791439Sandrei cmn_err(CE_NOTE, 1562ae115bc7Smrj "System detected %d cpus, but " 1563ae115bc7Smrj "only %d cpu(s) were enabled during boot.", 1564a3114836SGerry Liu boot_max_ncpus, ncpus); 156541791439Sandrei cmn_err(CE_NOTE, 156641791439Sandrei "Use \"boot-ncpus\" parameter to enable more CPU(s). " 156741791439Sandrei "See eeprom(1M)."); 156841791439Sandrei } 15697c478bd9Sstevel@tonic-gate } 15707c478bd9Sstevel@tonic-gate 15717c478bd9Sstevel@tonic-gate int 15727c478bd9Sstevel@tonic-gate mp_cpu_configure(int cpuid) 15737c478bd9Sstevel@tonic-gate { 1574a3114836SGerry Liu cpu_t *cp; 1575a3114836SGerry Liu 1576a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1577a3114836SGerry Liu return (ENOTSUP); 1578a3114836SGerry Liu } 1579a3114836SGerry Liu 1580a3114836SGerry Liu cp = cpu_get(cpuid); 1581a3114836SGerry Liu if (cp != NULL) { 1582a3114836SGerry Liu return (EALREADY); 1583a3114836SGerry Liu } 1584a3114836SGerry Liu 1585a3114836SGerry Liu /* 1586a3114836SGerry Liu * Check if there's at least a Mbyte of kmem available 1587a3114836SGerry Liu * before attempting to start the cpu. 1588a3114836SGerry Liu */ 1589a3114836SGerry Liu if (kmem_avail() < 1024 * 1024) { 1590a3114836SGerry Liu /* 1591a3114836SGerry Liu * Kick off a reap in case that helps us with 1592a3114836SGerry Liu * later attempts .. 1593a3114836SGerry Liu */ 1594a3114836SGerry Liu kmem_reap(); 1595a3114836SGerry Liu return (ENOMEM); 1596a3114836SGerry Liu } 1597a3114836SGerry Liu 1598a3114836SGerry Liu cp = mp_cpu_configure_common(cpuid, B_FALSE); 1599a3114836SGerry Liu ASSERT(cp != NULL && cpu_get(cpuid) == cp); 1600a3114836SGerry Liu 1601a3114836SGerry Liu return (cp != NULL ? 0 : EAGAIN); 16027c478bd9Sstevel@tonic-gate } 16037c478bd9Sstevel@tonic-gate 16047c478bd9Sstevel@tonic-gate int 16057c478bd9Sstevel@tonic-gate mp_cpu_unconfigure(int cpuid) 16067c478bd9Sstevel@tonic-gate { 1607a3114836SGerry Liu cpu_t *cp; 1608a3114836SGerry Liu 1609a3114836SGerry Liu if (use_mp == 0 || plat_dr_support_cpu() == 0) { 1610a3114836SGerry Liu return (ENOTSUP); 1611a3114836SGerry Liu } else if (cpuid < 0 || cpuid >= max_ncpus) { 1612a3114836SGerry Liu return (EINVAL); 1613a3114836SGerry Liu } 1614a3114836SGerry Liu 1615a3114836SGerry Liu cp = cpu_get(cpuid); 1616a3114836SGerry Liu if (cp == NULL) { 1617a3114836SGerry Liu return (ENODEV); 1618a3114836SGerry Liu } 1619a3114836SGerry Liu mp_cpu_unconfigure_common(cp, 0); 1620a3114836SGerry Liu 1621a3114836SGerry Liu return (0); 16227c478bd9Sstevel@tonic-gate } 16237c478bd9Sstevel@tonic-gate 16247c478bd9Sstevel@tonic-gate /* 16257c478bd9Sstevel@tonic-gate * Startup function for 'other' CPUs (besides boot cpu). 1626498697c5Sdmick * Called from real_mode_start. 1627b4b46911Skchow * 1628a3114836SGerry Liu * WARNING: until CPU_READY is set, mp_startup_common and routines called by 1629a3114836SGerry Liu * mp_startup_common should not call routines (e.g. kmem_free) that could call 1630b4b46911Skchow * hat_unload which requires CPU_READY to be set. 16317c478bd9Sstevel@tonic-gate */ 1632a3114836SGerry Liu static void 1633a3114836SGerry Liu mp_startup_common(boolean_t boot) 16347c478bd9Sstevel@tonic-gate { 1635a3114836SGerry Liu cpu_t *cp = CPU; 1636dfea898aSKuriakose Kuruvilla uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 1637a3114836SGerry Liu extern void cpu_event_init_cpu(cpu_t *); 16387c478bd9Sstevel@tonic-gate 163924a74e86Sdmick /* 164024a74e86Sdmick * We need to get TSC on this proc synced (i.e., any delta 164124a74e86Sdmick * from cpu0 accounted for) as soon as we can, because many 164224a74e86Sdmick * many things use gethrtime/pc_gethrestime, including 16434948216cSKeith M Wesolowski * interrupts, cmn_err, etc. Before we can do that, we want to 16444948216cSKeith M Wesolowski * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that 16454948216cSKeith M Wesolowski * right away. 164624a74e86Sdmick */ 16474948216cSKeith M Wesolowski bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES)); 16484948216cSKeith M Wesolowski cpuid_pass1(cp, new_x86_featureset); 16494948216cSKeith M Wesolowski 16504948216cSKeith M Wesolowski if (boot && get_hwenv() == HW_NATIVE && 16514948216cSKeith M Wesolowski cpuid_getvendor(CPU) == X86_VENDOR_Intel && 16524948216cSKeith M Wesolowski cpuid_getfamily(CPU) == 6 && 16534948216cSKeith M Wesolowski (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 16544948216cSKeith M Wesolowski is_x86_feature(new_x86_featureset, X86FSET_TSC)) { 16554948216cSKeith M Wesolowski (void) wrmsr(REG_TSC, 0UL); 16564948216cSKeith M Wesolowski } 165724a74e86Sdmick 1658a3114836SGerry Liu /* Let the control CPU continue into tsc_sync_master() */ 1659a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 166024a74e86Sdmick 1661843e1988Sjohnlev #ifndef __xpv 166224a74e86Sdmick if (tsc_gethrtime_enable) 166324a74e86Sdmick tsc_sync_slave(); 1664843e1988Sjohnlev #endif 166524a74e86Sdmick 1666498697c5Sdmick /* 1667498697c5Sdmick * Once this was done from assembly, but it's safer here; if 1668498697c5Sdmick * it blocks, we need to be able to swtch() to and from, and 1669498697c5Sdmick * since we get here by calling t_pc, we need to do that call 1670498697c5Sdmick * before swtch() overwrites it. 1671498697c5Sdmick */ 1672498697c5Sdmick (void) (*ap_mlsetup)(); 1673498697c5Sdmick 1674843e1988Sjohnlev #ifndef __xpv 16757c478bd9Sstevel@tonic-gate /* 16761d03c31eSjohnlev * Program this cpu's PAT 16777c478bd9Sstevel@tonic-gate */ 167858865bb7SJosef 'Jeff' Sipek pat_sync(); 1679843e1988Sjohnlev #endif 16807c478bd9Sstevel@tonic-gate 1681ae115bc7Smrj /* 1682ae115bc7Smrj * Set up TSC_AUX to contain the cpuid for this processor 1683ae115bc7Smrj * for the rdtscp instruction. 1684ae115bc7Smrj */ 16857417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 1686ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1687ae115bc7Smrj 16887c478bd9Sstevel@tonic-gate /* 16897c478bd9Sstevel@tonic-gate * Initialize this CPU's syscall handlers 16907c478bd9Sstevel@tonic-gate */ 16917c478bd9Sstevel@tonic-gate init_cpu_syscall(cp); 16927c478bd9Sstevel@tonic-gate 16937c478bd9Sstevel@tonic-gate /* 16947c478bd9Sstevel@tonic-gate * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 16957c478bd9Sstevel@tonic-gate * highest level at which a routine is permitted to block on 16967c478bd9Sstevel@tonic-gate * an adaptive mutex (allows for cpu poke interrupt in case 16977c478bd9Sstevel@tonic-gate * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 16987c478bd9Sstevel@tonic-gate * device interrupts that may end up in the hat layer issuing cross 16997c478bd9Sstevel@tonic-gate * calls before CPU_READY is set. 17007c478bd9Sstevel@tonic-gate */ 1701ae115bc7Smrj splx(ipltospl(LOCK_LEVEL)); 1702ae115bc7Smrj sti(); 17037c478bd9Sstevel@tonic-gate 17047c478bd9Sstevel@tonic-gate /* 17057c478bd9Sstevel@tonic-gate * Do a sanity check to make sure this new CPU is a sane thing 17067c478bd9Sstevel@tonic-gate * to add to the collection of processors running this system. 17077c478bd9Sstevel@tonic-gate * 17087c478bd9Sstevel@tonic-gate * XXX Clearly this needs to get more sophisticated, if x86 17097c478bd9Sstevel@tonic-gate * systems start to get built out of heterogenous CPUs; as is 17107c478bd9Sstevel@tonic-gate * likely to happen once the number of processors in a configuration 17117c478bd9Sstevel@tonic-gate * gets large enough. 17127c478bd9Sstevel@tonic-gate */ 17137417cfdeSKuriakose Kuruvilla if (compare_x86_featureset(x86_featureset, new_x86_featureset) == 17147417cfdeSKuriakose Kuruvilla B_FALSE) { 17157417cfdeSKuriakose Kuruvilla cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id); 17167417cfdeSKuriakose Kuruvilla print_x86_featureset(new_x86_featureset); 17177c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 17187c478bd9Sstevel@tonic-gate } 17197c478bd9Sstevel@tonic-gate 1720f98fbcecSbholler /* 1721f98fbcecSbholler * We do not support cpus with mixed monitor/mwait support if the 1722f98fbcecSbholler * boot cpu supports monitor/mwait. 1723f98fbcecSbholler */ 17247417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MWAIT) != 17257417cfdeSKuriakose Kuruvilla is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) 1726f98fbcecSbholler panic("unsupported mixed cpu monitor/mwait support detected"); 1727f98fbcecSbholler 17287c478bd9Sstevel@tonic-gate /* 17297c478bd9Sstevel@tonic-gate * We could be more sophisticated here, and just mark the CPU 17307c478bd9Sstevel@tonic-gate * as "faulted" but at this point we'll opt for the easier 1731fb2caebeSRandy Fishel * answer of dying horribly. Provided the boot cpu is ok, 17327c478bd9Sstevel@tonic-gate * the system can be recovered by booting with use_mp set to zero. 17337c478bd9Sstevel@tonic-gate */ 17347c478bd9Sstevel@tonic-gate if (workaround_errata(cp) != 0) 17357c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 17367c478bd9Sstevel@tonic-gate 1737a3114836SGerry Liu /* 1738a3114836SGerry Liu * We can touch cpu_flags here without acquiring the cpu_lock here 1739a3114836SGerry Liu * because the cpu_lock is held by the control CPU which is running 1740a3114836SGerry Liu * mp_start_cpu_common(). 1741a3114836SGerry Liu * Need to clear CPU_QUIESCED flag before calling any function which 1742a3114836SGerry Liu * may cause thread context switching, such as kmem_alloc() etc. 1743a3114836SGerry Liu * The idle thread checks for CPU_QUIESCED flag and loops for ever if 1744a3114836SGerry Liu * it's set. So the startup thread may have no chance to switch back 1745a3114836SGerry Liu * again if it's switched away with CPU_QUIESCED set. 1746a3114836SGerry Liu */ 1747a3114836SGerry Liu cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED); 1748a3114836SGerry Liu 17497af88ac7SKuriakose Kuruvilla /* 17507af88ac7SKuriakose Kuruvilla * Setup this processor for XSAVE. 17517af88ac7SKuriakose Kuruvilla */ 17527af88ac7SKuriakose Kuruvilla if (fp_save_mech == FP_XSAVE) { 17537af88ac7SKuriakose Kuruvilla xsave_setup_msr(cp); 17547af88ac7SKuriakose Kuruvilla } 17557af88ac7SKuriakose Kuruvilla 17567c478bd9Sstevel@tonic-gate cpuid_pass2(cp); 17577c478bd9Sstevel@tonic-gate cpuid_pass3(cp); 1758ebb8ac07SRobert Mustacchi cpuid_pass4(cp, NULL); 17597c478bd9Sstevel@tonic-gate 17602449e17fSsherrym /* 1761a3114836SGerry Liu * Correct cpu_idstr and cpu_brandstr on target CPU after 1762a3114836SGerry Liu * cpuid_pass1() is done. 17632449e17fSsherrym */ 1764a3114836SGerry Liu (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN); 1765a3114836SGerry Liu (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN); 17662449e17fSsherrym 1767a3114836SGerry Liu cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS; 17687c478bd9Sstevel@tonic-gate 1769e774b42bSBill Holler post_startup_cpu_fixups(); 1770e774b42bSBill Holler 1771a3114836SGerry Liu cpu_event_init_cpu(cp); 1772a3114836SGerry Liu 1773aa7b6435Ssethg /* 1774aa7b6435Ssethg * Enable preemption here so that contention for any locks acquired 1775a3114836SGerry Liu * later in mp_startup_common may be preempted if the thread owning 1776a3114836SGerry Liu * those locks is continuously executing on other CPUs (for example, 1777a3114836SGerry Liu * this CPU must be preemptible to allow other CPUs to pause it during 1778a3114836SGerry Liu * their startup phases). It's safe to enable preemption here because 1779a3114836SGerry Liu * the CPU state is pretty-much fully constructed. 1780aa7b6435Ssethg */ 1781aa7b6435Ssethg curthread->t_preempt = 0; 1782aa7b6435Ssethg 1783da43ceabSsethg /* The base spl should still be at LOCK LEVEL here */ 1784da43ceabSsethg ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1785da43ceabSsethg set_base_spl(); /* Restore the spl to its proper value */ 1786da43ceabSsethg 1787a3114836SGerry Liu pghw_physid_create(cp); 17880e751525SEric Saxe /* 1789a3114836SGerry Liu * Delegate initialization tasks, which need to access the cpu_lock, 1790a3114836SGerry Liu * to mp_start_cpu_common() because we can't acquire the cpu_lock here 1791a3114836SGerry Liu * during CPU DR operations. 17920e751525SEric Saxe */ 1793a3114836SGerry Liu mp_startup_signal(&procset_slave, cp->cpu_id); 1794a3114836SGerry Liu mp_startup_wait(&procset_master, cp->cpu_id); 17950e751525SEric Saxe pg_cmt_cpu_startup(cp); 1796a3114836SGerry Liu 1797a3114836SGerry Liu if (boot) { 1798a3114836SGerry Liu mutex_enter(&cpu_lock); 1799a3114836SGerry Liu cp->cpu_flags &= ~CPU_OFFLINE; 1800a3114836SGerry Liu cpu_enable_intr(cp); 1801a3114836SGerry Liu cpu_add_active(cp); 1802a3114836SGerry Liu mutex_exit(&cpu_lock); 1803a3114836SGerry Liu } 18040e751525SEric Saxe 1805afbc4541Ssherrym /* Enable interrupts */ 1806afbc4541Ssherrym (void) spl0(); 18070e751525SEric Saxe 1808a3114836SGerry Liu /* 1809a3114836SGerry Liu * Fill out cpu_ucode_info. Update microcode if necessary. 1810a3114836SGerry Liu */ 1811a3114836SGerry Liu ucode_check(cp); 1812afbc4541Ssherrym 181320c794b3Sgavinm #ifndef __xpv 181420c794b3Sgavinm { 181520c794b3Sgavinm /* 181620c794b3Sgavinm * Set up the CPU module for this CPU. This can't be done 181720c794b3Sgavinm * before this CPU is made CPU_READY, because we may (in 181820c794b3Sgavinm * heterogeneous systems) need to go load another CPU module. 181920c794b3Sgavinm * The act of attempting to load a module may trigger a 182020c794b3Sgavinm * cross-call, which will ASSERT unless this cpu is CPU_READY. 182120c794b3Sgavinm */ 182220c794b3Sgavinm cmi_hdl_t hdl; 18237aec1d6eScindi 182420c794b3Sgavinm if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU), 1825e4b86885SCheng Sean Ye cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) { 18267417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MCA)) 182720c794b3Sgavinm cmi_mca_init(hdl); 1828a3114836SGerry Liu cp->cpu_m.mcpu_cmi_hdl = hdl; 182920c794b3Sgavinm } 183020c794b3Sgavinm } 183120c794b3Sgavinm #endif /* __xpv */ 18327aec1d6eScindi 18337c478bd9Sstevel@tonic-gate if (boothowto & RB_DEBUG) 1834ae115bc7Smrj kdi_cpu_init(); 18357c478bd9Sstevel@tonic-gate 18367c478bd9Sstevel@tonic-gate /* 18377c478bd9Sstevel@tonic-gate * Setting the bit in cpu_ready_set must be the last operation in 18387c478bd9Sstevel@tonic-gate * processor initialization; the boot CPU will continue to boot once 18397c478bd9Sstevel@tonic-gate * it sees this bit set for all active CPUs. 18407c478bd9Sstevel@tonic-gate */ 18417c478bd9Sstevel@tonic-gate CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 18427c478bd9Sstevel@tonic-gate 1843fa96bd91SMichael Corcoran (void) mach_cpu_create_device_node(cp, NULL); 1844fa96bd91SMichael Corcoran 1845a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 1846a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 1847a3114836SGerry Liu cmn_err(CE_CONT, "?cpu%d initialization complete - online\n", 1848a3114836SGerry Liu cp->cpu_id); 1849a3114836SGerry Liu 18507c478bd9Sstevel@tonic-gate /* 18517c478bd9Sstevel@tonic-gate * Now we are done with the startup thread, so free it up. 18527c478bd9Sstevel@tonic-gate */ 18537c478bd9Sstevel@tonic-gate thread_exit(); 18547c478bd9Sstevel@tonic-gate panic("mp_startup: cannot return"); 18557c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 18567c478bd9Sstevel@tonic-gate } 18577c478bd9Sstevel@tonic-gate 1858a3114836SGerry Liu /* 1859a3114836SGerry Liu * Startup function for 'other' CPUs at boot time (besides boot cpu). 1860a3114836SGerry Liu */ 1861a3114836SGerry Liu static void 1862a3114836SGerry Liu mp_startup_boot(void) 1863a3114836SGerry Liu { 1864a3114836SGerry Liu mp_startup_common(B_TRUE); 1865a3114836SGerry Liu } 1866a3114836SGerry Liu 1867a3114836SGerry Liu /* 1868a3114836SGerry Liu * Startup function for hotplug CPUs at runtime. 1869a3114836SGerry Liu */ 1870a3114836SGerry Liu void 1871a3114836SGerry Liu mp_startup_hotplug(void) 1872a3114836SGerry Liu { 1873a3114836SGerry Liu mp_startup_common(B_FALSE); 1874a3114836SGerry Liu } 18757c478bd9Sstevel@tonic-gate 18767c478bd9Sstevel@tonic-gate /* 18777c478bd9Sstevel@tonic-gate * Start CPU on user request. 18787c478bd9Sstevel@tonic-gate */ 18797c478bd9Sstevel@tonic-gate /* ARGSUSED */ 18807c478bd9Sstevel@tonic-gate int 18817c478bd9Sstevel@tonic-gate mp_cpu_start(struct cpu *cp) 18827c478bd9Sstevel@tonic-gate { 18837c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 18847c478bd9Sstevel@tonic-gate return (0); 18857c478bd9Sstevel@tonic-gate } 18867c478bd9Sstevel@tonic-gate 18877c478bd9Sstevel@tonic-gate /* 18887c478bd9Sstevel@tonic-gate * Stop CPU on user request. 18897c478bd9Sstevel@tonic-gate */ 18907c478bd9Sstevel@tonic-gate int 18917c478bd9Sstevel@tonic-gate mp_cpu_stop(struct cpu *cp) 18927c478bd9Sstevel@tonic-gate { 1893d90554ebSdmick extern int cbe_psm_timer_mode; 18947c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 1895d90554ebSdmick 1896843e1988Sjohnlev #ifdef __xpv 1897843e1988Sjohnlev /* 1898843e1988Sjohnlev * We can't offline vcpu0. 1899843e1988Sjohnlev */ 1900843e1988Sjohnlev if (cp->cpu_id == 0) 1901843e1988Sjohnlev return (EBUSY); 1902843e1988Sjohnlev #endif 1903843e1988Sjohnlev 1904d90554ebSdmick /* 1905d90554ebSdmick * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1906d90554ebSdmick * can't stop it. (This is true only for machines with no TSC.) 1907d90554ebSdmick */ 1908d90554ebSdmick 1909d90554ebSdmick if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1910843e1988Sjohnlev return (EBUSY); 19117c478bd9Sstevel@tonic-gate 19127c478bd9Sstevel@tonic-gate return (0); 19137c478bd9Sstevel@tonic-gate } 19147c478bd9Sstevel@tonic-gate 19157c478bd9Sstevel@tonic-gate /* 19167c478bd9Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 19177c478bd9Sstevel@tonic-gate */ 19187c478bd9Sstevel@tonic-gate int 19197c478bd9Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 19207c478bd9Sstevel@tonic-gate { 19217c478bd9Sstevel@tonic-gate if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 19227c478bd9Sstevel@tonic-gate return (EBUSY); 19237c478bd9Sstevel@tonic-gate 19247c478bd9Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 19257c478bd9Sstevel@tonic-gate return (0); 19267c478bd9Sstevel@tonic-gate } 19277c478bd9Sstevel@tonic-gate 19287c478bd9Sstevel@tonic-gate /* 19297c478bd9Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 19307c478bd9Sstevel@tonic-gate */ 19317c478bd9Sstevel@tonic-gate void 19327c478bd9Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 19337c478bd9Sstevel@tonic-gate { 19347c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 19357c478bd9Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 19367c478bd9Sstevel@tonic-gate psm_enable_intr(cp->cpu_id); 19377c478bd9Sstevel@tonic-gate } 19387c478bd9Sstevel@tonic-gate 19397c478bd9Sstevel@tonic-gate void 19407c478bd9Sstevel@tonic-gate mp_cpu_faulted_enter(struct cpu *cp) 19417aec1d6eScindi { 1942a3114836SGerry Liu #ifdef __xpv 1943a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1944a3114836SGerry Liu #else 1945a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 194620c794b3Sgavinm 1947a3114836SGerry Liu if (hdl != NULL) { 1948a3114836SGerry Liu cmi_hdl_hold(hdl); 1949a3114836SGerry Liu } else { 1950a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1951a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1952a3114836SGerry Liu } 195320c794b3Sgavinm if (hdl != NULL) { 195420c794b3Sgavinm cmi_faulted_enter(hdl); 195520c794b3Sgavinm cmi_hdl_rele(hdl); 195620c794b3Sgavinm } 195720c794b3Sgavinm #endif 19587aec1d6eScindi } 19597c478bd9Sstevel@tonic-gate 19607c478bd9Sstevel@tonic-gate void 19617c478bd9Sstevel@tonic-gate mp_cpu_faulted_exit(struct cpu *cp) 19627aec1d6eScindi { 1963a3114836SGerry Liu #ifdef __xpv 1964a3114836SGerry Liu _NOTE(ARGUNUSED(cp)); 1965a3114836SGerry Liu #else 1966a3114836SGerry Liu cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl; 196720c794b3Sgavinm 1968a3114836SGerry Liu if (hdl != NULL) { 1969a3114836SGerry Liu cmi_hdl_hold(hdl); 1970a3114836SGerry Liu } else { 1971a3114836SGerry Liu hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp), 1972a3114836SGerry Liu cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp)); 1973a3114836SGerry Liu } 197420c794b3Sgavinm if (hdl != NULL) { 197520c794b3Sgavinm cmi_faulted_exit(hdl); 197620c794b3Sgavinm cmi_hdl_rele(hdl); 197720c794b3Sgavinm } 197820c794b3Sgavinm #endif 19797aec1d6eScindi } 19807c478bd9Sstevel@tonic-gate 19817c478bd9Sstevel@tonic-gate /* 19827c478bd9Sstevel@tonic-gate * The following two routines are used as context operators on threads belonging 19837c478bd9Sstevel@tonic-gate * to processes with a private LDT (see sysi86). Due to the rarity of such 19847c478bd9Sstevel@tonic-gate * processes, these routines are currently written for best code readability and 19857417cfdeSKuriakose Kuruvilla * organization rather than speed. We could avoid checking x86_featureset at 19867417cfdeSKuriakose Kuruvilla * every context switch by installing different context ops, depending on 19877417cfdeSKuriakose Kuruvilla * x86_featureset, at LDT creation time -- one for each combination of fast 19887417cfdeSKuriakose Kuruvilla * syscall features. 19897c478bd9Sstevel@tonic-gate */ 19907c478bd9Sstevel@tonic-gate 19917c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 19927c478bd9Sstevel@tonic-gate void 19937c478bd9Sstevel@tonic-gate cpu_fast_syscall_disable(void *arg) 19947c478bd9Sstevel@tonic-gate { 19957417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 19967417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 19977c478bd9Sstevel@tonic-gate cpu_sep_disable(); 19987417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 19997417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 20007c478bd9Sstevel@tonic-gate cpu_asysc_disable(); 20017c478bd9Sstevel@tonic-gate } 20027c478bd9Sstevel@tonic-gate 20037c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 20047c478bd9Sstevel@tonic-gate void 20057c478bd9Sstevel@tonic-gate cpu_fast_syscall_enable(void *arg) 20067c478bd9Sstevel@tonic-gate { 20077417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20087417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SEP)) 20097c478bd9Sstevel@tonic-gate cpu_sep_enable(); 20107417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_MSR) && 20117417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_ASYSC)) 20127c478bd9Sstevel@tonic-gate cpu_asysc_enable(); 20137c478bd9Sstevel@tonic-gate } 20147c478bd9Sstevel@tonic-gate 20157c478bd9Sstevel@tonic-gate static void 20167c478bd9Sstevel@tonic-gate cpu_sep_enable(void) 20177c478bd9Sstevel@tonic-gate { 20187417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 20197c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20207c478bd9Sstevel@tonic-gate 20210ac7d7d8Skucharsk wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 20227c478bd9Sstevel@tonic-gate } 20237c478bd9Sstevel@tonic-gate 20247c478bd9Sstevel@tonic-gate static void 20257c478bd9Sstevel@tonic-gate cpu_sep_disable(void) 20267c478bd9Sstevel@tonic-gate { 20277417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP)); 20287c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20297c478bd9Sstevel@tonic-gate 20307c478bd9Sstevel@tonic-gate /* 20317c478bd9Sstevel@tonic-gate * Setting the SYSENTER_CS_MSR register to 0 causes software executing 20327c478bd9Sstevel@tonic-gate * the sysenter or sysexit instruction to trigger a #gp fault. 20337c478bd9Sstevel@tonic-gate */ 2034ae115bc7Smrj wrmsr(MSR_INTC_SEP_CS, 0); 20357c478bd9Sstevel@tonic-gate } 20367c478bd9Sstevel@tonic-gate 20377c478bd9Sstevel@tonic-gate static void 20387c478bd9Sstevel@tonic-gate cpu_asysc_enable(void) 20397c478bd9Sstevel@tonic-gate { 20407417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 20417c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20427c478bd9Sstevel@tonic-gate 20430ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 20440ac7d7d8Skucharsk (uint64_t)(uintptr_t)AMD_EFER_SCE); 20457c478bd9Sstevel@tonic-gate } 20467c478bd9Sstevel@tonic-gate 20477c478bd9Sstevel@tonic-gate static void 20487c478bd9Sstevel@tonic-gate cpu_asysc_disable(void) 20497c478bd9Sstevel@tonic-gate { 20507417cfdeSKuriakose Kuruvilla ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC)); 20517c478bd9Sstevel@tonic-gate ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 20527c478bd9Sstevel@tonic-gate 20537c478bd9Sstevel@tonic-gate /* 20547c478bd9Sstevel@tonic-gate * Turn off the SCE (syscall enable) bit in the EFER register. Software 20557c478bd9Sstevel@tonic-gate * executing syscall or sysret with this bit off will incur a #ud trap. 20567c478bd9Sstevel@tonic-gate */ 20570ac7d7d8Skucharsk wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 20580ac7d7d8Skucharsk ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 20597c478bd9Sstevel@tonic-gate } 2060