1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/disp.h> 31 #include <sys/promif.h> 32 #include <sys/clock.h> 33 #include <sys/cpuvar.h> 34 #include <sys/stack.h> 35 #include <vm/as.h> 36 #include <vm/hat.h> 37 #include <sys/reboot.h> 38 #include <sys/avintr.h> 39 #include <sys/vtrace.h> 40 #include <sys/proc.h> 41 #include <sys/thread.h> 42 #include <sys/cpupart.h> 43 #include <sys/pset.h> 44 #include <sys/copyops.h> 45 #include <sys/chip.h> 46 #include <sys/disp.h> 47 #include <sys/debug.h> 48 #include <sys/sunddi.h> 49 #include <sys/x86_archext.h> 50 #include <sys/privregs.h> 51 #include <sys/machsystm.h> 52 #include <sys/ontrap.h> 53 #include <sys/bootconf.h> 54 #include <sys/kdi.h> 55 #include <sys/archsystm.h> 56 #include <sys/promif.h> 57 #include <sys/bootconf.h> 58 #include <sys/kobj.h> 59 #include <sys/kobj_lex.h> 60 #include <sys/pci_cfgspace.h> 61 #if defined(__amd64) 62 #include <sys/bootsvcs.h> 63 64 /* 65 * XX64 This stuff deals with switching stacks in case a trapping 66 * thread wants to call back into boot -after- boot has lost track 67 * of the mappings but before the kernel owns the console. 68 * 69 * (A better way to hide this would be to add a 'this' pointer to 70 * every boot syscall so that vmx could get at the resulting save 71 * area.) 72 */ 73 74 struct boot_syscalls *_vmx_sysp; 75 static struct boot_syscalls __kbootsvcs; 76 extern struct boot_syscalls *sysp; 77 extern void _stack_safe_putchar(int c); 78 #endif 79 80 /* 81 * some globals for patching the result of cpuid 82 * to solve problems w/ creative cpu vendors 83 */ 84 85 extern uint32_t cpuid_feature_ecx_include; 86 extern uint32_t cpuid_feature_ecx_exclude; 87 extern uint32_t cpuid_feature_edx_include; 88 extern uint32_t cpuid_feature_edx_exclude; 89 90 /* 91 * External Routines: 92 */ 93 94 extern void init_tables(void); 95 96 97 static uint32_t 98 cpuid_getval(char *name) 99 { 100 char prop[32]; 101 u_longlong_t ll; 102 extern struct bootops *bootops; 103 if ((BOP_GETPROPLEN(bootops, name) > sizeof (prop)) || 104 (BOP_GETPROP(bootops, name, prop) < 0) || 105 (kobj_getvalue(prop, &ll) == -1)) 106 return (0); 107 return ((uint32_t)ll); 108 } 109 110 /* 111 * Setup routine called right before main(). Interposing this function 112 * before main() allows us to call it in a machine-independent fashion. 113 */ 114 void 115 mlsetup(struct regs *rp) 116 { 117 extern struct classfuncs sys_classfuncs; 118 extern struct chip cpu0_chip; 119 extern disp_t cpu0_disp; 120 extern char t0stack[]; 121 122 ASSERT_STACK_ALIGNED(); 123 124 #if defined(__amd64) 125 126 #if (BS_VERSION > 4) 127 /* 128 * When new boot_syscalls are added to the vector, this routine 129 * must be modified to copy them into the kernel's copy of the 130 * vector. 131 */ 132 #error mlsetup() must be updated for amd64 to support new boot_syscalls 133 #endif /* (BS_VERSION > 4) */ 134 135 /* 136 * XX64 This remaps vmx's putchar to use the kernel's version 137 * that switches stacks before diving into vmx 138 * See explanation/complaints in commentary above. 139 */ 140 _vmx_sysp = sysp; 141 sysp = &__kbootsvcs; 142 143 sysp->bsvc_getchar = _vmx_sysp->bsvc_getchar; 144 sysp->bsvc_putchar = _stack_safe_putchar; 145 sysp->bsvc_ischar = _vmx_sysp->bsvc_ischar; 146 #endif 147 /* 148 * initialize cpu_self 149 */ 150 cpu[0]->cpu_self = cpu[0]; 151 152 /* 153 * check if we've got special bits to clear or set 154 * when checking cpu features 155 */ 156 157 cpuid_feature_ecx_include = 158 cpuid_getval("cpuid_feature_ecx_include"); 159 cpuid_feature_ecx_exclude = 160 cpuid_getval("cpuid_feature_ecx_exclude"); 161 cpuid_feature_edx_include = 162 cpuid_getval("cpuid_feature_edx_include"); 163 cpuid_feature_edx_exclude = 164 cpuid_getval("cpuid_feature_edx_exclude"); 165 166 /* 167 * The first lightweight pass (pass0) through the cpuid data 168 * was done in locore before mlsetup was called. Do the next 169 * pass in C code. 170 * 171 * The x86_feature bits are set here on the basis of the capabilities 172 * of the boot CPU. Note that if we choose to support CPUs that have 173 * different feature sets (at which point we would almost certainly 174 * want to set the feature bits to correspond to the feature 175 * minimum) this value may be altered. 176 */ 177 178 x86_feature = cpuid_pass1(cpu[0]); 179 180 /* 181 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 182 */ 183 init_tables(); 184 185 #if defined(__amd64) 186 /*CSTYLED*/ 187 { 188 /* 189 * setup %gs for the kernel 190 */ 191 uint64_t addr64 = (uint64_t)&cpus[0]; 192 wrmsr(MSR_AMD_GSBASE, &addr64); 193 /* 194 * XX64 We should never dereference off "other gsbase" or 195 * "fsbase". So, we should arrange to point FSBASE and 196 * KGSBASE somewhere truly awful e.g. point it at the last 197 * valid address below the hole so that any attempts to index 198 * off them cause an exception. 199 * 200 * For now, point it at 8G -- at least it should be unmapped 201 * until some 64-bit processes run. 202 */ 203 addr64 = 0x200000000ul; 204 wrmsr(MSR_AMD_FSBASE, &addr64); 205 wrmsr(MSR_AMD_KGSBASE, &addr64); 206 } 207 208 #elif defined(__i386) 209 /* 210 * enable large page support right here. 211 */ 212 if (x86_feature & X86_LARGEPAGE) { 213 cr4_value |= CR4_PSE; 214 if (x86_feature & X86_PGE) 215 cr4_value |= CR4_PGE; 216 setup_121_andcall(enable_big_page_support, cr4_value); 217 } 218 219 /* 220 * Some i386 processors do not implement the rdtsc instruction, 221 * or at least they do not implement it correctly. 222 * 223 * For those that do, patch in the rdtsc instructions in 224 * various parts of the kernel right now while the text is 225 * still writable. 226 */ 227 if (x86_feature & X86_TSC) 228 patch_tsc(); 229 #endif 230 231 /* 232 * initialize t0 233 */ 234 t0.t_stk = (caddr_t)rp - MINFRAME; 235 t0.t_stkbase = t0stack; 236 t0.t_pri = maxclsyspri - 3; 237 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 238 t0.t_procp = &p0; 239 t0.t_plockp = &p0lock.pl_lock; 240 t0.t_lwp = &lwp0; 241 t0.t_forw = &t0; 242 t0.t_back = &t0; 243 t0.t_next = &t0; 244 t0.t_prev = &t0; 245 t0.t_cpu = cpu[0]; 246 t0.t_disp_queue = &cpu0_disp; 247 t0.t_bind_cpu = PBIND_NONE; 248 t0.t_bind_pset = PS_NONE; 249 t0.t_cpupart = &cp_default; 250 t0.t_clfuncs = &sys_classfuncs.thread; 251 t0.t_copyops = NULL; 252 THREAD_ONPROC(&t0, CPU); 253 254 lwp0.lwp_thread = &t0; 255 lwp0.lwp_regs = (void *) rp; 256 lwp0.lwp_procp = &p0; 257 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 258 259 p0.p_exec = NULL; 260 p0.p_stat = SRUN; 261 p0.p_flag = SSYS; 262 p0.p_tlist = &t0; 263 p0.p_stksize = 2*PAGESIZE; 264 p0.p_stkpageszc = 0; 265 p0.p_as = &kas; 266 p0.p_lockp = &p0lock; 267 p0.p_brkpageszc = 0; 268 sigorset(&p0.p_ignore, &ignoredefault); 269 270 CPU->cpu_thread = &t0; 271 bzero(&cpu0_disp, sizeof (disp_t)); 272 CPU->cpu_disp = &cpu0_disp; 273 CPU->cpu_disp->disp_cpu = CPU; 274 CPU->cpu_dispthread = &t0; 275 CPU->cpu_idle_thread = &t0; 276 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 277 CPU->cpu_dispatch_pri = t0.t_pri; 278 279 CPU->cpu_mask = 1; 280 CPU->cpu_id = 0; 281 282 CPU->cpu_tss = &ktss0; 283 284 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 285 286 CPU->cpu_ldt = ldt0_default; /* default LDT */ 287 CPU->cpu_gdt = gdt0; 288 289 /* 290 * This must be done _after_ init_tables(), called above, has set up 291 * ldt0_default_desc. 292 */ 293 #if defined(__amd64) 294 /* 295 * ldt0_default64 contains all invalid entries. We use that as p0's LDT 296 * because p0 should never have any reason to use the LDT. This will 297 * catch things early if such a scenario should ever occur. 298 */ 299 p0.p_ldt_desc = ldt0_default64_desc; 300 #else 301 p0.p_ldt_desc = ldt0_default_desc; 302 #endif /* __amd64 */ 303 304 /* 305 * Kernel IDT. 306 */ 307 CPU->cpu_idt = idt0; 308 309 /* 310 * Initialize thread/cpu microstate accounting here 311 */ 312 init_mstate(&t0, LMS_SYSTEM); 313 init_cpu_mstate(CPU, CMS_SYSTEM); 314 315 /* 316 * Initialize lists of available and active CPUs. 317 */ 318 cpu_list_init(CPU); 319 320 cpu_vm_data_init(CPU); 321 322 /* lgrp_init() needs PCI config space access */ 323 pci_cfgspace_init(); 324 325 /* 326 * Initialize the lgrp framework 327 */ 328 lgrp_init(); 329 330 /* 331 * The lgroup code needs to at least know about a CPU's 332 * chip association, but it's too early to fully initialize 333 * cpu0_chip, since the device node for the boot CPU doesn't 334 * exist yet. Initialize enough of it to get by until formal 335 * initialization. 336 */ 337 CPU->cpu_rechoose = rechoose_interval; 338 CPU->cpu_chip = &cpu0_chip; 339 340 rp->r_fp = 0; /* terminate kernel stack traces! */ 341 342 prom_init("kernel", (void *)NULL); 343 344 if (boothowto & RB_HALT) { 345 prom_printf("unix: kernel halted by -h flag\n"); 346 prom_enter_mon(); 347 } 348 349 ASSERT_STACK_ALIGNED(); 350 351 if (workaround_errata(CPU) != 0) 352 panic("critical workaround(s) missing for boot cpu"); 353 } 354