xref: /illumos-gate/usr/src/uts/i86pc/os/mlsetup.c (revision ae115bc77f6fcde83175c75b4206dc2e50747966)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 #include <sys/types.h>
29 #include <sys/sysmacros.h>
30 #include <sys/disp.h>
31 #include <sys/promif.h>
32 #include <sys/clock.h>
33 #include <sys/cpuvar.h>
34 #include <sys/stack.h>
35 #include <vm/as.h>
36 #include <vm/hat.h>
37 #include <sys/reboot.h>
38 #include <sys/avintr.h>
39 #include <sys/vtrace.h>
40 #include <sys/proc.h>
41 #include <sys/thread.h>
42 #include <sys/cpupart.h>
43 #include <sys/pset.h>
44 #include <sys/copyops.h>
45 #include <sys/pg.h>
46 #include <sys/disp.h>
47 #include <sys/debug.h>
48 #include <sys/sunddi.h>
49 #include <sys/x86_archext.h>
50 #include <sys/privregs.h>
51 #include <sys/machsystm.h>
52 #include <sys/ontrap.h>
53 #include <sys/bootconf.h>
54 #include <sys/kdi_machimpl.h>
55 #include <sys/archsystm.h>
56 #include <sys/promif.h>
57 #include <sys/bootconf.h>
58 #include <sys/kobj.h>
59 #include <sys/kobj_lex.h>
60 #include <sys/pci_cfgspace.h>
61 
62 /*
63  * some globals for patching the result of cpuid
64  * to solve problems w/ creative cpu vendors
65  */
66 
67 extern uint32_t cpuid_feature_ecx_include;
68 extern uint32_t cpuid_feature_ecx_exclude;
69 extern uint32_t cpuid_feature_edx_include;
70 extern uint32_t cpuid_feature_edx_exclude;
71 
72 /*
73  * Dummy spl priority masks
74  */
75 static unsigned char dummy_cpu_pri[MAXIPL + 1] = {
76 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf,
77 	0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf
78 };
79 
80 
81 static uint32_t
82 bootprop_getval(char *name)
83 {
84 	char prop[32];
85 	u_longlong_t ll;
86 	extern struct bootops *bootops;
87 	if ((BOP_GETPROPLEN(bootops, name) > sizeof (prop)) ||
88 	    (BOP_GETPROP(bootops, name, prop) < 0) ||
89 	    (kobj_getvalue(prop, &ll) == -1))
90 		return (0);
91 	return ((uint32_t)ll);
92 }
93 
94 /*
95  * Setup routine called right before main(). Interposing this function
96  * before main() allows us to call it in a machine-independent fashion.
97  */
98 void
99 mlsetup(struct regs *rp)
100 {
101 	extern struct classfuncs sys_classfuncs;
102 	extern disp_t cpu0_disp;
103 	extern char t0stack[];
104 	int boot_ncpus;
105 
106 	ASSERT_STACK_ALIGNED();
107 
108 	/*
109 	 * initialize cpu_self
110 	 */
111 	cpu[0]->cpu_self = cpu[0];
112 
113 	/*
114 	 * Set up dummy cpu_pri_data values till psm spl code is
115 	 * installed.  This allows splx() to work on amd64.
116 	 */
117 
118 	cpu[0]->cpu_pri_data = dummy_cpu_pri;
119 
120 	/*
121 	 * check if we've got special bits to clear or set
122 	 * when checking cpu features
123 	 */
124 
125 	cpuid_feature_ecx_include =
126 	    bootprop_getval("cpuid_feature_ecx_include");
127 	cpuid_feature_ecx_exclude =
128 	    bootprop_getval("cpuid_feature_ecx_exclude");
129 	cpuid_feature_edx_include =
130 	    bootprop_getval("cpuid_feature_edx_include");
131 	cpuid_feature_edx_exclude =
132 	    bootprop_getval("cpuid_feature_edx_exclude");
133 
134 	/*
135 	 * The first lightweight pass (pass0) through the cpuid data
136 	 * was done in locore before mlsetup was called.  Do the next
137 	 * pass in C code.
138 	 *
139 	 * The x86_feature bits are set here on the basis of the capabilities
140 	 * of the boot CPU.  Note that if we choose to support CPUs that have
141 	 * different feature sets (at which point we would almost certainly
142 	 * want to set the feature bits to correspond to the feature
143 	 * minimum) this value may be altered.
144 	 */
145 	x86_feature = cpuid_pass1(cpu[0]);
146 
147 	/*
148 	 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
149 	 */
150 	init_desctbls();
151 
152 
153 #if defined(__i386)
154 	/*
155 	 * Some i386 processors do not implement the rdtsc instruction,
156 	 * or at least they do not implement it correctly.
157 	 *
158 	 * For those that do, patch in the rdtsc instructions in
159 	 * various parts of the kernel right now while the text is
160 	 * still writable.
161 	 */
162 	if (x86_feature & X86_TSC)
163 		patch_tsc();
164 #endif	/* __i386 */
165 
166 	/*
167 	 * While we're thinking about the TSC, let's set up %cr4 so that
168 	 * userland can issue rdtsc, and initialize the TSC_AUX value
169 	 * (the cpuid) for the rdtscp instruction on appropriately
170 	 * capable hardware.
171 	 */
172 	if (x86_feature & X86_TSC)
173 		setcr4(getcr4() & ~CR4_TSD);
174 
175 	if (x86_feature & X86_TSCP)
176 		(void) wrmsr(MSR_AMD_TSCAUX, 0);
177 
178 	if (x86_feature & X86_DE)
179 		setcr4(getcr4() | CR4_DE);
180 
181 	/*
182 	 * initialize t0
183 	 */
184 	t0.t_stk = (caddr_t)rp - MINFRAME;
185 	t0.t_stkbase = t0stack;
186 	t0.t_pri = maxclsyspri - 3;
187 	t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
188 	t0.t_procp = &p0;
189 	t0.t_plockp = &p0lock.pl_lock;
190 	t0.t_lwp = &lwp0;
191 	t0.t_forw = &t0;
192 	t0.t_back = &t0;
193 	t0.t_next = &t0;
194 	t0.t_prev = &t0;
195 	t0.t_cpu = cpu[0];
196 	t0.t_disp_queue = &cpu0_disp;
197 	t0.t_bind_cpu = PBIND_NONE;
198 	t0.t_bind_pset = PS_NONE;
199 	t0.t_cpupart = &cp_default;
200 	t0.t_clfuncs = &sys_classfuncs.thread;
201 	t0.t_copyops = NULL;
202 	THREAD_ONPROC(&t0, CPU);
203 
204 	lwp0.lwp_thread = &t0;
205 	lwp0.lwp_regs = (void *)rp;
206 	lwp0.lwp_procp = &p0;
207 	t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
208 
209 	p0.p_exec = NULL;
210 	p0.p_stat = SRUN;
211 	p0.p_flag = SSYS;
212 	p0.p_tlist = &t0;
213 	p0.p_stksize = 2*PAGESIZE;
214 	p0.p_stkpageszc = 0;
215 	p0.p_as = &kas;
216 	p0.p_lockp = &p0lock;
217 	p0.p_brkpageszc = 0;
218 	sigorset(&p0.p_ignore, &ignoredefault);
219 
220 	CPU->cpu_thread = &t0;
221 	bzero(&cpu0_disp, sizeof (disp_t));
222 	CPU->cpu_disp = &cpu0_disp;
223 	CPU->cpu_disp->disp_cpu = CPU;
224 	CPU->cpu_dispthread = &t0;
225 	CPU->cpu_idle_thread = &t0;
226 	CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
227 	CPU->cpu_dispatch_pri = t0.t_pri;
228 
229 	CPU->cpu_id = 0;
230 
231 	CPU->cpu_pri = 12;		/* initial PIL for the boot CPU */
232 
233 	/*
234 	 * The kernel doesn't use LDTs unless a process explicitly requests one.
235 	 */
236 	p0.p_ldt_desc = zero_sdesc;
237 
238 	/*
239 	 * Initialize thread/cpu microstate accounting
240 	 */
241 	init_mstate(&t0, LMS_SYSTEM);
242 	init_cpu_mstate(CPU, CMS_SYSTEM);
243 
244 	/*
245 	 * Initialize lists of available and active CPUs.
246 	 */
247 	cpu_list_init(CPU);
248 
249 	/*
250 	 * Now that we have taken over the GDT, IDT and have initialized
251 	 * active CPU list it's time to inform kmdb if present.
252 	 */
253 	if (boothowto & RB_DEBUG)
254 		kdi_idt_sync();
255 
256 	/*
257 	 * If requested (boot -d) drop into kmdb.
258 	 *
259 	 * This must be done after cpu_list_init() on the 64-bit kernel
260 	 * since taking a trap requires that we re-compute gsbase based
261 	 * on the cpu list.
262 	 */
263 	if (boothowto & RB_DEBUGENTER)
264 		kmdb_enter();
265 
266 	cpu_vm_data_init(CPU);
267 
268 	/* lgrp_init() needs PCI config space access */
269 	pci_cfgspace_init();
270 
271 	/*
272 	 * Initialize the lgrp framework
273 	 */
274 	lgrp_init();
275 
276 	rp->r_fp = 0;	/* terminate kernel stack traces! */
277 
278 	prom_init("kernel", (void *)NULL);
279 
280 	boot_ncpus = bootprop_getval("boot-ncpus");
281 
282 	if (boot_ncpus <= 0 || boot_ncpus > NCPU)
283 		boot_ncpus = NCPU;
284 
285 	max_ncpus = boot_max_ncpus = boot_ncpus;
286 
287 	if (boothowto & RB_HALT) {
288 		prom_printf("unix: kernel halted by -h flag\n");
289 		prom_enter_mon();
290 	}
291 
292 	ASSERT_STACK_ALIGNED();
293 
294 	if (workaround_errata(CPU) != 0)
295 		panic("critical workaround(s) missing for boot cpu");
296 }
297