1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/types.h> 27 #include <sys/sysmacros.h> 28 #include <sys/disp.h> 29 #include <sys/promif.h> 30 #include <sys/clock.h> 31 #include <sys/cpuvar.h> 32 #include <sys/stack.h> 33 #include <vm/as.h> 34 #include <vm/hat.h> 35 #include <sys/reboot.h> 36 #include <sys/avintr.h> 37 #include <sys/vtrace.h> 38 #include <sys/proc.h> 39 #include <sys/thread.h> 40 #include <sys/cpupart.h> 41 #include <sys/pset.h> 42 #include <sys/copyops.h> 43 #include <sys/pg.h> 44 #include <sys/disp.h> 45 #include <sys/debug.h> 46 #include <sys/sunddi.h> 47 #include <sys/x86_archext.h> 48 #include <sys/privregs.h> 49 #include <sys/machsystm.h> 50 #include <sys/ontrap.h> 51 #include <sys/bootconf.h> 52 #include <sys/boot_console.h> 53 #include <sys/kdi_machimpl.h> 54 #include <sys/archsystm.h> 55 #include <sys/promif.h> 56 #include <sys/pci_cfgspace.h> 57 #ifdef __xpv 58 #include <sys/hypervisor.h> 59 #else 60 #include <sys/xpv_support.h> 61 #endif 62 63 /* 64 * some globals for patching the result of cpuid 65 * to solve problems w/ creative cpu vendors 66 */ 67 68 extern uint32_t cpuid_feature_ecx_include; 69 extern uint32_t cpuid_feature_ecx_exclude; 70 extern uint32_t cpuid_feature_edx_include; 71 extern uint32_t cpuid_feature_edx_exclude; 72 73 /* 74 * Dummy spl priority masks 75 */ 76 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 77 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 78 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 79 }; 80 81 /* 82 * Set console mode 83 */ 84 static void 85 set_console_mode(uint8_t val) 86 { 87 struct bop_regs rp = {0}; 88 89 rp.eax.byte.ah = 0x0; 90 rp.eax.byte.al = val; 91 rp.ebx.word.bx = 0x0; 92 93 BOP_DOINT(bootops, 0x10, &rp); 94 } 95 96 97 /* 98 * Setup routine called right before main(). Interposing this function 99 * before main() allows us to call it in a machine-independent fashion. 100 */ 101 void 102 mlsetup(struct regs *rp) 103 { 104 u_longlong_t prop_value; 105 extern struct classfuncs sys_classfuncs; 106 extern disp_t cpu0_disp; 107 extern char t0stack[]; 108 extern int post_fastreboot; 109 extern int console; 110 111 ASSERT_STACK_ALIGNED(); 112 113 /* 114 * initialize cpu_self 115 */ 116 cpu[0]->cpu_self = cpu[0]; 117 118 #if defined(__xpv) 119 /* 120 * Point at the hypervisor's virtual cpu structure 121 */ 122 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 123 #endif 124 125 /* 126 * Set up dummy cpu_pri_data values till psm spl code is 127 * installed. This allows splx() to work on amd64. 128 */ 129 130 cpu[0]->cpu_pri_data = dummy_cpu_pri; 131 132 /* 133 * check if we've got special bits to clear or set 134 * when checking cpu features 135 */ 136 137 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 138 cpuid_feature_ecx_include = 0; 139 else 140 cpuid_feature_ecx_include = (uint32_t)prop_value; 141 142 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 143 cpuid_feature_ecx_exclude = 0; 144 else 145 cpuid_feature_ecx_exclude = (uint32_t)prop_value; 146 147 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 148 cpuid_feature_edx_include = 0; 149 else 150 cpuid_feature_edx_include = (uint32_t)prop_value; 151 152 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 153 cpuid_feature_edx_exclude = 0; 154 else 155 cpuid_feature_edx_exclude = (uint32_t)prop_value; 156 157 /* 158 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 159 */ 160 init_desctbls(); 161 162 /* 163 * lgrp_init() and possibly cpuid_pass1() need PCI config 164 * space access 165 */ 166 #if defined(__xpv) 167 if (DOMAIN_IS_INITDOMAIN(xen_info)) 168 pci_cfgspace_init(); 169 #else 170 pci_cfgspace_init(); 171 #endif 172 173 /* 174 * The first lightweight pass (pass0) through the cpuid data 175 * was done in locore before mlsetup was called. Do the next 176 * pass in C code. 177 * 178 * The x86_feature bits are set here on the basis of the capabilities 179 * of the boot CPU. Note that if we choose to support CPUs that have 180 * different feature sets (at which point we would almost certainly 181 * want to set the feature bits to correspond to the feature 182 * minimum) this value may be altered. 183 */ 184 x86_feature = cpuid_pass1(cpu[0]); 185 186 #if !defined(__xpv) 187 188 if (get_hwenv() == HW_XEN_HVM) 189 xen_hvm_init(); 190 191 /* 192 * Patch the tsc_read routine with appropriate set of instructions, 193 * depending on the processor family and architecure, to read the 194 * time-stamp counter while ensuring no out-of-order execution. 195 * Patch it while the kernel text is still writable. 196 * 197 * Note: tsc_read is not patched for intel processors whose family 198 * is >6 and for amd whose family >f (in case they don't support rdtscp 199 * instruction, unlikely). By default tsc_read will use cpuid for 200 * serialization in such cases. The following code needs to be 201 * revisited if intel processors of family >= f retains the 202 * instruction serialization nature of mfence instruction. 203 * Note: tsc_read is not patched for x86 processors which do 204 * not support "mfence". By default tsc_read will use cpuid for 205 * serialization in such cases. 206 * 207 * The Xen hypervisor does not correctly report whether rdtscp is 208 * supported or not, so we must assume that it is not. 209 */ 210 if (get_hwenv() != HW_XEN_HVM && (x86_feature & X86_TSCP)) 211 patch_tsc_read(X86_HAVE_TSCP); 212 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 213 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 214 patch_tsc_read(X86_TSC_MFENCE); 215 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 216 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 217 patch_tsc_read(X86_TSC_LFENCE); 218 219 #endif /* !__xpv */ 220 221 #if defined(__i386) && !defined(__xpv) 222 /* 223 * Some i386 processors do not implement the rdtsc instruction, 224 * or at least they do not implement it correctly. Patch them to 225 * return 0. 226 */ 227 if ((x86_feature & X86_TSC) == 0) 228 patch_tsc_read(X86_NO_TSC); 229 #endif /* __i386 && !__xpv */ 230 231 #if defined(__amd64) && !defined(__xpv) 232 patch_memops(cpuid_getvendor(CPU)); 233 #endif /* __amd64 && !__xpv */ 234 235 #if !defined(__xpv) 236 /* XXPV what, if anything, should be dorked with here under xen? */ 237 238 /* 239 * While we're thinking about the TSC, let's set up %cr4 so that 240 * userland can issue rdtsc, and initialize the TSC_AUX value 241 * (the cpuid) for the rdtscp instruction on appropriately 242 * capable hardware. 243 */ 244 if (x86_feature & X86_TSC) 245 setcr4(getcr4() & ~CR4_TSD); 246 247 if (x86_feature & X86_TSCP) 248 (void) wrmsr(MSR_AMD_TSCAUX, 0); 249 250 if (x86_feature & X86_DE) 251 setcr4(getcr4() | CR4_DE); 252 #endif /* __xpv */ 253 254 /* 255 * initialize t0 256 */ 257 t0.t_stk = (caddr_t)rp - MINFRAME; 258 t0.t_stkbase = t0stack; 259 t0.t_pri = maxclsyspri - 3; 260 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 261 t0.t_procp = &p0; 262 t0.t_plockp = &p0lock.pl_lock; 263 t0.t_lwp = &lwp0; 264 t0.t_forw = &t0; 265 t0.t_back = &t0; 266 t0.t_next = &t0; 267 t0.t_prev = &t0; 268 t0.t_cpu = cpu[0]; 269 t0.t_disp_queue = &cpu0_disp; 270 t0.t_bind_cpu = PBIND_NONE; 271 t0.t_bind_pset = PS_NONE; 272 t0.t_bindflag = (uchar_t)default_binding_mode; 273 t0.t_cpupart = &cp_default; 274 t0.t_clfuncs = &sys_classfuncs.thread; 275 t0.t_copyops = NULL; 276 THREAD_ONPROC(&t0, CPU); 277 278 lwp0.lwp_thread = &t0; 279 lwp0.lwp_regs = (void *)rp; 280 lwp0.lwp_procp = &p0; 281 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 282 283 p0.p_exec = NULL; 284 p0.p_stat = SRUN; 285 p0.p_flag = SSYS; 286 p0.p_tlist = &t0; 287 p0.p_stksize = 2*PAGESIZE; 288 p0.p_stkpageszc = 0; 289 p0.p_as = &kas; 290 p0.p_lockp = &p0lock; 291 p0.p_brkpageszc = 0; 292 p0.p_t1_lgrpid = LGRP_NONE; 293 p0.p_tr_lgrpid = LGRP_NONE; 294 sigorset(&p0.p_ignore, &ignoredefault); 295 296 CPU->cpu_thread = &t0; 297 bzero(&cpu0_disp, sizeof (disp_t)); 298 CPU->cpu_disp = &cpu0_disp; 299 CPU->cpu_disp->disp_cpu = CPU; 300 CPU->cpu_dispthread = &t0; 301 CPU->cpu_idle_thread = &t0; 302 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 303 CPU->cpu_dispatch_pri = t0.t_pri; 304 305 CPU->cpu_id = 0; 306 307 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 308 309 /* 310 * The kernel doesn't use LDTs unless a process explicitly requests one. 311 */ 312 p0.p_ldt_desc = null_sdesc; 313 314 /* 315 * Initialize thread/cpu microstate accounting 316 */ 317 init_mstate(&t0, LMS_SYSTEM); 318 init_cpu_mstate(CPU, CMS_SYSTEM); 319 320 /* 321 * Initialize lists of available and active CPUs. 322 */ 323 cpu_list_init(CPU); 324 325 pg_cpu_bootstrap(CPU); 326 327 /* 328 * Now that we have taken over the GDT, IDT and have initialized 329 * active CPU list it's time to inform kmdb if present. 330 */ 331 if (boothowto & RB_DEBUG) 332 kdi_idt_sync(); 333 334 /* 335 * Explicitly set console to text mode (0x3) if this is a boot 336 * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT. 337 */ 338 if (post_fastreboot && console == CONS_SCREEN_TEXT) 339 set_console_mode(0x3); 340 341 /* 342 * If requested (boot -d) drop into kmdb. 343 * 344 * This must be done after cpu_list_init() on the 64-bit kernel 345 * since taking a trap requires that we re-compute gsbase based 346 * on the cpu list. 347 */ 348 if (boothowto & RB_DEBUGENTER) 349 kmdb_enter(); 350 351 cpu_vm_data_init(CPU); 352 353 rp->r_fp = 0; /* terminate kernel stack traces! */ 354 355 prom_init("kernel", (void *)NULL); 356 357 if (bootprop_getval("boot-ncpus", &prop_value) != 0) 358 boot_ncpus = NCPU; 359 else { 360 boot_ncpus = (int)prop_value; 361 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 362 boot_ncpus = NCPU; 363 } 364 365 max_ncpus = boot_max_ncpus = boot_ncpus; 366 367 /* 368 * Initialize the lgrp framework 369 */ 370 lgrp_init(); 371 372 if (boothowto & RB_HALT) { 373 prom_printf("unix: kernel halted by -h flag\n"); 374 prom_enter_mon(); 375 } 376 377 ASSERT_STACK_ALIGNED(); 378 379 /* 380 * Fill out cpu_ucode_info. Update microcode if necessary. 381 */ 382 ucode_check(CPU); 383 384 if (workaround_errata(CPU) != 0) 385 panic("critical workaround(s) missing for boot cpu"); 386 } 387 388 389 void 390 mach_modpath(char *path, const char *filename) 391 { 392 /* 393 * Construct the directory path from the filename. 394 */ 395 396 int len; 397 char *p; 398 const char isastr[] = "/amd64"; 399 size_t isalen = strlen(isastr); 400 401 if ((p = strrchr(filename, '/')) == NULL) 402 return; 403 404 while (p > filename && *(p - 1) == '/') 405 p--; /* remove trailing '/' characters */ 406 if (p == filename) 407 p++; /* so "/" -is- the modpath in this case */ 408 409 /* 410 * Remove optional isa-dependent directory name - the module 411 * subsystem will put this back again (!) 412 */ 413 len = p - filename; 414 if (len > isalen && 415 strncmp(&filename[len - isalen], isastr, isalen) == 0) 416 p -= isalen; 417 418 /* 419 * "/platform/mumblefrotz" + " " + MOD_DEFPATH 420 */ 421 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 422 (void) strncpy(path, filename, p - filename); 423 } 424