17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 541791439Sandrei * Common Development and Distribution License (the "License"). 641791439Sandrei * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 220d928757SGary Mills * Copyright (c) 2012 Gary Mills 230d928757SGary Mills * 247417cfdeSKuriakose Kuruvilla * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 25cfe84b82SMatt Amdur * Copyright (c) 2011 by Delphix. All rights reserved. 26*2428aad8SPatrick Mooney * Copyright 2016 Joyent, Inc. 277c478bd9Sstevel@tonic-gate */ 28a3114836SGerry Liu /* 29a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation. 30a3114836SGerry Liu * All rights reserved. 31a3114836SGerry Liu */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/types.h> 34ae115bc7Smrj #include <sys/sysmacros.h> 357c478bd9Sstevel@tonic-gate #include <sys/disp.h> 367c478bd9Sstevel@tonic-gate #include <sys/promif.h> 377c478bd9Sstevel@tonic-gate #include <sys/clock.h> 387c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 397c478bd9Sstevel@tonic-gate #include <sys/stack.h> 407c478bd9Sstevel@tonic-gate #include <vm/as.h> 417c478bd9Sstevel@tonic-gate #include <vm/hat.h> 427c478bd9Sstevel@tonic-gate #include <sys/reboot.h> 437c478bd9Sstevel@tonic-gate #include <sys/avintr.h> 447c478bd9Sstevel@tonic-gate #include <sys/vtrace.h> 457c478bd9Sstevel@tonic-gate #include <sys/proc.h> 467c478bd9Sstevel@tonic-gate #include <sys/thread.h> 477c478bd9Sstevel@tonic-gate #include <sys/cpupart.h> 487c478bd9Sstevel@tonic-gate #include <sys/pset.h> 497c478bd9Sstevel@tonic-gate #include <sys/copyops.h> 50fb2f18f8Sesaxe #include <sys/pg.h> 517c478bd9Sstevel@tonic-gate #include <sys/disp.h> 527c478bd9Sstevel@tonic-gate #include <sys/debug.h> 537c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 547c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 557c478bd9Sstevel@tonic-gate #include <sys/privregs.h> 567c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> 577c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 587c478bd9Sstevel@tonic-gate #include <sys/bootconf.h> 599db7147eSSherry Moore #include <sys/boot_console.h> 60ae115bc7Smrj #include <sys/kdi_machimpl.h> 617c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 627c478bd9Sstevel@tonic-gate #include <sys/promif.h> 63c88420b3Sdmick #include <sys/pci_cfgspace.h> 640181461bSKeith M Wesolowski #include <sys/bootvfs.h> 65*2428aad8SPatrick Mooney #include <sys/tsc.h> 66843e1988Sjohnlev #ifdef __xpv 67843e1988Sjohnlev #include <sys/hypervisor.h> 68349b53ddSStuart Maybee #else 69349b53ddSStuart Maybee #include <sys/xpv_support.h> 70843e1988Sjohnlev #endif 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate /* 737c478bd9Sstevel@tonic-gate * some globals for patching the result of cpuid 747c478bd9Sstevel@tonic-gate * to solve problems w/ creative cpu vendors 757c478bd9Sstevel@tonic-gate */ 767c478bd9Sstevel@tonic-gate 777c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_ecx_include; 787c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_ecx_exclude; 797c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_edx_include; 807c478bd9Sstevel@tonic-gate extern uint32_t cpuid_feature_edx_exclude; 817c478bd9Sstevel@tonic-gate 829db7147eSSherry Moore /* 839db7147eSSherry Moore * Set console mode 849db7147eSSherry Moore */ 859db7147eSSherry Moore static void 869db7147eSSherry Moore set_console_mode(uint8_t val) 879db7147eSSherry Moore { 889db7147eSSherry Moore struct bop_regs rp = {0}; 899db7147eSSherry Moore 909db7147eSSherry Moore rp.eax.byte.ah = 0x0; 919db7147eSSherry Moore rp.eax.byte.al = val; 929db7147eSSherry Moore rp.ebx.word.bx = 0x0; 939db7147eSSherry Moore 949db7147eSSherry Moore BOP_DOINT(bootops, 0x10, &rp); 959db7147eSSherry Moore } 969db7147eSSherry Moore 977c478bd9Sstevel@tonic-gate 987c478bd9Sstevel@tonic-gate /* 997c478bd9Sstevel@tonic-gate * Setup routine called right before main(). Interposing this function 1007c478bd9Sstevel@tonic-gate * before main() allows us to call it in a machine-independent fashion. 1017c478bd9Sstevel@tonic-gate */ 1027c478bd9Sstevel@tonic-gate void 1037c478bd9Sstevel@tonic-gate mlsetup(struct regs *rp) 1047c478bd9Sstevel@tonic-gate { 1052baa66a0SJonathan Chew u_longlong_t prop_value; 1067c478bd9Sstevel@tonic-gate extern struct classfuncs sys_classfuncs; 1077c478bd9Sstevel@tonic-gate extern disp_t cpu0_disp; 1087c478bd9Sstevel@tonic-gate extern char t0stack[]; 1099db7147eSSherry Moore extern int post_fastreboot; 110a3114836SGerry Liu extern uint64_t plat_dr_options; 1117c478bd9Sstevel@tonic-gate 1127c478bd9Sstevel@tonic-gate ASSERT_STACK_ALIGNED(); 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate /* 1157c478bd9Sstevel@tonic-gate * initialize cpu_self 1167c478bd9Sstevel@tonic-gate */ 1177c478bd9Sstevel@tonic-gate cpu[0]->cpu_self = cpu[0]; 1187c478bd9Sstevel@tonic-gate 119843e1988Sjohnlev #if defined(__xpv) 120843e1988Sjohnlev /* 121843e1988Sjohnlev * Point at the hypervisor's virtual cpu structure 122843e1988Sjohnlev */ 123843e1988Sjohnlev cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 124843e1988Sjohnlev #endif 125843e1988Sjohnlev 1267c478bd9Sstevel@tonic-gate /* 1277c478bd9Sstevel@tonic-gate * check if we've got special bits to clear or set 1287c478bd9Sstevel@tonic-gate * when checking cpu features 1297c478bd9Sstevel@tonic-gate */ 1307c478bd9Sstevel@tonic-gate 1312baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0) 1322baa66a0SJonathan Chew cpuid_feature_ecx_include = 0; 1332baa66a0SJonathan Chew else 1342baa66a0SJonathan Chew cpuid_feature_ecx_include = (uint32_t)prop_value; 1352baa66a0SJonathan Chew 1362baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0) 1372baa66a0SJonathan Chew cpuid_feature_ecx_exclude = 0; 1382baa66a0SJonathan Chew else 1392baa66a0SJonathan Chew cpuid_feature_ecx_exclude = (uint32_t)prop_value; 1402baa66a0SJonathan Chew 1412baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0) 1422baa66a0SJonathan Chew cpuid_feature_edx_include = 0; 1432baa66a0SJonathan Chew else 1442baa66a0SJonathan Chew cpuid_feature_edx_include = (uint32_t)prop_value; 1452baa66a0SJonathan Chew 1462baa66a0SJonathan Chew if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0) 1472baa66a0SJonathan Chew cpuid_feature_edx_exclude = 0; 1482baa66a0SJonathan Chew else 1492baa66a0SJonathan Chew cpuid_feature_edx_exclude = (uint32_t)prop_value; 1507c478bd9Sstevel@tonic-gate 15145e032f7SDan Mick /* 15245e032f7SDan Mick * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 15345e032f7SDan Mick */ 15445e032f7SDan Mick init_desctbls(); 15545e032f7SDan Mick 15645e032f7SDan Mick /* 15745e032f7SDan Mick * lgrp_init() and possibly cpuid_pass1() need PCI config 15845e032f7SDan Mick * space access 15945e032f7SDan Mick */ 16045e032f7SDan Mick #if defined(__xpv) 16145e032f7SDan Mick if (DOMAIN_IS_INITDOMAIN(xen_info)) 16245e032f7SDan Mick pci_cfgspace_init(); 16345e032f7SDan Mick #else 16445e032f7SDan Mick pci_cfgspace_init(); 165cfe84b82SMatt Amdur /* 166cfe84b82SMatt Amdur * Initialize the platform type from CPU 0 to ensure that 167cfe84b82SMatt Amdur * determine_platform() is only ever called once. 168cfe84b82SMatt Amdur */ 169cfe84b82SMatt Amdur determine_platform(); 17045e032f7SDan Mick #endif 17145e032f7SDan Mick 1727c478bd9Sstevel@tonic-gate /* 1737c478bd9Sstevel@tonic-gate * The first lightweight pass (pass0) through the cpuid data 1747c478bd9Sstevel@tonic-gate * was done in locore before mlsetup was called. Do the next 1757c478bd9Sstevel@tonic-gate * pass in C code. 1767c478bd9Sstevel@tonic-gate * 1777417cfdeSKuriakose Kuruvilla * The x86_featureset is initialized here based on the capabilities 1787c478bd9Sstevel@tonic-gate * of the boot CPU. Note that if we choose to support CPUs that have 1797c478bd9Sstevel@tonic-gate * different feature sets (at which point we would almost certainly 1807c478bd9Sstevel@tonic-gate * want to set the feature bits to correspond to the feature 1817c478bd9Sstevel@tonic-gate * minimum) this value may be altered. 1827c478bd9Sstevel@tonic-gate */ 183dfea898aSKuriakose Kuruvilla cpuid_pass1(cpu[0], x86_featureset); 1847c478bd9Sstevel@tonic-gate 185247dbb3dSsudheer #if !defined(__xpv) 18679ec9da8SYuri Pankov if ((get_hwenv() & HW_XEN_HVM) != 0) 187349b53ddSStuart Maybee xen_hvm_init(); 188349b53ddSStuart Maybee 1894948216cSKeith M Wesolowski /* 1904948216cSKeith M Wesolowski * Before we do anything with the TSCs, we need to work around 1914948216cSKeith M Wesolowski * Intel erratum BT81. On some CPUs, warm reset does not 1924948216cSKeith M Wesolowski * clear the TSC. If we are on such a CPU, we will clear TSC ourselves 1934948216cSKeith M Wesolowski * here. Other CPUs will clear it when we boot them later, and the 1944948216cSKeith M Wesolowski * resulting skew will be handled by tsc_sync_master()/_slave(); 1954948216cSKeith M Wesolowski * note that such skew already exists and has to be handled anyway. 1964948216cSKeith M Wesolowski * 1974948216cSKeith M Wesolowski * We do this only on metal. This same problem can occur with a 1984948216cSKeith M Wesolowski * hypervisor that does not happen to virtualise a TSC that starts from 1994948216cSKeith M Wesolowski * zero, regardless of CPU type; however, we do not expect hypervisors 2004948216cSKeith M Wesolowski * that do not virtualise TSC that way to handle writes to TSC 2014948216cSKeith M Wesolowski * correctly, either. 2024948216cSKeith M Wesolowski */ 2034948216cSKeith M Wesolowski if (get_hwenv() == HW_NATIVE && 2044948216cSKeith M Wesolowski cpuid_getvendor(CPU) == X86_VENDOR_Intel && 2054948216cSKeith M Wesolowski cpuid_getfamily(CPU) == 6 && 2064948216cSKeith M Wesolowski (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) && 2074948216cSKeith M Wesolowski is_x86_feature(x86_featureset, X86FSET_TSC)) { 2084948216cSKeith M Wesolowski (void) wrmsr(REG_TSC, 0UL); 2094948216cSKeith M Wesolowski } 2104948216cSKeith M Wesolowski 211247dbb3dSsudheer /* 212247dbb3dSsudheer * Patch the tsc_read routine with appropriate set of instructions, 213247dbb3dSsudheer * depending on the processor family and architecure, to read the 214247dbb3dSsudheer * time-stamp counter while ensuring no out-of-order execution. 215247dbb3dSsudheer * Patch it while the kernel text is still writable. 216247dbb3dSsudheer * 217247dbb3dSsudheer * Note: tsc_read is not patched for intel processors whose family 218247dbb3dSsudheer * is >6 and for amd whose family >f (in case they don't support rdtscp 219247dbb3dSsudheer * instruction, unlikely). By default tsc_read will use cpuid for 220247dbb3dSsudheer * serialization in such cases. The following code needs to be 221247dbb3dSsudheer * revisited if intel processors of family >= f retains the 222247dbb3dSsudheer * instruction serialization nature of mfence instruction. 2232b0bcb26Ssudheer * Note: tsc_read is not patched for x86 processors which do 2242b0bcb26Ssudheer * not support "mfence". By default tsc_read will use cpuid for 2252b0bcb26Ssudheer * serialization in such cases. 226551bc2a6Smrj * 227551bc2a6Smrj * The Xen hypervisor does not correctly report whether rdtscp is 228551bc2a6Smrj * supported or not, so we must assume that it is not. 229247dbb3dSsudheer */ 23079ec9da8SYuri Pankov if ((get_hwenv() & HW_XEN_HVM) == 0 && 2317417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_TSCP)) 232*2428aad8SPatrick Mooney patch_tsc_read(TSC_TSCP); 233247dbb3dSsudheer else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 2347417cfdeSKuriakose Kuruvilla cpuid_getfamily(CPU) <= 0xf && 2357417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SSE2)) 236*2428aad8SPatrick Mooney patch_tsc_read(TSC_RDTSC_MFENCE); 237247dbb3dSsudheer else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 2387417cfdeSKuriakose Kuruvilla cpuid_getfamily(CPU) <= 6 && 2397417cfdeSKuriakose Kuruvilla is_x86_feature(x86_featureset, X86FSET_SSE2)) 240*2428aad8SPatrick Mooney patch_tsc_read(TSC_RDTSC_LFENCE); 241247dbb3dSsudheer 242247dbb3dSsudheer #endif /* !__xpv */ 2437c478bd9Sstevel@tonic-gate 244843e1988Sjohnlev #if defined(__i386) && !defined(__xpv) 2457c478bd9Sstevel@tonic-gate /* 2467c478bd9Sstevel@tonic-gate * Some i386 processors do not implement the rdtsc instruction, 247247dbb3dSsudheer * or at least they do not implement it correctly. Patch them to 248247dbb3dSsudheer * return 0. 2497c478bd9Sstevel@tonic-gate */ 2507417cfdeSKuriakose Kuruvilla if (!is_x86_feature(x86_featureset, X86FSET_TSC)) 251*2428aad8SPatrick Mooney patch_tsc_read(TSC_NONE); 252843e1988Sjohnlev #endif /* __i386 && !__xpv */ 253843e1988Sjohnlev 25422cc0e45SBill Holler #if defined(__amd64) && !defined(__xpv) 25522cc0e45SBill Holler patch_memops(cpuid_getvendor(CPU)); 25622cc0e45SBill Holler #endif /* __amd64 && !__xpv */ 25722cc0e45SBill Holler 258843e1988Sjohnlev #if !defined(__xpv) 259843e1988Sjohnlev /* XXPV what, if anything, should be dorked with here under xen? */ 260ae115bc7Smrj 261ae115bc7Smrj /* 262ae115bc7Smrj * While we're thinking about the TSC, let's set up %cr4 so that 263ae115bc7Smrj * userland can issue rdtsc, and initialize the TSC_AUX value 264ae115bc7Smrj * (the cpuid) for the rdtscp instruction on appropriately 265ae115bc7Smrj * capable hardware. 266ae115bc7Smrj */ 2677417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSC)) 268ae115bc7Smrj setcr4(getcr4() & ~CR4_TSD); 269ae115bc7Smrj 2707417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_TSCP)) 271ae115bc7Smrj (void) wrmsr(MSR_AMD_TSCAUX, 0); 272ae115bc7Smrj 273799823bbSRobert Mustacchi /* 2743ce2fcdcSRobert Mustacchi * Let's get the other %cr4 stuff while we're here. Note, we defer 2753ce2fcdcSRobert Mustacchi * enabling CR4_SMAP until startup_end(); however, that's importantly 2763ce2fcdcSRobert Mustacchi * before we start other CPUs. That ensures that it will be synced out 2773ce2fcdcSRobert Mustacchi * to other CPUs. 278799823bbSRobert Mustacchi */ 2797417cfdeSKuriakose Kuruvilla if (is_x86_feature(x86_featureset, X86FSET_DE)) 280ae115bc7Smrj setcr4(getcr4() | CR4_DE); 281799823bbSRobert Mustacchi 282799823bbSRobert Mustacchi if (is_x86_feature(x86_featureset, X86FSET_SMEP)) 283799823bbSRobert Mustacchi setcr4(getcr4() | CR4_SMEP); 284843e1988Sjohnlev #endif /* __xpv */ 2857c478bd9Sstevel@tonic-gate 2867c478bd9Sstevel@tonic-gate /* 2877c478bd9Sstevel@tonic-gate * initialize t0 2887c478bd9Sstevel@tonic-gate */ 2897c478bd9Sstevel@tonic-gate t0.t_stk = (caddr_t)rp - MINFRAME; 2907c478bd9Sstevel@tonic-gate t0.t_stkbase = t0stack; 2917c478bd9Sstevel@tonic-gate t0.t_pri = maxclsyspri - 3; 2927c478bd9Sstevel@tonic-gate t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 2937c478bd9Sstevel@tonic-gate t0.t_procp = &p0; 2947c478bd9Sstevel@tonic-gate t0.t_plockp = &p0lock.pl_lock; 2957c478bd9Sstevel@tonic-gate t0.t_lwp = &lwp0; 2967c478bd9Sstevel@tonic-gate t0.t_forw = &t0; 2977c478bd9Sstevel@tonic-gate t0.t_back = &t0; 2987c478bd9Sstevel@tonic-gate t0.t_next = &t0; 2997c478bd9Sstevel@tonic-gate t0.t_prev = &t0; 3007c478bd9Sstevel@tonic-gate t0.t_cpu = cpu[0]; 3017c478bd9Sstevel@tonic-gate t0.t_disp_queue = &cpu0_disp; 3027c478bd9Sstevel@tonic-gate t0.t_bind_cpu = PBIND_NONE; 3037c478bd9Sstevel@tonic-gate t0.t_bind_pset = PS_NONE; 3040b70c467Sakolb t0.t_bindflag = (uchar_t)default_binding_mode; 3057c478bd9Sstevel@tonic-gate t0.t_cpupart = &cp_default; 3067c478bd9Sstevel@tonic-gate t0.t_clfuncs = &sys_classfuncs.thread; 3077c478bd9Sstevel@tonic-gate t0.t_copyops = NULL; 3087c478bd9Sstevel@tonic-gate THREAD_ONPROC(&t0, CPU); 3097c478bd9Sstevel@tonic-gate 3107c478bd9Sstevel@tonic-gate lwp0.lwp_thread = &t0; 311ae115bc7Smrj lwp0.lwp_regs = (void *)rp; 3127c478bd9Sstevel@tonic-gate lwp0.lwp_procp = &p0; 3137c478bd9Sstevel@tonic-gate t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 3147c478bd9Sstevel@tonic-gate 3157c478bd9Sstevel@tonic-gate p0.p_exec = NULL; 3167c478bd9Sstevel@tonic-gate p0.p_stat = SRUN; 3177c478bd9Sstevel@tonic-gate p0.p_flag = SSYS; 3187c478bd9Sstevel@tonic-gate p0.p_tlist = &t0; 3197c478bd9Sstevel@tonic-gate p0.p_stksize = 2*PAGESIZE; 3207c478bd9Sstevel@tonic-gate p0.p_stkpageszc = 0; 3217c478bd9Sstevel@tonic-gate p0.p_as = &kas; 3227c478bd9Sstevel@tonic-gate p0.p_lockp = &p0lock; 3237c478bd9Sstevel@tonic-gate p0.p_brkpageszc = 0; 3242cb27123Saguzovsk p0.p_t1_lgrpid = LGRP_NONE; 3252cb27123Saguzovsk p0.p_tr_lgrpid = LGRP_NONE; 326d2a70789SRichard Lowe psecflags_default(&p0.p_secflags); 327d2a70789SRichard Lowe 3287c478bd9Sstevel@tonic-gate sigorset(&p0.p_ignore, &ignoredefault); 3297c478bd9Sstevel@tonic-gate 3307c478bd9Sstevel@tonic-gate CPU->cpu_thread = &t0; 3317c478bd9Sstevel@tonic-gate bzero(&cpu0_disp, sizeof (disp_t)); 3327c478bd9Sstevel@tonic-gate CPU->cpu_disp = &cpu0_disp; 3337c478bd9Sstevel@tonic-gate CPU->cpu_disp->disp_cpu = CPU; 3347c478bd9Sstevel@tonic-gate CPU->cpu_dispthread = &t0; 3357c478bd9Sstevel@tonic-gate CPU->cpu_idle_thread = &t0; 3367c478bd9Sstevel@tonic-gate CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 3377c478bd9Sstevel@tonic-gate CPU->cpu_dispatch_pri = t0.t_pri; 3387c478bd9Sstevel@tonic-gate 3397c478bd9Sstevel@tonic-gate CPU->cpu_id = 0; 3407c478bd9Sstevel@tonic-gate 3417c478bd9Sstevel@tonic-gate CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 3427c478bd9Sstevel@tonic-gate 3437c478bd9Sstevel@tonic-gate /* 3440baeff3dSrab * The kernel doesn't use LDTs unless a process explicitly requests one. 3457c478bd9Sstevel@tonic-gate */ 346843e1988Sjohnlev p0.p_ldt_desc = null_sdesc; 3477c478bd9Sstevel@tonic-gate 3487c478bd9Sstevel@tonic-gate /* 349ae115bc7Smrj * Initialize thread/cpu microstate accounting 3507c478bd9Sstevel@tonic-gate */ 3517c478bd9Sstevel@tonic-gate init_mstate(&t0, LMS_SYSTEM); 3527c478bd9Sstevel@tonic-gate init_cpu_mstate(CPU, CMS_SYSTEM); 3537c478bd9Sstevel@tonic-gate 3547c478bd9Sstevel@tonic-gate /* 3557c478bd9Sstevel@tonic-gate * Initialize lists of available and active CPUs. 3567c478bd9Sstevel@tonic-gate */ 3577c478bd9Sstevel@tonic-gate cpu_list_init(CPU); 3580e751525SEric Saxe 3590e751525SEric Saxe pg_cpu_bootstrap(CPU); 3607c478bd9Sstevel@tonic-gate 361ae115bc7Smrj /* 362ae115bc7Smrj * Now that we have taken over the GDT, IDT and have initialized 363ae115bc7Smrj * active CPU list it's time to inform kmdb if present. 364ae115bc7Smrj */ 365ae115bc7Smrj if (boothowto & RB_DEBUG) 366ae115bc7Smrj kdi_idt_sync(); 367ae115bc7Smrj 3689db7147eSSherry Moore /* 3699db7147eSSherry Moore * Explicitly set console to text mode (0x3) if this is a boot 3709db7147eSSherry Moore * post Fast Reboot, and the console is set to CONS_SCREEN_TEXT. 3719db7147eSSherry Moore */ 3720d928757SGary Mills if (post_fastreboot && boot_console_type(NULL) == CONS_SCREEN_TEXT) 3739db7147eSSherry Moore set_console_mode(0x3); 3749db7147eSSherry Moore 375ae115bc7Smrj /* 376ae115bc7Smrj * If requested (boot -d) drop into kmdb. 377ae115bc7Smrj * 378ae115bc7Smrj * This must be done after cpu_list_init() on the 64-bit kernel 379ae115bc7Smrj * since taking a trap requires that we re-compute gsbase based 380ae115bc7Smrj * on the cpu list. 381ae115bc7Smrj */ 382ae115bc7Smrj if (boothowto & RB_DEBUGENTER) 383ae115bc7Smrj kmdb_enter(); 384ae115bc7Smrj 385affbd3ccSkchow cpu_vm_data_init(CPU); 386affbd3ccSkchow 3877c478bd9Sstevel@tonic-gate rp->r_fp = 0; /* terminate kernel stack traces! */ 3887c478bd9Sstevel@tonic-gate 3897c478bd9Sstevel@tonic-gate prom_init("kernel", (void *)NULL); 3907c478bd9Sstevel@tonic-gate 391a3114836SGerry Liu /* User-set option overrides firmware value. */ 392a3114836SGerry Liu if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) { 393a3114836SGerry Liu plat_dr_options = (uint64_t)prop_value; 394a3114836SGerry Liu } 395a3114836SGerry Liu #if defined(__xpv) 396a3114836SGerry Liu /* No support of DR operations on xpv */ 397a3114836SGerry Liu plat_dr_options = 0; 398a3114836SGerry Liu #else /* __xpv */ 399a3114836SGerry Liu /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */ 400a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED; 401a3114836SGerry Liu #ifndef __amd64 402a3114836SGerry Liu /* Only enable CPU/memory DR on 64 bits kernel. */ 403a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY; 404a3114836SGerry Liu plat_dr_options &= ~PLAT_DR_FEATURE_CPU; 405a3114836SGerry Liu #endif /* __amd64 */ 406a3114836SGerry Liu #endif /* __xpv */ 407a3114836SGerry Liu 408a3114836SGerry Liu /* 409a3114836SGerry Liu * Get value of "plat_dr_physmax" boot option. 410a3114836SGerry Liu * It overrides values calculated from MSCT or SRAT table. 411a3114836SGerry Liu */ 412a3114836SGerry Liu if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) { 413a3114836SGerry Liu plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT; 414a3114836SGerry Liu } 415a3114836SGerry Liu 416a3114836SGerry Liu /* Get value of boot_ncpus. */ 417a3114836SGerry Liu if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) { 418ae115bc7Smrj boot_ncpus = NCPU; 419a3114836SGerry Liu } else { 4202baa66a0SJonathan Chew boot_ncpus = (int)prop_value; 4212baa66a0SJonathan Chew if (boot_ncpus <= 0 || boot_ncpus > NCPU) 4222baa66a0SJonathan Chew boot_ncpus = NCPU; 4232baa66a0SJonathan Chew } 42441791439Sandrei 425a3114836SGerry Liu /* 426a3114836SGerry Liu * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't 427a3114836SGerry Liu * support CPU DR operations. 428a3114836SGerry Liu */ 429a3114836SGerry Liu if (plat_dr_support_cpu() == 0) { 430a3114836SGerry Liu max_ncpus = boot_max_ncpus = boot_ncpus; 431a3114836SGerry Liu } else { 432a3114836SGerry Liu if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) { 433a3114836SGerry Liu max_ncpus = NCPU; 434a3114836SGerry Liu } else { 435a3114836SGerry Liu max_ncpus = (int)prop_value; 436a3114836SGerry Liu if (max_ncpus <= 0 || max_ncpus > NCPU) { 437a3114836SGerry Liu max_ncpus = NCPU; 438a3114836SGerry Liu } 439a3114836SGerry Liu if (boot_ncpus > max_ncpus) { 440a3114836SGerry Liu boot_ncpus = max_ncpus; 441a3114836SGerry Liu } 442a3114836SGerry Liu } 443a3114836SGerry Liu 444a3114836SGerry Liu if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) { 445a3114836SGerry Liu boot_max_ncpus = boot_ncpus; 446a3114836SGerry Liu } else { 447a3114836SGerry Liu boot_max_ncpus = (int)prop_value; 448a3114836SGerry Liu if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) { 449a3114836SGerry Liu boot_max_ncpus = boot_ncpus; 450a3114836SGerry Liu } else if (boot_max_ncpus > max_ncpus) { 451a3114836SGerry Liu boot_max_ncpus = max_ncpus; 452a3114836SGerry Liu } 453a3114836SGerry Liu } 454a3114836SGerry Liu } 45541791439Sandrei 4562e2c009bSjjc /* 4572e2c009bSjjc * Initialize the lgrp framework 4582e2c009bSjjc */ 459d5d7cf4eSJonathan Chew lgrp_init(LGRP_INIT_STAGE1); 4602e2c009bSjjc 4617c478bd9Sstevel@tonic-gate if (boothowto & RB_HALT) { 4627c478bd9Sstevel@tonic-gate prom_printf("unix: kernel halted by -h flag\n"); 4637c478bd9Sstevel@tonic-gate prom_enter_mon(); 4647c478bd9Sstevel@tonic-gate } 4657c478bd9Sstevel@tonic-gate 4667c478bd9Sstevel@tonic-gate ASSERT_STACK_ALIGNED(); 4677c478bd9Sstevel@tonic-gate 4682449e17fSsherrym /* 4692449e17fSsherrym * Fill out cpu_ucode_info. Update microcode if necessary. 4702449e17fSsherrym */ 4712449e17fSsherrym ucode_check(CPU); 4722449e17fSsherrym 4737c478bd9Sstevel@tonic-gate if (workaround_errata(CPU) != 0) 4747c478bd9Sstevel@tonic-gate panic("critical workaround(s) missing for boot cpu"); 4757c478bd9Sstevel@tonic-gate } 476986fd29aSsetje 477986fd29aSsetje 478986fd29aSsetje void 479986fd29aSsetje mach_modpath(char *path, const char *filename) 480986fd29aSsetje { 481986fd29aSsetje /* 482986fd29aSsetje * Construct the directory path from the filename. 483986fd29aSsetje */ 484986fd29aSsetje 485986fd29aSsetje int len; 486986fd29aSsetje char *p; 487986fd29aSsetje const char isastr[] = "/amd64"; 488986fd29aSsetje size_t isalen = strlen(isastr); 489986fd29aSsetje 4900181461bSKeith M Wesolowski len = strlen(SYSTEM_BOOT_PATH "/kernel"); 4910181461bSKeith M Wesolowski (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel "); 4920181461bSKeith M Wesolowski path += len + 1; 4930181461bSKeith M Wesolowski 494986fd29aSsetje if ((p = strrchr(filename, '/')) == NULL) 495986fd29aSsetje return; 496986fd29aSsetje 497986fd29aSsetje while (p > filename && *(p - 1) == '/') 498986fd29aSsetje p--; /* remove trailing '/' characters */ 499986fd29aSsetje if (p == filename) 500986fd29aSsetje p++; /* so "/" -is- the modpath in this case */ 501986fd29aSsetje 502986fd29aSsetje /* 503986fd29aSsetje * Remove optional isa-dependent directory name - the module 504986fd29aSsetje * subsystem will put this back again (!) 505986fd29aSsetje */ 506986fd29aSsetje len = p - filename; 507986fd29aSsetje if (len > isalen && 508986fd29aSsetje strncmp(&filename[len - isalen], isastr, isalen) == 0) 509986fd29aSsetje p -= isalen; 510986fd29aSsetje 511986fd29aSsetje /* 512986fd29aSsetje * "/platform/mumblefrotz" + " " + MOD_DEFPATH 513986fd29aSsetje */ 514986fd29aSsetje len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1; 515986fd29aSsetje (void) strncpy(path, filename, p - filename); 516986fd29aSsetje } 517