xref: /illumos-gate/usr/src/uts/i86pc/os/cpuid_subr.c (revision bdc24928)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  *
26  * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
27  */
28 
29 /*
30  * Portions Copyright 2009 Advanced Micro Devices, Inc.
31  */
32 
33 /*
34  * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
35  * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
36  * Copyright 2019 Joyent, Inc.
37  * Copyright 2021 Oxide Computer Company
38  */
39 
40 /*
41  * Support functions that interpret CPUID and similar information.
42  * These should not be used from anywhere other than cpuid.c and
43  * cmi_hw.c - as such we will not list them in any header file
44  * such as x86_archext.h.
45  *
46  * In cpuid.c we process CPUID information for each cpu_t instance
47  * we're presented with, and stash this raw information and material
48  * derived from it in per-cpu_t structures.
49  *
50  * If we are virtualized then the CPUID information derived from CPUID
51  * instructions executed in the guest is based on whatever the hypervisor
52  * wanted to make things look like, and the cpu_t are not necessarily in 1:1
53  * or fixed correspondence with real processor execution resources.  In cmi_hw.c
54  * we are interested in the native properties of a processor - for fault
55  * management (and potentially other, such as power management) purposes;
56  * it will tunnel through to real hardware information, and use the
57  * functionality provided in this file to process it.
58  */
59 
60 #include <sys/types.h>
61 #include <sys/systm.h>
62 #include <sys/bitmap.h>
63 #include <sys/x86_archext.h>
64 #include <sys/pci_cfgspace.h>
65 #include <sys/sysmacros.h>
66 #ifdef __xpv
67 #include <sys/hypervisor.h>
68 #endif
69 
70 /*
71  * AMD socket types.
72  * First index :
73  *		0 for family 0xf, revs B thru E
74  *		1 for family 0xf, revs F and G
75  *		2 for family 0x10
76  *		3 for family 0x11
77  *		4 for family 0x12
78  *		5 for family 0x14
79  *		6 for family 0x15, models 00 - 0f
80  *		7 for family 0x15, models 10 - 1f
81  *		8 for family 0x15, models 30 - 3f
82  *		9 for family 0x15, models 60 - 6f
83  *		10 for family 0x15, models 70 - 7f
84  *		11 for family 0x16, models 00 - 0f
85  *		12 for family 0x16, models 30 - 3f
86  *		13 for family 0x17, models 00 - 0f
87  *		14 for family 0x17, models 10 - 2f
88  *		15 for family 0x17, models 30 - 3f
89  *		16 for family 0x17, models 60 - 6f
90  *		17 for family 0x17, models 70 - 7f
91  *		18 for family 0x18, models 00 - 0f
92  *		19 for family 0x19, models 00 - 0f
93  *		20 for family 0x19, models 20 - 2f
94  * Second index by (model & 0x3) for family 0fh,
95  * CPUID pkg bits (Fn8000_0001_EBX[31:28]) for later families.
96  */
97 static uint32_t amd_skts[21][8] = {
98 	/*
99 	 * Family 0xf revisions B through E
100 	 */
101 #define	A_SKTS_0			0
102 	{
103 		X86_SOCKET_754,		/* 0b000 */
104 		X86_SOCKET_940,		/* 0b001 */
105 		X86_SOCKET_754,		/* 0b010 */
106 		X86_SOCKET_939,		/* 0b011 */
107 		X86_SOCKET_UNKNOWN,	/* 0b100 */
108 		X86_SOCKET_UNKNOWN,	/* 0b101 */
109 		X86_SOCKET_UNKNOWN,	/* 0b110 */
110 		X86_SOCKET_UNKNOWN	/* 0b111 */
111 	},
112 	/*
113 	 * Family 0xf revisions F and G
114 	 */
115 #define	A_SKTS_1			1
116 	{
117 		X86_SOCKET_S1g1,	/* 0b000 */
118 		X86_SOCKET_F1207,	/* 0b001 */
119 		X86_SOCKET_UNKNOWN,	/* 0b010 */
120 		X86_SOCKET_AM2,		/* 0b011 */
121 		X86_SOCKET_UNKNOWN,	/* 0b100 */
122 		X86_SOCKET_UNKNOWN,	/* 0b101 */
123 		X86_SOCKET_UNKNOWN,	/* 0b110 */
124 		X86_SOCKET_UNKNOWN	/* 0b111 */
125 	},
126 	/*
127 	 * Family 0x10
128 	 */
129 #define	A_SKTS_2			2
130 	{
131 		X86_SOCKET_F1207,	/* 0b000 */
132 		X86_SOCKET_AM2R2,	/* 0b001 */
133 		X86_SOCKET_S1g3,	/* 0b010 */
134 		X86_SOCKET_G34,		/* 0b011 */
135 		X86_SOCKET_ASB2,	/* 0b100 */
136 		X86_SOCKET_C32,		/* 0b101 */
137 		X86_SOCKET_UNKNOWN,	/* 0b110 */
138 		X86_SOCKET_UNKNOWN	/* 0b111 */
139 	},
140 
141 	/*
142 	 * Family 0x11
143 	 */
144 #define	A_SKTS_3			3
145 	{
146 		X86_SOCKET_UNKNOWN,	/* 0b000 */
147 		X86_SOCKET_UNKNOWN,	/* 0b001 */
148 		X86_SOCKET_S1g2,	/* 0b010 */
149 		X86_SOCKET_UNKNOWN,	/* 0b011 */
150 		X86_SOCKET_UNKNOWN,	/* 0b100 */
151 		X86_SOCKET_UNKNOWN,	/* 0b101 */
152 		X86_SOCKET_UNKNOWN,	/* 0b110 */
153 		X86_SOCKET_UNKNOWN	/* 0b111 */
154 	},
155 
156 	/*
157 	 * Family 0x12
158 	 */
159 #define	A_SKTS_4			4
160 	{
161 		X86_SOCKET_UNKNOWN,	/* 0b000 */
162 		X86_SOCKET_FS1,		/* 0b001 */
163 		X86_SOCKET_FM1,		/* 0b010 */
164 		X86_SOCKET_UNKNOWN,	/* 0b011 */
165 		X86_SOCKET_UNKNOWN,	/* 0b100 */
166 		X86_SOCKET_UNKNOWN,	/* 0b101 */
167 		X86_SOCKET_UNKNOWN,	/* 0b110 */
168 		X86_SOCKET_UNKNOWN	/* 0b111 */
169 	},
170 
171 	/*
172 	 * Family 0x14
173 	 */
174 #define	A_SKTS_5			5
175 	{
176 		X86_SOCKET_FT1,		/* 0b000 */
177 		X86_SOCKET_UNKNOWN,	/* 0b001 */
178 		X86_SOCKET_UNKNOWN,	/* 0b010 */
179 		X86_SOCKET_UNKNOWN,	/* 0b011 */
180 		X86_SOCKET_UNKNOWN,	/* 0b100 */
181 		X86_SOCKET_UNKNOWN,	/* 0b101 */
182 		X86_SOCKET_UNKNOWN,	/* 0b110 */
183 		X86_SOCKET_UNKNOWN	/* 0b111 */
184 	},
185 
186 	/*
187 	 * Family 0x15 models 00 - 0f
188 	 */
189 #define	A_SKTS_6			6
190 	{
191 		X86_SOCKET_UNKNOWN,	/* 0b000 */
192 		X86_SOCKET_AM3R2,	/* 0b001 */
193 		X86_SOCKET_UNKNOWN,	/* 0b010 */
194 		X86_SOCKET_G34,		/* 0b011 */
195 		X86_SOCKET_UNKNOWN,	/* 0b100 */
196 		X86_SOCKET_C32,		/* 0b101 */
197 		X86_SOCKET_UNKNOWN,	/* 0b110 */
198 		X86_SOCKET_UNKNOWN	/* 0b111 */
199 	},
200 
201 	/*
202 	 * Family 0x15 models 10 - 1f
203 	 */
204 #define	A_SKTS_7			7
205 	{
206 		X86_SOCKET_FP2,		/* 0b000 */
207 		X86_SOCKET_FS1R2,	/* 0b001 */
208 		X86_SOCKET_FM2,		/* 0b010 */
209 		X86_SOCKET_UNKNOWN,	/* 0b011 */
210 		X86_SOCKET_UNKNOWN,	/* 0b100 */
211 		X86_SOCKET_UNKNOWN,	/* 0b101 */
212 		X86_SOCKET_UNKNOWN,	/* 0b110 */
213 		X86_SOCKET_UNKNOWN	/* 0b111 */
214 	},
215 
216 	/*
217 	 * Family 0x15 models 30-3f
218 	 */
219 #define	A_SKTS_8			8
220 	{
221 		X86_SOCKET_FP3,		/* 0b000 */
222 		X86_SOCKET_FM2R2,	/* 0b001 */
223 		X86_SOCKET_UNKNOWN,	/* 0b010 */
224 		X86_SOCKET_UNKNOWN,	/* 0b011 */
225 		X86_SOCKET_UNKNOWN,	/* 0b100 */
226 		X86_SOCKET_UNKNOWN,	/* 0b101 */
227 		X86_SOCKET_UNKNOWN,	/* 0b110 */
228 		X86_SOCKET_UNKNOWN	/* 0b111 */
229 	},
230 
231 	/*
232 	 * Family 0x15 models 60-6f
233 	 */
234 #define	A_SKTS_9			9
235 	{
236 		X86_SOCKET_FP4,		/* 0b000 */
237 		X86_SOCKET_UNKNOWN,	/* 0b001 */
238 		X86_SOCKET_AM4,		/* 0b010 */
239 		X86_SOCKET_FM2R2,	/* 0b011 */
240 		X86_SOCKET_UNKNOWN,	/* 0b100 */
241 		X86_SOCKET_UNKNOWN,	/* 0b101 */
242 		X86_SOCKET_UNKNOWN,	/* 0b110 */
243 		X86_SOCKET_UNKNOWN	/* 0b111 */
244 	},
245 
246 	/*
247 	 * Family 0x15 models 70-7f
248 	 */
249 #define	A_SKTS_10			10
250 	{
251 		X86_SOCKET_FP4,		/* 0b000 */
252 		X86_SOCKET_UNKNOWN,	/* 0b001 */
253 		X86_SOCKET_AM4,		/* 0b010 */
254 		X86_SOCKET_UNKNOWN,	/* 0b011 */
255 		X86_SOCKET_FT4,		/* 0b100 */
256 		X86_SOCKET_UNKNOWN,	/* 0b101 */
257 		X86_SOCKET_UNKNOWN,	/* 0b110 */
258 		X86_SOCKET_UNKNOWN	/* 0b111 */
259 	},
260 
261 	/*
262 	 * Family 0x16 models 00-0f
263 	 */
264 #define	A_SKTS_11			11
265 	{
266 		X86_SOCKET_FT3,		/* 0b000 */
267 		X86_SOCKET_FS1B,	/* 0b001 */
268 		X86_SOCKET_UNKNOWN,	/* 0b010 */
269 		X86_SOCKET_UNKNOWN,	/* 0b011 */
270 		X86_SOCKET_UNKNOWN,	/* 0b100 */
271 		X86_SOCKET_UNKNOWN,	/* 0b101 */
272 		X86_SOCKET_UNKNOWN,	/* 0b110 */
273 		X86_SOCKET_UNKNOWN	/* 0b111 */
274 	},
275 
276 	/*
277 	 * Family 0x16 models 30-3f
278 	 */
279 #define	A_SKTS_12			12
280 	{
281 		X86_SOCKET_FT3B,	/* 0b000 */
282 		X86_SOCKET_UNKNOWN,	/* 0b001 */
283 		X86_SOCKET_UNKNOWN,	/* 0b010 */
284 		X86_SOCKET_FP4,		/* 0b011 */
285 		X86_SOCKET_UNKNOWN,	/* 0b100 */
286 		X86_SOCKET_UNKNOWN,	/* 0b101 */
287 		X86_SOCKET_UNKNOWN,	/* 0b110 */
288 		X86_SOCKET_UNKNOWN	/* 0b111 */
289 	},
290 
291 	/*
292 	 * Family 0x17 models 00-0f	(Zen 1 - Naples, Ryzen)
293 	 */
294 #define	A_SKTS_13			13
295 	{
296 		X86_SOCKET_UNKNOWN,	/* 0b000 */
297 		X86_SOCKET_UNKNOWN,	/* 0b001 */
298 		X86_SOCKET_AM4,		/* 0b010 */
299 		X86_SOCKET_UNKNOWN,	/* 0b011 */
300 		X86_SOCKET_SP3,		/* 0b100 */
301 		X86_SOCKET_UNKNOWN,	/* 0b101 */
302 		X86_SOCKET_UNKNOWN,	/* 0b110 */
303 		X86_SOCKET_SP3R2	/* 0b111 */
304 	},
305 
306 	/*
307 	 * Family 0x17 models 10-2f	(Zen 1 - APU: Raven Ridge)
308 	 *				(Zen 1 - APU: Banded Kestrel)
309 	 *				(Zen 1 - APU: Dali)
310 	 */
311 #define	A_SKTS_14			14
312 	{
313 		X86_SOCKET_FP5,		/* 0b000 */
314 		X86_SOCKET_UNKNOWN,	/* 0b001 */
315 		X86_SOCKET_AM4,		/* 0b010 */
316 		X86_SOCKET_UNKNOWN,	/* 0b011 */
317 		X86_SOCKET_UNKNOWN,	/* 0b100 */
318 		X86_SOCKET_UNKNOWN,	/* 0b101 */
319 		X86_SOCKET_UNKNOWN,	/* 0b110 */
320 		X86_SOCKET_UNKNOWN	/* 0b111 */
321 	},
322 
323 	/*
324 	 * Family 0x17 models 30-3f	(Zen 2 - Rome)
325 	 */
326 #define	A_SKTS_15			15
327 	{
328 		X86_SOCKET_UNKNOWN,	/* 0b000 */
329 		X86_SOCKET_UNKNOWN,	/* 0b001 */
330 		X86_SOCKET_UNKNOWN,	/* 0b010 */
331 		X86_SOCKET_UNKNOWN,	/* 0b011 */
332 		X86_SOCKET_SP3,		/* 0b100 */
333 		X86_SOCKET_UNKNOWN,	/* 0b101 */
334 		X86_SOCKET_UNKNOWN,	/* 0b110 */
335 		X86_SOCKET_SP3R2	/* 0b111 */
336 	},
337 
338 	/*
339 	 * Family 0x17 models 60-6f	(Zen 2 - Renoir)
340 	 */
341 #define	A_SKTS_16			16
342 	{
343 		X86_SOCKET_FP6,		/* 0b000 */
344 		X86_SOCKET_UNKNOWN,	/* 0b001 */
345 		X86_SOCKET_AM4,		/* 0b010 */
346 		X86_SOCKET_UNKNOWN,	/* 0b011 */
347 		X86_SOCKET_UNKNOWN,	/* 0b100 */
348 		X86_SOCKET_UNKNOWN,	/* 0b101 */
349 		X86_SOCKET_UNKNOWN,	/* 0b110 */
350 		X86_SOCKET_UNKNOWN	/* 0b111 */
351 	},
352 
353 	/*
354 	 * Family 0x17 models 70-7f	(Zen 2 - Matisse)
355 	 */
356 #define	A_SKTS_17			17
357 	{
358 		X86_SOCKET_UNKNOWN,	/* 0b000 */
359 		X86_SOCKET_UNKNOWN,	/* 0b001 */
360 		X86_SOCKET_AM4,		/* 0b010 */
361 		X86_SOCKET_UNKNOWN,	/* 0b011 */
362 		X86_SOCKET_UNKNOWN,	/* 0b100 */
363 		X86_SOCKET_UNKNOWN,	/* 0b101 */
364 		X86_SOCKET_UNKNOWN,	/* 0b110 */
365 		X86_SOCKET_UNKNOWN	/* 0b111 */
366 	},
367 
368 	/*
369 	 * Family 0x18 models 00-0f	(Dhyana)
370 	 */
371 #define	A_SKTS_18			18
372 	{
373 		X86_SOCKET_UNKNOWN,	/* 0b000 */
374 		X86_SOCKET_UNKNOWN,	/* 0b001 */
375 		X86_SOCKET_UNKNOWN,	/* 0b010 */
376 		X86_SOCKET_UNKNOWN,	/* 0b011 */
377 		X86_SOCKET_SL1,		/* 0b100 */
378 		X86_SOCKET_UNKNOWN,	/* 0b101 */
379 		X86_SOCKET_DM1,		/* 0b110 */
380 		X86_SOCKET_SL1R2	/* 0b111 */
381 	},
382 
383 	/*
384 	 * Family 0x19 models 00-0f	(Zen 3 - Milan)
385 	 */
386 #define	A_SKTS_19			19
387 	{
388 		X86_SOCKET_UNKNOWN,	/* 0b000 */
389 		X86_SOCKET_UNKNOWN,	/* 0b001 */
390 		X86_SOCKET_UNKNOWN,	/* 0b010 */
391 		X86_SOCKET_UNKNOWN,	/* 0b011 */
392 		X86_SOCKET_SP3,		/* 0b100 */
393 		X86_SOCKET_UNKNOWN,	/* 0b101 */
394 		X86_SOCKET_UNKNOWN,	/* 0b110 */
395 		X86_SOCKET_STRX4	/* 0b111 */
396 	},
397 
398 	/*
399 	 * Family 0x19 models 20-2f	(Zen 3 - Vermeer)
400 	 */
401 #define	A_SKTS_20			20
402 	{
403 		X86_SOCKET_UNKNOWN,	/* 0b000 */
404 		X86_SOCKET_UNKNOWN,	/* 0b001 */
405 		X86_SOCKET_AM4,		/* 0b010 */
406 		X86_SOCKET_UNKNOWN,	/* 0b011 */
407 		X86_SOCKET_UNKNOWN,	/* 0b100 */
408 		X86_SOCKET_UNKNOWN,	/* 0b101 */
409 		X86_SOCKET_UNKNOWN,	/* 0b110 */
410 		X86_SOCKET_UNKNOWN	/* 0b111 */
411 	}
412 };
413 
414 struct amd_sktmap_s {
415 	uint32_t	skt_code;
416 	char		sktstr[16];
417 };
418 static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS + 1] = {
419 	{ X86_SOCKET_754,	"754" },
420 	{ X86_SOCKET_939,	"939" },
421 	{ X86_SOCKET_940,	"940" },
422 	{ X86_SOCKET_S1g1,	"S1g1" },
423 	{ X86_SOCKET_AM2,	"AM2" },
424 	{ X86_SOCKET_F1207,	"F(1207)" },
425 	{ X86_SOCKET_S1g2,	"S1g2" },
426 	{ X86_SOCKET_S1g3,	"S1g3" },
427 	{ X86_SOCKET_AM,	"AM" },
428 	{ X86_SOCKET_AM2R2,	"AM2r2" },
429 	{ X86_SOCKET_AM3,	"AM3" },
430 	{ X86_SOCKET_G34,	"G34" },
431 	{ X86_SOCKET_ASB2,	"ASB2" },
432 	{ X86_SOCKET_C32,	"C32" },
433 	{ X86_SOCKET_FT1,	"FT1" },
434 	{ X86_SOCKET_FM1,	"FM1" },
435 	{ X86_SOCKET_FS1,	"FS1" },
436 	{ X86_SOCKET_AM3R2,	"AM3r2" },
437 	{ X86_SOCKET_FP2,	"FP2" },
438 	{ X86_SOCKET_FS1R2,	"FS1r2" },
439 	{ X86_SOCKET_FM2,	"FM2" },
440 	{ X86_SOCKET_FP3,	"FP3" },
441 	{ X86_SOCKET_FM2R2,	"FM2r2" },
442 	{ X86_SOCKET_FP4,	"FP4" },
443 	{ X86_SOCKET_AM4,	"AM4" },
444 	{ X86_SOCKET_FT3,	"FT3" },
445 	{ X86_SOCKET_FT4,	"FT4" },
446 	{ X86_SOCKET_FS1B,	"FS1b" },
447 	{ X86_SOCKET_FT3B,	"FT3b" },
448 	{ X86_SOCKET_SP3,	"SP3" },
449 	{ X86_SOCKET_SP3R2,	"SP3r2" },
450 	{ X86_SOCKET_FP5,	"FP5" },
451 	{ X86_SOCKET_FP6,	"FP6" },
452 	{ X86_SOCKET_STRX4,	"sTRX4" },
453 	{ X86_SOCKET_SL1,	"SL1" },
454 	{ X86_SOCKET_SL1R2,	"SL1R2" },
455 	{ X86_SOCKET_DM1,	"DM1" },
456 	{ X86_SOCKET_UNKNOWN,	"Unknown" }
457 };
458 
459 static const struct amd_skt_mapent {
460 	uint_t sm_family;
461 	uint_t sm_modello;
462 	uint_t sm_modelhi;
463 	uint_t sm_sktidx;
464 } amd_sktmap[] = {
465 	{ 0x10, 0x00, 0xff, A_SKTS_2 },
466 	{ 0x11, 0x00, 0xff, A_SKTS_3 },
467 	{ 0x12, 0x00, 0xff, A_SKTS_4 },
468 	{ 0x14, 0x00, 0x0f, A_SKTS_5 },
469 	{ 0x15, 0x00, 0x0f, A_SKTS_6 },
470 	{ 0x15, 0x10, 0x1f, A_SKTS_7 },
471 	{ 0x15, 0x30, 0x3f, A_SKTS_8 },
472 	{ 0x15, 0x60, 0x6f, A_SKTS_9 },
473 	{ 0x15, 0x70, 0x7f, A_SKTS_10 },
474 	{ 0x16, 0x00, 0x0f, A_SKTS_11 },
475 	{ 0x16, 0x30, 0x3f, A_SKTS_12 },
476 	{ 0x17, 0x00, 0x0f, A_SKTS_13 },
477 	{ 0x17, 0x10, 0x2f, A_SKTS_14 },
478 	{ 0x17, 0x30, 0x3f, A_SKTS_15 },
479 	{ 0x17, 0x60, 0x6f, A_SKTS_16 },
480 	{ 0x17, 0x70, 0x7f, A_SKTS_17 },
481 	{ 0x18, 0x00, 0x0f, A_SKTS_18 },
482 	{ 0x19, 0x00, 0x0f, A_SKTS_19 },
483 	{ 0x19, 0x20, 0x2f, A_SKTS_20 }
484 };
485 
486 /*
487  * Table for mapping AMD Family 0xf and AMD Family 0x10 model/stepping
488  * combination to chip "revision" and socket type.
489  *
490  * The first member of this array that matches a given family, extended model
491  * plus model range, and stepping range will be considered a match.
492  */
493 static const struct amd_rev_mapent {
494 	uint_t rm_family;
495 	uint_t rm_modello;
496 	uint_t rm_modelhi;
497 	uint_t rm_steplo;
498 	uint_t rm_stephi;
499 	uint32_t rm_chiprev;
500 	const char *rm_chiprevstr;
501 	uint_t rm_sktidx;
502 } amd_revmap[] = {
503 	/*
504 	 * =============== AuthenticAMD Family 0xf ===============
505 	 */
506 
507 	/*
508 	 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
509 	 */
510 	{ 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
511 	{ 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", A_SKTS_0 },
512 	/*
513 	 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
514 	 */
515 	{ 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", A_SKTS_0 },
516 	/*
517 	 * Rev CG is the rest of extended model 0x0 - i.e., everything
518 	 * but the rev B and C0 combinations covered above.
519 	 */
520 	{ 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", A_SKTS_0 },
521 	/*
522 	 * Rev D has extended model 0x1.
523 	 */
524 	{ 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", A_SKTS_0 },
525 	/*
526 	 * Rev E has extended model 0x2.
527 	 * Extended model 0x3 is unused but available to grow into.
528 	 */
529 	{ 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", A_SKTS_0 },
530 	/*
531 	 * Rev F has extended models 0x4 and 0x5.
532 	 */
533 	{ 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", A_SKTS_1 },
534 	/*
535 	 * Rev G has extended model 0x6.
536 	 */
537 	{ 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", A_SKTS_1 },
538 
539 	/*
540 	 * =============== AuthenticAMD Family 0x10 ===============
541 	 */
542 
543 	/*
544 	 * Rev A has model 0 and stepping 0/1/2 for DR-{A0,A1,A2}.
545 	 * Give all of model 0 stepping range to rev A.
546 	 */
547 	{ 0x10, 0x00, 0x00, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_A, "A", A_SKTS_2 },
548 
549 	/*
550 	 * Rev B has model 2 and steppings 0/1/0xa/2 for DR-{B0,B1,BA,B2}.
551 	 * Give all of model 2 stepping range to rev B.
552 	 */
553 	{ 0x10, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_B, "B", A_SKTS_2 },
554 
555 	/*
556 	 * Rev C has models 4-6 (depending on L3 cache configuration)
557 	 * Give all of models 4-6 stepping range 0-2 to rev C2.
558 	 */
559 	{ 0x10, 0x4, 0x6, 0x0, 0x2, X86_CHIPREV_AMD_10_REV_C2, "C2", A_SKTS_2 },
560 
561 	/*
562 	 * Rev C has models 4-6 (depending on L3 cache configuration)
563 	 * Give all of models 4-6 stepping range >= 3 to rev C3.
564 	 */
565 	{ 0x10, 0x4, 0x6, 0x3, 0xf, X86_CHIPREV_AMD_10_REV_C3, "C3", A_SKTS_2 },
566 
567 	/*
568 	 * Rev D has models 8 and 9
569 	 * Give all of model 8 and 9 stepping 0 to rev D0.
570 	 */
571 	{ 0x10, 0x8, 0x9, 0x0, 0x0, X86_CHIPREV_AMD_10_REV_D0, "D0", A_SKTS_2 },
572 
573 	/*
574 	 * Rev D has models 8 and 9
575 	 * Give all of model 8 and 9 stepping range >= 1 to rev D1.
576 	 */
577 	{ 0x10, 0x8, 0x9, 0x1, 0xf, X86_CHIPREV_AMD_10_REV_D1, "D1", A_SKTS_2 },
578 
579 	/*
580 	 * Rev E has models A and stepping 0
581 	 * Give all of model A stepping range to rev E.
582 	 */
583 	{ 0x10, 0xA, 0xA, 0x0, 0xf, X86_CHIPREV_AMD_10_REV_E, "E", A_SKTS_2 },
584 
585 	/*
586 	 * =============== AuthenticAMD Family 0x11 ===============
587 	 */
588 	{ 0x11, 0x03, 0x03, 0x0, 0xf, X86_CHIPREV_AMD_11_REV_B, "B", A_SKTS_3 },
589 
590 	/*
591 	 * =============== AuthenticAMD Family 0x12 ===============
592 	 */
593 	{ 0x12, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_12_REV_B, "B", A_SKTS_4 },
594 
595 	/*
596 	 * =============== AuthenticAMD Family 0x14 ===============
597 	 */
598 	{ 0x14, 0x01, 0x01, 0x0, 0xf, X86_CHIPREV_AMD_14_REV_B, "B", A_SKTS_5 },
599 	{ 0x14, 0x02, 0x02, 0x0, 0xf, X86_CHIPREV_AMD_14_REV_C, "C", A_SKTS_5 },
600 
601 	/*
602 	 * =============== AuthenticAMD Family 0x15 ===============
603 	 */
604 	{ 0x15, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_15OR_REV_B2, "OR-B2",
605 	    A_SKTS_6 },
606 	{ 0x15, 0x02, 0x02, 0x0, 0x0, X86_CHIPREV_AMD_150R_REV_C0, "OR-C0",
607 	    A_SKTS_6 },
608 	{ 0x15, 0x10, 0x10, 0x1, 0x1, X86_CHIPREV_AMD_15TN_REV_A1, "TN-A1",
609 	    A_SKTS_7 },
610 	{ 0x15, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_15KV_REV_A1, "KV-A1",
611 	    A_SKTS_8 },
612 	/*
613 	 * There is no Family 15 Models 60-6f revision guide available, so at
614 	 * least get the socket information.
615 	 */
616 	{ 0x15, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_15F60, "??",
617 	    A_SKTS_9 },
618 	{ 0x15, 0x70, 0x70, 0x0, 0x0, X86_CHIPREV_AMD_15ST_REV_A0, "ST-A0",
619 	    A_SKTS_10 },
620 
621 	/*
622 	 * =============== AuthenticAMD Family 0x16 ===============
623 	 */
624 	{ 0x16, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_AMD_16_KB_A1, "KB-A1",
625 	    A_SKTS_11 },
626 	{ 0x16, 0x30, 0x30, 0x1, 0x1, X86_CHIPREV_AMD_16_ML_A1, "ML-A1",
627 	    A_SKTS_12 },
628 
629 	/*
630 	 * =============== AuthenticAMD Family 0x17 ===============
631 	 */
632 	{ 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_17_ZP_B1, "ZP-B1",
633 	    A_SKTS_13 },
634 	{ 0x17, 0x01, 0x01, 0x2, 0x2, X86_CHIPREV_AMD_17_ZP_B2, "ZP-B2",
635 	    A_SKTS_13 },
636 	{ 0x17, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_17_PiR_B2, "PiR-B2",
637 	    A_SKTS_13 },
638 
639 	{ 0x17, 0x11, 0x11, 0x0, 0x0, X86_CHIPREV_AMD_17_RV_B0, "RV-B0",
640 	    A_SKTS_14 },
641 	{ 0x17, 0x11, 0x11, 0x1, 0x1, X86_CHIPREV_AMD_17_RV_B1, "RV-B1",
642 	    A_SKTS_14 },
643 	{ 0x17, 0x18, 0x18, 0x1, 0x1, X86_CHIPREV_AMD_17_PCO_B1, "PCO-B1",
644 	    A_SKTS_14 },
645 
646 	{ 0x17, 0x30, 0x30, 0x0, 0x0, X86_CHIPREV_AMD_17_SSP_A0, "SSP-A0",
647 	    A_SKTS_15 },
648 	{ 0x17, 0x31, 0x31, 0x0, 0x0, X86_CHIPREV_AMD_17_SSP_B0, "SSP-B0",
649 	    A_SKTS_15 },
650 
651 	{ 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_17_MTS_B0, "MTS-B0",
652 	    A_SKTS_17 },
653 
654 	/*
655 	 * =============== HygonGenuine Family 0x18 ===============
656 	 */
657 	{ 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_18_DN_A1, "DN_A1",
658 	    A_SKTS_18 },
659 
660 	/*
661 	 * =============== AuthenticAMD Family 0x19 ===============
662 	 */
663 	{ 0x19, 0x00, 0x00, 0x0, 0x0, X86_CHIPREV_AMD_19_GN_A0, "GN-A0",
664 	    A_SKTS_19 },
665 	{ 0x19, 0x01, 0x01, 0x0, 0x0, X86_CHIPREV_AMD_19_GN_B0, "GN-B0",
666 	    A_SKTS_19 },
667 	{ 0x19, 0x01, 0x01, 0x1, 0x1, X86_CHIPREV_AMD_19_GN_B1, "GN-B1",
668 	    A_SKTS_19 },
669 
670 	{ 0x19, 0x21, 0x21, 0x0, 0x0, X86_CHIPREV_AMD_19_VMR_B0, "VMR-B0",
671 	    A_SKTS_20 },
672 	{ 0x19, 0x21, 0x21, 0x2, 0x2, X86_CHIPREV_AMD_19_VMR_B1, "VMR-B1",
673 	    A_SKTS_20 },
674 };
675 
676 /*
677  * AMD keeps the socket type in CPUID Fn8000_0001_EBX, bits 31:28.
678  */
679 static uint32_t
synth_amd_skt_cpuid(uint_t family,uint_t sktid)680 synth_amd_skt_cpuid(uint_t family, uint_t sktid)
681 {
682 	struct cpuid_regs cp;
683 	uint_t idx;
684 
685 	cp.cp_eax = 0x80000001;
686 	(void) __cpuid_insn(&cp);
687 
688 	/* PkgType bits */
689 	idx = BITX(cp.cp_ebx, 31, 28);
690 
691 	if (idx > 7) {
692 		return (X86_SOCKET_UNKNOWN);
693 	}
694 
695 	if (family == 0x10) {
696 		uint32_t val;
697 
698 		val = pci_getl_func(0, 24, 2, 0x94);
699 		if (BITX(val, 8, 8)) {
700 			if (amd_skts[sktid][idx] == X86_SOCKET_AM2R2) {
701 				return (X86_SOCKET_AM3);
702 			} else if (amd_skts[sktid][idx] == X86_SOCKET_S1g3) {
703 				return (X86_SOCKET_S1g4);
704 			}
705 		}
706 	}
707 
708 	return (amd_skts[sktid][idx]);
709 }
710 
711 static void
synth_amd_skt(uint_t family,uint_t model,uint32_t * skt_p)712 synth_amd_skt(uint_t family, uint_t model, uint32_t *skt_p)
713 {
714 	int platform;
715 	const struct amd_skt_mapent *skt;
716 	uint_t i;
717 
718 	if (skt_p == NULL || family < 0xf)
719 		return;
720 
721 #ifdef __xpv
722 	/* PV guest */
723 	if (!is_controldom()) {
724 		*skt_p = X86_SOCKET_UNKNOWN;
725 		return;
726 	}
727 #endif
728 	platform = get_hwenv();
729 
730 	if ((platform & HW_VIRTUAL) != 0) {
731 		*skt_p = X86_SOCKET_UNKNOWN;
732 		return;
733 	}
734 
735 	for (i = 0, skt = amd_sktmap; i < ARRAY_SIZE(amd_sktmap);
736 	    i++, skt++) {
737 		if (family == skt->sm_family &&
738 		    model >= skt->sm_modello && model <= skt->sm_modelhi) {
739 			*skt_p = synth_amd_skt_cpuid(family, skt->sm_sktidx);
740 		}
741 	}
742 }
743 
744 static void
synth_amd_info(uint_t family,uint_t model,uint_t step,uint32_t * skt_p,uint32_t * chiprev_p,const char ** chiprevstr_p)745 synth_amd_info(uint_t family, uint_t model, uint_t step,
746     uint32_t *skt_p, uint32_t *chiprev_p, const char **chiprevstr_p)
747 {
748 	const struct amd_rev_mapent *rmp;
749 	int found = 0;
750 	int i;
751 
752 	if (family < 0xf)
753 		return;
754 
755 	for (i = 0, rmp = amd_revmap; i < ARRAY_SIZE(amd_revmap); i++, rmp++) {
756 		if (family == rmp->rm_family &&
757 		    model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
758 		    step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
759 			found = 1;
760 			break;
761 		}
762 	}
763 
764 	if (!found) {
765 		synth_amd_skt(family, model, skt_p);
766 		return;
767 	}
768 
769 	if (chiprev_p != NULL)
770 		*chiprev_p = rmp->rm_chiprev;
771 	if (chiprevstr_p != NULL)
772 		*chiprevstr_p = rmp->rm_chiprevstr;
773 
774 	if (skt_p != NULL) {
775 		int platform;
776 
777 #ifdef __xpv
778 		/* PV guest */
779 		if (!is_controldom()) {
780 			*skt_p = X86_SOCKET_UNKNOWN;
781 			return;
782 		}
783 #endif
784 		platform = get_hwenv();
785 
786 		if ((platform & HW_VIRTUAL) != 0) {
787 			*skt_p = X86_SOCKET_UNKNOWN;
788 		} else if (family == 0xf) {
789 			*skt_p = amd_skts[rmp->rm_sktidx][model & 0x3];
790 		} else {
791 			*skt_p = synth_amd_skt_cpuid(family, rmp->rm_sktidx);
792 		}
793 	}
794 }
795 
796 uint32_t
_cpuid_skt(uint_t vendor,uint_t family,uint_t model,uint_t step)797 _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step)
798 {
799 	uint32_t skt = X86_SOCKET_UNKNOWN;
800 
801 	switch (vendor) {
802 	case X86_VENDOR_AMD:
803 	case X86_VENDOR_HYGON:
804 		synth_amd_info(family, model, step, &skt, NULL, NULL);
805 		break;
806 
807 	default:
808 		break;
809 
810 	}
811 
812 	return (skt);
813 }
814 
815 const char *
_cpuid_sktstr(uint_t vendor,uint_t family,uint_t model,uint_t step)816 _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
817 {
818 	const char *sktstr = "Unknown";
819 	struct amd_sktmap_s *sktmapp;
820 	uint32_t skt = X86_SOCKET_UNKNOWN;
821 
822 	switch (vendor) {
823 	case X86_VENDOR_AMD:
824 	case X86_VENDOR_HYGON:
825 		synth_amd_info(family, model, step, &skt, NULL, NULL);
826 
827 		sktmapp = amd_sktmap_strs;
828 		while (sktmapp->skt_code != X86_SOCKET_UNKNOWN) {
829 			if (sktmapp->skt_code == skt)
830 				break;
831 			sktmapp++;
832 		}
833 		sktstr = sktmapp->sktstr;
834 		break;
835 
836 	default:
837 		break;
838 
839 	}
840 
841 	return (sktstr);
842 }
843 
844 uint32_t
_cpuid_chiprev(uint_t vendor,uint_t family,uint_t model,uint_t step)845 _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step)
846 {
847 	uint32_t chiprev = X86_CHIPREV_UNKNOWN;
848 
849 	switch (vendor) {
850 	case X86_VENDOR_AMD:
851 	case X86_VENDOR_HYGON:
852 		synth_amd_info(family, model, step, NULL, &chiprev, NULL);
853 		break;
854 
855 	default:
856 		break;
857 
858 	}
859 
860 	return (chiprev);
861 }
862 
863 const char *
_cpuid_chiprevstr(uint_t vendor,uint_t family,uint_t model,uint_t step)864 _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
865 {
866 	const char *revstr = "Unknown";
867 
868 	switch (vendor) {
869 	case X86_VENDOR_AMD:
870 	case X86_VENDOR_HYGON:
871 		synth_amd_info(family, model, step, NULL, NULL, &revstr);
872 		break;
873 
874 	default:
875 		break;
876 
877 	}
878 
879 	return (revstr);
880 
881 }
882 
883 /*
884  * CyrixInstead is a variable used by the Cyrix detection code
885  * in locore.
886  */
887 const char CyrixInstead[] = X86_VENDORSTR_CYRIX;
888 
889 /*
890  * Map the vendor string to a type code
891  */
892 uint_t
_cpuid_vendorstr_to_vendorcode(char * vendorstr)893 _cpuid_vendorstr_to_vendorcode(char *vendorstr)
894 {
895 	if (strcmp(vendorstr, X86_VENDORSTR_Intel) == 0)
896 		return (X86_VENDOR_Intel);
897 	else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
898 		return (X86_VENDOR_AMD);
899 	else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0)
900 		return (X86_VENDOR_HYGON);
901 	else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
902 		return (X86_VENDOR_TM);
903 	else if (strcmp(vendorstr, CyrixInstead) == 0)
904 		return (X86_VENDOR_Cyrix);
905 	else if (strcmp(vendorstr, X86_VENDORSTR_UMC) == 0)
906 		return (X86_VENDOR_UMC);
907 	else if (strcmp(vendorstr, X86_VENDORSTR_NexGen) == 0)
908 		return (X86_VENDOR_NexGen);
909 	else if (strcmp(vendorstr, X86_VENDORSTR_Centaur) == 0)
910 		return (X86_VENDOR_Centaur);
911 	else if (strcmp(vendorstr, X86_VENDORSTR_Rise) == 0)
912 		return (X86_VENDOR_Rise);
913 	else if (strcmp(vendorstr, X86_VENDORSTR_SiS) == 0)
914 		return (X86_VENDOR_SiS);
915 	else if (strcmp(vendorstr, X86_VENDORSTR_NSC) == 0)
916 		return (X86_VENDOR_NSC);
917 	else
918 		return (X86_VENDOR_IntelClone);
919 }
920