1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23 * Use is subject to license terms.
24 * Copyright 2018 Joyent, Inc.
25 */
26
27#define	PSMI_1_7
28
29#include <sys/mutex.h>
30#include <sys/types.h>
31#include <sys/time.h>
32#include <sys/machlock.h>
33#include <sys/smp_impldefs.h>
34#include <sys/uadmin.h>
35#include <sys/promif.h>
36#include <sys/psm.h>
37#include <sys/pit.h>
38#include <sys/apic.h>
39#include <sys/psm_common.h>
40#include <sys/atomic.h>
41#include <sys/archsystm.h>
42
43#define	NSEC_IN_SEC		1000000000
44
45/*
46 * Local Function Prototypes
47 */
48static void uppc_softinit(void);
49static void uppc_picinit();
50static int uppc_post_cpu_start(void);
51static int uppc_clkinit(int);
52static int uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl);
53static int uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl);
54static processorid_t uppc_get_next_processorid(processorid_t cpu_id);
55static int uppc_get_clockirq(int ipl);
56static int uppc_probe(void);
57static int uppc_translate_irq(dev_info_t *dip, int irqno);
58static void uppc_shutdown(int cmd, int fcn);
59static void uppc_preshutdown(int cmd, int fcn);
60static int uppc_state(psm_state_request_t *request);
61static int uppc_init_acpi(void);
62static void uppc_setspl(int);
63static int uppc_intr_enter(int, int *);
64static void uppc_intr_exit(int, int);
65static hrtime_t uppc_gethrtime();
66
67static int uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
68    int *pci_irqp, iflag_t *intr_flagp);
69
70/*
71 * Global Data
72 */
73static struct standard_pic pics0;
74int uppc_use_acpi = 1;	/* Use ACPI by default */
75int uppc_enable_acpi = 0;
76
77
78/*
79 * For interrupt link devices, if uppc_unconditional_srs is set, an irq resource
80 * will be assigned (via _SRS). If it is not set, use the current
81 * irq setting (via _CRS), but only if that irq is in the set of possible
82 * irqs (returned by _PRS) for the device.
83 */
84int uppc_unconditional_srs = 1;
85
86/*
87 * For interrupt link devices, if uppc_prefer_crs is set when we are
88 * assigning an IRQ resource to a device, prefer the current IRQ setting
89 * over other possible irq settings under same conditions.
90 */
91int uppc_prefer_crs = 1;
92
93int uppc_verbose = 0;
94
95/* flag definitions for uppc_verbose */
96#define	UPPC_VERBOSE_IRQ_FLAG			0x00000001
97#define	UPPC_VERBOSE_POWEROFF_FLAG		0x00000002
98#define	UPPC_VERBOSE_POWEROFF_PAUSE_FLAG	0x00000004
99
100
101#define	UPPC_VERBOSE_IRQ(fmt) \
102	if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG) \
103		cmn_err fmt;
104
105#define	UPPC_VERBOSE_POWEROFF(fmt) \
106	if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG) \
107		prom_printf fmt;
108
109uchar_t uppc_reserved_irqlist[MAX_ISA_IRQ + 1];
110
111static uint16_t uppc_irq_shared_table[MAX_ISA_IRQ + 1];
112
113/*
114 * Contains SCI irqno from FADT after initialization
115 */
116static int uppc_sci = -1;
117
118/*
119 * Local Static Data
120 */
121
122static lock_t uppc_gethrtime_lock;
123static hrtime_t uppc_lasthrtime;
124
125
126#ifdef UPPC_DEBUG
127#define	DENT	0x0001
128
129static int	uppc_debug = 0;
130
131
132#endif
133
134
135static struct	psm_ops uppc_ops = {
136	uppc_probe,				/* psm_probe		*/
137
138	uppc_softinit,				/* psm_init		*/
139	uppc_picinit,				/* psm_picinit		*/
140	uppc_intr_enter,			/* psm_intr_enter	*/
141	uppc_intr_exit,				/* psm_intr_exit	*/
142	uppc_setspl,				/* psm_setspl		*/
143	uppc_addspl,				/* psm_addspl		*/
144	uppc_delspl,				/* psm_delspl		*/
145	(int (*)(processorid_t))NULL,		/* psm_disable_intr	*/
146	(void (*)(processorid_t))NULL,		/* psm_enable_intr	*/
147	(int (*)(int))NULL,			/* psm_softlvl_to_irq	*/
148	(void (*)(int))NULL,			/* psm_set_softintr	*/
149	(void (*)(processorid_t))NULL,		/* psm_set_idlecpu	*/
150	(void (*)(processorid_t))NULL,		/* psm_unset_idlecpu	*/
151
152	uppc_clkinit,				/* psm_clkinit		*/
153	uppc_get_clockirq,			/* psm_get_clockirq	*/
154	(void (*)(void))NULL,			/* psm_hrtimeinit	*/
155	uppc_gethrtime,				/* psm_gethrtime	*/
156
157	uppc_get_next_processorid,		/* psm_get_next_processorid */
158	(int (*)(processorid_t, caddr_t))NULL,	/* psm_cpu_start	*/
159	uppc_post_cpu_start,			/* psm_post_cpu_start	*/
160	uppc_shutdown,				/* psm_shutdown		*/
161	(int (*)(int, int))NULL,		/* psm_get_ipivect	*/
162	(void (*)(processorid_t, int))NULL,	/* psm_send_ipi		*/
163
164	uppc_translate_irq,			/* psm_translate_irq	*/
165
166	(void (*)(int, char *))NULL,		/* psm_notify_error	*/
167	(void (*)(int msg))NULL,		/* psm_notify_func	*/
168	(void (*)(hrtime_t time))NULL,		/* psm_timer_reprogram	*/
169	(void (*)(void))NULL,			/* psm_timer_enable	*/
170	(void (*)(void))NULL,			/* psm_timer_disable	*/
171	(void (*)(void *arg))NULL,		/* psm_post_cyclic_setup */
172	uppc_preshutdown,			/* psm_preshutdown	*/
173
174	(int (*)(dev_info_t *, ddi_intr_handle_impl_t *,
175	    psm_intr_op_t, int *))NULL,		/* psm_intr_ops		*/
176
177	uppc_state,				/* psm_state		*/
178	(int (*)(psm_cpu_request_t *))NULL,	/* psm_cpu_ops		*/
179
180	(int (*)(void))NULL,			/* psm_get_pir_ipivect	*/
181	(void (*)(processorid_t))NULL,		/* psm_send_pir_ipi	*/
182	(void (*)(processorid_t, boolean_t))NULL	/* psm_cmci_setup */
183};
184
185
186static struct	psm_info uppc_info = {
187	PSM_INFO_VER01_7,	/* version				*/
188	PSM_OWN_SYS_DEFAULT,	/* ownership				*/
189	(struct psm_ops *)&uppc_ops, /* operation			*/
190	"uppc",			/* machine name				*/
191	"UniProcessor PC",	/* machine descriptions			*/
192};
193
194/*
195 * Configuration Data
196 */
197
198/*
199 * This is the loadable module wrapper.
200 */
201#include <sys/modctl.h>
202
203static void *uppc_hdlp;
204
205int
206_init(void)
207{
208	return (psm_mod_init(&uppc_hdlp, &uppc_info));
209}
210
211int
212_fini(void)
213{
214	return (psm_mod_fini(&uppc_hdlp, &uppc_info));
215}
216
217int
218_info(struct modinfo *modinfop)
219{
220	return (psm_mod_info(&uppc_hdlp, &uppc_info, modinfop));
221}
222
223/*
224 * Autoconfiguration Routines
225 */
226
227static int
228uppc_probe(void)
229{
230
231
232	return (PSM_SUCCESS);
233}
234
235static void
236uppc_softinit(void)
237{
238	struct standard_pic *pp;
239	int i;
240
241	pp = &pics0;
242
243
244	if (uppc_use_acpi && uppc_init_acpi()) {
245		build_reserved_irqlist((uchar_t *)uppc_reserved_irqlist);
246		for (i = 0; i <= MAX_ISA_IRQ; i++)
247			uppc_irq_shared_table[i] = 0;
248		uppc_enable_acpi = 1;
249	}
250
251	/*
252	 * initialize the ipl mask
253	 */
254	for (i = 0; i < (MAXIPL << 1); i += 2) {
255		/* enable slave lines on master */
256		pp->c_iplmask[i] = 0xff;
257		pp->c_iplmask[i+1] = (0xff & ~(1 << MASTERLINE));
258	}
259}
260
261/*ARGSUSED*/
262static int
263uppc_clkinit(int hertz)
264{
265	ulong_t clkticks = PIT_HZ / hz;
266
267	if (hertz == 0)
268		return (0);	/* One shot mode not supported */
269
270	/*
271	 * program timer 0
272	 */
273	outb(PITCTL_PORT, (PIT_C0|PIT_NDIVMODE|PIT_READMODE));
274	outb(PITCTR0_PORT, (uchar_t)clkticks);
275	outb(PITCTR0_PORT, (uchar_t)(clkticks>>8));
276
277	return (NSEC_IN_SEC / hertz);
278}
279
280static void
281uppc_picinit()
282{
283	picsetup();
284
285	/*
286	 * If a valid SCI is present, manually addspl()
287	 * since we're not set-up early enough in boot
288	 * to do it "conventionally" (via add_avintr)
289	 */
290	if (uppc_sci >= 0)
291		(void) uppc_addspl(uppc_sci, SCI_IPL, SCI_IPL, SCI_IPL);
292}
293
294static int
295uppc_post_cpu_start(void)
296{
297	/*
298	 * On uppc machines psm_post_cpu_start is called during S3 resume
299	 * on the boot cpu from assembly, using the ap_mlsetup vector.
300	 */
301
302	/*
303	 * Init master and slave pic
304	 */
305	picsetup();
306
307	/*
308	 * program timer 0
309	 */
310	(void) uppc_clkinit(hz);
311
312	return (PSM_SUCCESS);
313}
314
315/*ARGSUSED3*/
316static int
317uppc_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
318{
319	struct standard_pic *pp;
320	int i;
321	int startidx;
322	uchar_t	vectmask;
323
324	if (irqno <= MAX_ISA_IRQ)
325		atomic_inc_16(&uppc_irq_shared_table[irqno]);
326
327	if (ipl != min_ipl)
328		return (0);
329
330	if (irqno > 7) {
331		vectmask = 1 << (irqno - 8);
332		startidx = (ipl << 1);
333	} else {
334		vectmask = 1 << irqno;
335		startidx = (ipl << 1) + 1;
336	}
337
338	/*
339	 * mask intr same or above ipl
340	 * level MAXIPL has all intr off as init. default
341	 */
342	pp = &pics0;
343	for (i = startidx; i < (MAXIPL << 1); i += 2) {
344		if (pp->c_iplmask[i] & vectmask)
345			break;
346		pp->c_iplmask[i] |= vectmask;
347	}
348
349	/*
350	 * unmask intr below ipl
351	 */
352	for (i = startidx-2; i >= 0; i -= 2) {
353		if (!(pp->c_iplmask[i] & vectmask))
354			break;
355		pp->c_iplmask[i] &= ~vectmask;
356	}
357	return (0);
358}
359
360static int
361uppc_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
362{
363	struct standard_pic *pp;
364	int i;
365	uchar_t	vectmask;
366
367	if (irqno <= MAX_ISA_IRQ)
368		atomic_dec_16(&uppc_irq_shared_table[irqno]);
369
370	/*
371	 * skip if we are not deleting the last handler
372	 * and the ipl is higher than minimum
373	 */
374	if ((max_ipl != PSM_INVALID_IPL) && (ipl >= min_ipl))
375		return (0);
376
377	if (irqno > 7) {
378		vectmask = 1 << (irqno - 8);
379		i = 0;
380	} else {
381		vectmask = 1 << irqno;
382		i = 1;
383	}
384
385	pp = &pics0;
386
387	/*
388	 * check any handlers left for this irqno
389	 */
390	if (max_ipl != PSM_INVALID_IPL) {
391		/*
392		 * unmasks all levels below the lowest priority
393		 */
394		i += ((min_ipl - 1) << 1);
395		for (; i >= 0; i -= 2) {
396			if (!(pp->c_iplmask[i] & vectmask))
397				break;
398			pp->c_iplmask[i] &= ~vectmask;
399		}
400	} else {
401		/*
402		 * set mask to all levels
403		 */
404		for (; i < (MAXIPL << 1); i += 2) {
405			if (pp->c_iplmask[i] & vectmask)
406				break;
407			pp->c_iplmask[i] |= vectmask;
408		}
409	}
410	return (0);
411}
412
413static processorid_t
414uppc_get_next_processorid(processorid_t cpu_id)
415{
416	if (cpu_id == -1)
417		return (0);
418	return (-1);
419}
420
421/*ARGSUSED*/
422static int
423uppc_get_clockirq(int ipl)
424{
425	return (CLOCK_VECTOR);
426}
427
428
429static int
430uppc_init_acpi(void)
431{
432	int verboseflags = 0;
433	int	sci;
434	iflag_t sci_flags;
435
436	/*
437	 * Process SCI configuration here; this may return
438	 * an error if acpi-user-options has specified
439	 * legacy mode (use ACPI without ACPI mode or SCI)
440	 */
441	if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
442		sci = -1;
443
444	/*
445	 * Initialize sub-system - if error is returns, ACPI is not
446	 * used.
447	 */
448	if (acpica_init() != AE_OK)
449		return (0);
450
451	/*
452	 * uppc implies system is in PIC mode; set edge/level
453	 * via ELCR based on return value from get_sci; this
454	 * will default to level/low if no override present,
455	 * as recommended by Intel ACPI CA team.
456	 */
457	if (sci >= 0) {
458		ASSERT((sci_flags.intr_el == INTR_EL_LEVEL) ||
459		    (sci_flags.intr_el == INTR_EL_EDGE));
460
461		psm_set_elcr(sci, sci_flags.intr_el == INTR_EL_LEVEL);
462	}
463
464	/*
465	 * Remember SCI for later use
466	 */
467	uppc_sci = sci;
468
469	if (uppc_verbose & UPPC_VERBOSE_IRQ_FLAG)
470		verboseflags |= PSM_VERBOSE_IRQ_FLAG;
471
472	if (uppc_verbose & UPPC_VERBOSE_POWEROFF_FLAG)
473		verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
474
475	if (uppc_verbose & UPPC_VERBOSE_POWEROFF_PAUSE_FLAG)
476		verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
477
478	if (acpi_psm_init(uppc_info.p_mach_idstring, verboseflags) ==
479	    ACPI_PSM_FAILURE) {
480		return (0);
481	}
482
483	return (1);
484}
485
486
487static void
488uppc_preshutdown(int cmd, int fcn)
489{
490	UPPC_VERBOSE_POWEROFF(("uppc_preshutdown(%d,%d);\n", cmd, fcn));
491
492}
493
494static void
495uppc_shutdown(int cmd, int fcn)
496{
497	UPPC_VERBOSE_POWEROFF(("uppc_shutdown(%d,%d);\n", cmd, fcn));
498
499	/*
500	 * Return if passed a command other than A_SHUTDOWN or
501	 * if we're not using ACPI.
502	 */
503	if ((cmd != A_SHUTDOWN) || (!uppc_enable_acpi))
504		return;
505
506	/*
507	 * Switch system back into Legacy-Mode if using ACPI and
508	 * not powering-off.  Some BIOSes need to remain in ACPI-mode
509	 * for power-off to succeed (Dell Dimension 4600)
510	 */
511	if (fcn != AD_POWEROFF) {
512		(void) AcpiDisable();
513		return;
514	}
515
516	(void) acpi_poweroff();
517}
518
519
520static int
521uppc_acpi_enter_picmode(void)
522{
523	ACPI_OBJECT_LIST	arglist;
524	ACPI_OBJECT		arg;
525	ACPI_STATUS		status;
526
527	/* Setup parameter object */
528	arglist.Count = 1;
529	arglist.Pointer = &arg;
530	arg.Type = ACPI_TYPE_INTEGER;
531	arg.Integer.Value = ACPI_PIC_MODE;
532
533	status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
534	if (ACPI_FAILURE(status))
535		return (PSM_FAILURE);
536	else
537		return (PSM_SUCCESS);
538}
539
540
541struct pic_state {
542	int8_t		mmask;
543	int8_t		smask;
544	uint16_t	elcr;
545};
546
547
548static void
549pic_save_state(struct pic_state *sp)
550{
551	struct standard_pic *pp;
552	int	vecno;
553
554	/*
555	 * Only the PIC masks and the ELCR can be saved;
556	 * other 8259 state is write-only
557	 */
558
559	/*
560	 * save current master and slave interrupt mask
561	 */
562	pp = &pics0;
563	sp->smask = pp->c_curmask[0];
564	sp->mmask = pp->c_curmask[1];
565
566	/*
567	 * save edge/level configuration for isa interrupts
568	 */
569	sp->elcr = 0;
570	for (vecno = 0; vecno <= MAX_ISA_IRQ; vecno++)
571		sp->elcr |= psm_get_elcr(vecno) << vecno;
572}
573
574static void
575pic_restore_state(struct pic_state *sp)
576{
577	int	vecno;
578
579	/* Restore master and slave interrupt masks */
580	outb(SIMR_PORT, sp->smask);
581	outb(MIMR_PORT, sp->mmask);
582
583	/* Read master to allow pics to settle */
584	(void) inb(MIMR_PORT);
585
586	/* Restore edge/level configuration for isa interupts */
587	for (vecno = 0; vecno <= MAX_ISA_IRQ; vecno++)
588		psm_set_elcr(vecno, sp->elcr & (1 << vecno));
589
590	/* Reenter PIC mode before restoring LNK devices */
591	(void) uppc_acpi_enter_picmode();
592
593	/* Restore ACPI link device mappings */
594	acpi_restore_link_devices();
595}
596
597static int
598uppc_state(psm_state_request_t *rp)
599{
600	switch (rp->psr_cmd) {
601	case PSM_STATE_ALLOC:
602		rp->req.psm_state_req.psr_state =
603		    kmem_zalloc(sizeof (struct pic_state), KM_NOSLEEP);
604		if (rp->req.psm_state_req.psr_state == NULL)
605			return (ENOMEM);
606		rp->req.psm_state_req.psr_state_size =
607		    sizeof (struct pic_state);
608		return (0);
609	case PSM_STATE_FREE:
610		kmem_free(rp->req.psm_state_req.psr_state,
611		    rp->req.psm_state_req.psr_state_size);
612		return (0);
613	case PSM_STATE_SAVE:
614		pic_save_state(rp->req.psm_state_req.psr_state);
615		return (0);
616	case PSM_STATE_RESTORE:
617		pic_restore_state(rp->req.psm_state_req.psr_state);
618		return (0);
619	default:
620		return (EINVAL);
621	}
622}
623
624
625static int
626uppc_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
627    int ipin, int *pci_irqp, iflag_t *intr_flagp)
628{
629	int status;
630	acpi_psm_lnk_t acpipsmlnk;
631
632	if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
633	    intr_flagp)) == ACPI_PSM_SUCCESS) {
634		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Found irqno %d "
635		    "from cache for device %s, instance #%d\n", *pci_irqp,
636		    ddi_get_name(dip), ddi_get_instance(dip)));
637		return (status);
638	}
639
640	bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
641
642	if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp,
643	    intr_flagp, &acpipsmlnk)) == ACPI_PSM_FAILURE) {
644		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: "
645		    " acpi_translate_pci_irq failed for device %s, instance"
646		    " #%d\n", ddi_get_name(dip), ddi_get_instance(dip)));
647
648		return (status);
649	}
650
651	if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
652		status = uppc_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
653		    intr_flagp);
654		if (status != ACPI_PSM_SUCCESS) {
655			status = acpi_get_current_irq_resource(&acpipsmlnk,
656			    pci_irqp, intr_flagp);
657		}
658	}
659
660	if (status == ACPI_PSM_SUCCESS) {
661		acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
662		    intr_flagp, &acpipsmlnk);
663		psm_set_elcr(*pci_irqp, 1);	/* set IRQ to PCI mode */
664
665		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] "
666		    "new irq %d for device %s, instance #%d\n",
667		    *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
668	}
669
670	return (status);
671}
672
673/*
674 * Configures the irq for the interrupt link device identified by
675 * acpipsmlnkp.
676 *
677 * Gets the current and the list of possible irq settings for the
678 * device. If uppc_unconditional_srs is not set, and the current
679 * resource setting is in the list of possible irq settings,
680 * current irq resource setting is passed to the caller.
681 *
682 * Otherwise, picks an irq number from the list of possible irq
683 * settings, and sets the irq of the device to this value.
684 * If prefer_crs is set, among a set of irq numbers in the list that have
685 * the least number of devices sharing the interrupt, we pick current irq
686 * resource setting if it is a member of this set.
687 *
688 * Passes the irq number in the value pointed to by pci_irqp, and
689 * polarity and sensitivity in the structure pointed to by dipintrflagp
690 * to the caller.
691 *
692 * Note that if setting the irq resource failed, but successfuly obtained
693 * the current irq resource settings, passes the current irq resources
694 * and considers it a success.
695 *
696 * Returns:
697 * ACPI_PSM_SUCCESS on success.
698 *
699 * ACPI_PSM_FAILURE if an error occured during the configuration or
700 * if a suitable irq was not found for this device, or if setting the
701 * irq resource and obtaining the current resource fails.
702 *
703 */
704static int
705uppc_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
706    int *pci_irqp, iflag_t *dipintr_flagp)
707{
708	int i, min_share, foundnow, done = 0;
709	int32_t irq;
710	int32_t share_irq = -1;
711	int32_t chosen_irq = -1;
712	int cur_irq = -1;
713	acpi_irqlist_t *irqlistp;
714	acpi_irqlist_t *irqlistent;
715
716	if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
717	    == ACPI_PSM_FAILURE) {
718		UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Unable to determine "
719		    "or assign IRQ for device %s, instance #%d: The system was "
720		    "unable to get the list of potential IRQs from ACPI.",
721		    ddi_get_name(dip), ddi_get_instance(dip)));
722
723		return (ACPI_PSM_FAILURE);
724	}
725
726	if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
727	    dipintr_flagp) == ACPI_PSM_SUCCESS) && (!uppc_unconditional_srs) &&
728	    (cur_irq > 0)) {
729
730		if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
731		    == ACPI_PSM_SUCCESS) {
732
733			acpi_free_irqlist(irqlistp);
734			ASSERT(pci_irqp != NULL);
735			*pci_irqp = cur_irq;
736			return (ACPI_PSM_SUCCESS);
737		}
738		UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: Could not find the "
739		    "current irq %d for device %s, instance #%d in ACPI's "
740		    "list of possible irqs for this device. Picking one from "
741		    " the latter list.", cur_irq, ddi_get_name(dip),
742		    ddi_get_instance(dip)));
743
744	}
745
746	irqlistent = irqlistp;
747	min_share = 255;
748
749	while (irqlistent != NULL) {
750
751		for (foundnow = 0, i = 0; i < irqlistent->num_irqs; i++) {
752
753			irq = irqlistp->irqs[i];
754
755			if ((irq > MAX_ISA_IRQ) ||
756			    (irqlistent->intr_flags.intr_el == INTR_EL_EDGE) ||
757			    (irq == 0))
758				continue;
759
760			if (uppc_reserved_irqlist[irq])
761				continue;
762
763			if (uppc_irq_shared_table[irq] == 0) {
764				chosen_irq = irq;
765				foundnow = 1;
766				if (!(uppc_prefer_crs) || (irq == cur_irq)) {
767					done = 1;
768					break;
769				}
770			}
771
772			if ((uppc_irq_shared_table[irq] < min_share) ||
773			    ((uppc_irq_shared_table[irq] == min_share) &&
774			    (cur_irq == irq) && (uppc_prefer_crs))) {
775				min_share = uppc_irq_shared_table[irq];
776				share_irq = irq;
777				foundnow = 1;
778			}
779		}
780
781		/* If we found an IRQ in the inner loop, save the details */
782		if (foundnow && ((chosen_irq != -1) || (share_irq != -1))) {
783			/*
784			 * Copy the acpi_prs_private_t and flags from this
785			 * irq list entry, since we found an irq from this
786			 * entry.
787			 */
788			acpipsmlnkp->acpi_prs_prv = irqlistent->acpi_prs_prv;
789			*dipintr_flagp = irqlistent->intr_flags;
790		}
791
792		if (done)
793			break;
794
795		/* Load the next entry in the irqlist */
796		irqlistent = irqlistent->next;
797	}
798
799	acpi_free_irqlist(irqlistp);
800
801	if (chosen_irq != -1)
802		irq = chosen_irq;
803	else if (share_irq != -1)
804		irq = share_irq;
805	else {
806		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Could not find a "
807		    "suitable irq from the list of possible irqs for device "
808		    "%s, instance #%d in ACPI's list of possible\n",
809		    ddi_get_name(dip), ddi_get_instance(dip)));
810
811		return (ACPI_PSM_FAILURE);
812	}
813
814
815	UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: Setting irq %d for device %s "
816	    "instance #%d\n", irq, ddi_get_name(dip), ddi_get_instance(dip)));
817
818	if ((acpi_set_irq_resource(acpipsmlnkp, irq)) == ACPI_PSM_SUCCESS) {
819		/*
820		 * setting irq was successful, check to make sure CRS
821		 * reflects that. If CRS does not agree with what we
822		 * set, return the irq that was set.
823		 */
824
825		if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
826		    dipintr_flagp) == ACPI_PSM_SUCCESS) {
827
828			if (cur_irq != irq)
829				UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: "
830				    "IRQ resource set (irqno %d) for device %s "
831				    "instance #%d, differs from current "
832				    "setting irqno %d",
833				    irq, ddi_get_name(dip),
834				    ddi_get_instance(dip), cur_irq));
835		}
836		/*
837		 * return the irq that was set, and not what CRS reports,
838		 * since CRS has been seen to be bogus on some systems
839		 */
840		cur_irq = irq;
841	} else {
842		UPPC_VERBOSE_IRQ((CE_WARN, "!uppc: set resource irq %d "
843		    "failed for device %s instance #%d",
844		    irq, ddi_get_name(dip), ddi_get_instance(dip)));
845		if (cur_irq == -1)
846			return (ACPI_PSM_FAILURE);
847	}
848
849	ASSERT(pci_irqp != NULL);
850	*pci_irqp = cur_irq;
851	return (ACPI_PSM_SUCCESS);
852}
853
854
855/*ARGSUSED*/
856static int
857uppc_translate_irq(dev_info_t *dip, int irqno)
858{
859	char dev_type[16];
860	int dev_len, pci_irq, devid, busid;
861	ddi_acc_handle_t cfg_handle;
862	uchar_t ipin, iline;
863	iflag_t intr_flag;
864
865	if (dip == NULL) {
866		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno = %d"
867		    " dip = NULL\n", irqno));
868		return (irqno);
869	}
870
871	if (!uppc_enable_acpi) {
872		return (irqno);
873	}
874
875	dev_len = sizeof (dev_type);
876	if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
877	    DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
878	    &dev_len) != DDI_PROP_SUCCESS) {
879		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: irqno %d"
880		    "device %s instance %d no device_type\n", irqno,
881		    ddi_get_name(dip), ddi_get_instance(dip)));
882		return (irqno);
883	}
884
885	if ((strcmp(dev_type, "pci") == 0) ||
886	    (strcmp(dev_type, "pciex") == 0)) {
887
888		/* pci device */
889		if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
890			return (irqno);
891
892		if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
893			return (irqno);
894
895		ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
896		iline = pci_config_get8(cfg_handle, PCI_CONF_ILINE);
897		if (uppc_acpi_translate_pci_irq(dip, busid, devid,
898		    ipin, &pci_irq, &intr_flag) == ACPI_PSM_SUCCESS) {
899
900			UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: [ACPI] new irq "
901			    "%d old irq %d device %s, instance %d\n", pci_irq,
902			    irqno, ddi_get_name(dip), ddi_get_instance(dip)));
903
904			/*
905			 * Make sure pci_irq is within range.
906			 * Otherwise, fall through and return irqno.
907			 */
908			if (pci_irq <= MAX_ISA_IRQ) {
909				if (iline != pci_irq) {
910					/*
911					 * Update the device's ILINE byte,
912					 * in case uppc_acpi_translate_pci_irq
913					 * has choosen a different pci_irq
914					 * than the BIOS has configured.
915					 * Some chipsets use the value in
916					 * ILINE to control interrupt routing,
917					 * in conflict with the PCI spec.
918					 */
919					pci_config_put8(cfg_handle,
920					    PCI_CONF_ILINE, pci_irq);
921				}
922				pci_config_teardown(&cfg_handle);
923				return (pci_irq);
924			}
925		}
926		pci_config_teardown(&cfg_handle);
927
928		/* FALLTHRU to common case - returning irqno */
929	} else {
930		/* non-PCI; assumes ISA-style edge-triggered */
931		psm_set_elcr(irqno, 0);		/* set IRQ to ISA mode */
932
933		UPPC_VERBOSE_IRQ((CE_CONT, "!uppc: non-pci,"
934		    "irqno %d device %s instance %d\n", irqno,
935		    ddi_get_name(dip), ddi_get_instance(dip)));
936	}
937
938	return (irqno);
939}
940
941/*
942 * uppc_intr_enter() raises the ipl to the level of the current interrupt,
943 * and sends EOI to the pics.
944 * If interrupt is 7 or 15 and not spurious interrupt, send specific EOI
945 * else send non-specific EOI
946 * uppc_intr_enter() returns the new priority level,
947 * or -1 for spurious interrupt
948 */
949static int
950uppc_intr_enter(int ipl, int *vector)
951{
952	int newipl;
953	int intno;
954
955	intno = (*vector);
956
957	ASSERT(intno < 256);
958
959	newipl = autovect[intno].avh_hi_pri;
960
961	/*
962	 * During wait_till_seen() periods when interrupt vector is being
963	 * removed in remove_av(), the removed hardware interrupt could
964	 * trigger and got here with newipl 0.  It has to send EOI
965	 * as usual but no need to call setspl and returns -1 like spurious.
966	 */
967	if ((intno & 7) != 7) {
968		if (newipl)
969			uppc_setspl(newipl);
970		outb(MCMD_PORT, PIC_NSEOI);
971		if (intno >= 8) {
972			outb(SCMD_PORT, PIC_NSEOI);
973		}
974	} else { /* int was 7 or 15 */
975		if (newipl && newipl <= ipl) { /* Check for spurious int */
976			if (intno != 7)
977				outb(MCMD_PORT, PIC_NSEOI);
978			return (-1); /* Spurious int */
979		} else {
980			if (newipl)
981				uppc_setspl(newipl);
982			if (intno != 7) {
983				outb(MCMD_PORT, PIC_NSEOI);
984				outb(SCMD_PORT, PIC_SEOI_LVL7);
985			} else  {
986				outb(MCMD_PORT, PIC_SEOI_LVL7);
987			}
988		}
989	}
990
991	if (newipl)
992		return (newipl);
993	else
994		return (-1); /* not real spurious int */
995}
996
997/*
998 * uppc_intr_exit() restores the old interrupt
999 * priority level after processing an interrupt.
1000 * It is called with interrupts disabled, and does not enable interrupts.
1001 */
1002/* ARGSUSED */
1003static void
1004uppc_intr_exit(int ipl, int vector)
1005{
1006	uppc_setspl(ipl);
1007}
1008
1009/*
1010 * uppc_setspl() loads new interrupt masks into the pics
1011 * based on input ipl.
1012 */
1013/* ARGSUSED */
1014static void
1015uppc_setspl(int ipl)
1016{
1017	struct standard_pic *pp;
1018	uint8_t smask, mmask;
1019	uint8_t cursmask, curmmask;
1020
1021	pp = &pics0;
1022	smask = pp->c_iplmask[ipl * 2];
1023	mmask = pp->c_iplmask[ipl * 2 + 1];
1024	cursmask = pp->c_curmask[0];
1025	curmmask = pp->c_curmask[1];
1026	if (cursmask == smask && curmmask == mmask)
1027		return;
1028	pp->c_curmask[0] = smask;
1029	pp->c_curmask[1] = mmask;
1030
1031	if (cursmask != smask) {
1032		/*
1033		 * program new slave pic mask
1034		 */
1035		outb(SIMR_PORT, smask);
1036	}
1037	if (curmmask != mmask) {
1038		/*
1039		 * program new master pic mask
1040		 */
1041		outb(MIMR_PORT, mmask);
1042	}
1043	/*
1044	 * read master to allow pics to settle
1045	 */
1046	(void) inb(MIMR_PORT);
1047}
1048
1049/*
1050 * uppc_gethrtime() returns high resolution timer value
1051 */
1052static hrtime_t
1053uppc_gethrtime()
1054{
1055	hrtime_t timeval, temp;
1056	unsigned int ctr0;
1057	ulong_t oflags;
1058
1059	oflags = intr_clear(); /* disable ints */
1060	lock_set(&uppc_gethrtime_lock);
1061retry:
1062	temp = hrtime_base;
1063	outb(PITCTL_PORT, 0);	/* latch counter 0 */
1064	/*
1065	 * read counter 0
1066	 */
1067	ctr0 = inb(PITCTR0_PORT);
1068	ctr0 |= inb(PITCTR0_PORT) << 8;
1069	timeval = (hrtime_t)ctr0 * (NANOSEC / PIT_HZ);
1070	if (temp != hrtime_base)
1071		goto retry;
1072	timeval -= temp;
1073	if (timeval < uppc_lasthrtime)
1074		timeval = uppc_lasthrtime;
1075	uppc_lasthrtime = timeval;
1076	lock_clear(&uppc_gethrtime_lock);
1077	intr_restore(oflags);
1078	return (timeval);
1079}
1080