17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate * CDDL HEADER START
37c478bd9Sstevel@tonic-gate *
47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
56f796756Sdmick * Common Development and Distribution License (the "License").
66f796756Sdmick * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate *
87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate * and limitations under the License.
127c478bd9Sstevel@tonic-gate *
137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate *
197c478bd9Sstevel@tonic-gate * CDDL HEADER END
207c478bd9Sstevel@tonic-gate */
21ae115bc7Smrj
227c478bd9Sstevel@tonic-gate /*
23e7c3cdaeSjiang.liu@intel.com * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
247c478bd9Sstevel@tonic-gate */
25a3114836SGerry Liu /*
26a3114836SGerry Liu * Copyright (c) 2010, Intel Corporation.
27a3114836SGerry Liu * All rights reserved.
28c3377ee9SJohn Levon * Copyright 2019 Joyent, Inc.
29*fdcca78fSJoshua M. Clulow * Copyright 2020 Oxide Computer Company
30a288e5a9SJoshua M. Clulow */
317c478bd9Sstevel@tonic-gate
32636dfb4bSJerry Jelinek /*
33636dfb4bSJerry Jelinek * To understand how the pcplusmp module interacts with the interrupt subsystem
34636dfb4bSJerry Jelinek * read the theory statement in uts/i86pc/os/intr.c.
35636dfb4bSJerry Jelinek */
367ff178cdSJimmy Vetayases
377c478bd9Sstevel@tonic-gate /*
387c478bd9Sstevel@tonic-gate * PSMI 1.1 extensions are supported only in 2.6 and later versions.
397c478bd9Sstevel@tonic-gate * PSMI 1.2 extensions are supported only in 2.7 and later versions.
407c478bd9Sstevel@tonic-gate * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
417c478bd9Sstevel@tonic-gate * PSMI 1.5 extensions are supported in Solaris Nevada.
422df1fe9cSrandyf * PSMI 1.6 extensions are supported in Solaris Nevada.
43a3114836SGerry Liu * PSMI 1.7 extensions are supported in Solaris Nevada.
447c478bd9Sstevel@tonic-gate */
45a3114836SGerry Liu #define PSMI_1_7
467c478bd9Sstevel@tonic-gate
477c478bd9Sstevel@tonic-gate #include <sys/processor.h>
487c478bd9Sstevel@tonic-gate #include <sys/time.h>
497c478bd9Sstevel@tonic-gate #include <sys/psm.h>
507c478bd9Sstevel@tonic-gate #include <sys/smp_impldefs.h>
517c478bd9Sstevel@tonic-gate #include <sys/cram.h>
527c478bd9Sstevel@tonic-gate #include <sys/acpi/acpi.h>
537c478bd9Sstevel@tonic-gate #include <sys/acpica.h>
547c478bd9Sstevel@tonic-gate #include <sys/psm_common.h>
55ae115bc7Smrj #include <sys/apic.h>
567c478bd9Sstevel@tonic-gate #include <sys/pit.h>
577c478bd9Sstevel@tonic-gate #include <sys/ddi.h>
587c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
597c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
607c478bd9Sstevel@tonic-gate #include <sys/pci.h>
617c478bd9Sstevel@tonic-gate #include <sys/promif.h>
62*fdcca78fSJoshua M. Clulow #include <sys/prom_debug.h>
637c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h>
647c478bd9Sstevel@tonic-gate #include <sys/cpc_impl.h>
657c478bd9Sstevel@tonic-gate #include <sys/uadmin.h>
667c478bd9Sstevel@tonic-gate #include <sys/panic.h>
677c478bd9Sstevel@tonic-gate #include <sys/debug.h>
687c478bd9Sstevel@tonic-gate #include <sys/archsystm.h>
697c478bd9Sstevel@tonic-gate #include <sys/trap.h>
707c478bd9Sstevel@tonic-gate #include <sys/machsystm.h>
71ae115bc7Smrj #include <sys/sysmacros.h>
727c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h>
737c478bd9Sstevel@tonic-gate #include <sys/rm_platter.h>
747c478bd9Sstevel@tonic-gate #include <sys/privregs.h>
757c478bd9Sstevel@tonic-gate #include <sys/note.h>
767c478bd9Sstevel@tonic-gate #include <sys/pci_intr_lib.h>
77ae115bc7Smrj #include <sys/spl.h>
78843e1988Sjohnlev #include <sys/clock.h>
79a288e5a9SJoshua M. Clulow #include <sys/cyclic.h>
80dd4eeefdSeota #include <sys/dditypes.h>
81dd4eeefdSeota #include <sys/sunddi.h>
82e3d60c9bSAdrian Frost #include <sys/x_call.h>
83325e77f4SSaurabh Misra #include <sys/reboot.h>
840e751525SEric Saxe #include <sys/hpet.h>
857ff178cdSJimmy Vetayases #include <sys/apic_common.h>
8641afdfa7SKrishnendu Sadhukhan - Sun Microsystems #include <sys/apic_timer.h>
87c3377ee9SJohn Levon #include <sys/smt.h>
887c478bd9Sstevel@tonic-gate
897c478bd9Sstevel@tonic-gate /*
907c478bd9Sstevel@tonic-gate * Local Function Prototypes
917c478bd9Sstevel@tonic-gate */
927ff178cdSJimmy Vetayases static void apic_init_intr(void);
937c478bd9Sstevel@tonic-gate
947c478bd9Sstevel@tonic-gate /*
957c478bd9Sstevel@tonic-gate * standard MP entries
967c478bd9Sstevel@tonic-gate */
977ff178cdSJimmy Vetayases static int apic_probe(void);
987c478bd9Sstevel@tonic-gate static int apic_getclkirq(int ipl);
997ff178cdSJimmy Vetayases static void apic_init(void);
1007c478bd9Sstevel@tonic-gate static void apic_picinit(void);
1017c478bd9Sstevel@tonic-gate static int apic_post_cpu_start(void);
1027c478bd9Sstevel@tonic-gate static int apic_intr_enter(int ipl, int *vect);
1037c478bd9Sstevel@tonic-gate static void apic_setspl(int ipl);
1047c478bd9Sstevel@tonic-gate static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
1057c478bd9Sstevel@tonic-gate static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
1067c478bd9Sstevel@tonic-gate static int apic_disable_intr(processorid_t cpun);
1077c478bd9Sstevel@tonic-gate static void apic_enable_intr(processorid_t cpun);
1087c478bd9Sstevel@tonic-gate static int apic_get_ipivect(int ipl, int type);
1097c478bd9Sstevel@tonic-gate static void apic_post_cyclic_setup(void *arg);
110a3114836SGerry Liu
11130acb30dSHans Rosenfeld #define UCHAR_MAX UINT8_MAX
11230acb30dSHans Rosenfeld
1137c478bd9Sstevel@tonic-gate /*
1147c478bd9Sstevel@tonic-gate * The following vector assignments influence the value of ipltopri and
1157c478bd9Sstevel@tonic-gate * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
116c8589f13Ssethg * idle to 0 and IPL 0 to 0xf to differentiate idle in case
1177c478bd9Sstevel@tonic-gate * we care to do so in future. Note some IPLs which are rarely used
1187c478bd9Sstevel@tonic-gate * will share the vector ranges and heavily used IPLs (5 and 6) have
1197c478bd9Sstevel@tonic-gate * a wide range.
120c8589f13Ssethg *
121c8589f13Ssethg * This array is used to initialize apic_ipls[] (in apic_init()).
122c8589f13Ssethg *
1237c478bd9Sstevel@tonic-gate * IPL Vector range. as passed to intr_enter
1247c478bd9Sstevel@tonic-gate * 0 none.
1257c478bd9Sstevel@tonic-gate * 1,2,3 0x20-0x2f 0x0-0xf
1267c478bd9Sstevel@tonic-gate * 4 0x30-0x3f 0x10-0x1f
1277c478bd9Sstevel@tonic-gate * 5 0x40-0x5f 0x20-0x3f
1287c478bd9Sstevel@tonic-gate * 6 0x60-0x7f 0x40-0x5f
1297c478bd9Sstevel@tonic-gate * 7,8,9 0x80-0x8f 0x60-0x6f
1307c478bd9Sstevel@tonic-gate * 10 0x90-0x9f 0x70-0x7f
1317c478bd9Sstevel@tonic-gate * 11 0xa0-0xaf 0x80-0x8f
1327c478bd9Sstevel@tonic-gate * ... ...
133c8589f13Ssethg * 15 0xe0-0xef 0xc0-0xcf
134c8589f13Ssethg * 15 0xf0-0xff 0xd0-0xdf
1357c478bd9Sstevel@tonic-gate */
1367c478bd9Sstevel@tonic-gate uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
137c8589f13Ssethg 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
1387c478bd9Sstevel@tonic-gate };
1397c478bd9Sstevel@tonic-gate /*
140c8589f13Ssethg * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
1417c478bd9Sstevel@tonic-gate * NOTE that this is vector as passed into intr_enter which is
1427c478bd9Sstevel@tonic-gate * programmed vector - 0x20 (APIC_BASE_VECT)
1437c478bd9Sstevel@tonic-gate */
1447c478bd9Sstevel@tonic-gate
1457c478bd9Sstevel@tonic-gate uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
1467c478bd9Sstevel@tonic-gate /* The taskpri to be programmed into apic to mask given ipl */
1477c478bd9Sstevel@tonic-gate
148c8589f13Ssethg /*
149c8589f13Ssethg * Correlation of the hardware vector to the IPL in use, initialized
150c8589f13Ssethg * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
151c8589f13Ssethg * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
152c8589f13Ssethg * connected to errata-stricken IOAPICs
153c8589f13Ssethg */
154c8589f13Ssethg uchar_t apic_ipls[APIC_AVAIL_VECTOR];
155c8589f13Ssethg
1567c478bd9Sstevel@tonic-gate /*
1577c478bd9Sstevel@tonic-gate * Patchable global variables.
1587c478bd9Sstevel@tonic-gate */
1597c478bd9Sstevel@tonic-gate int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
1607c478bd9Sstevel@tonic-gate int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
161a3114836SGerry Liu
1627c478bd9Sstevel@tonic-gate /*
1637c478bd9Sstevel@tonic-gate * Local static data
1647c478bd9Sstevel@tonic-gate */
1657c478bd9Sstevel@tonic-gate static struct psm_ops apic_ops = {
1667c478bd9Sstevel@tonic-gate apic_probe,
1677c478bd9Sstevel@tonic-gate
1687c478bd9Sstevel@tonic-gate apic_init,
1697c478bd9Sstevel@tonic-gate apic_picinit,
1707c478bd9Sstevel@tonic-gate apic_intr_enter,
1717c478bd9Sstevel@tonic-gate apic_intr_exit,
1727c478bd9Sstevel@tonic-gate apic_setspl,
1737c478bd9Sstevel@tonic-gate apic_addspl,
1747c478bd9Sstevel@tonic-gate apic_delspl,
1757c478bd9Sstevel@tonic-gate apic_disable_intr,
1767c478bd9Sstevel@tonic-gate apic_enable_intr,
177a1af7ba0Scwb (int (*)(int))NULL, /* psm_softlvl_to_irq */
178a1af7ba0Scwb (void (*)(int))NULL, /* psm_set_softintr */
1797c478bd9Sstevel@tonic-gate
1807c478bd9Sstevel@tonic-gate apic_set_idlecpu,
1817c478bd9Sstevel@tonic-gate apic_unset_idlecpu,
1827c478bd9Sstevel@tonic-gate
1837c478bd9Sstevel@tonic-gate apic_clkinit,
1847c478bd9Sstevel@tonic-gate apic_getclkirq,
1857c478bd9Sstevel@tonic-gate (void (*)(void))NULL, /* psm_hrtimeinit */
1867c478bd9Sstevel@tonic-gate apic_gethrtime,
1877c478bd9Sstevel@tonic-gate
1887c478bd9Sstevel@tonic-gate apic_get_next_processorid,
1897c478bd9Sstevel@tonic-gate apic_cpu_start,
1907c478bd9Sstevel@tonic-gate apic_post_cpu_start,
1917c478bd9Sstevel@tonic-gate apic_shutdown,
1927c478bd9Sstevel@tonic-gate apic_get_ipivect,
1937c478bd9Sstevel@tonic-gate apic_send_ipi,
1947c478bd9Sstevel@tonic-gate
1957c478bd9Sstevel@tonic-gate (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
1967c478bd9Sstevel@tonic-gate (void (*)(int, char *))NULL, /* psm_notify_error */
1977c478bd9Sstevel@tonic-gate (void (*)(int))NULL, /* psm_notify_func */
1987c478bd9Sstevel@tonic-gate apic_timer_reprogram,
1997c478bd9Sstevel@tonic-gate apic_timer_enable,
2007c478bd9Sstevel@tonic-gate apic_timer_disable,
2017c478bd9Sstevel@tonic-gate apic_post_cyclic_setup,
2027c478bd9Sstevel@tonic-gate apic_preshutdown,
2032df1fe9cSrandyf apic_intr_ops, /* Advanced DDI Interrupt framework */
2042df1fe9cSrandyf apic_state, /* save, restore apic state for S3 */
205a3114836SGerry Liu apic_cpu_ops, /* CPU control interface. */
2061c2d0470SPatrick Mooney
2071c2d0470SPatrick Mooney apic_get_pir_ipivect,
2081c2d0470SPatrick Mooney apic_send_pir_ipi,
209918e0d92SRobert Mustacchi apic_cmci_setup,
2107c478bd9Sstevel@tonic-gate };
2117c478bd9Sstevel@tonic-gate
2127ff178cdSJimmy Vetayases struct psm_ops *psmops = &apic_ops;
2137c478bd9Sstevel@tonic-gate
2147c478bd9Sstevel@tonic-gate static struct psm_info apic_psm_info = {
215a3114836SGerry Liu PSM_INFO_VER01_7, /* version */
2167c478bd9Sstevel@tonic-gate PSM_OWN_EXCLUSIVE, /* ownership */
2177c478bd9Sstevel@tonic-gate (struct psm_ops *)&apic_ops, /* operation */
2182917a9c9Sschwartz APIC_PCPLUSMP_NAME, /* machine name */
219da2743adSdmick "pcplusmp v1.4 compatible",
2207c478bd9Sstevel@tonic-gate };
2217c478bd9Sstevel@tonic-gate
2227c478bd9Sstevel@tonic-gate static void *apic_hdlp;
2237c478bd9Sstevel@tonic-gate
2247c478bd9Sstevel@tonic-gate /* to gather intr data and redistribute */
2257c478bd9Sstevel@tonic-gate static void apic_redistribute_compute(void);
2267c478bd9Sstevel@tonic-gate
2277c478bd9Sstevel@tonic-gate /*
2287c478bd9Sstevel@tonic-gate * This is the loadable module wrapper
2297c478bd9Sstevel@tonic-gate */
2307c478bd9Sstevel@tonic-gate
2317c478bd9Sstevel@tonic-gate int
_init(void)2327c478bd9Sstevel@tonic-gate _init(void)
2337c478bd9Sstevel@tonic-gate {
2347c478bd9Sstevel@tonic-gate if (apic_coarse_hrtime)
2357c478bd9Sstevel@tonic-gate apic_ops.psm_gethrtime = &apic_gettime;
2367c478bd9Sstevel@tonic-gate return (psm_mod_init(&apic_hdlp, &apic_psm_info));
2377c478bd9Sstevel@tonic-gate }
2387c478bd9Sstevel@tonic-gate
2397c478bd9Sstevel@tonic-gate int
_fini(void)2407c478bd9Sstevel@tonic-gate _fini(void)
2417c478bd9Sstevel@tonic-gate {
2427c478bd9Sstevel@tonic-gate return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
2437c478bd9Sstevel@tonic-gate }
2447c478bd9Sstevel@tonic-gate
2457c478bd9Sstevel@tonic-gate int
_info(struct modinfo * modinfop)2467c478bd9Sstevel@tonic-gate _info(struct modinfo *modinfop)
2477c478bd9Sstevel@tonic-gate {
2487c478bd9Sstevel@tonic-gate return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
2497c478bd9Sstevel@tonic-gate }
2507c478bd9Sstevel@tonic-gate
2517c478bd9Sstevel@tonic-gate static int
apic_probe(void)2527ff178cdSJimmy Vetayases apic_probe(void)
2537c478bd9Sstevel@tonic-gate {
254*fdcca78fSJoshua M. Clulow PRM_POINT("apic_probe()");
255*fdcca78fSJoshua M. Clulow
2567ff178cdSJimmy Vetayases /* check if apix is initialized */
257*fdcca78fSJoshua M. Clulow if (apix_enable && apix_loaded()) {
258*fdcca78fSJoshua M. Clulow PRM_POINT("apic_probe FAILURE: apix is loaded");
2597ff178cdSJimmy Vetayases return (PSM_FAILURE);
260*fdcca78fSJoshua M. Clulow }
261a51869cdSHans Rosenfeld
262a51869cdSHans Rosenfeld /*
263a51869cdSHans Rosenfeld * Check whether x2APIC mode was activated by BIOS. We don't support
264a51869cdSHans Rosenfeld * that in pcplusmp as apix normally handles that.
265a51869cdSHans Rosenfeld */
266*fdcca78fSJoshua M. Clulow PRM_POINT("apic_local_mode()");
267*fdcca78fSJoshua M. Clulow if (apic_local_mode() == LOCAL_X2APIC) {
268*fdcca78fSJoshua M. Clulow PRM_POINT("apic_probe FAILURE: in x2apic mode");
269a51869cdSHans Rosenfeld return (PSM_FAILURE);
270*fdcca78fSJoshua M. Clulow }
271a51869cdSHans Rosenfeld
272a51869cdSHans Rosenfeld /* continue using pcplusmp PSM */
273a51869cdSHans Rosenfeld apix_enable = 0;
2747ff178cdSJimmy Vetayases
275ae115bc7Smrj return (apic_probe_common(apic_psm_info.p_mach_idstring));
2767c478bd9Sstevel@tonic-gate }
2777c478bd9Sstevel@tonic-gate
2787ff178cdSJimmy Vetayases static uchar_t
apic_xlate_vector_by_irq(uchar_t irq)2797ff178cdSJimmy Vetayases apic_xlate_vector_by_irq(uchar_t irq)
2807ff178cdSJimmy Vetayases {
2817ff178cdSJimmy Vetayases if (apic_irq_table[irq] == NULL)
2827ff178cdSJimmy Vetayases return (0);
2837ff178cdSJimmy Vetayases
2847ff178cdSJimmy Vetayases return (apic_irq_table[irq]->airq_vector);
2857ff178cdSJimmy Vetayases }
2867ff178cdSJimmy Vetayases
287ae115bc7Smrj void
apic_init(void)2887ff178cdSJimmy Vetayases apic_init(void)
2897c478bd9Sstevel@tonic-gate {
290ae115bc7Smrj int i;
291ae115bc7Smrj int j = 1;
2927c478bd9Sstevel@tonic-gate
2937ff178cdSJimmy Vetayases psm_get_ioapicid = apic_get_ioapicid;
2947ff178cdSJimmy Vetayases psm_get_localapicid = apic_get_localapicid;
2957ff178cdSJimmy Vetayases psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
2967ff178cdSJimmy Vetayases
297ae115bc7Smrj apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
298ae115bc7Smrj for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
299ae115bc7Smrj if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
300ae115bc7Smrj (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
301ae115bc7Smrj /* get to highest vector at the same ipl */
302ae115bc7Smrj continue;
303ae115bc7Smrj for (; j <= apic_vectortoipl[i]; j++) {
304ae115bc7Smrj apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
305ae115bc7Smrj APIC_BASE_VECT;
3067c478bd9Sstevel@tonic-gate }
3077c478bd9Sstevel@tonic-gate }
308ae115bc7Smrj for (; j < MAXIPL + 1; j++)
309ae115bc7Smrj /* fill up any empty ipltopri slots */
310ae115bc7Smrj apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
311ae115bc7Smrj apic_init_common();
31232842aabSJosef 'Jeff' Sipek
313455e370cSJohn Levon /*
314455e370cSJohn Levon * For pcplusmp, we'll keep things simple and always disable this.
315455e370cSJohn Levon */
316c3377ee9SJohn Levon smt_intr_alloc_pil(XC_CPUPOKE_PIL);
317455e370cSJohn Levon
3181c2d0470SPatrick Mooney apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1);
3191c2d0470SPatrick Mooney
3207c478bd9Sstevel@tonic-gate }
3217c478bd9Sstevel@tonic-gate
3227c478bd9Sstevel@tonic-gate static void
apic_init_intr(void)3237ff178cdSJimmy Vetayases apic_init_intr(void)
3247c478bd9Sstevel@tonic-gate {
3257c478bd9Sstevel@tonic-gate processorid_t cpun = psm_get_cpu_id();
326da2743adSdmick uint_t nlvt;
327b6917abeSmishra uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
3287c478bd9Sstevel@tonic-gate
329b6917abeSmishra apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
330b6917abeSmishra
331583cd330SHans Rosenfeld ASSERT(apic_mode == LOCAL_APIC);
332b6917abeSmishra
333583cd330SHans Rosenfeld /*
334583cd330SHans Rosenfeld * We are running APIC in MMIO mode.
335583cd330SHans Rosenfeld */
336583cd330SHans Rosenfeld if (apic_flat_model) {
337583cd330SHans Rosenfeld apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL);
338583cd330SHans Rosenfeld } else {
339583cd330SHans Rosenfeld apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL);
340b6917abeSmishra }
341b6917abeSmishra
342583cd330SHans Rosenfeld apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun);
343583cd330SHans Rosenfeld
344e511d54dSSaurabh Misra if (apic_directed_EOI_supported()) {
345b6917abeSmishra /*
346e511d54dSSaurabh Misra * Setting the 12th bit in the Spurious Interrupt Vector
347e511d54dSSaurabh Misra * Register suppresses broadcast EOIs generated by the local
348e511d54dSSaurabh Misra * APIC. The suppression of broadcast EOIs happens only when
349e511d54dSSaurabh Misra * interrupts are level-triggered.
350b6917abeSmishra */
351e511d54dSSaurabh Misra svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
352b6917abeSmishra }
3537c478bd9Sstevel@tonic-gate
3547c478bd9Sstevel@tonic-gate /* need to enable APIC before unmasking NMI */
355b6917abeSmishra apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
3567c478bd9Sstevel@tonic-gate
357da2743adSdmick /*
358da2743adSdmick * Presence of an invalid vector with delivery mode AV_FIXED can
359da2743adSdmick * cause an error interrupt, even if the entry is masked...so
360da2743adSdmick * write a valid vector to LVT entries along with the mask bit
361da2743adSdmick */
362da2743adSdmick
363da2743adSdmick /* All APICs have timer and LINT0/1 */
364b6917abeSmishra apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
365b6917abeSmishra apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
366b6917abeSmishra apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
3677c478bd9Sstevel@tonic-gate
368da2743adSdmick /*
369da2743adSdmick * On integrated APICs, the number of LVT entries is
370da2743adSdmick * 'Max LVT entry' + 1; on 82489DX's (non-integrated
371da2743adSdmick * APICs), nlvt is "3" (LINT0, LINT1, and timer)
372da2743adSdmick */
3737c478bd9Sstevel@tonic-gate
374da2743adSdmick if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
375da2743adSdmick nlvt = 3;
376da2743adSdmick } else {
377a898d95bSSaurabh Misra nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
378a898d95bSSaurabh Misra 0xFF) + 1;
379da2743adSdmick }
3807c478bd9Sstevel@tonic-gate
381da2743adSdmick if (nlvt >= 5) {
382da2743adSdmick /* Enable performance counter overflow interrupt */
383da2743adSdmick
3847417cfdeSKuriakose Kuruvilla if (!is_x86_feature(x86_featureset, X86FSET_MSR))
385da2743adSdmick apic_enable_cpcovf_intr = 0;
386da2743adSdmick if (apic_enable_cpcovf_intr) {
387da2743adSdmick if (apic_cpcovf_vect == 0) {
388da2743adSdmick int ipl = APIC_PCINT_IPL;
389da2743adSdmick int irq = apic_get_ipivect(ipl, -1);
390da2743adSdmick
391da2743adSdmick ASSERT(irq != -1);
392da2743adSdmick apic_cpcovf_vect =
393da2743adSdmick apic_irq_table[irq]->airq_vector;
394da2743adSdmick ASSERT(apic_cpcovf_vect);
395da2743adSdmick (void) add_avintr(NULL, ipl,
396da2743adSdmick (avfunc)kcpc_hw_overflow_intr,
397da2743adSdmick "apic pcint", irq, NULL, NULL, NULL, NULL);
398da2743adSdmick kcpc_hw_overflow_intr_installed = 1;
399da2743adSdmick kcpc_hw_enable_cpc_intr =
400da2743adSdmick apic_cpcovf_mask_clear;
401da2743adSdmick }
402b6917abeSmishra apic_reg_ops->apic_write(APIC_PCINT_VECT,
403b6917abeSmishra apic_cpcovf_vect);
404da2743adSdmick }
405da2743adSdmick }
4067c478bd9Sstevel@tonic-gate
407da2743adSdmick if (nlvt >= 6) {
408da2743adSdmick /* Only mask TM intr if the BIOS apparently doesn't use it */
409da2743adSdmick
410da2743adSdmick uint32_t lvtval;
411da2743adSdmick
412b6917abeSmishra lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
413da2743adSdmick if (((lvtval & AV_MASK) == AV_MASK) ||
414da2743adSdmick ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
415b6917abeSmishra apic_reg_ops->apic_write(APIC_THERM_VECT,
416b6917abeSmishra AV_MASK|APIC_RESV_IRQ);
4177c478bd9Sstevel@tonic-gate }
4187c478bd9Sstevel@tonic-gate }
4197c478bd9Sstevel@tonic-gate
4207c478bd9Sstevel@tonic-gate /* Enable error interrupt */
4217c478bd9Sstevel@tonic-gate
422da2743adSdmick if (nlvt >= 4 && apic_enable_error_intr) {
4237c478bd9Sstevel@tonic-gate if (apic_errvect == 0) {
4247c478bd9Sstevel@tonic-gate int ipl = 0xf; /* get highest priority intr */
4257c478bd9Sstevel@tonic-gate int irq = apic_get_ipivect(ipl, -1);
4267c478bd9Sstevel@tonic-gate
4277c478bd9Sstevel@tonic-gate ASSERT(irq != -1);
4287c478bd9Sstevel@tonic-gate apic_errvect = apic_irq_table[irq]->airq_vector;
4297c478bd9Sstevel@tonic-gate ASSERT(apic_errvect);
4307c478bd9Sstevel@tonic-gate /*
4317c478bd9Sstevel@tonic-gate * Not PSMI compliant, but we are going to merge
4327c478bd9Sstevel@tonic-gate * with ON anyway
4337c478bd9Sstevel@tonic-gate */
4347c478bd9Sstevel@tonic-gate (void) add_avintr((void *)NULL, ipl,
4357c478bd9Sstevel@tonic-gate (avfunc)apic_error_intr, "apic error intr",
4367a364d25Sschwartz irq, NULL, NULL, NULL, NULL);
4377c478bd9Sstevel@tonic-gate }
438b6917abeSmishra apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
439b6917abeSmishra apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
440b6917abeSmishra apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
4417c478bd9Sstevel@tonic-gate }
442da2743adSdmick
443918e0d92SRobert Mustacchi /*
444918e0d92SRobert Mustacchi * Ensure a CMCI interrupt is allocated, regardless of whether it is
445918e0d92SRobert Mustacchi * enabled or not.
446918e0d92SRobert Mustacchi */
447918e0d92SRobert Mustacchi if (apic_cmci_vect == 0) {
448918e0d92SRobert Mustacchi const int ipl = 0x2;
449918e0d92SRobert Mustacchi int irq = apic_get_ipivect(ipl, -1);
450e3d60c9bSAdrian Frost
451918e0d92SRobert Mustacchi ASSERT(irq != -1);
452918e0d92SRobert Mustacchi apic_cmci_vect = apic_irq_table[irq]->airq_vector;
453918e0d92SRobert Mustacchi ASSERT(apic_cmci_vect);
454e3d60c9bSAdrian Frost
455918e0d92SRobert Mustacchi (void) add_avintr(NULL, ipl,
456918e0d92SRobert Mustacchi (avfunc)cmi_cmci_trap,
457918e0d92SRobert Mustacchi "apic cmci intr", irq, NULL, NULL, NULL, NULL);
458e3d60c9bSAdrian Frost }
4597c478bd9Sstevel@tonic-gate }
4607c478bd9Sstevel@tonic-gate
4617c478bd9Sstevel@tonic-gate static void
apic_picinit(void)4627c478bd9Sstevel@tonic-gate apic_picinit(void)
4637c478bd9Sstevel@tonic-gate {
464ae115bc7Smrj int i, j;
4657c478bd9Sstevel@tonic-gate uint_t isr;
4667c478bd9Sstevel@tonic-gate
4671de082f7SVikram Hegde /*
468f7a1836aSSaurabh Misra * Initialize and enable interrupt remapping before apic
4691de082f7SVikram Hegde * hardware initialization
4701de082f7SVikram Hegde */
4713a634bfcSVikram Hegde apic_intrmap_init(apic_mode);
4721de082f7SVikram Hegde
4737c478bd9Sstevel@tonic-gate /*
4747c478bd9Sstevel@tonic-gate * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
4757c478bd9Sstevel@tonic-gate * bit on without clearing it with EOI. Since softint
4767c478bd9Sstevel@tonic-gate * uses vector 0x20 to interrupt itself, so softint will
4777c478bd9Sstevel@tonic-gate * not work on this machine. In order to fix this problem
4787c478bd9Sstevel@tonic-gate * a check is made to verify all the isr bits are clear.
4797c478bd9Sstevel@tonic-gate * If not, EOIs are issued to clear the bits.
4807c478bd9Sstevel@tonic-gate */
4817c478bd9Sstevel@tonic-gate for (i = 7; i >= 1; i--) {
482b6917abeSmishra isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
483b6917abeSmishra if (isr != 0)
4847c478bd9Sstevel@tonic-gate for (j = 0; ((j < 32) && (isr != 0)); j++)
4857c478bd9Sstevel@tonic-gate if (isr & (1 << j)) {
486b6917abeSmishra apic_reg_ops->apic_write(
487b6917abeSmishra APIC_EOI_REG, 0);
4887c478bd9Sstevel@tonic-gate isr &= ~(1 << j);
4897c478bd9Sstevel@tonic-gate apic_error |= APIC_ERR_BOOT_EOI;
4907c478bd9Sstevel@tonic-gate }
4917c478bd9Sstevel@tonic-gate }
4927c478bd9Sstevel@tonic-gate
4937c478bd9Sstevel@tonic-gate /* set a flag so we know we have run apic_picinit() */
494843e1988Sjohnlev apic_picinit_called = 1;
4957c478bd9Sstevel@tonic-gate LOCK_INIT_CLEAR(&apic_gethrtime_lock);
4967c478bd9Sstevel@tonic-gate LOCK_INIT_CLEAR(&apic_ioapic_lock);
4977c478bd9Sstevel@tonic-gate LOCK_INIT_CLEAR(&apic_error_lock);
498a3114836SGerry Liu LOCK_INIT_CLEAR(&apic_mode_switch_lock);
4997c478bd9Sstevel@tonic-gate
5007c478bd9Sstevel@tonic-gate picsetup(); /* initialise the 8259 */
5017c478bd9Sstevel@tonic-gate
5027c478bd9Sstevel@tonic-gate /* add nmi handler - least priority nmi handler */
5037c478bd9Sstevel@tonic-gate LOCK_INIT_CLEAR(&apic_nmi_lock);
5047c478bd9Sstevel@tonic-gate
5057c478bd9Sstevel@tonic-gate if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
5067c478bd9Sstevel@tonic-gate "pcplusmp NMI handler", (caddr_t)NULL))
5077c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
5087c478bd9Sstevel@tonic-gate
509f7a1836aSSaurabh Misra /*
510f7a1836aSSaurabh Misra * Check for directed-EOI capability in the local APIC.
511f7a1836aSSaurabh Misra */
512f7a1836aSSaurabh Misra if (apic_directed_EOI_supported() == 1) {
513f7a1836aSSaurabh Misra apic_set_directed_EOI_handler();
514f7a1836aSSaurabh Misra }
515f7a1836aSSaurabh Misra
5167c478bd9Sstevel@tonic-gate apic_init_intr();
5177c478bd9Sstevel@tonic-gate
5187c478bd9Sstevel@tonic-gate /* enable apic mode if imcr present */
5197c478bd9Sstevel@tonic-gate if (apic_imcrp) {
5207c478bd9Sstevel@tonic-gate outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
5217c478bd9Sstevel@tonic-gate outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
5227c478bd9Sstevel@tonic-gate }
5237c478bd9Sstevel@tonic-gate
524ae115bc7Smrj ioapic_init_intr(IOAPIC_MASK);
5257c478bd9Sstevel@tonic-gate }
5267c478bd9Sstevel@tonic-gate
5277c478bd9Sstevel@tonic-gate #ifdef DEBUG
5287c478bd9Sstevel@tonic-gate void
apic_break(void)5297ff178cdSJimmy Vetayases apic_break(void)
5307c478bd9Sstevel@tonic-gate {
5317c478bd9Sstevel@tonic-gate }
5327c478bd9Sstevel@tonic-gate #endif /* DEBUG */
5337c478bd9Sstevel@tonic-gate
5347c478bd9Sstevel@tonic-gate /*
5357c478bd9Sstevel@tonic-gate * platform_intr_enter
5367c478bd9Sstevel@tonic-gate *
5377c478bd9Sstevel@tonic-gate * Called at the beginning of the interrupt service routine to
5387c478bd9Sstevel@tonic-gate * mask all level equal to and below the interrupt priority
5397c478bd9Sstevel@tonic-gate * of the interrupting vector. An EOI should be given to
5407c478bd9Sstevel@tonic-gate * the interrupt controller to enable other HW interrupts.
5417c478bd9Sstevel@tonic-gate *
5427c478bd9Sstevel@tonic-gate * Return -1 for spurious interrupts
5437c478bd9Sstevel@tonic-gate *
5447c478bd9Sstevel@tonic-gate */
5457c478bd9Sstevel@tonic-gate /*ARGSUSED*/
5467c478bd9Sstevel@tonic-gate static int
apic_intr_enter(int ipl,int * vectorp)5477c478bd9Sstevel@tonic-gate apic_intr_enter(int ipl, int *vectorp)
5487c478bd9Sstevel@tonic-gate {
5497c478bd9Sstevel@tonic-gate uchar_t vector;
5507c478bd9Sstevel@tonic-gate int nipl;
551ae115bc7Smrj int irq;
552ae115bc7Smrj ulong_t iflag;
5537c478bd9Sstevel@tonic-gate apic_cpus_info_t *cpu_infop;
5547c478bd9Sstevel@tonic-gate
5557c478bd9Sstevel@tonic-gate /*
556c8589f13Ssethg * The real vector delivered is (*vectorp + 0x20), but our caller
557c8589f13Ssethg * subtracts 0x20 from the vector before passing it to us.
558c8589f13Ssethg * (That's why APIC_BASE_VECT is 0x20.)
5597c478bd9Sstevel@tonic-gate */
5607c478bd9Sstevel@tonic-gate vector = (uchar_t)*vectorp;
5617c478bd9Sstevel@tonic-gate
5627c478bd9Sstevel@tonic-gate /* if interrupted by the clock, increment apic_nsec_since_boot */
5637c478bd9Sstevel@tonic-gate if (vector == apic_clkvect) {
5647c478bd9Sstevel@tonic-gate if (!apic_oneshot) {
5657c478bd9Sstevel@tonic-gate /* NOTE: this is not MT aware */
5667c478bd9Sstevel@tonic-gate apic_hrtime_stamp++;
5677c478bd9Sstevel@tonic-gate apic_nsec_since_boot += apic_nsec_per_intr;
5687c478bd9Sstevel@tonic-gate apic_hrtime_stamp++;
5697c478bd9Sstevel@tonic-gate last_count_read = apic_hertz_count;
5707c478bd9Sstevel@tonic-gate apic_redistribute_compute();
5717c478bd9Sstevel@tonic-gate }
5727c478bd9Sstevel@tonic-gate
5737c478bd9Sstevel@tonic-gate /* We will avoid all the book keeping overhead for clock */
574c8589f13Ssethg nipl = apic_ipls[vector];
575c8589f13Ssethg
576b6917abeSmishra *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
57729ddbbefSJosef 'Jeff' Sipek
57829ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
57929ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_send_eoi(0);
580b6917abeSmishra
5817c478bd9Sstevel@tonic-gate return (nipl);
5827c478bd9Sstevel@tonic-gate }
5837c478bd9Sstevel@tonic-gate
5847c478bd9Sstevel@tonic-gate cpu_infop = &apic_cpus[psm_get_cpu_id()];
5857c478bd9Sstevel@tonic-gate
5867c478bd9Sstevel@tonic-gate if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
5877c478bd9Sstevel@tonic-gate cpu_infop->aci_spur_cnt++;
5887c478bd9Sstevel@tonic-gate return (APIC_INT_SPURIOUS);
5897c478bd9Sstevel@tonic-gate }
5907c478bd9Sstevel@tonic-gate
5917c478bd9Sstevel@tonic-gate /* Check if the vector we got is really what we need */
5927c478bd9Sstevel@tonic-gate if (apic_revector_pending) {
5937c478bd9Sstevel@tonic-gate /*
5947c478bd9Sstevel@tonic-gate * Disable interrupts for the duration of
5957c478bd9Sstevel@tonic-gate * the vector translation to prevent a self-race for
5967c478bd9Sstevel@tonic-gate * the apic_revector_lock. This cannot be done
5977c478bd9Sstevel@tonic-gate * in apic_xlate_vector because it is recursive and
5987c478bd9Sstevel@tonic-gate * we want the vector translation to be atomic with
5997c478bd9Sstevel@tonic-gate * respect to other (higher-priority) interrupts.
6007c478bd9Sstevel@tonic-gate */
6017c478bd9Sstevel@tonic-gate iflag = intr_clear();
6027c478bd9Sstevel@tonic-gate vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
6037c478bd9Sstevel@tonic-gate APIC_BASE_VECT;
6047c478bd9Sstevel@tonic-gate intr_restore(iflag);
6057c478bd9Sstevel@tonic-gate }
6067c478bd9Sstevel@tonic-gate
607c8589f13Ssethg nipl = apic_ipls[vector];
6087c478bd9Sstevel@tonic-gate *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
6097c478bd9Sstevel@tonic-gate
61029ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
6117c478bd9Sstevel@tonic-gate
6127c478bd9Sstevel@tonic-gate cpu_infop->aci_current[nipl] = (uchar_t)irq;
6137c478bd9Sstevel@tonic-gate cpu_infop->aci_curipl = (uchar_t)nipl;
6147c478bd9Sstevel@tonic-gate cpu_infop->aci_ISR_in_progress |= 1 << nipl;
6157c478bd9Sstevel@tonic-gate
6167c478bd9Sstevel@tonic-gate /*
6177c478bd9Sstevel@tonic-gate * apic_level_intr could have been assimilated into the irq struct.
6187c478bd9Sstevel@tonic-gate * but, having it as a character array is more efficient in terms of
6197c478bd9Sstevel@tonic-gate * cache usage. So, we leave it as is.
6207c478bd9Sstevel@tonic-gate */
621b6917abeSmishra if (!apic_level_intr[irq]) {
62229ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_send_eoi(0);
623b6917abeSmishra }
6247c478bd9Sstevel@tonic-gate
6257c478bd9Sstevel@tonic-gate #ifdef DEBUG
6267c478bd9Sstevel@tonic-gate APIC_DEBUG_BUF_PUT(vector);
6277c478bd9Sstevel@tonic-gate APIC_DEBUG_BUF_PUT(irq);
6287c478bd9Sstevel@tonic-gate APIC_DEBUG_BUF_PUT(nipl);
6297c478bd9Sstevel@tonic-gate APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
6307c478bd9Sstevel@tonic-gate if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
6317c478bd9Sstevel@tonic-gate drv_usecwait(apic_stretch_interrupts);
6327c478bd9Sstevel@tonic-gate
6337c478bd9Sstevel@tonic-gate if (apic_break_on_cpu == psm_get_cpu_id())
6347c478bd9Sstevel@tonic-gate apic_break();
6357c478bd9Sstevel@tonic-gate #endif /* DEBUG */
6367c478bd9Sstevel@tonic-gate return (nipl);
6377c478bd9Sstevel@tonic-gate }
6387c478bd9Sstevel@tonic-gate
639ae115bc7Smrj void
apic_intr_exit(int prev_ipl,int irq)6407c478bd9Sstevel@tonic-gate apic_intr_exit(int prev_ipl, int irq)
6417c478bd9Sstevel@tonic-gate {
6427c478bd9Sstevel@tonic-gate apic_cpus_info_t *cpu_infop;
6437c478bd9Sstevel@tonic-gate
64429ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
6457c478bd9Sstevel@tonic-gate
646583cd330SHans Rosenfeld cpu_infop = &apic_cpus[psm_get_cpu_id()];
647583cd330SHans Rosenfeld if (apic_level_intr[irq])
648583cd330SHans Rosenfeld apic_reg_ops->apic_send_eoi(irq);
649583cd330SHans Rosenfeld cpu_infop->aci_curipl = (uchar_t)prev_ipl;
650583cd330SHans Rosenfeld /* ISR above current pri could not be in progress */
651583cd330SHans Rosenfeld cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
6527c478bd9Sstevel@tonic-gate }
6537c478bd9Sstevel@tonic-gate
654843e1988Sjohnlev intr_exit_fn_t
psm_intr_exit_fn(void)655843e1988Sjohnlev psm_intr_exit_fn(void)
656843e1988Sjohnlev {
657843e1988Sjohnlev return (apic_intr_exit);
658843e1988Sjohnlev }
659843e1988Sjohnlev
6607c478bd9Sstevel@tonic-gate /*
661b6917abeSmishra * Mask all interrupts below or equal to the given IPL.
6627c478bd9Sstevel@tonic-gate */
6637c478bd9Sstevel@tonic-gate static void
apic_setspl(int ipl)6647c478bd9Sstevel@tonic-gate apic_setspl(int ipl)
6657c478bd9Sstevel@tonic-gate {
66629ddbbefSJosef 'Jeff' Sipek apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
6677c478bd9Sstevel@tonic-gate
6687c478bd9Sstevel@tonic-gate /* interrupts at ipl above this cannot be in progress */
6697c478bd9Sstevel@tonic-gate apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
6707c478bd9Sstevel@tonic-gate /*
6717c478bd9Sstevel@tonic-gate * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
6727c478bd9Sstevel@tonic-gate * have enough time to come in before the priority is raised again
6737c478bd9Sstevel@tonic-gate * during the idle() loop.
6747c478bd9Sstevel@tonic-gate */
6757c478bd9Sstevel@tonic-gate if (apic_setspl_delay)
676b6917abeSmishra (void) apic_reg_ops->apic_get_pri();
677b6917abeSmishra }
678b6917abeSmishra
6797c478bd9Sstevel@tonic-gate /*ARGSUSED*/
6807ff178cdSJimmy Vetayases static int
apic_addspl(int irqno,int ipl,int min_ipl,int max_ipl)6817ff178cdSJimmy Vetayases apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
6827c478bd9Sstevel@tonic-gate {
6837ff178cdSJimmy Vetayases return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
6847c478bd9Sstevel@tonic-gate }
6857c478bd9Sstevel@tonic-gate
6867ff178cdSJimmy Vetayases static int
apic_delspl(int irqno,int ipl,int min_ipl,int max_ipl)6877ff178cdSJimmy Vetayases apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
6887c478bd9Sstevel@tonic-gate {
6897ff178cdSJimmy Vetayases return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
6907c478bd9Sstevel@tonic-gate }
6917c478bd9Sstevel@tonic-gate
6927ff178cdSJimmy Vetayases static int
apic_post_cpu_start(void)6937ff178cdSJimmy Vetayases apic_post_cpu_start(void)
6947c478bd9Sstevel@tonic-gate {
6957ff178cdSJimmy Vetayases int cpun;
6967ff178cdSJimmy Vetayases static int cpus_started = 1;
6977c478bd9Sstevel@tonic-gate
6987ff178cdSJimmy Vetayases /* We know this CPU + BSP started successfully. */
6997ff178cdSJimmy Vetayases cpus_started++;
7007c478bd9Sstevel@tonic-gate
7017ff178cdSJimmy Vetayases splx(ipltospl(LOCK_LEVEL));
7027ff178cdSJimmy Vetayases apic_init_intr();
7037c478bd9Sstevel@tonic-gate
7045d8efbbcSSaurabh Misra APIC_AV_PENDING_SET();
7057c478bd9Sstevel@tonic-gate
706643e2e74Sbholler /*
707643e2e74Sbholler * We may be booting, or resuming from suspend; aci_status will
708643e2e74Sbholler * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
709643e2e74Sbholler * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
710643e2e74Sbholler */
711ae115bc7Smrj cpun = psm_get_cpu_id();
712643e2e74Sbholler apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
7137c478bd9Sstevel@tonic-gate
714b6917abeSmishra apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
715ae115bc7Smrj return (PSM_SUCCESS);
716ae115bc7Smrj }
717e250f1e2Ssethg
7187c478bd9Sstevel@tonic-gate /*
7197c478bd9Sstevel@tonic-gate * type == -1 indicates it is an internal request. Do not change
7207c478bd9Sstevel@tonic-gate * resv_vector for these requests
7217c478bd9Sstevel@tonic-gate */
7227c478bd9Sstevel@tonic-gate static int
apic_get_ipivect(int ipl,int type)7237c478bd9Sstevel@tonic-gate apic_get_ipivect(int ipl, int type)
7247c478bd9Sstevel@tonic-gate {
7257c478bd9Sstevel@tonic-gate uchar_t vector;
7267c478bd9Sstevel@tonic-gate int irq;
7277c478bd9Sstevel@tonic-gate
72886a9c507SGuoli Shu if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
729a833a696SJosef 'Jeff' Sipek if ((vector = apic_allocate_vector(ipl, irq, 1))) {
7307c478bd9Sstevel@tonic-gate apic_irq_table[irq]->airq_mps_intr_index =
7317c478bd9Sstevel@tonic-gate RESERVE_INDEX;
7327c478bd9Sstevel@tonic-gate apic_irq_table[irq]->airq_vector = vector;
7337c478bd9Sstevel@tonic-gate if (type != -1) {
7347c478bd9Sstevel@tonic-gate apic_resv_vector[ipl] = vector;
7357c478bd9Sstevel@tonic-gate }
7367c478bd9Sstevel@tonic-gate return (irq);
7377c478bd9Sstevel@tonic-gate }
7387c478bd9Sstevel@tonic-gate }
7397c478bd9Sstevel@tonic-gate apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
7407c478bd9Sstevel@tonic-gate return (-1); /* shouldn't happen */
7417c478bd9Sstevel@tonic-gate }
7427c478bd9Sstevel@tonic-gate
7437c478bd9Sstevel@tonic-gate static int
apic_getclkirq(int ipl)7447c478bd9Sstevel@tonic-gate apic_getclkirq(int ipl)
7457c478bd9Sstevel@tonic-gate {
7467c478bd9Sstevel@tonic-gate int irq;
7477c478bd9Sstevel@tonic-gate
7487c478bd9Sstevel@tonic-gate if ((irq = apic_get_ipivect(ipl, -1)) == -1)
7497c478bd9Sstevel@tonic-gate return (-1);
7507c478bd9Sstevel@tonic-gate /*
7517c478bd9Sstevel@tonic-gate * Note the vector in apic_clkvect for per clock handling.
7527c478bd9Sstevel@tonic-gate */
7537c478bd9Sstevel@tonic-gate apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
7547c478bd9Sstevel@tonic-gate APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
7557c478bd9Sstevel@tonic-gate apic_clkvect));
7567c478bd9Sstevel@tonic-gate return (irq);
7577c478bd9Sstevel@tonic-gate }
7587c478bd9Sstevel@tonic-gate
7597c478bd9Sstevel@tonic-gate /*
7607c478bd9Sstevel@tonic-gate * Try and disable all interrupts. We just assign interrupts to other
7617c478bd9Sstevel@tonic-gate * processors based on policy. If any were bound by user request, we
7627c478bd9Sstevel@tonic-gate * let them continue and return failure. We do not bother to check
7637c478bd9Sstevel@tonic-gate * for cache affinity while rebinding.
7647c478bd9Sstevel@tonic-gate */
7657c478bd9Sstevel@tonic-gate
7667c478bd9Sstevel@tonic-gate static int
apic_disable_intr(processorid_t cpun)7677c478bd9Sstevel@tonic-gate apic_disable_intr(processorid_t cpun)
7687c478bd9Sstevel@tonic-gate {
769ae115bc7Smrj int bind_cpu = 0, i, hardbound = 0;
7707c478bd9Sstevel@tonic-gate apic_irq_t *irq_ptr;
771ae115bc7Smrj ulong_t iflag;
7727c478bd9Sstevel@tonic-gate
7737c478bd9Sstevel@tonic-gate iflag = intr_clear();
7747c478bd9Sstevel@tonic-gate lock_set(&apic_ioapic_lock);
775e250f1e2Ssethg
776e250f1e2Ssethg for (i = 0; i <= APIC_MAX_VECTOR; i++) {
777e250f1e2Ssethg if (apic_reprogram_info[i].done == B_FALSE) {
778e250f1e2Ssethg if (apic_reprogram_info[i].bindcpu == cpun) {
779e250f1e2Ssethg /*
780e250f1e2Ssethg * CPU is busy -- it's the target of
781e250f1e2Ssethg * a pending reprogramming attempt
782e250f1e2Ssethg */
783e250f1e2Ssethg lock_clear(&apic_ioapic_lock);
784e250f1e2Ssethg intr_restore(iflag);
785e250f1e2Ssethg return (PSM_FAILURE);
786e250f1e2Ssethg }
787e250f1e2Ssethg }
788e250f1e2Ssethg }
789e250f1e2Ssethg
7907c478bd9Sstevel@tonic-gate apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
791e250f1e2Ssethg
7927c478bd9Sstevel@tonic-gate apic_cpus[cpun].aci_curipl = 0;
793e250f1e2Ssethg
7947c478bd9Sstevel@tonic-gate i = apic_min_device_irq;
7957c478bd9Sstevel@tonic-gate for (; i <= apic_max_device_irq; i++) {
7967c478bd9Sstevel@tonic-gate /*
7977c478bd9Sstevel@tonic-gate * If there are bound interrupts on this cpu, then
7987c478bd9Sstevel@tonic-gate * rebind them to other processors.
7997c478bd9Sstevel@tonic-gate */
8007c478bd9Sstevel@tonic-gate if ((irq_ptr = apic_irq_table[i]) != NULL) {
8017c478bd9Sstevel@tonic-gate ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
8027c478bd9Sstevel@tonic-gate (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
803a3114836SGerry Liu (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
8047c478bd9Sstevel@tonic-gate
8057c478bd9Sstevel@tonic-gate if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
8067c478bd9Sstevel@tonic-gate hardbound = 1;
8077c478bd9Sstevel@tonic-gate continue;
8087c478bd9Sstevel@tonic-gate }
8097c478bd9Sstevel@tonic-gate
8107c478bd9Sstevel@tonic-gate if (irq_ptr->airq_temp_cpu == cpun) {
8117c478bd9Sstevel@tonic-gate do {
812e7c3cdaeSjiang.liu@intel.com bind_cpu =
813e7c3cdaeSjiang.liu@intel.com apic_find_cpu(APIC_CPU_INTR_ENABLE);
814e250f1e2Ssethg } while (apic_rebind_all(irq_ptr, bind_cpu));
8157c478bd9Sstevel@tonic-gate }
8167c478bd9Sstevel@tonic-gate }
8177c478bd9Sstevel@tonic-gate }
818e250f1e2Ssethg
819e250f1e2Ssethg lock_clear(&apic_ioapic_lock);
820e250f1e2Ssethg intr_restore(iflag);
821e250f1e2Ssethg
8227c478bd9Sstevel@tonic-gate if (hardbound) {
8237c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "Could not disable interrupts on %d"
8247c478bd9Sstevel@tonic-gate "due to user bound interrupts", cpun);
8257c478bd9Sstevel@tonic-gate return (PSM_FAILURE);
8267c478bd9Sstevel@tonic-gate }
8277c478bd9Sstevel@tonic-gate else
8287c478bd9Sstevel@tonic-gate return (PSM_SUCCESS);
8297c478bd9Sstevel@tonic-gate }
8307c478bd9Sstevel@tonic-gate
831643e2e74Sbholler /*
832643e2e74Sbholler * Bind interrupts to the CPU's local APIC.
833643e2e74Sbholler * Interrupts should not be bound to a CPU's local APIC until the CPU
834643e2e74Sbholler * is ready to receive interrupts.
835643e2e74Sbholler */
8367c478bd9Sstevel@tonic-gate static void
apic_enable_intr(processorid_t cpun)8377c478bd9Sstevel@tonic-gate apic_enable_intr(processorid_t cpun)
8387c478bd9Sstevel@tonic-gate {
839ae115bc7Smrj int i;
8407c478bd9Sstevel@tonic-gate apic_irq_t *irq_ptr;
841ae115bc7Smrj ulong_t iflag;
8427c478bd9Sstevel@tonic-gate
8437c478bd9Sstevel@tonic-gate iflag = intr_clear();
8447c478bd9Sstevel@tonic-gate lock_set(&apic_ioapic_lock);
845e250f1e2Ssethg
8467c478bd9Sstevel@tonic-gate apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
8477c478bd9Sstevel@tonic-gate
8487c478bd9Sstevel@tonic-gate i = apic_min_device_irq;
8497c478bd9Sstevel@tonic-gate for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
8507c478bd9Sstevel@tonic-gate if ((irq_ptr = apic_irq_table[i]) != NULL) {
8517c478bd9Sstevel@tonic-gate if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
8527c478bd9Sstevel@tonic-gate (void) apic_rebind_all(irq_ptr,
853e250f1e2Ssethg irq_ptr->airq_cpu);
8547c478bd9Sstevel@tonic-gate }
8557c478bd9Sstevel@tonic-gate }
8567c478bd9Sstevel@tonic-gate }
857e250f1e2Ssethg
8587ff178cdSJimmy Vetayases if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
8597ff178cdSJimmy Vetayases apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
8607ff178cdSJimmy Vetayases
861e250f1e2Ssethg lock_clear(&apic_ioapic_lock);
862e250f1e2Ssethg intr_restore(iflag);
8637c478bd9Sstevel@tonic-gate }
8647c478bd9Sstevel@tonic-gate
8657c478bd9Sstevel@tonic-gate /*
866dd4eeefdSeota * If this module needs a periodic handler for the interrupt distribution, it
867dd4eeefdSeota * can be added here. The argument to the periodic handler is not currently
868dd4eeefdSeota * used, but is reserved for future.
8697c478bd9Sstevel@tonic-gate */
8707c478bd9Sstevel@tonic-gate static void
apic_post_cyclic_setup(void * arg)8717c478bd9Sstevel@tonic-gate apic_post_cyclic_setup(void *arg)
8727c478bd9Sstevel@tonic-gate {
8737c478bd9Sstevel@tonic-gate _NOTE(ARGUNUSED(arg))
874a288e5a9SJoshua M. Clulow
875a288e5a9SJoshua M. Clulow cyc_handler_t cyh;
876a288e5a9SJoshua M. Clulow cyc_time_t cyt;
877a288e5a9SJoshua M. Clulow
8787c478bd9Sstevel@tonic-gate /* cpu_lock is held */
879dd4eeefdSeota /* set up a periodic handler for intr redistribution */
8807c478bd9Sstevel@tonic-gate
8817c478bd9Sstevel@tonic-gate /*
8827c478bd9Sstevel@tonic-gate * In peridoc mode intr redistribution processing is done in
8837c478bd9Sstevel@tonic-gate * apic_intr_enter during clk intr processing
8847c478bd9Sstevel@tonic-gate */
8857c478bd9Sstevel@tonic-gate if (!apic_oneshot)
8867c478bd9Sstevel@tonic-gate return;
887a288e5a9SJoshua M. Clulow
888dd4eeefdSeota /*
889dd4eeefdSeota * Register a periodical handler for the redistribution processing.
890a288e5a9SJoshua M. Clulow * Though we would generally prefer to use the DDI interface for
891a288e5a9SJoshua M. Clulow * periodic handler invocation, ddi_periodic_add(9F), we are
892a288e5a9SJoshua M. Clulow * unfortunately already holding cpu_lock, which ddi_periodic_add will
893a288e5a9SJoshua M. Clulow * attempt to take for us. Thus, we add our own cyclic directly:
894dd4eeefdSeota */
895a288e5a9SJoshua M. Clulow cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
896a288e5a9SJoshua M. Clulow cyh.cyh_arg = NULL;
897a288e5a9SJoshua M. Clulow cyh.cyh_level = CY_LOW_LEVEL;
898a288e5a9SJoshua M. Clulow
899a288e5a9SJoshua M. Clulow cyt.cyt_when = 0;
900a288e5a9SJoshua M. Clulow cyt.cyt_interval = apic_redistribute_sample_interval;
901a288e5a9SJoshua M. Clulow
902a288e5a9SJoshua M. Clulow apic_cyclic_id = cyclic_add(&cyh, &cyt);
9037c478bd9Sstevel@tonic-gate }
9047c478bd9Sstevel@tonic-gate
9057c478bd9Sstevel@tonic-gate static void
apic_redistribute_compute(void)9067c478bd9Sstevel@tonic-gate apic_redistribute_compute(void)
9077c478bd9Sstevel@tonic-gate {
9087c478bd9Sstevel@tonic-gate int i, j, max_busy;
9097c478bd9Sstevel@tonic-gate
9107c478bd9Sstevel@tonic-gate if (apic_enable_dynamic_migration) {
9117c478bd9Sstevel@tonic-gate if (++apic_nticks == apic_sample_factor_redistribution) {
9127c478bd9Sstevel@tonic-gate /*
9137c478bd9Sstevel@tonic-gate * Time to call apic_intr_redistribute().
9147c478bd9Sstevel@tonic-gate * reset apic_nticks. This will cause max_busy
9157c478bd9Sstevel@tonic-gate * to be calculated below and if it is more than
9167c478bd9Sstevel@tonic-gate * apic_int_busy, we will do the whole thing
9177c478bd9Sstevel@tonic-gate */
9187c478bd9Sstevel@tonic-gate apic_nticks = 0;
9197c478bd9Sstevel@tonic-gate }
9207c478bd9Sstevel@tonic-gate max_busy = 0;
9217c478bd9Sstevel@tonic-gate for (i = 0; i < apic_nproc; i++) {
922a3114836SGerry Liu if (!apic_cpu_in_range(i))
923a3114836SGerry Liu continue;
9247c478bd9Sstevel@tonic-gate
9257c478bd9Sstevel@tonic-gate /*
9267c478bd9Sstevel@tonic-gate * Check if curipl is non zero & if ISR is in
9277c478bd9Sstevel@tonic-gate * progress
9287c478bd9Sstevel@tonic-gate */
9297c478bd9Sstevel@tonic-gate if (((j = apic_cpus[i].aci_curipl) != 0) &&
9307c478bd9Sstevel@tonic-gate (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
9317c478bd9Sstevel@tonic-gate
9327c478bd9Sstevel@tonic-gate int irq;
9337c478bd9Sstevel@tonic-gate apic_cpus[i].aci_busy++;
9347c478bd9Sstevel@tonic-gate irq = apic_cpus[i].aci_current[j];
9357c478bd9Sstevel@tonic-gate apic_irq_table[irq]->airq_busy++;
9367c478bd9Sstevel@tonic-gate }
9377c478bd9Sstevel@tonic-gate
9387c478bd9Sstevel@tonic-gate if (!apic_nticks &&
9397c478bd9Sstevel@tonic-gate (apic_cpus[i].aci_busy > max_busy))
9407c478bd9Sstevel@tonic-gate max_busy = apic_cpus[i].aci_busy;
9417c478bd9Sstevel@tonic-gate }
9427c478bd9Sstevel@tonic-gate if (!apic_nticks) {
9437c478bd9Sstevel@tonic-gate if (max_busy > apic_int_busy_mark) {
9447c478bd9Sstevel@tonic-gate /*
9457c478bd9Sstevel@tonic-gate * We could make the following check be
9467c478bd9Sstevel@tonic-gate * skipped > 1 in which case, we get a
9477c478bd9Sstevel@tonic-gate * redistribution at half the busy mark (due to
9487c478bd9Sstevel@tonic-gate * double interval). Need to be able to collect
9497c478bd9Sstevel@tonic-gate * more empirical data to decide if that is a
9507c478bd9Sstevel@tonic-gate * good strategy. Punt for now.
9517c478bd9Sstevel@tonic-gate */
952ae115bc7Smrj if (apic_skipped_redistribute) {
9537c478bd9Sstevel@tonic-gate apic_cleanup_busy();
954ae115bc7Smrj apic_skipped_redistribute = 0;
955ae115bc7Smrj } else {
9567c478bd9Sstevel@tonic-gate apic_intr_redistribute();
957ae115bc7Smrj }
9587c478bd9Sstevel@tonic-gate } else
9597c478bd9Sstevel@tonic-gate apic_skipped_redistribute++;
9607c478bd9Sstevel@tonic-gate }
9617c478bd9Sstevel@tonic-gate }
9627c478bd9Sstevel@tonic-gate }
9637c478bd9Sstevel@tonic-gate
9647c478bd9Sstevel@tonic-gate
965ae115bc7Smrj /*
966ae115bc7Smrj * The following functions are in the platform specific file so that they
967ae115bc7Smrj * can be different functions depending on whether we are running on
968ae115bc7Smrj * bare metal or a hypervisor.
969ae115bc7Smrj */
9707c478bd9Sstevel@tonic-gate
971e250f1e2Ssethg /*
972a7639048Sjohnny * Check to make sure there are enough irq slots
973e250f1e2Ssethg */
974ae115bc7Smrj int
apic_check_free_irqs(int count)975a7639048Sjohnny apic_check_free_irqs(int count)
976a7639048Sjohnny {
977a7639048Sjohnny int i, avail;
978a7639048Sjohnny
979a7639048Sjohnny avail = 0;
980a7639048Sjohnny for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
981a7639048Sjohnny if ((apic_irq_table[i] == NULL) ||
982a7639048Sjohnny apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
983a7639048Sjohnny if (++avail >= count)
984a7639048Sjohnny return (PSM_SUCCESS);
985a7639048Sjohnny }
986a7639048Sjohnny }
987a7639048Sjohnny return (PSM_FAILURE);
988a7639048Sjohnny }
989a7639048Sjohnny
990a7639048Sjohnny /*
991a7639048Sjohnny * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
992a7639048Sjohnny */
993a7639048Sjohnny int
apic_alloc_msi_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)994a7639048Sjohnny apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
995ae115bc7Smrj int behavior)
996e250f1e2Ssethg {
997ae115bc7Smrj int rcount, i;
998b6917abeSmishra uchar_t start, irqno;
99930acb30dSHans Rosenfeld uint32_t cpu = 0;
1000ae115bc7Smrj major_t major;
1001ae115bc7Smrj apic_irq_t *irqptr;
1002e250f1e2Ssethg
1003a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1004ae115bc7Smrj "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1005a7639048Sjohnny (void *)dip, inum, pri, count, behavior));
1006e250f1e2Ssethg
1007ae115bc7Smrj if (count > 1) {
1008ae115bc7Smrj if (behavior == DDI_INTR_ALLOC_STRICT &&
100963ea9ad2SEvan Yan apic_multi_msi_enable == 0)
1010ae115bc7Smrj return (0);
1011ae115bc7Smrj if (apic_multi_msi_enable == 0)
1012ae115bc7Smrj count = 1;
1013ae115bc7Smrj }
1014e250f1e2Ssethg
1015ae115bc7Smrj if ((rcount = apic_navail_vector(dip, pri)) > count)
1016ae115bc7Smrj rcount = count;
1017ae115bc7Smrj else if (rcount == 0 || (rcount < count &&
1018ae115bc7Smrj behavior == DDI_INTR_ALLOC_STRICT))
1019ae115bc7Smrj return (0);
1020e250f1e2Ssethg
1021ae115bc7Smrj /* if not ISP2, then round it down */
1022ae115bc7Smrj if (!ISP2(rcount))
1023ae115bc7Smrj rcount = 1 << (highbit(rcount) - 1);
1024e250f1e2Ssethg
1025ae115bc7Smrj mutex_enter(&airq_mutex);
1026e250f1e2Ssethg
1027ae115bc7Smrj for (start = 0; rcount > 0; rcount >>= 1) {
1028ae115bc7Smrj if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1029ae115bc7Smrj behavior == DDI_INTR_ALLOC_STRICT)
1030ae115bc7Smrj break;
1031ae115bc7Smrj }
1032e250f1e2Ssethg
1033ae115bc7Smrj if (start == 0) {
1034ae115bc7Smrj /* no vector available */
1035ae115bc7Smrj mutex_exit(&airq_mutex);
1036ae115bc7Smrj return (0);
1037ae115bc7Smrj }
1038e250f1e2Ssethg
1039a7639048Sjohnny if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1040a7639048Sjohnny /* not enough free irq slots available */
1041a7639048Sjohnny mutex_exit(&airq_mutex);
1042a7639048Sjohnny return (0);
1043a7639048Sjohnny }
1044a7639048Sjohnny
10455c066ec2SJerry Gilliam major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1046ae115bc7Smrj for (i = 0; i < rcount; i++) {
1047ae115bc7Smrj if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1048ae115bc7Smrj (uchar_t)-1) {
1049a7639048Sjohnny /*
1050a7639048Sjohnny * shouldn't happen because of the
1051a7639048Sjohnny * apic_check_free_irqs() check earlier
1052a7639048Sjohnny */
1053ae115bc7Smrj mutex_exit(&airq_mutex);
1054a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1055ae115bc7Smrj "apic_allocate_irq failed\n"));
1056ae115bc7Smrj return (i);
1057e250f1e2Ssethg }
1058ae115bc7Smrj apic_max_device_irq = max(irqno, apic_max_device_irq);
1059ae115bc7Smrj apic_min_device_irq = min(irqno, apic_min_device_irq);
1060ae115bc7Smrj irqptr = apic_irq_table[irqno];
1061ae115bc7Smrj #ifdef DEBUG
1062ae115bc7Smrj if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1063a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1064ae115bc7Smrj "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1065ae115bc7Smrj #endif
1066ae115bc7Smrj apic_vector_to_irq[start + i] = (uchar_t)irqno;
1067ae115bc7Smrj
1068ae115bc7Smrj irqptr->airq_vector = (uchar_t)(start + i);
1069ae115bc7Smrj irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1070ae115bc7Smrj irqptr->airq_intin_no = (uchar_t)rcount;
107130acb30dSHans Rosenfeld ASSERT(pri >= 0 && pri <= UCHAR_MAX);
107230acb30dSHans Rosenfeld irqptr->airq_ipl = (uchar_t)pri;
1073ae115bc7Smrj irqptr->airq_vector = start + i;
1074ae115bc7Smrj irqptr->airq_origirq = (uchar_t)(inum + i);
1075ae115bc7Smrj irqptr->airq_share_id = 0;
1076ae115bc7Smrj irqptr->airq_mps_intr_index = MSI_INDEX;
1077ae115bc7Smrj irqptr->airq_dip = dip;
1078ae115bc7Smrj irqptr->airq_major = major;
1079ae115bc7Smrj if (i == 0) /* they all bound to the same cpu */
1080ae115bc7Smrj cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
10812917a9c9Sschwartz 0xff, 0xff);
1082ae115bc7Smrj else
1083ae115bc7Smrj irqptr->airq_cpu = cpu;
1084a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1085ae115bc7Smrj "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1086ae115bc7Smrj (void *)irqptr->airq_dip, irqptr->airq_vector,
1087ae115bc7Smrj irqptr->airq_origirq, pri));
1088e250f1e2Ssethg }
1089ae115bc7Smrj mutex_exit(&airq_mutex);
1090ae115bc7Smrj return (rcount);
1091e250f1e2Ssethg }
1092e250f1e2Ssethg
1093a7639048Sjohnny /*
1094a7639048Sjohnny * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1095a7639048Sjohnny */
1096a7639048Sjohnny int
apic_alloc_msix_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)1097a7639048Sjohnny apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1098a7639048Sjohnny int behavior)
1099a7639048Sjohnny {
1100a7639048Sjohnny int rcount, i;
1101a7639048Sjohnny major_t major;
1102a7639048Sjohnny
1103a7639048Sjohnny mutex_enter(&airq_mutex);
1104a7639048Sjohnny
1105a7639048Sjohnny if ((rcount = apic_navail_vector(dip, pri)) > count)
1106a7639048Sjohnny rcount = count;
1107a7639048Sjohnny else if (rcount == 0 || (rcount < count &&
1108a7639048Sjohnny behavior == DDI_INTR_ALLOC_STRICT)) {
1109a7639048Sjohnny rcount = 0;
1110a7639048Sjohnny goto out;
1111a7639048Sjohnny }
1112a7639048Sjohnny
1113a7639048Sjohnny if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1114a7639048Sjohnny /* not enough free irq slots available */
1115a7639048Sjohnny rcount = 0;
1116a7639048Sjohnny goto out;
1117a7639048Sjohnny }
1118a7639048Sjohnny
11195c066ec2SJerry Gilliam major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1120a7639048Sjohnny for (i = 0; i < rcount; i++) {
1121a7639048Sjohnny uchar_t vector, irqno;
1122a7639048Sjohnny apic_irq_t *irqptr;
1123a7639048Sjohnny
1124a7639048Sjohnny if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1125a7639048Sjohnny (uchar_t)-1) {
1126a7639048Sjohnny /*
1127a7639048Sjohnny * shouldn't happen because of the
1128a7639048Sjohnny * apic_check_free_irqs() check earlier
1129a7639048Sjohnny */
1130a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1131a7639048Sjohnny "apic_allocate_irq failed\n"));
1132a7639048Sjohnny rcount = i;
1133a7639048Sjohnny goto out;
1134a7639048Sjohnny }
1135a7639048Sjohnny if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1136a7639048Sjohnny /*
1137a7639048Sjohnny * shouldn't happen because of the
1138a7639048Sjohnny * apic_navail_vector() call earlier
1139a7639048Sjohnny */
1140a7639048Sjohnny DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1141a7639048Sjohnny "apic_allocate_vector failed\n"));
1142a7639048Sjohnny rcount = i;
1143a7639048Sjohnny goto out;
1144a7639048Sjohnny }
1145a7639048Sjohnny apic_max_device_irq = max(irqno, apic_max_device_irq);
1146a7639048Sjohnny apic_min_device_irq = min(irqno, apic_min_device_irq);
1147a7639048Sjohnny irqptr = apic_irq_table[irqno];
1148a7639048Sjohnny irqptr->airq_vector = (uchar_t)vector;
114930acb30dSHans Rosenfeld ASSERT(pri >= 0 && pri <= UCHAR_MAX);
115030acb30dSHans Rosenfeld irqptr->airq_ipl = (uchar_t)pri;
1151a7639048Sjohnny irqptr->airq_origirq = (uchar_t)(inum + i);
1152a7639048Sjohnny irqptr->airq_share_id = 0;
1153a7639048Sjohnny irqptr->airq_mps_intr_index = MSIX_INDEX;
1154a7639048Sjohnny irqptr->airq_dip = dip;
1155a7639048Sjohnny irqptr->airq_major = major;
1156a7639048Sjohnny irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1157a7639048Sjohnny }
1158a7639048Sjohnny out:
1159a7639048Sjohnny mutex_exit(&airq_mutex);
1160a7639048Sjohnny return (rcount);
1161a7639048Sjohnny }
1162a7639048Sjohnny
11637c478bd9Sstevel@tonic-gate /*
1164ae115bc7Smrj * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1165ae115bc7Smrj * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1166ae115bc7Smrj * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1167ae115bc7Smrj * requests and allocated only when pri is set.
11687c478bd9Sstevel@tonic-gate */
1169ae115bc7Smrj uchar_t
apic_allocate_vector(int ipl,int irq,int pri)1170ae115bc7Smrj apic_allocate_vector(int ipl, int irq, int pri)
11717c478bd9Sstevel@tonic-gate {
1172ae115bc7Smrj int lowest, highest, i;
11737c478bd9Sstevel@tonic-gate
1174ae115bc7Smrj highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1175ae115bc7Smrj lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1176e250f1e2Ssethg
1177ae115bc7Smrj if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1178ae115bc7Smrj lowest -= APIC_VECTOR_PER_IPL;
11797c478bd9Sstevel@tonic-gate
1180ae115bc7Smrj #ifdef DEBUG
1181ae115bc7Smrj if (apic_restrict_vector) /* for testing shared interrupt logic */
1182ae115bc7Smrj highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1183ae115bc7Smrj #endif /* DEBUG */
1184ae115bc7Smrj if (pri == 0)
1185ae115bc7Smrj highest -= APIC_HI_PRI_VECTS;
11867c478bd9Sstevel@tonic-gate
118726896e4cSGuoli Shu for (i = lowest; i <= highest; i++) {
1188ae115bc7Smrj if (APIC_CHECK_RESERVE_VECTORS(i))
1189ae115bc7Smrj continue;
1190ae115bc7Smrj if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1191ae115bc7Smrj apic_vector_to_irq[i] = (uchar_t)irq;
119230acb30dSHans Rosenfeld ASSERT(i >= 0 && i <= UCHAR_MAX);
119330acb30dSHans Rosenfeld return ((uchar_t)i);
1194ae115bc7Smrj }
11957c478bd9Sstevel@tonic-gate }
11967c478bd9Sstevel@tonic-gate
1197ae115bc7Smrj return (0);
1198ae115bc7Smrj }
11997c478bd9Sstevel@tonic-gate
1200ae115bc7Smrj /* Mark vector as not being used by any irq */
1201ae115bc7Smrj void
apic_free_vector(uchar_t vector)1202ae115bc7Smrj apic_free_vector(uchar_t vector)
1203ae115bc7Smrj {
1204ae115bc7Smrj apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1205ae115bc7Smrj }
12067c478bd9Sstevel@tonic-gate
1207ae115bc7Smrj /*
1208ae115bc7Smrj * Call rebind to do the actual programming.
1209ae115bc7Smrj * Must be called with interrupts disabled and apic_ioapic_lock held
1210ae115bc7Smrj * 'p' is polymorphic -- if this function is called to process a deferred
1211ae115bc7Smrj * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1212ae115bc7Smrj * the irq pointer is retrieved. If not doing deferred reprogramming,
1213ae115bc7Smrj * p is of the type 'apic_irq_t *'.
1214ae115bc7Smrj *
1215ae115bc7Smrj * apic_ioapic_lock must be held across this call, as it protects apic_rebind
12167ff178cdSJimmy Vetayases * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1217a3114836SGerry Liu * taken offline after a cpu is selected, but before apic_rebind is called to
1218ae115bc7Smrj * bind interrupts to it.
1219ae115bc7Smrj */
1220ae115bc7Smrj int
apic_setup_io_intr(void * p,int irq,boolean_t deferred)1221ae115bc7Smrj apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1222ae115bc7Smrj {
1223ae115bc7Smrj apic_irq_t *irqptr;
1224ae115bc7Smrj struct ioapic_reprogram_data *drep = NULL;
1225ae115bc7Smrj int rv;
12267c478bd9Sstevel@tonic-gate
1227ae115bc7Smrj if (deferred) {
1228ae115bc7Smrj drep = (struct ioapic_reprogram_data *)p;
1229ae115bc7Smrj ASSERT(drep != NULL);
1230ae115bc7Smrj irqptr = drep->irqp;
1231ae115bc7Smrj } else
1232ae115bc7Smrj irqptr = (apic_irq_t *)p;
12337c478bd9Sstevel@tonic-gate
1234ae115bc7Smrj ASSERT(irqptr != NULL);
12357c478bd9Sstevel@tonic-gate
1236ae115bc7Smrj rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1237ae115bc7Smrj if (rv) {
1238ae115bc7Smrj /*
1239ae115bc7Smrj * CPU is not up or interrupts are disabled. Fall back to
1240ae115bc7Smrj * the first available CPU
1241ae115bc7Smrj */
1242e7c3cdaeSjiang.liu@intel.com rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1243e7c3cdaeSjiang.liu@intel.com drep);
12447c478bd9Sstevel@tonic-gate }
12457c478bd9Sstevel@tonic-gate
1246ae115bc7Smrj return (rv);
1247ae115bc7Smrj }
12487c478bd9Sstevel@tonic-gate
12497c478bd9Sstevel@tonic-gate
1250ae115bc7Smrj uchar_t
apic_modify_vector(uchar_t vector,int irq)1251ae115bc7Smrj apic_modify_vector(uchar_t vector, int irq)
1252ae115bc7Smrj {
1253ae115bc7Smrj apic_vector_to_irq[vector] = (uchar_t)irq;
1254ae115bc7Smrj return (vector);
12557c478bd9Sstevel@tonic-gate }
12562917a9c9Sschwartz
12572917a9c9Sschwartz char *
apic_get_apic_type(void)12587ff178cdSJimmy Vetayases apic_get_apic_type(void)
12592917a9c9Sschwartz {
12602917a9c9Sschwartz return (apic_psm_info.p_mach_idstring);
12612917a9c9Sschwartz }
1262b6917abeSmishra
1263b6917abeSmishra void
apic_switch_ipi_callback(boolean_t enter)1264583cd330SHans Rosenfeld apic_switch_ipi_callback(boolean_t enter)
1265b6917abeSmishra {
1266583cd330SHans Rosenfeld ASSERT(enter == B_TRUE);
1267583cd330SHans Rosenfeld }
1268b6917abeSmishra
1269583cd330SHans Rosenfeld int
apic_detect_x2apic(void)1270583cd330SHans Rosenfeld apic_detect_x2apic(void)
1271583cd330SHans Rosenfeld {
1272583cd330SHans Rosenfeld return (0);
1273583cd330SHans Rosenfeld }
12747ff178cdSJimmy Vetayases
1275583cd330SHans Rosenfeld void
apic_enable_x2apic(void)1276583cd330SHans Rosenfeld apic_enable_x2apic(void)
1277583cd330SHans Rosenfeld {
1278583cd330SHans Rosenfeld cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp");
1279583cd330SHans Rosenfeld }
1280325e77f4SSaurabh Misra
1281583cd330SHans Rosenfeld void
x2apic_update_psm(void)1282583cd330SHans Rosenfeld x2apic_update_psm(void)
1283583cd330SHans Rosenfeld {
1284583cd330SHans Rosenfeld cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp");
1285b6917abeSmishra }
1286