1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 * Copyright 2019 Joyent, Inc.
29 * Copyright 2020 Oxide Computer Company
30 */
31
32 /*
33 * To understand how the pcplusmp module interacts with the interrupt subsystem
34 * read the theory statement in uts/i86pc/os/intr.c.
35 */
36
37 /*
38 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
39 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
40 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
41 * PSMI 1.5 extensions are supported in Solaris Nevada.
42 * PSMI 1.6 extensions are supported in Solaris Nevada.
43 * PSMI 1.7 extensions are supported in Solaris Nevada.
44 */
45 #define PSMI_1_7
46
47 #include <sys/processor.h>
48 #include <sys/time.h>
49 #include <sys/psm.h>
50 #include <sys/smp_impldefs.h>
51 #include <sys/cram.h>
52 #include <sys/acpi/acpi.h>
53 #include <sys/acpica.h>
54 #include <sys/psm_common.h>
55 #include <sys/apic.h>
56 #include <sys/pit.h>
57 #include <sys/ddi.h>
58 #include <sys/sunddi.h>
59 #include <sys/ddi_impldefs.h>
60 #include <sys/pci.h>
61 #include <sys/promif.h>
62 #include <sys/prom_debug.h>
63 #include <sys/x86_archext.h>
64 #include <sys/cpc_impl.h>
65 #include <sys/uadmin.h>
66 #include <sys/panic.h>
67 #include <sys/debug.h>
68 #include <sys/archsystm.h>
69 #include <sys/trap.h>
70 #include <sys/machsystm.h>
71 #include <sys/sysmacros.h>
72 #include <sys/cpuvar.h>
73 #include <sys/rm_platter.h>
74 #include <sys/privregs.h>
75 #include <sys/note.h>
76 #include <sys/pci_intr_lib.h>
77 #include <sys/spl.h>
78 #include <sys/clock.h>
79 #include <sys/cyclic.h>
80 #include <sys/dditypes.h>
81 #include <sys/sunddi.h>
82 #include <sys/x_call.h>
83 #include <sys/reboot.h>
84 #include <sys/hpet.h>
85 #include <sys/apic_common.h>
86 #include <sys/apic_timer.h>
87 #include <sys/smt.h>
88
89 /*
90 * Local Function Prototypes
91 */
92 static void apic_init_intr(void);
93
94 /*
95 * standard MP entries
96 */
97 static int apic_probe(void);
98 static int apic_getclkirq(int ipl);
99 static void apic_init(void);
100 static void apic_picinit(void);
101 static int apic_post_cpu_start(void);
102 static int apic_intr_enter(int ipl, int *vect);
103 static void apic_setspl(int ipl);
104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 static int apic_disable_intr(processorid_t cpun);
107 static void apic_enable_intr(processorid_t cpun);
108 static int apic_get_ipivect(int ipl, int type);
109 static void apic_post_cyclic_setup(void *arg);
110
111 #define UCHAR_MAX UINT8_MAX
112
113 /*
114 * The following vector assignments influence the value of ipltopri and
115 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
116 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
117 * we care to do so in future. Note some IPLs which are rarely used
118 * will share the vector ranges and heavily used IPLs (5 and 6) have
119 * a wide range.
120 *
121 * This array is used to initialize apic_ipls[] (in apic_init()).
122 *
123 * IPL Vector range. as passed to intr_enter
124 * 0 none.
125 * 1,2,3 0x20-0x2f 0x0-0xf
126 * 4 0x30-0x3f 0x10-0x1f
127 * 5 0x40-0x5f 0x20-0x3f
128 * 6 0x60-0x7f 0x40-0x5f
129 * 7,8,9 0x80-0x8f 0x60-0x6f
130 * 10 0x90-0x9f 0x70-0x7f
131 * 11 0xa0-0xaf 0x80-0x8f
132 * ... ...
133 * 15 0xe0-0xef 0xc0-0xcf
134 * 15 0xf0-0xff 0xd0-0xdf
135 */
136 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
137 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
138 };
139 /*
140 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
141 * NOTE that this is vector as passed into intr_enter which is
142 * programmed vector - 0x20 (APIC_BASE_VECT)
143 */
144
145 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
146 /* The taskpri to be programmed into apic to mask given ipl */
147
148 /*
149 * Correlation of the hardware vector to the IPL in use, initialized
150 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
151 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
152 * connected to errata-stricken IOAPICs
153 */
154 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
155
156 /*
157 * Patchable global variables.
158 */
159 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
160 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
161
162 /*
163 * Local static data
164 */
165 static struct psm_ops apic_ops = {
166 apic_probe,
167
168 apic_init,
169 apic_picinit,
170 apic_intr_enter,
171 apic_intr_exit,
172 apic_setspl,
173 apic_addspl,
174 apic_delspl,
175 apic_disable_intr,
176 apic_enable_intr,
177 (int (*)(int))NULL, /* psm_softlvl_to_irq */
178 (void (*)(int))NULL, /* psm_set_softintr */
179
180 apic_set_idlecpu,
181 apic_unset_idlecpu,
182
183 apic_clkinit,
184 apic_getclkirq,
185 (void (*)(void))NULL, /* psm_hrtimeinit */
186 apic_gethrtime,
187
188 apic_get_next_processorid,
189 apic_cpu_start,
190 apic_post_cpu_start,
191 apic_shutdown,
192 apic_get_ipivect,
193 apic_send_ipi,
194
195 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
196 (void (*)(int, char *))NULL, /* psm_notify_error */
197 (void (*)(int))NULL, /* psm_notify_func */
198 apic_timer_reprogram,
199 apic_timer_enable,
200 apic_timer_disable,
201 apic_post_cyclic_setup,
202 apic_preshutdown,
203 apic_intr_ops, /* Advanced DDI Interrupt framework */
204 apic_state, /* save, restore apic state for S3 */
205 apic_cpu_ops, /* CPU control interface. */
206
207 apic_get_pir_ipivect,
208 apic_send_pir_ipi,
209 apic_cmci_setup,
210 };
211
212 struct psm_ops *psmops = &apic_ops;
213
214 static struct psm_info apic_psm_info = {
215 PSM_INFO_VER01_7, /* version */
216 PSM_OWN_EXCLUSIVE, /* ownership */
217 (struct psm_ops *)&apic_ops, /* operation */
218 APIC_PCPLUSMP_NAME, /* machine name */
219 "pcplusmp v1.4 compatible",
220 };
221
222 static void *apic_hdlp;
223
224 /* to gather intr data and redistribute */
225 static void apic_redistribute_compute(void);
226
227 /*
228 * This is the loadable module wrapper
229 */
230
231 int
_init(void)232 _init(void)
233 {
234 if (apic_coarse_hrtime)
235 apic_ops.psm_gethrtime = &apic_gettime;
236 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
237 }
238
239 int
_fini(void)240 _fini(void)
241 {
242 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
243 }
244
245 int
_info(struct modinfo * modinfop)246 _info(struct modinfo *modinfop)
247 {
248 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
249 }
250
251 static int
apic_probe(void)252 apic_probe(void)
253 {
254 PRM_POINT("apic_probe()");
255
256 /* check if apix is initialized */
257 if (apix_enable && apix_loaded()) {
258 PRM_POINT("apic_probe FAILURE: apix is loaded");
259 return (PSM_FAILURE);
260 }
261
262 /*
263 * Check whether x2APIC mode was activated by BIOS. We don't support
264 * that in pcplusmp as apix normally handles that.
265 */
266 PRM_POINT("apic_local_mode()");
267 if (apic_local_mode() == LOCAL_X2APIC) {
268 PRM_POINT("apic_probe FAILURE: in x2apic mode");
269 return (PSM_FAILURE);
270 }
271
272 /* continue using pcplusmp PSM */
273 apix_enable = 0;
274
275 return (apic_probe_common(apic_psm_info.p_mach_idstring));
276 }
277
278 static uchar_t
apic_xlate_vector_by_irq(uchar_t irq)279 apic_xlate_vector_by_irq(uchar_t irq)
280 {
281 if (apic_irq_table[irq] == NULL)
282 return (0);
283
284 return (apic_irq_table[irq]->airq_vector);
285 }
286
287 void
apic_init(void)288 apic_init(void)
289 {
290 int i;
291 int j = 1;
292
293 psm_get_ioapicid = apic_get_ioapicid;
294 psm_get_localapicid = apic_get_localapicid;
295 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
296
297 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
298 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
299 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
300 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
301 /* get to highest vector at the same ipl */
302 continue;
303 for (; j <= apic_vectortoipl[i]; j++) {
304 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
305 APIC_BASE_VECT;
306 }
307 }
308 for (; j < MAXIPL + 1; j++)
309 /* fill up any empty ipltopri slots */
310 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
311 apic_init_common();
312
313 /*
314 * For pcplusmp, we'll keep things simple and always disable this.
315 */
316 smt_intr_alloc_pil(XC_CPUPOKE_PIL);
317
318 apic_pir_vect = apic_get_ipivect(XC_CPUPOKE_PIL, -1);
319
320 }
321
322 static void
apic_init_intr(void)323 apic_init_intr(void)
324 {
325 processorid_t cpun = psm_get_cpu_id();
326 uint_t nlvt;
327 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
328
329 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
330
331 ASSERT(apic_mode == LOCAL_APIC);
332
333 /*
334 * We are running APIC in MMIO mode.
335 */
336 if (apic_flat_model) {
337 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_FLAT_MODEL);
338 } else {
339 apic_reg_ops->apic_write(APIC_FORMAT_REG, APIC_CLUSTER_MODEL);
340 }
341
342 apic_reg_ops->apic_write(APIC_DEST_REG, AV_HIGH_ORDER >> cpun);
343
344 if (apic_directed_EOI_supported()) {
345 /*
346 * Setting the 12th bit in the Spurious Interrupt Vector
347 * Register suppresses broadcast EOIs generated by the local
348 * APIC. The suppression of broadcast EOIs happens only when
349 * interrupts are level-triggered.
350 */
351 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
352 }
353
354 /* need to enable APIC before unmasking NMI */
355 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
356
357 /*
358 * Presence of an invalid vector with delivery mode AV_FIXED can
359 * cause an error interrupt, even if the entry is masked...so
360 * write a valid vector to LVT entries along with the mask bit
361 */
362
363 /* All APICs have timer and LINT0/1 */
364 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
365 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
366 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
367
368 /*
369 * On integrated APICs, the number of LVT entries is
370 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
371 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
372 */
373
374 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
375 nlvt = 3;
376 } else {
377 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
378 0xFF) + 1;
379 }
380
381 if (nlvt >= 5) {
382 /* Enable performance counter overflow interrupt */
383
384 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
385 apic_enable_cpcovf_intr = 0;
386 if (apic_enable_cpcovf_intr) {
387 if (apic_cpcovf_vect == 0) {
388 int ipl = APIC_PCINT_IPL;
389 int irq = apic_get_ipivect(ipl, -1);
390
391 ASSERT(irq != -1);
392 apic_cpcovf_vect =
393 apic_irq_table[irq]->airq_vector;
394 ASSERT(apic_cpcovf_vect);
395 (void) add_avintr(NULL, ipl,
396 (avfunc)kcpc_hw_overflow_intr,
397 "apic pcint", irq, NULL, NULL, NULL, NULL);
398 kcpc_hw_overflow_intr_installed = 1;
399 kcpc_hw_enable_cpc_intr =
400 apic_cpcovf_mask_clear;
401 }
402 apic_reg_ops->apic_write(APIC_PCINT_VECT,
403 apic_cpcovf_vect);
404 }
405 }
406
407 if (nlvt >= 6) {
408 /* Only mask TM intr if the BIOS apparently doesn't use it */
409
410 uint32_t lvtval;
411
412 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
413 if (((lvtval & AV_MASK) == AV_MASK) ||
414 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
415 apic_reg_ops->apic_write(APIC_THERM_VECT,
416 AV_MASK|APIC_RESV_IRQ);
417 }
418 }
419
420 /* Enable error interrupt */
421
422 if (nlvt >= 4 && apic_enable_error_intr) {
423 if (apic_errvect == 0) {
424 int ipl = 0xf; /* get highest priority intr */
425 int irq = apic_get_ipivect(ipl, -1);
426
427 ASSERT(irq != -1);
428 apic_errvect = apic_irq_table[irq]->airq_vector;
429 ASSERT(apic_errvect);
430 /*
431 * Not PSMI compliant, but we are going to merge
432 * with ON anyway
433 */
434 (void) add_avintr((void *)NULL, ipl,
435 (avfunc)apic_error_intr, "apic error intr",
436 irq, NULL, NULL, NULL, NULL);
437 }
438 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
439 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
440 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
441 }
442
443 /*
444 * Ensure a CMCI interrupt is allocated, regardless of whether it is
445 * enabled or not.
446 */
447 if (apic_cmci_vect == 0) {
448 const int ipl = 0x2;
449 int irq = apic_get_ipivect(ipl, -1);
450
451 ASSERT(irq != -1);
452 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
453 ASSERT(apic_cmci_vect);
454
455 (void) add_avintr(NULL, ipl,
456 (avfunc)cmi_cmci_trap,
457 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
458 }
459 }
460
461 static void
apic_picinit(void)462 apic_picinit(void)
463 {
464 int i, j;
465 uint_t isr;
466
467 /*
468 * Initialize and enable interrupt remapping before apic
469 * hardware initialization
470 */
471 apic_intrmap_init(apic_mode);
472
473 /*
474 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
475 * bit on without clearing it with EOI. Since softint
476 * uses vector 0x20 to interrupt itself, so softint will
477 * not work on this machine. In order to fix this problem
478 * a check is made to verify all the isr bits are clear.
479 * If not, EOIs are issued to clear the bits.
480 */
481 for (i = 7; i >= 1; i--) {
482 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
483 if (isr != 0)
484 for (j = 0; ((j < 32) && (isr != 0)); j++)
485 if (isr & (1 << j)) {
486 apic_reg_ops->apic_write(
487 APIC_EOI_REG, 0);
488 isr &= ~(1 << j);
489 apic_error |= APIC_ERR_BOOT_EOI;
490 }
491 }
492
493 /* set a flag so we know we have run apic_picinit() */
494 apic_picinit_called = 1;
495 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
496 LOCK_INIT_CLEAR(&apic_ioapic_lock);
497 LOCK_INIT_CLEAR(&apic_error_lock);
498 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
499
500 picsetup(); /* initialise the 8259 */
501
502 /* add nmi handler - least priority nmi handler */
503 LOCK_INIT_CLEAR(&apic_nmi_lock);
504
505 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
506 "pcplusmp NMI handler", (caddr_t)NULL))
507 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
508
509 /*
510 * Check for directed-EOI capability in the local APIC.
511 */
512 if (apic_directed_EOI_supported() == 1) {
513 apic_set_directed_EOI_handler();
514 }
515
516 apic_init_intr();
517
518 /* enable apic mode if imcr present */
519 if (apic_imcrp) {
520 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
521 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
522 }
523
524 ioapic_init_intr(IOAPIC_MASK);
525 }
526
527 #ifdef DEBUG
528 void
apic_break(void)529 apic_break(void)
530 {
531 }
532 #endif /* DEBUG */
533
534 /*
535 * platform_intr_enter
536 *
537 * Called at the beginning of the interrupt service routine to
538 * mask all level equal to and below the interrupt priority
539 * of the interrupting vector. An EOI should be given to
540 * the interrupt controller to enable other HW interrupts.
541 *
542 * Return -1 for spurious interrupts
543 *
544 */
545 /*ARGSUSED*/
546 static int
apic_intr_enter(int ipl,int * vectorp)547 apic_intr_enter(int ipl, int *vectorp)
548 {
549 uchar_t vector;
550 int nipl;
551 int irq;
552 ulong_t iflag;
553 apic_cpus_info_t *cpu_infop;
554
555 /*
556 * The real vector delivered is (*vectorp + 0x20), but our caller
557 * subtracts 0x20 from the vector before passing it to us.
558 * (That's why APIC_BASE_VECT is 0x20.)
559 */
560 vector = (uchar_t)*vectorp;
561
562 /* if interrupted by the clock, increment apic_nsec_since_boot */
563 if (vector == apic_clkvect) {
564 if (!apic_oneshot) {
565 /* NOTE: this is not MT aware */
566 apic_hrtime_stamp++;
567 apic_nsec_since_boot += apic_nsec_per_intr;
568 apic_hrtime_stamp++;
569 last_count_read = apic_hertz_count;
570 apic_redistribute_compute();
571 }
572
573 /* We will avoid all the book keeping overhead for clock */
574 nipl = apic_ipls[vector];
575
576 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
577
578 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
579 apic_reg_ops->apic_send_eoi(0);
580
581 return (nipl);
582 }
583
584 cpu_infop = &apic_cpus[psm_get_cpu_id()];
585
586 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
587 cpu_infop->aci_spur_cnt++;
588 return (APIC_INT_SPURIOUS);
589 }
590
591 /* Check if the vector we got is really what we need */
592 if (apic_revector_pending) {
593 /*
594 * Disable interrupts for the duration of
595 * the vector translation to prevent a self-race for
596 * the apic_revector_lock. This cannot be done
597 * in apic_xlate_vector because it is recursive and
598 * we want the vector translation to be atomic with
599 * respect to other (higher-priority) interrupts.
600 */
601 iflag = intr_clear();
602 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
603 APIC_BASE_VECT;
604 intr_restore(iflag);
605 }
606
607 nipl = apic_ipls[vector];
608 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
609
610 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]);
611
612 cpu_infop->aci_current[nipl] = (uchar_t)irq;
613 cpu_infop->aci_curipl = (uchar_t)nipl;
614 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
615
616 /*
617 * apic_level_intr could have been assimilated into the irq struct.
618 * but, having it as a character array is more efficient in terms of
619 * cache usage. So, we leave it as is.
620 */
621 if (!apic_level_intr[irq]) {
622 apic_reg_ops->apic_send_eoi(0);
623 }
624
625 #ifdef DEBUG
626 APIC_DEBUG_BUF_PUT(vector);
627 APIC_DEBUG_BUF_PUT(irq);
628 APIC_DEBUG_BUF_PUT(nipl);
629 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
630 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
631 drv_usecwait(apic_stretch_interrupts);
632
633 if (apic_break_on_cpu == psm_get_cpu_id())
634 apic_break();
635 #endif /* DEBUG */
636 return (nipl);
637 }
638
639 void
apic_intr_exit(int prev_ipl,int irq)640 apic_intr_exit(int prev_ipl, int irq)
641 {
642 apic_cpus_info_t *cpu_infop;
643
644 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]);
645
646 cpu_infop = &apic_cpus[psm_get_cpu_id()];
647 if (apic_level_intr[irq])
648 apic_reg_ops->apic_send_eoi(irq);
649 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
650 /* ISR above current pri could not be in progress */
651 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
652 }
653
654 intr_exit_fn_t
psm_intr_exit_fn(void)655 psm_intr_exit_fn(void)
656 {
657 return (apic_intr_exit);
658 }
659
660 /*
661 * Mask all interrupts below or equal to the given IPL.
662 */
663 static void
apic_setspl(int ipl)664 apic_setspl(int ipl)
665 {
666 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]);
667
668 /* interrupts at ipl above this cannot be in progress */
669 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
670 /*
671 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
672 * have enough time to come in before the priority is raised again
673 * during the idle() loop.
674 */
675 if (apic_setspl_delay)
676 (void) apic_reg_ops->apic_get_pri();
677 }
678
679 /*ARGSUSED*/
680 static int
apic_addspl(int irqno,int ipl,int min_ipl,int max_ipl)681 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
682 {
683 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
684 }
685
686 static int
apic_delspl(int irqno,int ipl,int min_ipl,int max_ipl)687 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
688 {
689 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
690 }
691
692 static int
apic_post_cpu_start(void)693 apic_post_cpu_start(void)
694 {
695 int cpun;
696 static int cpus_started = 1;
697
698 /* We know this CPU + BSP started successfully. */
699 cpus_started++;
700
701 splx(ipltospl(LOCK_LEVEL));
702 apic_init_intr();
703
704 APIC_AV_PENDING_SET();
705
706 /*
707 * We may be booting, or resuming from suspend; aci_status will
708 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
709 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
710 */
711 cpun = psm_get_cpu_id();
712 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
713
714 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
715 return (PSM_SUCCESS);
716 }
717
718 /*
719 * type == -1 indicates it is an internal request. Do not change
720 * resv_vector for these requests
721 */
722 static int
apic_get_ipivect(int ipl,int type)723 apic_get_ipivect(int ipl, int type)
724 {
725 uchar_t vector;
726 int irq;
727
728 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
729 if ((vector = apic_allocate_vector(ipl, irq, 1))) {
730 apic_irq_table[irq]->airq_mps_intr_index =
731 RESERVE_INDEX;
732 apic_irq_table[irq]->airq_vector = vector;
733 if (type != -1) {
734 apic_resv_vector[ipl] = vector;
735 }
736 return (irq);
737 }
738 }
739 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
740 return (-1); /* shouldn't happen */
741 }
742
743 static int
apic_getclkirq(int ipl)744 apic_getclkirq(int ipl)
745 {
746 int irq;
747
748 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
749 return (-1);
750 /*
751 * Note the vector in apic_clkvect for per clock handling.
752 */
753 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
754 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
755 apic_clkvect));
756 return (irq);
757 }
758
759 /*
760 * Try and disable all interrupts. We just assign interrupts to other
761 * processors based on policy. If any were bound by user request, we
762 * let them continue and return failure. We do not bother to check
763 * for cache affinity while rebinding.
764 */
765
766 static int
apic_disable_intr(processorid_t cpun)767 apic_disable_intr(processorid_t cpun)
768 {
769 int bind_cpu = 0, i, hardbound = 0;
770 apic_irq_t *irq_ptr;
771 ulong_t iflag;
772
773 iflag = intr_clear();
774 lock_set(&apic_ioapic_lock);
775
776 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
777 if (apic_reprogram_info[i].done == B_FALSE) {
778 if (apic_reprogram_info[i].bindcpu == cpun) {
779 /*
780 * CPU is busy -- it's the target of
781 * a pending reprogramming attempt
782 */
783 lock_clear(&apic_ioapic_lock);
784 intr_restore(iflag);
785 return (PSM_FAILURE);
786 }
787 }
788 }
789
790 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
791
792 apic_cpus[cpun].aci_curipl = 0;
793
794 i = apic_min_device_irq;
795 for (; i <= apic_max_device_irq; i++) {
796 /*
797 * If there are bound interrupts on this cpu, then
798 * rebind them to other processors.
799 */
800 if ((irq_ptr = apic_irq_table[i]) != NULL) {
801 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
802 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
803 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
804
805 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
806 hardbound = 1;
807 continue;
808 }
809
810 if (irq_ptr->airq_temp_cpu == cpun) {
811 do {
812 bind_cpu =
813 apic_find_cpu(APIC_CPU_INTR_ENABLE);
814 } while (apic_rebind_all(irq_ptr, bind_cpu));
815 }
816 }
817 }
818
819 lock_clear(&apic_ioapic_lock);
820 intr_restore(iflag);
821
822 if (hardbound) {
823 cmn_err(CE_WARN, "Could not disable interrupts on %d"
824 "due to user bound interrupts", cpun);
825 return (PSM_FAILURE);
826 }
827 else
828 return (PSM_SUCCESS);
829 }
830
831 /*
832 * Bind interrupts to the CPU's local APIC.
833 * Interrupts should not be bound to a CPU's local APIC until the CPU
834 * is ready to receive interrupts.
835 */
836 static void
apic_enable_intr(processorid_t cpun)837 apic_enable_intr(processorid_t cpun)
838 {
839 int i;
840 apic_irq_t *irq_ptr;
841 ulong_t iflag;
842
843 iflag = intr_clear();
844 lock_set(&apic_ioapic_lock);
845
846 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
847
848 i = apic_min_device_irq;
849 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
850 if ((irq_ptr = apic_irq_table[i]) != NULL) {
851 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
852 (void) apic_rebind_all(irq_ptr,
853 irq_ptr->airq_cpu);
854 }
855 }
856 }
857
858 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
859 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
860
861 lock_clear(&apic_ioapic_lock);
862 intr_restore(iflag);
863 }
864
865 /*
866 * If this module needs a periodic handler for the interrupt distribution, it
867 * can be added here. The argument to the periodic handler is not currently
868 * used, but is reserved for future.
869 */
870 static void
apic_post_cyclic_setup(void * arg)871 apic_post_cyclic_setup(void *arg)
872 {
873 _NOTE(ARGUNUSED(arg))
874
875 cyc_handler_t cyh;
876 cyc_time_t cyt;
877
878 /* cpu_lock is held */
879 /* set up a periodic handler for intr redistribution */
880
881 /*
882 * In peridoc mode intr redistribution processing is done in
883 * apic_intr_enter during clk intr processing
884 */
885 if (!apic_oneshot)
886 return;
887
888 /*
889 * Register a periodical handler for the redistribution processing.
890 * Though we would generally prefer to use the DDI interface for
891 * periodic handler invocation, ddi_periodic_add(9F), we are
892 * unfortunately already holding cpu_lock, which ddi_periodic_add will
893 * attempt to take for us. Thus, we add our own cyclic directly:
894 */
895 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
896 cyh.cyh_arg = NULL;
897 cyh.cyh_level = CY_LOW_LEVEL;
898
899 cyt.cyt_when = 0;
900 cyt.cyt_interval = apic_redistribute_sample_interval;
901
902 apic_cyclic_id = cyclic_add(&cyh, &cyt);
903 }
904
905 static void
apic_redistribute_compute(void)906 apic_redistribute_compute(void)
907 {
908 int i, j, max_busy;
909
910 if (apic_enable_dynamic_migration) {
911 if (++apic_nticks == apic_sample_factor_redistribution) {
912 /*
913 * Time to call apic_intr_redistribute().
914 * reset apic_nticks. This will cause max_busy
915 * to be calculated below and if it is more than
916 * apic_int_busy, we will do the whole thing
917 */
918 apic_nticks = 0;
919 }
920 max_busy = 0;
921 for (i = 0; i < apic_nproc; i++) {
922 if (!apic_cpu_in_range(i))
923 continue;
924
925 /*
926 * Check if curipl is non zero & if ISR is in
927 * progress
928 */
929 if (((j = apic_cpus[i].aci_curipl) != 0) &&
930 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
931
932 int irq;
933 apic_cpus[i].aci_busy++;
934 irq = apic_cpus[i].aci_current[j];
935 apic_irq_table[irq]->airq_busy++;
936 }
937
938 if (!apic_nticks &&
939 (apic_cpus[i].aci_busy > max_busy))
940 max_busy = apic_cpus[i].aci_busy;
941 }
942 if (!apic_nticks) {
943 if (max_busy > apic_int_busy_mark) {
944 /*
945 * We could make the following check be
946 * skipped > 1 in which case, we get a
947 * redistribution at half the busy mark (due to
948 * double interval). Need to be able to collect
949 * more empirical data to decide if that is a
950 * good strategy. Punt for now.
951 */
952 if (apic_skipped_redistribute) {
953 apic_cleanup_busy();
954 apic_skipped_redistribute = 0;
955 } else {
956 apic_intr_redistribute();
957 }
958 } else
959 apic_skipped_redistribute++;
960 }
961 }
962 }
963
964
965 /*
966 * The following functions are in the platform specific file so that they
967 * can be different functions depending on whether we are running on
968 * bare metal or a hypervisor.
969 */
970
971 /*
972 * Check to make sure there are enough irq slots
973 */
974 int
apic_check_free_irqs(int count)975 apic_check_free_irqs(int count)
976 {
977 int i, avail;
978
979 avail = 0;
980 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
981 if ((apic_irq_table[i] == NULL) ||
982 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
983 if (++avail >= count)
984 return (PSM_SUCCESS);
985 }
986 }
987 return (PSM_FAILURE);
988 }
989
990 /*
991 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
992 */
993 int
apic_alloc_msi_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)994 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
995 int behavior)
996 {
997 int rcount, i;
998 uchar_t start, irqno;
999 uint32_t cpu = 0;
1000 major_t major;
1001 apic_irq_t *irqptr;
1002
1003 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1004 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1005 (void *)dip, inum, pri, count, behavior));
1006
1007 if (count > 1) {
1008 if (behavior == DDI_INTR_ALLOC_STRICT &&
1009 apic_multi_msi_enable == 0)
1010 return (0);
1011 if (apic_multi_msi_enable == 0)
1012 count = 1;
1013 }
1014
1015 if ((rcount = apic_navail_vector(dip, pri)) > count)
1016 rcount = count;
1017 else if (rcount == 0 || (rcount < count &&
1018 behavior == DDI_INTR_ALLOC_STRICT))
1019 return (0);
1020
1021 /* if not ISP2, then round it down */
1022 if (!ISP2(rcount))
1023 rcount = 1 << (highbit(rcount) - 1);
1024
1025 mutex_enter(&airq_mutex);
1026
1027 for (start = 0; rcount > 0; rcount >>= 1) {
1028 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1029 behavior == DDI_INTR_ALLOC_STRICT)
1030 break;
1031 }
1032
1033 if (start == 0) {
1034 /* no vector available */
1035 mutex_exit(&airq_mutex);
1036 return (0);
1037 }
1038
1039 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1040 /* not enough free irq slots available */
1041 mutex_exit(&airq_mutex);
1042 return (0);
1043 }
1044
1045 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1046 for (i = 0; i < rcount; i++) {
1047 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1048 (uchar_t)-1) {
1049 /*
1050 * shouldn't happen because of the
1051 * apic_check_free_irqs() check earlier
1052 */
1053 mutex_exit(&airq_mutex);
1054 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1055 "apic_allocate_irq failed\n"));
1056 return (i);
1057 }
1058 apic_max_device_irq = max(irqno, apic_max_device_irq);
1059 apic_min_device_irq = min(irqno, apic_min_device_irq);
1060 irqptr = apic_irq_table[irqno];
1061 #ifdef DEBUG
1062 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1063 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1064 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1065 #endif
1066 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1067
1068 irqptr->airq_vector = (uchar_t)(start + i);
1069 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1070 irqptr->airq_intin_no = (uchar_t)rcount;
1071 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1072 irqptr->airq_ipl = (uchar_t)pri;
1073 irqptr->airq_vector = start + i;
1074 irqptr->airq_origirq = (uchar_t)(inum + i);
1075 irqptr->airq_share_id = 0;
1076 irqptr->airq_mps_intr_index = MSI_INDEX;
1077 irqptr->airq_dip = dip;
1078 irqptr->airq_major = major;
1079 if (i == 0) /* they all bound to the same cpu */
1080 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1081 0xff, 0xff);
1082 else
1083 irqptr->airq_cpu = cpu;
1084 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1085 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1086 (void *)irqptr->airq_dip, irqptr->airq_vector,
1087 irqptr->airq_origirq, pri));
1088 }
1089 mutex_exit(&airq_mutex);
1090 return (rcount);
1091 }
1092
1093 /*
1094 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1095 */
1096 int
apic_alloc_msix_vectors(dev_info_t * dip,int inum,int count,int pri,int behavior)1097 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1098 int behavior)
1099 {
1100 int rcount, i;
1101 major_t major;
1102
1103 mutex_enter(&airq_mutex);
1104
1105 if ((rcount = apic_navail_vector(dip, pri)) > count)
1106 rcount = count;
1107 else if (rcount == 0 || (rcount < count &&
1108 behavior == DDI_INTR_ALLOC_STRICT)) {
1109 rcount = 0;
1110 goto out;
1111 }
1112
1113 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1114 /* not enough free irq slots available */
1115 rcount = 0;
1116 goto out;
1117 }
1118
1119 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1120 for (i = 0; i < rcount; i++) {
1121 uchar_t vector, irqno;
1122 apic_irq_t *irqptr;
1123
1124 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1125 (uchar_t)-1) {
1126 /*
1127 * shouldn't happen because of the
1128 * apic_check_free_irqs() check earlier
1129 */
1130 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1131 "apic_allocate_irq failed\n"));
1132 rcount = i;
1133 goto out;
1134 }
1135 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1136 /*
1137 * shouldn't happen because of the
1138 * apic_navail_vector() call earlier
1139 */
1140 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1141 "apic_allocate_vector failed\n"));
1142 rcount = i;
1143 goto out;
1144 }
1145 apic_max_device_irq = max(irqno, apic_max_device_irq);
1146 apic_min_device_irq = min(irqno, apic_min_device_irq);
1147 irqptr = apic_irq_table[irqno];
1148 irqptr->airq_vector = (uchar_t)vector;
1149 ASSERT(pri >= 0 && pri <= UCHAR_MAX);
1150 irqptr->airq_ipl = (uchar_t)pri;
1151 irqptr->airq_origirq = (uchar_t)(inum + i);
1152 irqptr->airq_share_id = 0;
1153 irqptr->airq_mps_intr_index = MSIX_INDEX;
1154 irqptr->airq_dip = dip;
1155 irqptr->airq_major = major;
1156 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1157 }
1158 out:
1159 mutex_exit(&airq_mutex);
1160 return (rcount);
1161 }
1162
1163 /*
1164 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1165 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1166 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1167 * requests and allocated only when pri is set.
1168 */
1169 uchar_t
apic_allocate_vector(int ipl,int irq,int pri)1170 apic_allocate_vector(int ipl, int irq, int pri)
1171 {
1172 int lowest, highest, i;
1173
1174 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1175 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1176
1177 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1178 lowest -= APIC_VECTOR_PER_IPL;
1179
1180 #ifdef DEBUG
1181 if (apic_restrict_vector) /* for testing shared interrupt logic */
1182 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1183 #endif /* DEBUG */
1184 if (pri == 0)
1185 highest -= APIC_HI_PRI_VECTS;
1186
1187 for (i = lowest; i <= highest; i++) {
1188 if (APIC_CHECK_RESERVE_VECTORS(i))
1189 continue;
1190 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1191 apic_vector_to_irq[i] = (uchar_t)irq;
1192 ASSERT(i >= 0 && i <= UCHAR_MAX);
1193 return ((uchar_t)i);
1194 }
1195 }
1196
1197 return (0);
1198 }
1199
1200 /* Mark vector as not being used by any irq */
1201 void
apic_free_vector(uchar_t vector)1202 apic_free_vector(uchar_t vector)
1203 {
1204 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1205 }
1206
1207 /*
1208 * Call rebind to do the actual programming.
1209 * Must be called with interrupts disabled and apic_ioapic_lock held
1210 * 'p' is polymorphic -- if this function is called to process a deferred
1211 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1212 * the irq pointer is retrieved. If not doing deferred reprogramming,
1213 * p is of the type 'apic_irq_t *'.
1214 *
1215 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1216 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1217 * taken offline after a cpu is selected, but before apic_rebind is called to
1218 * bind interrupts to it.
1219 */
1220 int
apic_setup_io_intr(void * p,int irq,boolean_t deferred)1221 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1222 {
1223 apic_irq_t *irqptr;
1224 struct ioapic_reprogram_data *drep = NULL;
1225 int rv;
1226
1227 if (deferred) {
1228 drep = (struct ioapic_reprogram_data *)p;
1229 ASSERT(drep != NULL);
1230 irqptr = drep->irqp;
1231 } else
1232 irqptr = (apic_irq_t *)p;
1233
1234 ASSERT(irqptr != NULL);
1235
1236 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1237 if (rv) {
1238 /*
1239 * CPU is not up or interrupts are disabled. Fall back to
1240 * the first available CPU
1241 */
1242 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1243 drep);
1244 }
1245
1246 return (rv);
1247 }
1248
1249
1250 uchar_t
apic_modify_vector(uchar_t vector,int irq)1251 apic_modify_vector(uchar_t vector, int irq)
1252 {
1253 apic_vector_to_irq[vector] = (uchar_t)irq;
1254 return (vector);
1255 }
1256
1257 char *
apic_get_apic_type(void)1258 apic_get_apic_type(void)
1259 {
1260 return (apic_psm_info.p_mach_idstring);
1261 }
1262
1263 void
apic_switch_ipi_callback(boolean_t enter)1264 apic_switch_ipi_callback(boolean_t enter)
1265 {
1266 ASSERT(enter == B_TRUE);
1267 }
1268
1269 int
apic_detect_x2apic(void)1270 apic_detect_x2apic(void)
1271 {
1272 return (0);
1273 }
1274
1275 void
apic_enable_x2apic(void)1276 apic_enable_x2apic(void)
1277 {
1278 cmn_err(CE_PANIC, "apic_enable_x2apic() called in pcplusmp");
1279 }
1280
1281 void
x2apic_update_psm(void)1282 x2apic_update_psm(void)
1283 {
1284 cmn_err(CE_PANIC, "x2apic_update_psm() called in pcplusmp");
1285 }
1286