1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21/*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 * Copyright (c) 2019, Joyent, Inc.
26 */
27/*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
31
32/*
33 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
34 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
35 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
36 * PSMI 1.5 extensions are supported in Solaris Nevada.
37 * PSMI 1.6 extensions are supported in Solaris Nevada.
38 * PSMI 1.7 extensions are supported in Solaris Nevada.
39 */
40#define	PSMI_1_7
41
42#include <sys/processor.h>
43#include <sys/time.h>
44#include <sys/psm.h>
45#include <sys/smp_impldefs.h>
46#include <sys/cram.h>
47#include <sys/acpi/acpi.h>
48#include <sys/acpica.h>
49#include <sys/psm_common.h>
50#include <sys/apic.h>
51#include <sys/apic_timer.h>
52#include <sys/pit.h>
53#include <sys/ddi.h>
54#include <sys/sunddi.h>
55#include <sys/ddi_impldefs.h>
56#include <sys/pci.h>
57#include <sys/promif.h>
58#include <sys/x86_archext.h>
59#include <sys/cpc_impl.h>
60#include <sys/uadmin.h>
61#include <sys/panic.h>
62#include <sys/debug.h>
63#include <sys/archsystm.h>
64#include <sys/trap.h>
65#include <sys/machsystm.h>
66#include <sys/cpuvar.h>
67#include <sys/rm_platter.h>
68#include <sys/privregs.h>
69#include <sys/cyclic.h>
70#include <sys/note.h>
71#include <sys/pci_intr_lib.h>
72#include <sys/sunndi.h>
73#if !defined(__xpv)
74#include <sys/hpet.h>
75#include <sys/clock.h>
76#endif
77
78/*
79 *	Local Function Prototypes
80 */
81static int apic_handle_defconf();
82static int apic_parse_mpct(caddr_t mpct, int bypass);
83static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
84static int apic_checksum(caddr_t bptr, int len);
85static int apic_find_bus_type(char *bus);
86static int apic_find_bus(int busid);
87static struct apic_io_intr *apic_find_io_intr(int irqno);
88static int apic_find_free_irq(int start, int end);
89struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
90static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
91static void apic_free_apic_cpus(void);
92static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
93static int apic_acpi_enter_apicmode(void);
94
95int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
96    int child_ipin, struct apic_io_intr **intrp);
97int apic_find_bus_id(int bustype);
98int apic_find_intin(uchar_t ioapic, uchar_t intin);
99void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
100
101int apic_debug_mps_id = 0;	/* 1 - print MPS ID strings */
102
103/* ACPI SCI interrupt configuration; -1 if SCI not used */
104int apic_sci_vect = -1;
105iflag_t apic_sci_flags;
106
107#if !defined(__xpv)
108/* ACPI HPET interrupt configuration; -1 if HPET not used */
109int apic_hpet_vect = -1;
110iflag_t apic_hpet_flags;
111#endif
112
113/*
114 * psm name pointer
115 */
116char *psm_name;
117
118/* ACPI support routines */
119static int acpi_probe(char *);
120static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
121    int *pci_irqp, iflag_t *intr_flagp);
122
123int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
124    int ipin, int *pci_irqp, iflag_t *intr_flagp);
125uchar_t acpi_find_ioapic(int irq);
126static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
127
128/* Max wait time (in repetitions) for flags to clear in an RDT entry. */
129int apic_max_reps_clear_pending = 1000;
130
131int	apic_intr_policy = INTR_ROUND_ROBIN;
132
133int	apic_next_bind_cpu = 1; /* For round robin assignment */
134				/* start with cpu 1 */
135
136/*
137 * If enabled, the distribution works as follows:
138 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
139 * and the irq corresponding to the ipl is also set in the aci_current array.
140 * interrupt exit and setspl (due to soft interrupts) will cause the current
141 * ipl to be be changed. This is cache friendly as these frequently used
142 * paths write into a per cpu structure.
143 *
144 * Sampling is done by checking the structures for all CPUs and incrementing
145 * the busy field of the irq (if any) executing on each CPU and the busy field
146 * of the corresponding CPU.
147 * In periodic mode this is done on every clock interrupt.
148 * In one-shot mode, this is done thru a cyclic with an interval of
149 * apic_redistribute_sample_interval (default 10 milli sec).
150 *
151 * Every apic_sample_factor_redistribution times we sample, we do computations
152 * to decide which interrupt needs to be migrated (see comments
153 * before apic_intr_redistribute().
154 */
155
156/*
157 * Following 3 variables start as % and can be patched or set using an
158 * API to be defined in future. They will be scaled to
159 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
160 * mode), or 101 in one-shot mode to stagger it away from one sec processing
161 */
162
163int	apic_int_busy_mark = 60;
164int	apic_int_free_mark = 20;
165int	apic_diff_for_redistribution = 10;
166
167/* sampling interval for interrupt redistribution for dynamic migration */
168int	apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
169
170/*
171 * number of times we sample before deciding to redistribute interrupts
172 * for dynamic migration
173 */
174int	apic_sample_factor_redistribution = 101;
175
176int	apic_redist_cpu_skip = 0;
177int	apic_num_imbalance = 0;
178int	apic_num_rebind = 0;
179
180/*
181 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
182 * allocation of CPU ids is disabled.
183 */
184int 	apic_max_nproc = -1;
185int	apic_nproc = 0;
186size_t	apic_cpus_size = 0;
187int	apic_defconf = 0;
188int	apic_irq_translate = 0;
189int	apic_spec_rev = 0;
190int	apic_imcrp = 0;
191
192int	apic_use_acpi = 1;	/* 1 = use ACPI, 0 = don't use ACPI */
193int	apic_use_acpi_madt_only = 0;	/* 1=ONLY use MADT from ACPI */
194
195/*
196 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
197 * will be assigned (via _SRS). If it is not set, use the current
198 * irq setting (via _CRS), but only if that irq is in the set of possible
199 * irqs (returned by _PRS) for the device.
200 */
201int	apic_unconditional_srs = 1;
202
203/*
204 * For interrupt link devices, if apic_prefer_crs is set when we are
205 * assigning an IRQ resource to a device, prefer the current IRQ setting
206 * over other possible irq settings under same conditions.
207 */
208
209int	apic_prefer_crs = 1;
210
211uchar_t apic_io_id[MAX_IO_APIC];
212volatile uint32_t *apicioadr[MAX_IO_APIC];
213uchar_t	apic_io_ver[MAX_IO_APIC];
214uchar_t	apic_io_vectbase[MAX_IO_APIC];
215uchar_t	apic_io_vectend[MAX_IO_APIC];
216uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
217uint32_t apic_physaddr[MAX_IO_APIC];
218
219boolean_t ioapic_mask_workaround[MAX_IO_APIC];
220
221/*
222 * First available slot to be used as IRQ index into the apic_irq_table
223 * for those interrupts (like MSI/X) that don't have a physical IRQ.
224 */
225int apic_first_avail_irq  = APIC_FIRST_FREE_IRQ;
226
227/*
228 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
229 * and bound elements of cpus_info and the temp_cpu element of irq_struct
230 */
231lock_t	apic_ioapic_lock;
232
233int	apic_io_max = 0;	/* no. of i/o apics enabled */
234
235struct apic_io_intr *apic_io_intrp = NULL;
236static	struct apic_bus	*apic_busp;
237
238uchar_t	apic_resv_vector[MAXIPL+1];
239
240char	apic_level_intr[APIC_MAX_VECTOR+1];
241
242uint32_t	eisa_level_intr_mask = 0;
243	/* At least MSB will be set if EISA bus */
244
245int	apic_pci_bus_total = 0;
246uchar_t	apic_single_pci_busid = 0;
247
248/*
249 * airq_mutex protects additions to the apic_irq_table - the first
250 * pointer and any airq_nexts off of that one. It also protects
251 * apic_max_device_irq & apic_min_device_irq. It also guarantees
252 * that share_id is unique as new ids are generated only when new
253 * irq_t structs are linked in. Once linked in the structs are never
254 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
255 * or allocated. Note that there is a slight gap between allocating in
256 * apic_introp_xlate and programming in addspl.
257 */
258kmutex_t	airq_mutex;
259apic_irq_t	*apic_irq_table[APIC_MAX_VECTOR+1];
260int		apic_max_device_irq = 0;
261int		apic_min_device_irq = APIC_MAX_VECTOR;
262
263typedef struct prs_irq_list_ent {
264	int			list_prio;
265	int32_t			irq;
266	iflag_t			intrflags;
267	acpi_prs_private_t	prsprv;
268	struct prs_irq_list_ent	*next;
269} prs_irq_list_t;
270
271
272/*
273 * ACPI variables
274 */
275/* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
276int apic_enable_acpi = 0;
277
278/* ACPI Multiple APIC Description Table ptr */
279static	ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
280
281/* ACPI Interrupt Source Override Structure ptr */
282ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
283int acpi_iso_cnt = 0;
284
285/* ACPI Non-maskable Interrupt Sources ptr */
286static	ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
287static	int acpi_nmi_scnt = 0;
288static	ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
289static	int acpi_nmi_ccnt = 0;
290
291static	boolean_t acpi_found_smp_config = B_FALSE;
292
293/*
294 * The following added to identify a software poweroff method if available.
295 */
296
297static struct {
298	int	poweroff_method;
299	char	oem_id[APIC_MPS_OEM_ID_LEN + 1];	/* MAX + 1 for NULL */
300	char	prod_id[APIC_MPS_PROD_ID_LEN + 1];	/* MAX + 1 for NULL */
301} apic_mps_ids[] = {
302	{ APIC_POWEROFF_VIA_RTC,	"INTEL",	"ALDER" },   /* 4300 */
303	{ APIC_POWEROFF_VIA_RTC,	"NCR",		"AMC" },    /* 4300 */
304	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"A450NX" },  /* 4400? */
305	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"AD450NX" }, /* 4400 */
306	{ APIC_POWEROFF_VIA_ASPEN_BMC,	"INTEL",	"AC450NX" }, /* 4400R */
307	{ APIC_POWEROFF_VIA_SITKA_BMC,	"INTEL",	"S450NX" },  /* S50  */
308	{ APIC_POWEROFF_VIA_SITKA_BMC,	"INTEL",	"SC450NX" }  /* S50? */
309};
310
311int	apic_poweroff_method = APIC_POWEROFF_NONE;
312
313/*
314 * Auto-configuration routines
315 */
316
317/*
318 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
319 * May work with 1.1 - but not guaranteed.
320 * According to the MP Spec, the MP floating pointer structure
321 * will be searched in the order described below:
322 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
323 * 2. Within the last kilobyte of system base memory
324 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
325 * Once we find the right signature with proper checksum, we call
326 * either handle_defconf or parse_mpct to get all info necessary for
327 * subsequent operations.
328 */
329int
330apic_probe_common(char *modname)
331{
332	uint32_t mpct_addr, ebda_start = 0, base_mem_end;
333	caddr_t	biosdatap;
334	caddr_t	mpct = NULL;
335	caddr_t	fptr;
336	int	i, mpct_size = 0, mapsize, retval = PSM_FAILURE;
337	ushort_t	ebda_seg, base_mem_size;
338	struct	apic_mpfps_hdr	*fpsp;
339	struct	apic_mp_cnf_hdr	*hdrp;
340	int bypass_cpu_and_ioapics_in_mptables;
341	int acpi_user_options;
342
343	if (apic_forceload < 0)
344		return (retval);
345
346	/*
347	 * Remember who we are
348	 */
349	psm_name = modname;
350
351	/* Allow override for MADT-only mode */
352	acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
353	    "acpi-user-options", 0);
354	apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
355
356	/* Allow apic_use_acpi to override MADT-only mode */
357	if (!apic_use_acpi)
358		apic_use_acpi_madt_only = 0;
359
360	retval = acpi_probe(modname);
361
362	/* in UEFI system, there is no BIOS data */
363	if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 0, "efi-systab"))
364		goto apic_ret;
365
366	/*
367	 * mapin the bios data area 40:0
368	 * 40:13h - two-byte location reports the base memory size
369	 * 40:0Eh - two-byte location for the exact starting address of
370	 *	    the EBDA segment for EISA
371	 */
372	biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
373	if (!biosdatap)
374		goto apic_ret;
375	fpsp = (struct apic_mpfps_hdr *)NULL;
376	mapsize = MPFPS_RAM_WIN_LEN;
377	/*LINTED: pointer cast may result in improper alignment */
378	ebda_seg = *((ushort_t *)(biosdatap+0xe));
379	/* check the 1k of EBDA */
380	if (ebda_seg) {
381		ebda_start = ((uint32_t)ebda_seg) << 4;
382		fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
383		if (fptr) {
384			if (!(fpsp =
385			    apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
386				psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
387		}
388	}
389	/* If not in EBDA, check the last k of system base memory */
390	if (!fpsp) {
391		/*LINTED: pointer cast may result in improper alignment */
392		base_mem_size = *((ushort_t *)(biosdatap + 0x13));
393
394		if (base_mem_size > 512)
395			base_mem_end = 639 * 1024;
396		else
397			base_mem_end = 511 * 1024;
398		/* if ebda == last k of base mem, skip to check BIOS ROM */
399		if (base_mem_end != ebda_start) {
400
401			fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
402			    PROT_READ);
403
404			if (fptr) {
405				if (!(fpsp = apic_find_fps_sig(fptr,
406				    MPFPS_RAM_WIN_LEN)))
407					psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
408			}
409		}
410	}
411	psm_unmap_phys(biosdatap, 0x20);
412
413	/* If still cannot find it, check the BIOS ROM space */
414	if (!fpsp) {
415		mapsize = MPFPS_ROM_WIN_LEN;
416		fptr = psm_map_phys(MPFPS_ROM_WIN_START,
417		    MPFPS_ROM_WIN_LEN, PROT_READ);
418		if (fptr) {
419			if (!(fpsp =
420			    apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
421				psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
422				goto apic_ret;
423			}
424		}
425	}
426
427	if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
428		psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
429		goto apic_ret;
430	}
431
432	apic_spec_rev = fpsp->mpfps_spec_rev;
433	if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
434		psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
435		goto apic_ret;
436	}
437
438	/* check IMCR is present or not */
439	apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
440
441	/* check default configuration (dual CPUs) */
442	if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
443		psm_unmap_phys(fptr, mapsize);
444		if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
445			return (retval);
446
447		goto apic_ret;
448	}
449
450	/* MP Configuration Table */
451	mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
452
453	psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
454
455	/*
456	 * Map in enough memory for the MP Configuration Table Header.
457	 * Use this table to read the total length of the BIOS data and
458	 * map in all the info
459	 */
460	/*LINTED: pointer cast may result in improper alignment */
461	hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
462	    sizeof (struct apic_mp_cnf_hdr), PROT_READ);
463	if (!hdrp)
464		goto apic_ret;
465
466	/* check mp configuration table signature PCMP */
467	if (hdrp->mpcnf_sig != 0x504d4350) {
468		psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
469		goto apic_ret;
470	}
471	mpct_size = (int)hdrp->mpcnf_tbl_length;
472
473	apic_set_pwroff_method_from_mpcnfhdr(hdrp);
474
475	psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
476
477	if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
478		/* This is an ACPI machine No need for further checks */
479		goto apic_ret;
480	}
481
482	/*
483	 * Map in the entries for this machine, ie. Processor
484	 * Entry Tables, Bus Entry Tables, etc.
485	 * They are in fixed order following one another
486	 */
487	mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
488	if (!mpct)
489		goto apic_ret;
490
491	if (apic_checksum(mpct, mpct_size) != 0)
492		goto apic_fail1;
493
494	/*LINTED: pointer cast may result in improper alignment */
495	hdrp = (struct apic_mp_cnf_hdr *)mpct;
496	apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
497	    APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
498	if (!apicadr)
499		goto apic_fail1;
500
501	/* Parse all information in the tables */
502	bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
503	if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
504	    PSM_SUCCESS) {
505		retval = PSM_SUCCESS;
506		goto apic_ret;
507	}
508
509apic_fail1:
510	psm_unmap_phys(mpct, mpct_size);
511	mpct = NULL;
512
513apic_ret:
514	if (retval == PSM_SUCCESS) {
515		extern int apic_ioapic_method_probe();
516
517		if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
518			return (PSM_SUCCESS);
519	}
520
521	for (i = 0; i < apic_io_max; i++)
522		mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
523	if (apic_cpus) {
524		kmem_free(apic_cpus, apic_cpus_size);
525		apic_cpus = NULL;
526	}
527	if (apicadr) {
528		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
529		apicadr = NULL;
530	}
531	if (mpct)
532		psm_unmap_phys(mpct, mpct_size);
533
534	return (retval);
535}
536
537static void
538apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
539{
540	int	i;
541
542	for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
543	    i++) {
544		if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
545		    strlen(apic_mps_ids[i].oem_id)) == 0) &&
546		    (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
547		    strlen(apic_mps_ids[i].prod_id)) == 0)) {
548
549			apic_poweroff_method = apic_mps_ids[i].poweroff_method;
550			break;
551		}
552	}
553
554	if (apic_debug_mps_id != 0) {
555		cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
556		    "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
557		    psm_name,
558		    hdrp->mpcnf_oem_str[0],
559		    hdrp->mpcnf_oem_str[1],
560		    hdrp->mpcnf_oem_str[2],
561		    hdrp->mpcnf_oem_str[3],
562		    hdrp->mpcnf_oem_str[4],
563		    hdrp->mpcnf_oem_str[5],
564		    hdrp->mpcnf_oem_str[6],
565		    hdrp->mpcnf_oem_str[7],
566		    hdrp->mpcnf_prod_str[0],
567		    hdrp->mpcnf_prod_str[1],
568		    hdrp->mpcnf_prod_str[2],
569		    hdrp->mpcnf_prod_str[3],
570		    hdrp->mpcnf_prod_str[4],
571		    hdrp->mpcnf_prod_str[5],
572		    hdrp->mpcnf_prod_str[6],
573		    hdrp->mpcnf_prod_str[7],
574		    hdrp->mpcnf_prod_str[8],
575		    hdrp->mpcnf_prod_str[9],
576		    hdrp->mpcnf_prod_str[10],
577		    hdrp->mpcnf_prod_str[11]);
578	}
579}
580
581static void
582apic_free_apic_cpus(void)
583{
584	if (apic_cpus != NULL) {
585		kmem_free(apic_cpus, apic_cpus_size);
586		apic_cpus = NULL;
587		apic_cpus_size = 0;
588	}
589}
590
591static int
592acpi_probe(char *modname)
593{
594	int			i, intmax, index;
595	uint32_t		id, ver;
596	int			acpi_verboseflags = 0;
597	int			madt_seen, madt_size;
598	ACPI_SUBTABLE_HEADER		*ap;
599	ACPI_MADT_LOCAL_APIC	*mpa;
600	ACPI_MADT_LOCAL_X2APIC	*mpx2a;
601	ACPI_MADT_IO_APIC		*mia;
602	ACPI_MADT_IO_SAPIC		*misa;
603	ACPI_MADT_INTERRUPT_OVERRIDE	*mio;
604	ACPI_MADT_NMI_SOURCE		*mns;
605	ACPI_MADT_INTERRUPT_SOURCE	*mis;
606	ACPI_MADT_LOCAL_APIC_NMI	*mlan;
607	ACPI_MADT_LOCAL_X2APIC_NMI	*mx2alan;
608	ACPI_MADT_LOCAL_APIC_OVERRIDE	*mao;
609	int			sci;
610	iflag_t			sci_flags;
611	volatile uint32_t	*ioapic;
612	int			ioapic_ix;
613	uint32_t		*local_ids;
614	uint32_t		*proc_ids;
615	uchar_t			hid;
616	int			warned = 0;
617
618	if (!apic_use_acpi)
619		return (PSM_FAILURE);
620
621	if (AcpiGetTable(ACPI_SIG_MADT, 1,
622	    (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
623		cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
624		return (PSM_FAILURE);
625	}
626
627	apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
628	    APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
629	if (!apicadr)
630		return (PSM_FAILURE);
631
632	if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
633	    KM_NOSLEEP)) == NULL)
634		return (PSM_FAILURE);
635
636	if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
637	    KM_NOSLEEP)) == NULL) {
638		kmem_free(local_ids, NCPU * sizeof (uint32_t));
639		return (PSM_FAILURE);
640	}
641
642	id = apic_reg_ops->apic_read(APIC_LID_REG);
643	local_ids[0] = (uchar_t)(id >> 24);
644	apic_nproc = index = 1;
645	apic_io_max = 0;
646
647	ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
648	madt_size = acpi_mapic_dtp->Header.Length;
649	madt_seen = sizeof (*acpi_mapic_dtp);
650
651	while (madt_seen < madt_size) {
652		switch (ap->Type) {
653		case ACPI_MADT_TYPE_LOCAL_APIC:
654			mpa = (ACPI_MADT_LOCAL_APIC *) ap;
655			if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
656				if (mpa->Id == 255) {
657					cmn_err(CE_WARN, "!%s: encountered "
658					    "invalid entry in MADT: CPU %d "
659					    "has Local APIC Id equal to 255 ",
660					    psm_name, mpa->ProcessorId);
661				}
662				if (mpa->Id == local_ids[0]) {
663					ASSERT(index == 1);
664					proc_ids[0] = mpa->ProcessorId;
665				} else if (apic_nproc < NCPU && use_mp &&
666				    apic_nproc < boot_ncpus) {
667					local_ids[index] = mpa->Id;
668					proc_ids[index] = mpa->ProcessorId;
669					index++;
670					apic_nproc++;
671				} else if (apic_nproc == NCPU && !warned) {
672					cmn_err(CE_WARN, "%s: CPU limit "
673					    "exceeded"
674#if !defined(__amd64)
675					    " for 32-bit mode"
676#endif
677					    "; Solaris will use %d CPUs.",
678					    psm_name,  NCPU);
679					warned = 1;
680				}
681			}
682			break;
683
684		case ACPI_MADT_TYPE_IO_APIC:
685			mia = (ACPI_MADT_IO_APIC *) ap;
686			if (apic_io_max < MAX_IO_APIC) {
687				ioapic_ix = apic_io_max;
688				apic_io_id[apic_io_max] = mia->Id;
689				apic_io_vectbase[apic_io_max] =
690				    mia->GlobalIrqBase;
691				apic_physaddr[apic_io_max] =
692				    (uint32_t)mia->Address;
693				ioapic = apicioadr[apic_io_max] =
694				    mapin_ioapic((uint32_t)mia->Address,
695				    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
696				if (!ioapic)
697					goto cleanup;
698				ioapic_mask_workaround[apic_io_max] =
699				    apic_is_ioapic_AMD_813x(mia->Address);
700				apic_io_max++;
701			}
702			break;
703
704		case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
705			mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
706			if (acpi_isop == NULL)
707				acpi_isop = mio;
708			acpi_iso_cnt++;
709			break;
710
711		case ACPI_MADT_TYPE_NMI_SOURCE:
712			/* UNIMPLEMENTED */
713			mns = (ACPI_MADT_NMI_SOURCE *) ap;
714			if (acpi_nmi_sp == NULL)
715				acpi_nmi_sp = mns;
716			acpi_nmi_scnt++;
717
718			cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
719			    mns->GlobalIrq, mns->IntiFlags);
720			break;
721
722		case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
723			/* UNIMPLEMENTED */
724			mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
725			if (acpi_nmi_cp == NULL)
726				acpi_nmi_cp = mlan;
727			acpi_nmi_ccnt++;
728
729			cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
730			    mlan->ProcessorId, mlan->IntiFlags,
731			    mlan->Lint);
732			break;
733
734		case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
735			/* UNIMPLEMENTED */
736			mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
737			cmn_err(CE_NOTE, "!apic: address override: %lx\n",
738			    (long)mao->Address);
739			break;
740
741		case ACPI_MADT_TYPE_IO_SAPIC:
742			/* UNIMPLEMENTED */
743			misa = (ACPI_MADT_IO_SAPIC *) ap;
744
745			cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
746			    misa->Id, misa->GlobalIrqBase,
747			    (long)misa->Address);
748			break;
749
750		case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
751			/* UNIMPLEMENTED */
752			mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
753
754			cmn_err(CE_NOTE,
755			    "!apic: irq source: %d %d %d 0x%x %d %d\n",
756			    mis->Id, mis->Eid, mis->GlobalIrq,
757			    mis->IntiFlags, mis->Type,
758			    mis->IoSapicVector);
759			break;
760
761		case ACPI_MADT_TYPE_LOCAL_X2APIC:
762			mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
763
764			if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
765				if (mpx2a->LocalApicId == local_ids[0]) {
766					ASSERT(index == 1);
767					proc_ids[0] = mpx2a->Uid;
768				} else if (apic_nproc < NCPU && use_mp &&
769				    apic_nproc < boot_ncpus) {
770					local_ids[index] = mpx2a->LocalApicId;
771					proc_ids[index] = mpx2a->Uid;
772					index++;
773					apic_nproc++;
774				} else if (apic_nproc == NCPU && !warned) {
775					cmn_err(CE_WARN, "%s: CPU limit "
776					    "exceeded"
777#if !defined(__amd64)
778					    " for 32-bit mode"
779#endif
780					    "; Solaris will use %d CPUs.",
781					    psm_name,  NCPU);
782					warned = 1;
783				}
784			}
785
786			break;
787
788		case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
789			/* UNIMPLEMENTED */
790			mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
791			if (mx2alan->Uid >> 8)
792				acpi_nmi_ccnt++;
793
794#ifdef	DEBUG
795			cmn_err(CE_NOTE,
796			    "!apic: local x2apic nmi: %d 0x%x %d\n",
797			    mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
798#endif
799
800			break;
801
802		case ACPI_MADT_TYPE_RESERVED:
803		default:
804			break;
805		}
806
807		/* advance to next entry */
808		madt_seen += ap->Length;
809		ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
810	}
811
812	/* We found multiple enabled cpus via MADT */
813	if ((apic_nproc > 1) && (apic_io_max > 0)) {
814		acpi_found_smp_config = B_TRUE;
815		cmn_err(CE_NOTE,
816		    "!apic: Using ACPI (MADT) for SMP configuration");
817	}
818
819	/*
820	 * allocate enough space for possible hot-adding of CPUs.
821	 * max_ncpus may be less than apic_nproc if it's set by user.
822	 */
823	if (plat_dr_support_cpu()) {
824		apic_max_nproc = max_ncpus;
825	}
826	apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
827	if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
828		goto cleanup;
829
830	/*
831	 * ACPI doesn't provide the local apic ver, get it directly from the
832	 * local apic
833	 */
834	ver = apic_reg_ops->apic_read(APIC_VERS_REG);
835	for (i = 0; i < apic_nproc; i++) {
836		apic_cpus[i].aci_local_id = local_ids[i];
837		apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
838		apic_cpus[i].aci_processor_id = proc_ids[i];
839		/* Only build mapping info for CPUs present at boot. */
840		if (i < boot_ncpus)
841			(void) acpica_map_cpu(i, proc_ids[i]);
842	}
843
844	/*
845	 * To support CPU dynamic reconfiguration, the apic CPU info structure
846	 * for each possible CPU will be pre-allocated at boot time.
847	 * The state for each apic CPU info structure will be assigned according
848	 * to the following rules:
849	 * Rule 1:
850	 * 	Slot index range: [0, min(apic_nproc, boot_ncpus))
851	 *	State flags: 0
852	 *	Note: cpu exists and will be configured/enabled at boot time
853	 * Rule 2:
854	 * 	Slot index range: [boot_ncpus, apic_nproc)
855	 *	State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
856	 *	Note: cpu exists but won't be configured/enabled at boot time
857	 * Rule 3:
858	 * 	Slot index range: [apic_nproc, boot_ncpus)
859	 *	State flags: APIC_CPU_FREE
860	 *	Note: cpu doesn't exist at boot time
861	 * Rule 4:
862	 * 	Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
863	 *	State flags: APIC_CPU_FREE
864	 *	Note: cpu doesn't exist at boot time
865	 */
866	CPUSET_ZERO(apic_cpumask);
867	for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
868		CPUSET_ADD(apic_cpumask, i);
869		apic_cpus[i].aci_status = 0;
870	}
871	for (i = boot_ncpus; i < apic_nproc; i++) {
872		apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
873	}
874	for (i = apic_nproc; i < boot_ncpus; i++) {
875		apic_cpus[i].aci_status = APIC_CPU_FREE;
876	}
877	for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
878		apic_cpus[i].aci_status = APIC_CPU_FREE;
879	}
880
881	for (i = 0; i < apic_io_max; i++) {
882		ioapic_ix = i;
883
884		/*
885		 * need to check Sitka on the following acpi problem
886		 * On the Sitka, the ioapic's apic_id field isn't reporting
887		 * the actual io apic id. We have reported this problem
888		 * to Intel. Until they fix the problem, we will get the
889		 * actual id directly from the ioapic.
890		 */
891		id = ioapic_read(ioapic_ix, APIC_ID_CMD);
892		hid = (uchar_t)(id >> 24);
893
894		if (hid != apic_io_id[i]) {
895			if (apic_io_id[i] == 0)
896				apic_io_id[i] = hid;
897			else { /* set ioapic id to whatever reported by ACPI */
898				id = ((uint32_t)apic_io_id[i]) << 24;
899				ioapic_write(ioapic_ix, APIC_ID_CMD, id);
900			}
901		}
902		ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
903		apic_io_ver[i] = (uchar_t)(ver & 0xff);
904		intmax = (ver >> 16) & 0xff;
905		apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
906		if (apic_first_avail_irq <= apic_io_vectend[i])
907			apic_first_avail_irq = apic_io_vectend[i] + 1;
908	}
909
910
911	/*
912	 * Process SCI configuration here
913	 * An error may be returned here if
914	 * acpi-user-options specifies legacy mode
915	 * (no SCI, no ACPI mode)
916	 */
917	if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
918		sci = -1;
919
920	/*
921	 * Now call acpi_init() to generate namespaces
922	 * If this fails, we don't attempt to use ACPI
923	 * even if we were able to get a MADT above
924	 */
925	if (acpica_init() != AE_OK) {
926		cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
927		goto cleanup;
928	}
929
930	/*
931	 * Call acpica_build_processor_map() now that we have
932	 * ACPI namesspace access
933	 */
934	(void) acpica_build_processor_map();
935
936	/*
937	 * Squirrel away the SCI and flags for later on
938	 * in apic_picinit() when we're ready
939	 */
940	apic_sci_vect = sci;
941	apic_sci_flags = sci_flags;
942
943	if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
944		acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
945
946	if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
947		acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
948
949	if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
950		acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
951
952	if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
953		goto cleanup;
954
955	/* Enable ACPI APIC interrupt routing */
956	if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
957		cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
958		build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
959		apic_enable_acpi = 1;
960		if (apic_sci_vect > 0) {
961			acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
962		}
963		if (apic_use_acpi_madt_only) {
964			cmn_err(CE_CONT,
965			    "?Using ACPI for CPU/IOAPIC information ONLY\n");
966		}
967
968#if !defined(__xpv)
969		/*
970		 * probe ACPI for hpet information here which is used later
971		 * in apic_picinit().
972		 */
973		if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
974			cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
975		}
976#endif
977
978		kmem_free(local_ids, NCPU * sizeof (uint32_t));
979		kmem_free(proc_ids, NCPU * sizeof (uint32_t));
980		return (PSM_SUCCESS);
981	}
982	/* if setting APIC mode failed above, we fall through to cleanup */
983
984cleanup:
985	cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
986	    acpi_found_smp_config ? "found" : "not found");
987	apic_free_apic_cpus();
988	if (apicadr != NULL) {
989		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
990		apicadr = NULL;
991	}
992	apic_max_nproc = -1;
993	apic_nproc = 0;
994	for (i = 0; i < apic_io_max; i++) {
995		mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
996		apicioadr[i] = NULL;
997	}
998	apic_io_max = 0;
999	acpi_isop = NULL;
1000	acpi_iso_cnt = 0;
1001	acpi_nmi_sp = NULL;
1002	acpi_nmi_scnt = 0;
1003	acpi_nmi_cp = NULL;
1004	acpi_nmi_ccnt = 0;
1005	acpi_found_smp_config = B_FALSE;
1006	kmem_free(local_ids, NCPU * sizeof (uint32_t));
1007	kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1008	return (PSM_FAILURE);
1009}
1010
1011/*
1012 * Handle default configuration. Fill in reqd global variables & tables
1013 * Fill all details as MP table does not give any more info
1014 */
1015static int
1016apic_handle_defconf()
1017{
1018	uint_t	lid;
1019
1020	/* Failed to probe ACPI MADT tables, disable CPU DR. */
1021	apic_max_nproc = -1;
1022	apic_free_apic_cpus();
1023	plat_dr_disable_cpu();
1024
1025	apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1026	    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1027	apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1028	    APIC_LOCAL_MEMLEN, PROT_READ);
1029	apic_cpus_size = 2 * sizeof (*apic_cpus);
1030	apic_cpus = (apic_cpus_info_t *)
1031	    kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1032	if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1033		goto apic_handle_defconf_fail;
1034	CPUSET_ONLY(apic_cpumask, 0);
1035	CPUSET_ADD(apic_cpumask, 1);
1036	apic_nproc = 2;
1037	lid = apic_reg_ops->apic_read(APIC_LID_REG);
1038	apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1039	/*
1040	 * According to the PC+MP spec 1.1, the local ids
1041	 * for the default configuration has to be 0 or 1
1042	 */
1043	if (apic_cpus[0].aci_local_id == 1)
1044		apic_cpus[1].aci_local_id = 0;
1045	else if (apic_cpus[0].aci_local_id == 0)
1046		apic_cpus[1].aci_local_id = 1;
1047	else
1048		goto apic_handle_defconf_fail;
1049
1050	apic_io_id[0] = 2;
1051	apic_io_max = 1;
1052	if (apic_defconf >= 5) {
1053		apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1054		apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1055		apic_io_ver[0] = APIC_INTEGRATED_VERS;
1056	} else {
1057		apic_cpus[0].aci_local_ver = 0;		/* 82489 DX */
1058		apic_cpus[1].aci_local_ver = 0;
1059		apic_io_ver[0] = 0;
1060	}
1061	if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1062		eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1063		    inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1064	return (PSM_SUCCESS);
1065
1066apic_handle_defconf_fail:
1067	if (apicadr)
1068		mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1069	if (apicioadr[0])
1070		mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1071	return (PSM_FAILURE);
1072}
1073
1074/* Parse the entries in MP configuration table and collect info that we need */
1075static int
1076apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1077{
1078	struct	apic_procent	*procp;
1079	struct	apic_bus	*busp;
1080	struct	apic_io_entry	*ioapicp;
1081	struct	apic_io_intr	*intrp;
1082	int			ioapic_ix;
1083	uint_t	lid;
1084	uint32_t	id;
1085	uchar_t hid;
1086	int	warned = 0;
1087
1088	/*LINTED: pointer cast may result in improper alignment */
1089	procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1090
1091	/* No need to count cpu entries if we won't use them */
1092	if (!bypass_cpus_and_ioapics) {
1093
1094		/* Find max # of CPUS and allocate structure accordingly */
1095		apic_nproc = 0;
1096		CPUSET_ZERO(apic_cpumask);
1097		while (procp->proc_entry == APIC_CPU_ENTRY) {
1098			if (procp->proc_cpuflags & CPUFLAGS_EN) {
1099				if (apic_nproc < NCPU && use_mp &&
1100				    apic_nproc < boot_ncpus) {
1101					CPUSET_ADD(apic_cpumask, apic_nproc);
1102					apic_nproc++;
1103				} else if (apic_nproc == NCPU && !warned) {
1104					cmn_err(CE_WARN, "%s: CPU limit "
1105					    "exceeded"
1106#if !defined(__amd64)
1107					    " for 32-bit mode"
1108#endif
1109					    "; Solaris will use %d CPUs.",
1110					    psm_name,  NCPU);
1111					warned = 1;
1112				}
1113
1114			}
1115			procp++;
1116		}
1117		apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1118		if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1119		    kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1120			return (PSM_FAILURE);
1121	}
1122
1123	/*LINTED: pointer cast may result in improper alignment */
1124	procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1125
1126	/*
1127	 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1128	 * if we're bypassing this information, it has already been filled
1129	 * in by acpi_probe(), so don't overwrite it.
1130	 */
1131	if (!bypass_cpus_and_ioapics)
1132		apic_nproc = 1;
1133
1134	while (procp->proc_entry == APIC_CPU_ENTRY) {
1135		/* check whether the cpu exists or not */
1136		if (!bypass_cpus_and_ioapics &&
1137		    procp->proc_cpuflags & CPUFLAGS_EN) {
1138			if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1139				lid = apic_reg_ops->apic_read(APIC_LID_REG);
1140				apic_cpus[0].aci_local_id = procp->proc_apicid;
1141				if (apic_cpus[0].aci_local_id !=
1142				    (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1143					return (PSM_FAILURE);
1144				}
1145				apic_cpus[0].aci_local_ver =
1146				    procp->proc_version;
1147			} else if (apic_nproc < NCPU && use_mp &&
1148			    apic_nproc < boot_ncpus) {
1149				apic_cpus[apic_nproc].aci_local_id =
1150				    procp->proc_apicid;
1151
1152				apic_cpus[apic_nproc].aci_local_ver =
1153				    procp->proc_version;
1154				apic_nproc++;
1155
1156			}
1157		}
1158		procp++;
1159	}
1160
1161	/*
1162	 * Save start of bus entries for later use.
1163	 * Get EISA level cntrl if EISA bus is present.
1164	 * Also get the CPI bus id for single CPI bus case
1165	 */
1166	apic_busp = busp = (struct apic_bus *)procp;
1167	while (busp->bus_entry == APIC_BUS_ENTRY) {
1168		lid = apic_find_bus_type((char *)&busp->bus_str1);
1169		if (lid	== BUS_EISA) {
1170			eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1171			    inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1172		} else if (lid == BUS_PCI) {
1173			/*
1174			 * apic_single_pci_busid will be used only if
1175			 * apic_pic_bus_total is equal to 1
1176			 */
1177			apic_pci_bus_total++;
1178			apic_single_pci_busid = busp->bus_id;
1179		}
1180		busp++;
1181	}
1182
1183	ioapicp = (struct apic_io_entry *)busp;
1184
1185	if (!bypass_cpus_and_ioapics)
1186		apic_io_max = 0;
1187	do {
1188		if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1189			if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1190				apic_io_id[apic_io_max] = ioapicp->io_apicid;
1191				apic_io_ver[apic_io_max] = ioapicp->io_version;
1192				apicioadr[apic_io_max] =
1193				    (void *)mapin_ioapic(
1194				    (uint32_t)ioapicp->io_apic_addr,
1195				    APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1196
1197				if (!apicioadr[apic_io_max])
1198					return (PSM_FAILURE);
1199
1200				ioapic_mask_workaround[apic_io_max] =
1201				    apic_is_ioapic_AMD_813x(
1202				    ioapicp->io_apic_addr);
1203
1204				ioapic_ix = apic_io_max;
1205				id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1206				hid = (uchar_t)(id >> 24);
1207
1208				if (hid != apic_io_id[apic_io_max]) {
1209					if (apic_io_id[apic_io_max] == 0)
1210						apic_io_id[apic_io_max] = hid;
1211					else {
1212						/*
1213						 * set ioapic id to whatever
1214						 * reported by MPS
1215						 *
1216						 * may not need to set index
1217						 * again ???
1218						 * take it out and try
1219						 */
1220
1221						id = ((uint32_t)
1222						    apic_io_id[apic_io_max]) <<
1223						    24;
1224
1225						ioapic_write(ioapic_ix,
1226						    APIC_ID_CMD, id);
1227					}
1228				}
1229				apic_io_max++;
1230			}
1231		}
1232		ioapicp++;
1233	} while (ioapicp->io_entry == APIC_IO_ENTRY);
1234
1235	apic_io_intrp = (struct apic_io_intr *)ioapicp;
1236
1237	intrp = apic_io_intrp;
1238	while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1239		if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1240		    (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1241			apic_irq_translate = 1;
1242			break;
1243		}
1244		intrp++;
1245	}
1246
1247	return (PSM_SUCCESS);
1248}
1249
1250boolean_t
1251apic_cpu_in_range(int cpu)
1252{
1253	cpu &= ~IRQ_USER_BOUND;
1254	/* Check whether cpu id is in valid range. */
1255	if (cpu < 0 || cpu >= apic_nproc) {
1256		return (B_FALSE);
1257	} else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1258		/*
1259		 * Check whether cpuid is in valid range if CPU DR is enabled.
1260		 */
1261		return (B_FALSE);
1262	} else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1263		return (B_FALSE);
1264	}
1265
1266	return (B_TRUE);
1267}
1268
1269processorid_t
1270apic_get_next_bind_cpu(void)
1271{
1272	int i, count;
1273	processorid_t cpuid = 0;
1274
1275	for (count = 0; count < apic_nproc; count++) {
1276		if (apic_next_bind_cpu >= apic_nproc) {
1277			apic_next_bind_cpu = 0;
1278		}
1279		i = apic_next_bind_cpu++;
1280		if (apic_cpu_in_range(i)) {
1281			cpuid = i;
1282			break;
1283		}
1284	}
1285
1286	return (cpuid);
1287}
1288
1289uint16_t
1290apic_get_apic_version()
1291{
1292	int i;
1293	uchar_t min_io_apic_ver = 0;
1294	static uint16_t version;		/* Cache as value is constant */
1295	static boolean_t found = B_FALSE;	/* Accomodate zero version */
1296
1297	if (found == B_FALSE) {
1298		found = B_TRUE;
1299
1300		/*
1301		 * Don't assume all IO APICs in the system are the same.
1302		 *
1303		 * Set to the minimum version.
1304		 */
1305		for (i = 0; i < apic_io_max; i++) {
1306			if ((apic_io_ver[i] != 0) &&
1307			    ((min_io_apic_ver == 0) ||
1308			    (min_io_apic_ver >= apic_io_ver[i])))
1309				min_io_apic_ver = apic_io_ver[i];
1310		}
1311
1312		/* Assume all local APICs are of the same version. */
1313		version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1314	}
1315	return (version);
1316}
1317
1318static struct apic_mpfps_hdr *
1319apic_find_fps_sig(caddr_t cptr, int len)
1320{
1321	int	i;
1322
1323	/* Look for the pattern "_MP_" */
1324	for (i = 0; i < len; i += 16) {
1325		if ((*(cptr+i) == '_') &&
1326		    (*(cptr+i+1) == 'M') &&
1327		    (*(cptr+i+2) == 'P') &&
1328		    (*(cptr+i+3) == '_'))
1329		    /*LINTED: pointer cast may result in improper alignment */
1330			return ((struct apic_mpfps_hdr *)(cptr + i));
1331	}
1332	return (NULL);
1333}
1334
1335static int
1336apic_checksum(caddr_t bptr, int len)
1337{
1338	int	i;
1339	uchar_t	cksum;
1340
1341	cksum = 0;
1342	for (i = 0; i < len; i++)
1343		cksum += *bptr++;
1344	return ((int)cksum);
1345}
1346
1347/*
1348 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1349 * needs special handling.  We may need to chase up the device tree,
1350 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1351 * to find the IPIN at the root bus that relates to the IPIN on the
1352 * subsidiary bus (for ACPI or MP).  We may, however, have an entry
1353 * in the MP table or the ACPI namespace for this device itself.
1354 * We handle both cases in the search below.
1355 */
1356/* this is the non-acpi version */
1357int
1358apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1359    struct apic_io_intr **intrp)
1360{
1361	dev_info_t *dipp, *dip;
1362	int pci_irq;
1363	ddi_acc_handle_t cfg_handle;
1364	int bridge_devno, bridge_bus;
1365	int ipin;
1366
1367	dip = idip;
1368
1369	/*CONSTCOND*/
1370	while (1) {
1371		if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1372		    (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1373			return (-1);
1374		if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1375		    PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1376		    PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1377			pci_config_teardown(&cfg_handle);
1378			if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1379			    NULL) != 0)
1380				return (-1);
1381			/*
1382			 * This is the rotating scheme documented in the
1383			 * PCI-to-PCI spec.  If the PCI-to-PCI bridge is
1384			 * behind another PCI-to-PCI bridge, then it needs
1385			 * to keep ascending until an interrupt entry is
1386			 * found or the root is reached.
1387			 */
1388			ipin = (child_devno + child_ipin) % PCI_INTD;
1389			if (bridge_bus == 0 && apic_pci_bus_total == 1)
1390				bridge_bus = (int)apic_single_pci_busid;
1391			pci_irq = ((bridge_devno & 0x1f) << 2) |
1392			    (ipin & 0x3);
1393			if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1394			    bridge_bus)) != NULL) {
1395				return (pci_irq);
1396			}
1397			dip = dipp;
1398			child_devno = bridge_devno;
1399			child_ipin = ipin;
1400		} else {
1401			pci_config_teardown(&cfg_handle);
1402			return (-1);
1403		}
1404	}
1405	/*LINTED: function will not fall off the bottom */
1406}
1407
1408uchar_t
1409acpi_find_ioapic(int irq)
1410{
1411	int i;
1412
1413	for (i = 0; i < apic_io_max; i++) {
1414		if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1415			return ((uchar_t)i);
1416	}
1417	return (0xFF);	/* shouldn't happen */
1418}
1419
1420/*
1421 * See if two irqs are compatible for sharing a vector.
1422 * Currently we only support sharing of PCI devices.
1423 */
1424static int
1425acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1426{
1427	uint_t	level1, po1;
1428	uint_t	level2, po2;
1429
1430	/* Assume active high by default */
1431	po1 = 0;
1432	po2 = 0;
1433
1434	if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1435		return (0);
1436
1437	if (iflag1.intr_el == INTR_EL_CONFORM)
1438		level1 = AV_LEVEL;
1439	else
1440		level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1441
1442	if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1443	    (iflag1.intr_po == INTR_PO_CONFORM)))
1444		po1 = AV_ACTIVE_LOW;
1445
1446	if (iflag2.intr_el == INTR_EL_CONFORM)
1447		level2 = AV_LEVEL;
1448	else
1449		level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1450
1451	if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1452	    (iflag2.intr_po == INTR_PO_CONFORM)))
1453		po2 = AV_ACTIVE_LOW;
1454
1455	if ((level1 == level2) && (po1 == po2))
1456		return (1);
1457
1458	return (0);
1459}
1460
1461struct apic_io_intr *
1462apic_find_io_intr_w_busid(int irqno, int busid)
1463{
1464	struct	apic_io_intr	*intrp;
1465
1466	/*
1467	 * It can have more than 1 entry with same source bus IRQ,
1468	 * but unique with the source bus id
1469	 */
1470	intrp = apic_io_intrp;
1471	if (intrp != NULL) {
1472		while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1473			if (intrp->intr_irq == irqno &&
1474			    intrp->intr_busid == busid &&
1475			    intrp->intr_type == IO_INTR_INT)
1476				return (intrp);
1477			intrp++;
1478		}
1479	}
1480	APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1481	    "busid %x:%x\n", irqno, busid));
1482	return ((struct apic_io_intr *)NULL);
1483}
1484
1485
1486struct mps_bus_info {
1487	char	*bus_name;
1488	int	bus_id;
1489} bus_info_array[] = {
1490	"ISA ", BUS_ISA,
1491	"PCI ", BUS_PCI,
1492	"EISA ", BUS_EISA,
1493	"XPRESS", BUS_XPRESS,
1494	"PCMCIA", BUS_PCMCIA,
1495	"VL ", BUS_VL,
1496	"CBUS ", BUS_CBUS,
1497	"CBUSII", BUS_CBUSII,
1498	"FUTURE", BUS_FUTURE,
1499	"INTERN", BUS_INTERN,
1500	"MBI ", BUS_MBI,
1501	"MBII ", BUS_MBII,
1502	"MPI ", BUS_MPI,
1503	"MPSA ", BUS_MPSA,
1504	"NUBUS ", BUS_NUBUS,
1505	"TC ", BUS_TC,
1506	"VME ", BUS_VME,
1507	"PCI-E ", BUS_PCIE
1508};
1509
1510static int
1511apic_find_bus_type(char *bus)
1512{
1513	int	i = 0;
1514
1515	for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1516		if (strncmp(bus, bus_info_array[i].bus_name,
1517		    strlen(bus_info_array[i].bus_name)) == 0)
1518			return (bus_info_array[i].bus_id);
1519	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1520	return (0);
1521}
1522
1523static int
1524apic_find_bus(int busid)
1525{
1526	struct	apic_bus	*busp;
1527
1528	busp = apic_busp;
1529	while (busp->bus_entry == APIC_BUS_ENTRY) {
1530		if (busp->bus_id == busid)
1531			return (apic_find_bus_type((char *)&busp->bus_str1));
1532		busp++;
1533	}
1534	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1535	return (0);
1536}
1537
1538int
1539apic_find_bus_id(int bustype)
1540{
1541	struct	apic_bus	*busp;
1542
1543	busp = apic_busp;
1544	while (busp->bus_entry == APIC_BUS_ENTRY) {
1545		if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1546			return (busp->bus_id);
1547		busp++;
1548	}
1549	APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1550	    bustype));
1551	return (-1);
1552}
1553
1554/*
1555 * Check if a particular irq need to be reserved for any io_intr
1556 */
1557static struct apic_io_intr *
1558apic_find_io_intr(int irqno)
1559{
1560	struct	apic_io_intr	*intrp;
1561
1562	intrp = apic_io_intrp;
1563	if (intrp != NULL) {
1564		while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1565			if (intrp->intr_irq == irqno &&
1566			    intrp->intr_type == IO_INTR_INT)
1567				return (intrp);
1568			intrp++;
1569		}
1570	}
1571	return ((struct apic_io_intr *)NULL);
1572}
1573
1574/*
1575 * Check if the given ioapicindex intin combination has already been assigned
1576 * an irq. If so return irqno. Else -1
1577 */
1578int
1579apic_find_intin(uchar_t ioapic, uchar_t intin)
1580{
1581	apic_irq_t *irqptr;
1582	int	i;
1583
1584	/* find ioapic and intin in the apic_irq_table[] and return the index */
1585	for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1586		irqptr = apic_irq_table[i];
1587		while (irqptr) {
1588			if ((irqptr->airq_mps_intr_index >= 0) &&
1589			    (irqptr->airq_intin_no == intin) &&
1590			    (irqptr->airq_ioapicindex == ioapic)) {
1591				APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1592				    "entry for ioapic:intin %x:%x "
1593				    "shared interrupts ?", ioapic, intin));
1594				return (i);
1595			}
1596			irqptr = irqptr->airq_next;
1597		}
1598	}
1599	return (-1);
1600}
1601
1602int
1603apic_allocate_irq(int irq)
1604{
1605	int	freeirq, i;
1606
1607	if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1) {
1608		if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1609		    (irq - 1))) == -1) {
1610			/*
1611			 * if BIOS really defines every single irq in the mps
1612			 * table, then don't worry about conflicting with
1613			 * them, just use any free slot in apic_irq_table
1614			 */
1615			for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1616				if ((apic_irq_table[i] == NULL) ||
1617				    apic_irq_table[i]->airq_mps_intr_index ==
1618				    FREE_INDEX) {
1619					freeirq = i;
1620					break;
1621				}
1622			}
1623
1624			if (freeirq == -1) {
1625				/* This shouldn't happen, but just in case */
1626				cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1627				return (-1);
1628			}
1629		}
1630	}
1631
1632	if (apic_irq_table[freeirq] == NULL) {
1633		apic_irq_table[freeirq] =
1634		    kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1635		if (apic_irq_table[freeirq] == NULL) {
1636			cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1637			    psm_name);
1638			return (-1);
1639		}
1640		apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1641		apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1642	}
1643	return (freeirq);
1644}
1645
1646static int
1647apic_find_free_irq(int start, int end)
1648{
1649	int	i;
1650
1651	for (i = start; i <= end; i++)
1652		/* Check if any I/O entry needs this IRQ */
1653		if (apic_find_io_intr(i) == NULL) {
1654			/* Then see if it is free */
1655			if ((apic_irq_table[i] == NULL) ||
1656			    (apic_irq_table[i]->airq_mps_intr_index ==
1657			    FREE_INDEX)) {
1658				return (i);
1659			}
1660		}
1661	return (-1);
1662}
1663
1664/*
1665 * compute the polarity, trigger mode and vector for programming into
1666 * the I/O apic and record in airq_rdt_entry.
1667 */
1668void
1669apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1670{
1671	int	ioapicindex, bus_type, vector;
1672	short	intr_index;
1673	uint_t	level, po, io_po;
1674	struct apic_io_intr *iointrp;
1675
1676	intr_index = irqptr->airq_mps_intr_index;
1677	DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1678	    "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1679	    (void *)irqptr->airq_dip, irqptr->airq_vector));
1680
1681	if (intr_index == RESERVE_INDEX) {
1682		apic_error |= APIC_ERR_INVALID_INDEX;
1683		return;
1684	} else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1685		return;
1686	}
1687
1688	vector = irqptr->airq_vector;
1689	ioapicindex = irqptr->airq_ioapicindex;
1690	/* Assume edge triggered by default */
1691	level = 0;
1692	/* Assume active high by default */
1693	po = 0;
1694
1695	if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1696		ASSERT(irq < 16);
1697		if (eisa_level_intr_mask & (1 << irq))
1698			level = AV_LEVEL;
1699		if (intr_index == FREE_INDEX && apic_defconf == 0)
1700			apic_error |= APIC_ERR_INVALID_INDEX;
1701	} else if (intr_index == ACPI_INDEX) {
1702		bus_type = irqptr->airq_iflag.bustype;
1703		if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1704			if (bus_type == BUS_PCI)
1705				level = AV_LEVEL;
1706		} else
1707			level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1708			    AV_LEVEL : 0;
1709		if (level &&
1710		    ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1711		    (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1712		    bus_type == BUS_PCI)))
1713			po = AV_ACTIVE_LOW;
1714	} else {
1715		iointrp = apic_io_intrp + intr_index;
1716		bus_type = apic_find_bus(iointrp->intr_busid);
1717		if (iointrp->intr_el == INTR_EL_CONFORM) {
1718			if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1719				level = AV_LEVEL;
1720			else if (bus_type == BUS_PCI)
1721				level = AV_LEVEL;
1722		} else
1723			level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1724			    AV_LEVEL : 0;
1725		if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1726		    (iointrp->intr_po == INTR_PO_CONFORM &&
1727		    bus_type == BUS_PCI)))
1728			po = AV_ACTIVE_LOW;
1729	}
1730	if (level)
1731		apic_level_intr[irq] = 1;
1732	/*
1733	 * The 82489DX External APIC cannot do active low polarity interrupts.
1734	 */
1735	if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1736		io_po = po;
1737	else
1738		io_po = 0;
1739
1740	if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1741		prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1742		    "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1743		    irqptr->airq_intin_no, level, io_po, vector,
1744		    irqptr->airq_cpu);
1745
1746	irqptr->airq_rdt_entry = level|io_po|vector;
1747}
1748
1749int
1750apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1751    int ipin, int *pci_irqp, iflag_t *intr_flagp)
1752{
1753
1754	int status;
1755	acpi_psm_lnk_t acpipsmlnk;
1756
1757	if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1758	    intr_flagp)) == ACPI_PSM_SUCCESS) {
1759		APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1760		    "from cache for device %s, instance #%d\n", psm_name,
1761		    *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1762		return (status);
1763	}
1764
1765	bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1766
1767	if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1768	    &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1769		APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1770		    " acpi_translate_pci_irq failed for device %s, instance"
1771		    " #%d", psm_name, ddi_get_name(dip),
1772		    ddi_get_instance(dip)));
1773		return (status);
1774	}
1775
1776	if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1777		status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1778		    intr_flagp);
1779		if (status != ACPI_PSM_SUCCESS) {
1780			status = acpi_get_current_irq_resource(&acpipsmlnk,
1781			    pci_irqp, intr_flagp);
1782		}
1783	}
1784
1785	if (status == ACPI_PSM_SUCCESS) {
1786		acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1787		    intr_flagp, &acpipsmlnk);
1788
1789		APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1790		    "new irq %d for device %s, instance #%d\n", psm_name,
1791		    *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1792	}
1793
1794	return (status);
1795}
1796
1797/*
1798 * Adds an entry to the irq list passed in, and returns the new list.
1799 * Entries are added in priority order (lower numerical priorities are
1800 * placed closer to the head of the list)
1801 */
1802static prs_irq_list_t *
1803acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1804    iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1805{
1806	struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1807
1808	newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1809
1810	newent->list_prio = priority;
1811	newent->irq = irq;
1812	newent->intrflags = *iflagp;
1813	newent->prsprv = *prsprvp;
1814	/* ->next is NULL from kmem_zalloc */
1815
1816	/*
1817	 * New list -- return the new entry as the list.
1818	 */
1819	if (listp == NULL)
1820		return (newent);
1821
1822	/*
1823	 * Save original list pointer for return (since we're not modifying
1824	 * the head)
1825	 */
1826	origlistp = listp;
1827
1828	/*
1829	 * Insertion sort, with entries with identical keys stored AFTER
1830	 * existing entries (the less-than-or-equal test of priority does
1831	 * this for us).
1832	 */
1833	while (listp != NULL && listp->list_prio <= priority) {
1834		prevp = listp;
1835		listp = listp->next;
1836	}
1837
1838	newent->next = listp;
1839
1840	if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1841		return (newent);
1842	} else {
1843		prevp->next = newent;
1844		return (origlistp);
1845	}
1846}
1847
1848/*
1849 * Frees the list passed in, deallocating all memory and leaving *listpp
1850 * set to NULL.
1851 */
1852static void
1853acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1854{
1855	struct prs_irq_list_ent *nextp;
1856
1857	ASSERT(listpp != NULL);
1858
1859	while (*listpp != NULL) {
1860		nextp = (*listpp)->next;
1861		kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1862		*listpp = nextp;
1863	}
1864}
1865
1866/*
1867 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1868 * irqs returned by the link device's _PRS method.  The irqs are chosen
1869 * to minimize contention in situations where the interrupt link device
1870 * can be programmed to steer interrupts to different interrupt controller
1871 * inputs (some of which may already be in use).  The list is sorted in order
1872 * of irqs to use, with the highest priority given to interrupt controller
1873 * inputs that are not shared.   When an interrupt controller input
1874 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1875 * returned list in the order that minimizes sharing (thereby ensuring lowest
1876 * possible latency from interrupt trigger time to ISR execution time).
1877 */
1878static prs_irq_list_t *
1879apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1880    int crs_irq)
1881{
1882	int32_t irq;
1883	int i;
1884	prs_irq_list_t *prsirqlistp = NULL;
1885	iflag_t iflags;
1886
1887	while (irqlistent != NULL) {
1888		irqlistent->intr_flags.bustype = BUS_PCI;
1889
1890		for (i = 0; i < irqlistent->num_irqs; i++) {
1891
1892			irq = irqlistent->irqs[i];
1893
1894			if (irq <= 0) {
1895				/* invalid irq number */
1896				continue;
1897			}
1898
1899			if ((irq < 16) && (apic_reserved_irqlist[irq]))
1900				continue;
1901
1902			if ((apic_irq_table[irq] == NULL) ||
1903			    (apic_irq_table[irq]->airq_dip == dip)) {
1904
1905				prsirqlistp = acpi_insert_prs_irq_ent(
1906				    prsirqlistp, 0 /* Highest priority */, irq,
1907				    &irqlistent->intr_flags,
1908				    &irqlistent->acpi_prs_prv);
1909
1910				/*
1911				 * If we do not prefer the current irq from _CRS
1912				 * or if we do and this irq is the same as the
1913				 * current irq from _CRS, this is the one
1914				 * to pick.
1915				 */
1916				if (!(apic_prefer_crs) || (irq == crs_irq)) {
1917					return (prsirqlistp);
1918				}
1919				continue;
1920			}
1921
1922			/*
1923			 * Edge-triggered interrupts cannot be shared
1924			 */
1925			if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1926				continue;
1927
1928			/*
1929			 * To work around BIOSes that contain incorrect
1930			 * interrupt polarity information in interrupt
1931			 * descriptors returned by _PRS, we assume that
1932			 * the polarity of the other device sharing this
1933			 * interrupt controller input is compatible.
1934			 * If it's not, the caller will catch it when
1935			 * the caller invokes the link device's _CRS method
1936			 * (after invoking its _SRS method).
1937			 */
1938			iflags = irqlistent->intr_flags;
1939			iflags.intr_po =
1940			    apic_irq_table[irq]->airq_iflag.intr_po;
1941
1942			if (!acpi_intr_compatible(iflags,
1943			    apic_irq_table[irq]->airq_iflag)) {
1944				APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1945				    "not compatible [%x:%x:%x !~ %x:%x:%x]",
1946				    psm_name, irq,
1947				    iflags.intr_po,
1948				    iflags.intr_el,
1949				    iflags.bustype,
1950				    apic_irq_table[irq]->airq_iflag.intr_po,
1951				    apic_irq_table[irq]->airq_iflag.intr_el,
1952				    apic_irq_table[irq]->airq_iflag.bustype));
1953				continue;
1954			}
1955
1956			/*
1957			 * If we prefer the irq from _CRS, no need
1958			 * to search any further (and make sure
1959			 * to add this irq with the highest priority
1960			 * so it's tried first).
1961			 */
1962			if (crs_irq == irq && apic_prefer_crs) {
1963
1964				return (acpi_insert_prs_irq_ent(
1965				    prsirqlistp,
1966				    0 /* Highest priority */,
1967				    irq, &iflags,
1968				    &irqlistent->acpi_prs_prv));
1969			}
1970
1971			/*
1972			 * Priority is equal to the share count (lower
1973			 * share count is higher priority). Note that
1974			 * the intr flags passed in here are the ones we
1975			 * changed above -- if incorrect, it will be
1976			 * caught by the caller's _CRS flags comparison.
1977			 */
1978			prsirqlistp = acpi_insert_prs_irq_ent(
1979			    prsirqlistp,
1980			    apic_irq_table[irq]->airq_share, irq,
1981			    &iflags, &irqlistent->acpi_prs_prv);
1982		}
1983
1984		/* Go to the next irqlist entry */
1985		irqlistent = irqlistent->next;
1986	}
1987
1988	return (prsirqlistp);
1989}
1990
1991/*
1992 * Configures the irq for the interrupt link device identified by
1993 * acpipsmlnkp.
1994 *
1995 * Gets the current and the list of possible irq settings for the
1996 * device. If apic_unconditional_srs is not set, and the current
1997 * resource setting is in the list of possible irq settings,
1998 * current irq resource setting is passed to the caller.
1999 *
2000 * Otherwise, picks an irq number from the list of possible irq
2001 * settings, and sets the irq of the device to this value.
2002 * If prefer_crs is set, among a set of irq numbers in the list that have
2003 * the least number of devices sharing the interrupt, we pick current irq
2004 * resource setting if it is a member of this set.
2005 *
2006 * Passes the irq number in the value pointed to by pci_irqp, and
2007 * polarity and sensitivity in the structure pointed to by dipintrflagp
2008 * to the caller.
2009 *
2010 * Note that if setting the irq resource failed, but successfuly obtained
2011 * the current irq resource settings, passes the current irq resources
2012 * and considers it a success.
2013 *
2014 * Returns:
2015 * ACPI_PSM_SUCCESS on success.
2016 *
2017 * ACPI_PSM_FAILURE if an error occured during the configuration or
2018 * if a suitable irq was not found for this device, or if setting the
2019 * irq resource and obtaining the current resource fails.
2020 *
2021 */
2022static int
2023apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2024    int *pci_irqp, iflag_t *dipintr_flagp)
2025{
2026	int32_t irq;
2027	int cur_irq = -1;
2028	acpi_irqlist_t *irqlistp;
2029	prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2030	boolean_t found_irq = B_FALSE;
2031
2032	dipintr_flagp->bustype = BUS_PCI;
2033
2034	if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2035	    == ACPI_PSM_FAILURE) {
2036		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2037		    "or assign IRQ for device %s, instance #%d: The system was "
2038		    "unable to get the list of potential IRQs from ACPI.",
2039		    psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2040
2041		return (ACPI_PSM_FAILURE);
2042	}
2043
2044	if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2045	    dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2046	    (cur_irq > 0)) {
2047		/*
2048		 * If an IRQ is set in CRS and that IRQ exists in the set
2049		 * returned from _PRS, return that IRQ, otherwise print
2050		 * a warning
2051		 */
2052
2053		if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2054		    == ACPI_PSM_SUCCESS) {
2055
2056			ASSERT(pci_irqp != NULL);
2057			*pci_irqp = cur_irq;
2058			acpi_free_irqlist(irqlistp);
2059			return (ACPI_PSM_SUCCESS);
2060		}
2061
2062		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2063		    "current irq %d for device %s, instance #%d in ACPI's "
2064		    "list of possible irqs for this device. Picking one from "
2065		    " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2066		    ddi_get_instance(dip)));
2067	}
2068
2069	if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2070	    cur_irq)) == NULL) {
2071
2072		APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2073		    "suitable irq from the list of possible irqs for device "
2074		    "%s, instance #%d in ACPI's list of possible irqs",
2075		    psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2076
2077		acpi_free_irqlist(irqlistp);
2078		return (ACPI_PSM_FAILURE);
2079	}
2080
2081	acpi_free_irqlist(irqlistp);
2082
2083	for (prs_irq_entp = prs_irq_listp;
2084	    prs_irq_entp != NULL && found_irq == B_FALSE;
2085	    prs_irq_entp = prs_irq_entp->next) {
2086
2087		acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2088		irq = prs_irq_entp->irq;
2089
2090		APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2091		    "device %s instance #%d\n", psm_name, irq,
2092		    ddi_get_name(dip), ddi_get_instance(dip)));
2093
2094		if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2095		    == ACPI_PSM_SUCCESS) {
2096			/*
2097			 * setting irq was successful, check to make sure CRS
2098			 * reflects that. If CRS does not agree with what we
2099			 * set, return the irq that was set.
2100			 */
2101
2102			if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2103			    dipintr_flagp) == ACPI_PSM_SUCCESS) {
2104
2105				if (cur_irq != irq)
2106					APIC_VERBOSE_IRQ((CE_WARN,
2107					    "!%s: IRQ resource set "
2108					    "(irqno %d) for device %s "
2109					    "instance #%d, differs from "
2110					    "current setting irqno %d",
2111					    psm_name, irq, ddi_get_name(dip),
2112					    ddi_get_instance(dip), cur_irq));
2113			} else {
2114				/*
2115				 * On at least one system, there was a bug in
2116				 * a DSDT method called by _STA, causing _STA to
2117				 * indicate that the link device was disabled
2118				 * (when, in fact, it was enabled).  Since _SRS
2119				 * succeeded, assume that _CRS is lying and use
2120				 * the iflags from this _PRS interrupt choice.
2121				 * If we're wrong about the flags, the polarity
2122				 * will be incorrect and we may get an interrupt
2123				 * storm, but there's not much else we can do
2124				 * at this point.
2125				 */
2126				*dipintr_flagp = prs_irq_entp->intrflags;
2127			}
2128
2129			/*
2130			 * Return the irq that was set, and not what _CRS
2131			 * reports, since _CRS has been seen to return
2132			 * different IRQs than what was passed to _SRS on some
2133			 * systems (and just not return successfully on others).
2134			 */
2135			cur_irq = irq;
2136			found_irq = B_TRUE;
2137		} else {
2138			APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2139			    "irq %d failed for device %s instance #%d",
2140			    psm_name, irq, ddi_get_name(dip),
2141			    ddi_get_instance(dip)));
2142
2143			if (cur_irq == -1) {
2144				acpi_destroy_prs_irq_list(&prs_irq_listp);
2145				return (ACPI_PSM_FAILURE);
2146			}
2147		}
2148	}
2149
2150	acpi_destroy_prs_irq_list(&prs_irq_listp);
2151
2152	if (!found_irq)
2153		return (ACPI_PSM_FAILURE);
2154
2155	ASSERT(pci_irqp != NULL);
2156	*pci_irqp = cur_irq;
2157	return (ACPI_PSM_SUCCESS);
2158}
2159
2160void
2161ioapic_disable_redirection()
2162{
2163	int ioapic_ix;
2164	int intin_max;
2165	int intin_ix;
2166
2167	/* Disable the I/O APIC redirection entries */
2168	for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2169
2170		/* Bits 23-16 define the maximum redirection entries */
2171		intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2172		    & 0xff;
2173
2174		for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2175			/*
2176			 * The assumption here is that this is safe, even for
2177			 * systems with IOAPICs that suffer from the hardware
2178			 * erratum because all devices have been quiesced before
2179			 * this function is called from apic_shutdown()
2180			 * (or equivalent). If that assumption turns out to be
2181			 * false, this mask operation can induce the same
2182			 * erratum result we're trying to avoid.
2183			 */
2184			ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2185			    AV_MASK);
2186		}
2187	}
2188}
2189
2190/*
2191 * Looks for an IOAPIC with the specified physical address in the /ioapics
2192 * node in the device tree (created by the PCI enumerator).
2193 */
2194static boolean_t
2195apic_is_ioapic_AMD_813x(uint32_t physaddr)
2196{
2197	/*
2198	 * Look in /ioapics, for the ioapic with
2199	 * the physical address given
2200	 */
2201	dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2202	dev_info_t *ioapic_child;
2203	boolean_t rv = B_FALSE;
2204	int vid, did;
2205	uint64_t ioapic_paddr;
2206	boolean_t done = B_FALSE;
2207
2208	if (ioapicsnode == NULL)
2209		return (B_FALSE);
2210
2211	/* Load first child: */
2212	ioapic_child = ddi_get_child(ioapicsnode);
2213	while (!done && ioapic_child != 0) { /* Iterate over children */
2214
2215		if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2216		    ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2217		    != 0 && physaddr == ioapic_paddr) {
2218
2219			vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2220			    DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2221
2222			if (vid == VENID_AMD) {
2223
2224				did = ddi_prop_get_int(DDI_DEV_T_ANY,
2225				    ioapic_child, DDI_PROP_DONTPASS,
2226				    IOAPICS_PROP_DEVID, 0);
2227
2228				if (did == DEVID_8131_IOAPIC ||
2229				    did == DEVID_8132_IOAPIC) {
2230					rv = B_TRUE;
2231					done = B_TRUE;
2232				}
2233			}
2234		}
2235
2236		if (!done)
2237			ioapic_child = ddi_get_next_sibling(ioapic_child);
2238	}
2239
2240	/* The ioapics node was held by ddi_find_devinfo, so release it */
2241	ndi_rele_devi(ioapicsnode);
2242	return (rv);
2243}
2244
2245struct apic_state {
2246	int32_t as_task_reg;
2247	int32_t as_dest_reg;
2248	int32_t as_format_reg;
2249	int32_t as_local_timer;
2250	int32_t as_pcint_vect;
2251	int32_t as_int_vect0;
2252	int32_t as_int_vect1;
2253	int32_t as_err_vect;
2254	int32_t as_init_count;
2255	int32_t as_divide_reg;
2256	int32_t as_spur_int_reg;
2257	uint32_t as_ioapic_ids[MAX_IO_APIC];
2258};
2259
2260
2261static int
2262apic_acpi_enter_apicmode(void)
2263{
2264	ACPI_OBJECT_LIST	arglist;
2265	ACPI_OBJECT		arg;
2266	ACPI_STATUS		status;
2267
2268	/* Setup parameter object */
2269	arglist.Count = 1;
2270	arglist.Pointer = &arg;
2271	arg.Type = ACPI_TYPE_INTEGER;
2272	arg.Integer.Value = ACPI_APIC_MODE;
2273
2274	status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2275	/*
2276	 * Per ACPI spec - section 5.8.1 _PIC Method
2277	 * calling the \_PIC control method is optional for the OS
2278	 * and might not be found. It's ok to not fail in such cases.
2279	 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2280	 */
2281	if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2282		cmn_err(CE_NOTE,
2283		    "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2284		    ACPI_FAILURE(status));
2285		return (PSM_FAILURE);
2286	} else {
2287		return (PSM_SUCCESS);
2288	}
2289}
2290
2291
2292static void
2293apic_save_state(struct apic_state *sp)
2294{
2295	int	i, cpuid;
2296	ulong_t	iflag;
2297
2298	PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2299	/*
2300	 * First the local APIC.
2301	 */
2302	sp->as_task_reg = apic_reg_ops->apic_get_pri();
2303	sp->as_dest_reg =  apic_reg_ops->apic_read(APIC_DEST_REG);
2304	if (apic_mode == LOCAL_APIC)
2305		sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2306	sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2307	sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2308	sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2309	sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2310	sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2311	sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2312	sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2313	sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2314
2315	/*
2316	 * If on the boot processor then save the IOAPICs' IDs
2317	 */
2318	if ((cpuid = psm_get_cpu_id()) == 0) {
2319
2320		iflag = intr_clear();
2321		lock_set(&apic_ioapic_lock);
2322
2323		for (i = 0; i < apic_io_max; i++)
2324			sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2325
2326		lock_clear(&apic_ioapic_lock);
2327		intr_restore(iflag);
2328	}
2329
2330	/* apic_state() is currently invoked only in Suspend/Resume */
2331	apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2332}
2333
2334static void
2335apic_restore_state(struct apic_state *sp)
2336{
2337	int	i;
2338	ulong_t	iflag;
2339
2340	/*
2341	 * First the local APIC.
2342	 */
2343	apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2344	if (apic_mode == LOCAL_APIC) {
2345		apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2346		apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2347	}
2348	apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2349	apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2350	apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2351	apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2352	apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2353	apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2354	apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2355	apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2356
2357	/*
2358	 * the following only needs to be done once, so we do it on the
2359	 * boot processor, since we know that we only have one of those
2360	 */
2361	if (psm_get_cpu_id() == 0) {
2362
2363		iflag = intr_clear();
2364		lock_set(&apic_ioapic_lock);
2365
2366		/* Restore IOAPICs' APIC IDs */
2367		for (i = 0; i < apic_io_max; i++) {
2368			ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2369		}
2370
2371		lock_clear(&apic_ioapic_lock);
2372		intr_restore(iflag);
2373
2374		/*
2375		 * Reenter APIC mode before restoring LNK devices
2376		 */
2377		(void) apic_acpi_enter_apicmode();
2378
2379		/*
2380		 * restore acpi link device mappings
2381		 */
2382		acpi_restore_link_devices();
2383	}
2384}
2385
2386/*
2387 * Returns 0 on success
2388 */
2389int
2390apic_state(psm_state_request_t *rp)
2391{
2392	PMD(PMD_SX, ("apic_state "))
2393	switch (rp->psr_cmd) {
2394	case PSM_STATE_ALLOC:
2395		rp->req.psm_state_req.psr_state =
2396		    kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2397		if (rp->req.psm_state_req.psr_state == NULL)
2398			return (ENOMEM);
2399		rp->req.psm_state_req.psr_state_size =
2400		    sizeof (struct apic_state);
2401		PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2402		    rp->req.psm_state_req.psr_state,
2403		    rp->req.psm_state_req.psr_state_size))
2404		return (0);
2405
2406	case PSM_STATE_FREE:
2407		kmem_free(rp->req.psm_state_req.psr_state,
2408		    rp->req.psm_state_req.psr_state_size);
2409		PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2410		    rp->req.psm_state_req.psr_state,
2411		    rp->req.psm_state_req.psr_state_size))
2412		return (0);
2413
2414	case PSM_STATE_SAVE:
2415		PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2416		    rp->req.psm_state_req.psr_state,
2417		    rp->req.psm_state_req.psr_state_size))
2418		apic_save_state(rp->req.psm_state_req.psr_state);
2419		return (0);
2420
2421	case PSM_STATE_RESTORE:
2422		apic_restore_state(rp->req.psm_state_req.psr_state);
2423		PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2424		    rp->req.psm_state_req.psr_state,
2425		    rp->req.psm_state_req.psr_state_size))
2426		return (0);
2427
2428	default:
2429		return (EINVAL);
2430	}
2431}
2432