17ff178cdSJimmy Vetayases /* 27ff178cdSJimmy Vetayases * CDDL HEADER START 37ff178cdSJimmy Vetayases * 47ff178cdSJimmy Vetayases * The contents of this file are subject to the terms of the 57ff178cdSJimmy Vetayases * Common Development and Distribution License (the "License"). 67ff178cdSJimmy Vetayases * You may not use this file except in compliance with the License. 77ff178cdSJimmy Vetayases * 87ff178cdSJimmy Vetayases * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97ff178cdSJimmy Vetayases * or http://www.opensolaris.org/os/licensing. 107ff178cdSJimmy Vetayases * See the License for the specific language governing permissions 117ff178cdSJimmy Vetayases * and limitations under the License. 127ff178cdSJimmy Vetayases * 137ff178cdSJimmy Vetayases * When distributing Covered Code, include this CDDL HEADER in each 147ff178cdSJimmy Vetayases * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157ff178cdSJimmy Vetayases * If applicable, add the following below this CDDL HEADER, with the 167ff178cdSJimmy Vetayases * fields enclosed by brackets "[]" replaced with your own identifying 177ff178cdSJimmy Vetayases * information: Portions Copyright [yyyy] [name of copyright owner] 187ff178cdSJimmy Vetayases * 197ff178cdSJimmy Vetayases * CDDL HEADER END 207ff178cdSJimmy Vetayases */ 217ff178cdSJimmy Vetayases 227ff178cdSJimmy Vetayases /* 237ff178cdSJimmy Vetayases * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 247ff178cdSJimmy Vetayases */ 257ff178cdSJimmy Vetayases /* 267ff178cdSJimmy Vetayases * Copyright (c) 2010, Intel Corporation. 277ff178cdSJimmy Vetayases * All rights reserved. 287ff178cdSJimmy Vetayases */ 29636dfb4bSJerry Jelinek /* 30a51869cdSHans Rosenfeld * Copyright (c) 2017, Joyent, Inc. All rights reserved. 31636dfb4bSJerry Jelinek */ 32636dfb4bSJerry Jelinek 33636dfb4bSJerry Jelinek /* 34636dfb4bSJerry Jelinek * To understand how the apix module interacts with the interrupt subsystem read 35636dfb4bSJerry Jelinek * the theory statement in uts/i86pc/os/intr.c. 36636dfb4bSJerry Jelinek */ 377ff178cdSJimmy Vetayases 387ff178cdSJimmy Vetayases /* 397ff178cdSJimmy Vetayases * PSMI 1.1 extensions are supported only in 2.6 and later versions. 407ff178cdSJimmy Vetayases * PSMI 1.2 extensions are supported only in 2.7 and later versions. 417ff178cdSJimmy Vetayases * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 427ff178cdSJimmy Vetayases * PSMI 1.5 extensions are supported in Solaris Nevada. 437ff178cdSJimmy Vetayases * PSMI 1.6 extensions are supported in Solaris Nevada. 447ff178cdSJimmy Vetayases * PSMI 1.7 extensions are supported in Solaris Nevada. 457ff178cdSJimmy Vetayases */ 467ff178cdSJimmy Vetayases #define PSMI_1_7 477ff178cdSJimmy Vetayases 487ff178cdSJimmy Vetayases #include <sys/processor.h> 497ff178cdSJimmy Vetayases #include <sys/time.h> 507ff178cdSJimmy Vetayases #include <sys/psm.h> 517ff178cdSJimmy Vetayases #include <sys/smp_impldefs.h> 527ff178cdSJimmy Vetayases #include <sys/cram.h> 537ff178cdSJimmy Vetayases #include <sys/acpi/acpi.h> 547ff178cdSJimmy Vetayases #include <sys/acpica.h> 557ff178cdSJimmy Vetayases #include <sys/psm_common.h> 567ff178cdSJimmy Vetayases #include <sys/pit.h> 577ff178cdSJimmy Vetayases #include <sys/ddi.h> 587ff178cdSJimmy Vetayases #include <sys/sunddi.h> 597ff178cdSJimmy Vetayases #include <sys/ddi_impldefs.h> 607ff178cdSJimmy Vetayases #include <sys/pci.h> 617ff178cdSJimmy Vetayases #include <sys/promif.h> 627ff178cdSJimmy Vetayases #include <sys/x86_archext.h> 637ff178cdSJimmy Vetayases #include <sys/cpc_impl.h> 647ff178cdSJimmy Vetayases #include <sys/uadmin.h> 657ff178cdSJimmy Vetayases #include <sys/panic.h> 667ff178cdSJimmy Vetayases #include <sys/debug.h> 677ff178cdSJimmy Vetayases #include <sys/archsystm.h> 687ff178cdSJimmy Vetayases #include <sys/trap.h> 697ff178cdSJimmy Vetayases #include <sys/machsystm.h> 707ff178cdSJimmy Vetayases #include <sys/sysmacros.h> 717ff178cdSJimmy Vetayases #include <sys/cpuvar.h> 727ff178cdSJimmy Vetayases #include <sys/rm_platter.h> 737ff178cdSJimmy Vetayases #include <sys/privregs.h> 747ff178cdSJimmy Vetayases #include <sys/note.h> 757ff178cdSJimmy Vetayases #include <sys/pci_intr_lib.h> 767ff178cdSJimmy Vetayases #include <sys/spl.h> 777ff178cdSJimmy Vetayases #include <sys/clock.h> 78a288e5a9SJoshua M. Clulow #include <sys/cyclic.h> 797ff178cdSJimmy Vetayases #include <sys/dditypes.h> 807ff178cdSJimmy Vetayases #include <sys/sunddi.h> 817ff178cdSJimmy Vetayases #include <sys/x_call.h> 827ff178cdSJimmy Vetayases #include <sys/reboot.h> 837ff178cdSJimmy Vetayases #include <sys/mach_intr.h> 847ff178cdSJimmy Vetayases #include <sys/apix.h> 857ff178cdSJimmy Vetayases #include <sys/apix_irm_impl.h> 867ff178cdSJimmy Vetayases 877ff178cdSJimmy Vetayases static int apix_probe(); 887ff178cdSJimmy Vetayases static void apix_init(); 897ff178cdSJimmy Vetayases static void apix_picinit(void); 907ff178cdSJimmy Vetayases static int apix_intr_enter(int, int *); 917ff178cdSJimmy Vetayases static void apix_intr_exit(int, int); 927ff178cdSJimmy Vetayases static void apix_setspl(int); 937ff178cdSJimmy Vetayases static int apix_disable_intr(processorid_t); 947ff178cdSJimmy Vetayases static void apix_enable_intr(processorid_t); 957ff178cdSJimmy Vetayases static int apix_get_clkvect(int); 967ff178cdSJimmy Vetayases static int apix_get_ipivect(int, int); 977ff178cdSJimmy Vetayases static void apix_post_cyclic_setup(void *); 987ff178cdSJimmy Vetayases static int apix_post_cpu_start(); 997ff178cdSJimmy Vetayases static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *, 1007ff178cdSJimmy Vetayases psm_intr_op_t, int *); 1017ff178cdSJimmy Vetayases 1027ff178cdSJimmy Vetayases /* 1037ff178cdSJimmy Vetayases * Helper functions for apix_intr_ops() 1047ff178cdSJimmy Vetayases */ 1057ff178cdSJimmy Vetayases static void apix_redistribute_compute(void); 1067ff178cdSJimmy Vetayases static int apix_get_pending(apix_vector_t *); 1077ff178cdSJimmy Vetayases static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t); 1087ff178cdSJimmy Vetayases static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *); 1097ff178cdSJimmy Vetayases static char *apix_get_apic_type(void); 1107ff178cdSJimmy Vetayases static int apix_intx_get_pending(int); 1117ff178cdSJimmy Vetayases static void apix_intx_set_mask(int irqno); 1127ff178cdSJimmy Vetayases static void apix_intx_clear_mask(int irqno); 1137ff178cdSJimmy Vetayases static int apix_intx_get_shared(int irqno); 1147ff178cdSJimmy Vetayases static void apix_intx_set_shared(int irqno, int delta); 1157ff178cdSJimmy Vetayases static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int, 1167ff178cdSJimmy Vetayases struct intrspec *); 1177ff178cdSJimmy Vetayases static int apix_intx_alloc_vector(dev_info_t *, int, struct intrspec *); 1187ff178cdSJimmy Vetayases 1197ff178cdSJimmy Vetayases extern int apic_clkinit(int); 1207ff178cdSJimmy Vetayases 1217ff178cdSJimmy Vetayases /* IRM initialization for APIX PSM module */ 1227ff178cdSJimmy Vetayases extern void apix_irm_init(void); 1237ff178cdSJimmy Vetayases 1247ff178cdSJimmy Vetayases extern int irm_enable; 1257ff178cdSJimmy Vetayases 1267ff178cdSJimmy Vetayases /* 1277ff178cdSJimmy Vetayases * Local static data 1287ff178cdSJimmy Vetayases */ 1297ff178cdSJimmy Vetayases static struct psm_ops apix_ops = { 1307ff178cdSJimmy Vetayases apix_probe, 1317ff178cdSJimmy Vetayases 1327ff178cdSJimmy Vetayases apix_init, 1337ff178cdSJimmy Vetayases apix_picinit, 1347ff178cdSJimmy Vetayases apix_intr_enter, 1357ff178cdSJimmy Vetayases apix_intr_exit, 1367ff178cdSJimmy Vetayases apix_setspl, 1377ff178cdSJimmy Vetayases apix_addspl, 1387ff178cdSJimmy Vetayases apix_delspl, 1397ff178cdSJimmy Vetayases apix_disable_intr, 1407ff178cdSJimmy Vetayases apix_enable_intr, 1417ff178cdSJimmy Vetayases NULL, /* psm_softlvl_to_irq */ 1427ff178cdSJimmy Vetayases NULL, /* psm_set_softintr */ 1437ff178cdSJimmy Vetayases 1447ff178cdSJimmy Vetayases apic_set_idlecpu, 1457ff178cdSJimmy Vetayases apic_unset_idlecpu, 1467ff178cdSJimmy Vetayases 1477ff178cdSJimmy Vetayases apic_clkinit, 1487ff178cdSJimmy Vetayases apix_get_clkvect, 1497ff178cdSJimmy Vetayases NULL, /* psm_hrtimeinit */ 1507ff178cdSJimmy Vetayases apic_gethrtime, 1517ff178cdSJimmy Vetayases 1527ff178cdSJimmy Vetayases apic_get_next_processorid, 1537ff178cdSJimmy Vetayases apic_cpu_start, 1547ff178cdSJimmy Vetayases apix_post_cpu_start, 1557ff178cdSJimmy Vetayases apic_shutdown, 1567ff178cdSJimmy Vetayases apix_get_ipivect, 1577ff178cdSJimmy Vetayases apic_send_ipi, 1587ff178cdSJimmy Vetayases 1597ff178cdSJimmy Vetayases NULL, /* psm_translate_irq */ 1607ff178cdSJimmy Vetayases NULL, /* psm_notify_error */ 1617ff178cdSJimmy Vetayases NULL, /* psm_notify_func */ 1627ff178cdSJimmy Vetayases apic_timer_reprogram, 1637ff178cdSJimmy Vetayases apic_timer_enable, 1647ff178cdSJimmy Vetayases apic_timer_disable, 1657ff178cdSJimmy Vetayases apix_post_cyclic_setup, 1667ff178cdSJimmy Vetayases apic_preshutdown, 1677ff178cdSJimmy Vetayases apix_intr_ops, /* Advanced DDI Interrupt framework */ 1687ff178cdSJimmy Vetayases apic_state, /* save, restore apic state for S3 */ 1697ff178cdSJimmy Vetayases apic_cpu_ops, /* CPU control interface. */ 1707ff178cdSJimmy Vetayases }; 1717ff178cdSJimmy Vetayases 1727ff178cdSJimmy Vetayases struct psm_ops *psmops = &apix_ops; 1737ff178cdSJimmy Vetayases 1747ff178cdSJimmy Vetayases static struct psm_info apix_psm_info = { 1757ff178cdSJimmy Vetayases PSM_INFO_VER01_7, /* version */ 1767ff178cdSJimmy Vetayases PSM_OWN_EXCLUSIVE, /* ownership */ 1777ff178cdSJimmy Vetayases &apix_ops, /* operation */ 1787ff178cdSJimmy Vetayases APIX_NAME, /* machine name */ 1797ff178cdSJimmy Vetayases "apix MPv1.4 compatible", 1807ff178cdSJimmy Vetayases }; 1817ff178cdSJimmy Vetayases 1827ff178cdSJimmy Vetayases static void *apix_hdlp; 1837ff178cdSJimmy Vetayases 1847ff178cdSJimmy Vetayases static int apix_is_enabled = 0; 1857ff178cdSJimmy Vetayases 1867ff178cdSJimmy Vetayases /* 1877ff178cdSJimmy Vetayases * Flag to indicate if APIX is to be enabled only for platforms 1887ff178cdSJimmy Vetayases * with specific hw feature(s). 1897ff178cdSJimmy Vetayases */ 1907ff178cdSJimmy Vetayases int apix_hw_chk_enable = 1; 1917ff178cdSJimmy Vetayases 1927ff178cdSJimmy Vetayases /* 1937ff178cdSJimmy Vetayases * Hw features that are checked for enabling APIX support. 1947ff178cdSJimmy Vetayases */ 1957ff178cdSJimmy Vetayases #define APIX_SUPPORT_X2APIC 0x00000001 1967ff178cdSJimmy Vetayases uint_t apix_supported_hw = APIX_SUPPORT_X2APIC; 1977ff178cdSJimmy Vetayases 1987ff178cdSJimmy Vetayases /* 1997ff178cdSJimmy Vetayases * apix_lock is used for cpu selection and vector re-binding 2007ff178cdSJimmy Vetayases */ 2017ff178cdSJimmy Vetayases lock_t apix_lock; 2027ff178cdSJimmy Vetayases apix_impl_t *apixs[NCPU]; 2037ff178cdSJimmy Vetayases /* 2047ff178cdSJimmy Vetayases * Mapping between device interrupt and the allocated vector. Indexed 2057ff178cdSJimmy Vetayases * by major number. 2067ff178cdSJimmy Vetayases */ 2077ff178cdSJimmy Vetayases apix_dev_vector_t **apix_dev_vector; 2087ff178cdSJimmy Vetayases /* 2097ff178cdSJimmy Vetayases * Mapping between device major number and cpu id. It gets used 2107ff178cdSJimmy Vetayases * when interrupt binding policy round robin with affinity is 2117ff178cdSJimmy Vetayases * applied. With that policy, devices with the same major number 2127ff178cdSJimmy Vetayases * will be bound to the same CPU. 2137ff178cdSJimmy Vetayases */ 2147ff178cdSJimmy Vetayases processorid_t *apix_major_to_cpu; /* major to cpu mapping */ 2157ff178cdSJimmy Vetayases kmutex_t apix_mutex; /* for apix_dev_vector & apix_major_to_cpu */ 2167ff178cdSJimmy Vetayases 2177ff178cdSJimmy Vetayases int apix_nipis = 16; /* Maximum number of IPIs */ 2187ff178cdSJimmy Vetayases /* 2197ff178cdSJimmy Vetayases * Maximum number of vectors in a CPU that can be used for interrupt 2207ff178cdSJimmy Vetayases * allocation (including IPIs and the reserved vectors). 2217ff178cdSJimmy Vetayases */ 2227ff178cdSJimmy Vetayases int apix_cpu_nvectors = APIX_NVECTOR; 2237ff178cdSJimmy Vetayases 224583cd330SHans Rosenfeld /* number of CPUs in power-on transition state */ 225583cd330SHans Rosenfeld static int apic_poweron_cnt = 0; 226583cd330SHans Rosenfeld 2277ff178cdSJimmy Vetayases /* gcpu.h */ 2287ff178cdSJimmy Vetayases 2297ff178cdSJimmy Vetayases extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp); 2307ff178cdSJimmy Vetayases extern void apic_change_eoi(); 2317ff178cdSJimmy Vetayases 2327ff178cdSJimmy Vetayases /* 2337ff178cdSJimmy Vetayases * This is the loadable module wrapper 2347ff178cdSJimmy Vetayases */ 2357ff178cdSJimmy Vetayases 2367ff178cdSJimmy Vetayases int 2377ff178cdSJimmy Vetayases _init(void) 2387ff178cdSJimmy Vetayases { 2397ff178cdSJimmy Vetayases if (apic_coarse_hrtime) 2407ff178cdSJimmy Vetayases apix_ops.psm_gethrtime = &apic_gettime; 2417ff178cdSJimmy Vetayases return (psm_mod_init(&apix_hdlp, &apix_psm_info)); 2427ff178cdSJimmy Vetayases } 2437ff178cdSJimmy Vetayases 2447ff178cdSJimmy Vetayases int 2457ff178cdSJimmy Vetayases _fini(void) 2467ff178cdSJimmy Vetayases { 2477ff178cdSJimmy Vetayases return (psm_mod_fini(&apix_hdlp, &apix_psm_info)); 2487ff178cdSJimmy Vetayases } 2497ff178cdSJimmy Vetayases 2507ff178cdSJimmy Vetayases int 2517ff178cdSJimmy Vetayases _info(struct modinfo *modinfop) 2527ff178cdSJimmy Vetayases { 2537ff178cdSJimmy Vetayases return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop)); 2547ff178cdSJimmy Vetayases } 2557ff178cdSJimmy Vetayases 2567ff178cdSJimmy Vetayases static int 2577ff178cdSJimmy Vetayases apix_probe() 2587ff178cdSJimmy Vetayases { 2597ff178cdSJimmy Vetayases int rval; 2607ff178cdSJimmy Vetayases 2617ff178cdSJimmy Vetayases if (apix_enable == 0) 2627ff178cdSJimmy Vetayases return (PSM_FAILURE); 2637ff178cdSJimmy Vetayases 26415f8fb31SYuri Pankov /* 26515f8fb31SYuri Pankov * FIXME Temporarily disable apix module on Xen HVM platform due to 26615f8fb31SYuri Pankov * known hang during boot (see #3605). 26715f8fb31SYuri Pankov * 26815f8fb31SYuri Pankov * Please remove when/if the issue is resolved. 26915f8fb31SYuri Pankov */ 270*0f8051a0SYuri Pankov if (get_hwenv() & HW_XEN_HVM) 27115f8fb31SYuri Pankov return (PSM_FAILURE); 27215f8fb31SYuri Pankov 2737ff178cdSJimmy Vetayases /* check for hw features if specified */ 2747ff178cdSJimmy Vetayases if (apix_hw_chk_enable) { 2757ff178cdSJimmy Vetayases /* check if x2APIC mode is supported */ 2767ff178cdSJimmy Vetayases if ((apix_supported_hw & APIX_SUPPORT_X2APIC) == 2777ff178cdSJimmy Vetayases APIX_SUPPORT_X2APIC) { 278a51869cdSHans Rosenfeld if (apic_local_mode() == LOCAL_X2APIC) { 279a51869cdSHans Rosenfeld /* x2APIC mode activated by BIOS, switch ops */ 280a51869cdSHans Rosenfeld apic_mode = LOCAL_X2APIC; 281a51869cdSHans Rosenfeld apic_change_ops(); 282a51869cdSHans Rosenfeld } else if (!apic_detect_x2apic()) { 2837ff178cdSJimmy Vetayases /* x2APIC mode is not supported in the hw */ 2847ff178cdSJimmy Vetayases apix_enable = 0; 2857ff178cdSJimmy Vetayases } 2867ff178cdSJimmy Vetayases } 2877ff178cdSJimmy Vetayases if (apix_enable == 0) 2887ff178cdSJimmy Vetayases return (PSM_FAILURE); 2897ff178cdSJimmy Vetayases } 2907ff178cdSJimmy Vetayases 2917ff178cdSJimmy Vetayases rval = apic_probe_common(apix_psm_info.p_mach_idstring); 2927ff178cdSJimmy Vetayases if (rval == PSM_SUCCESS) 2937ff178cdSJimmy Vetayases apix_is_enabled = 1; 2947ff178cdSJimmy Vetayases else 2957ff178cdSJimmy Vetayases apix_is_enabled = 0; 2967ff178cdSJimmy Vetayases return (rval); 2977ff178cdSJimmy Vetayases } 2987ff178cdSJimmy Vetayases 2997ff178cdSJimmy Vetayases /* 3007ff178cdSJimmy Vetayases * Initialize the data structures needed by pcplusmpx module. 3017ff178cdSJimmy Vetayases * Specifically, the data structures used by addspl() and delspl() 3027ff178cdSJimmy Vetayases * routines. 3037ff178cdSJimmy Vetayases */ 3047ff178cdSJimmy Vetayases static void 3057ff178cdSJimmy Vetayases apix_softinit() 3067ff178cdSJimmy Vetayases { 3077ff178cdSJimmy Vetayases int i, *iptr; 3087ff178cdSJimmy Vetayases apix_impl_t *hdlp; 3097ff178cdSJimmy Vetayases int nproc; 3107ff178cdSJimmy Vetayases 3117ff178cdSJimmy Vetayases nproc = max(apic_nproc, apic_max_nproc); 3127ff178cdSJimmy Vetayases 3137ff178cdSJimmy Vetayases hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP); 3147ff178cdSJimmy Vetayases for (i = 0; i < nproc; i++) { 3157ff178cdSJimmy Vetayases apixs[i] = &hdlp[i]; 3167ff178cdSJimmy Vetayases apixs[i]->x_cpuid = i; 3177ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apixs[i]->x_lock); 3187ff178cdSJimmy Vetayases } 3197ff178cdSJimmy Vetayases 3207ff178cdSJimmy Vetayases /* cpu 0 is always up (for now) */ 3217ff178cdSJimmy Vetayases apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE; 3227ff178cdSJimmy Vetayases 3237ff178cdSJimmy Vetayases iptr = (int *)&apic_irq_table[0]; 3247ff178cdSJimmy Vetayases for (i = 0; i <= APIC_MAX_VECTOR; i++) { 3257ff178cdSJimmy Vetayases apic_level_intr[i] = 0; 3267ff178cdSJimmy Vetayases *iptr++ = NULL; 3277ff178cdSJimmy Vetayases } 3287ff178cdSJimmy Vetayases mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL); 3297ff178cdSJimmy Vetayases 3307ff178cdSJimmy Vetayases apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt, 3317ff178cdSJimmy Vetayases KM_SLEEP); 3327ff178cdSJimmy Vetayases 3337ff178cdSJimmy Vetayases if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) { 3347ff178cdSJimmy Vetayases apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt, 3357ff178cdSJimmy Vetayases KM_SLEEP); 3367ff178cdSJimmy Vetayases for (i = 0; i < devcnt; i++) 3377ff178cdSJimmy Vetayases apix_major_to_cpu[i] = IRQ_UNINIT; 3387ff178cdSJimmy Vetayases } 3397ff178cdSJimmy Vetayases 3407ff178cdSJimmy Vetayases mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL); 3417ff178cdSJimmy Vetayases } 3427ff178cdSJimmy Vetayases 3437ff178cdSJimmy Vetayases static int 3447ff178cdSJimmy Vetayases apix_get_pending_spl(void) 3457ff178cdSJimmy Vetayases { 3467ff178cdSJimmy Vetayases int cpuid = CPU->cpu_id; 3477ff178cdSJimmy Vetayases 3487ff178cdSJimmy Vetayases return (bsrw_insn(apixs[cpuid]->x_intr_pending)); 3497ff178cdSJimmy Vetayases } 3507ff178cdSJimmy Vetayases 3517ff178cdSJimmy Vetayases static uintptr_t 3527ff178cdSJimmy Vetayases apix_get_intr_handler(int cpu, short vec) 3537ff178cdSJimmy Vetayases { 3547ff178cdSJimmy Vetayases apix_vector_t *apix_vector; 3557ff178cdSJimmy Vetayases 3567ff178cdSJimmy Vetayases ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR); 3577ff178cdSJimmy Vetayases if (cpu >= apic_nproc) 3587ff178cdSJimmy Vetayases return (NULL); 3597ff178cdSJimmy Vetayases 3607ff178cdSJimmy Vetayases apix_vector = apixs[cpu]->x_vectbl[vec]; 3617ff178cdSJimmy Vetayases 3627ff178cdSJimmy Vetayases return ((uintptr_t)(apix_vector->v_autovect)); 3637ff178cdSJimmy Vetayases } 3647ff178cdSJimmy Vetayases 3657ff178cdSJimmy Vetayases static void 3667ff178cdSJimmy Vetayases apix_init() 3677ff178cdSJimmy Vetayases { 3687ff178cdSJimmy Vetayases extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *); 3697ff178cdSJimmy Vetayases 3707ff178cdSJimmy Vetayases APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n")); 3717ff178cdSJimmy Vetayases 3727ff178cdSJimmy Vetayases do_interrupt_common = apix_do_interrupt; 3737ff178cdSJimmy Vetayases addintr = apix_add_avintr; 3747ff178cdSJimmy Vetayases remintr = apix_rem_avintr; 3757ff178cdSJimmy Vetayases get_pending_spl = apix_get_pending_spl; 3767ff178cdSJimmy Vetayases get_intr_handler = apix_get_intr_handler; 3777ff178cdSJimmy Vetayases psm_get_localapicid = apic_get_localapicid; 3787ff178cdSJimmy Vetayases psm_get_ioapicid = apic_get_ioapicid; 3797ff178cdSJimmy Vetayases 3807ff178cdSJimmy Vetayases apix_softinit(); 38132842aabSJosef 'Jeff' Sipek 38232842aabSJosef 'Jeff' Sipek #if !defined(__amd64) 3837ff178cdSJimmy Vetayases if (cpuid_have_cr8access(CPU)) 3847ff178cdSJimmy Vetayases apic_have_32bit_cr8 = 1; 38532842aabSJosef 'Jeff' Sipek #endif 3867ff178cdSJimmy Vetayases 3877ff178cdSJimmy Vetayases /* 3887ff178cdSJimmy Vetayases * Initialize IRM pool parameters 3897ff178cdSJimmy Vetayases */ 3907ff178cdSJimmy Vetayases if (irm_enable) { 3917ff178cdSJimmy Vetayases int i; 3927ff178cdSJimmy Vetayases int lowest_irq; 3937ff178cdSJimmy Vetayases int highest_irq; 3947ff178cdSJimmy Vetayases 3957ff178cdSJimmy Vetayases /* number of CPUs present */ 3967ff178cdSJimmy Vetayases apix_irminfo.apix_ncpus = apic_nproc; 3977ff178cdSJimmy Vetayases /* total number of entries in all of the IOAPICs present */ 3987ff178cdSJimmy Vetayases lowest_irq = apic_io_vectbase[0]; 3997ff178cdSJimmy Vetayases highest_irq = apic_io_vectend[0]; 4007ff178cdSJimmy Vetayases for (i = 1; i < apic_io_max; i++) { 4017ff178cdSJimmy Vetayases if (apic_io_vectbase[i] < lowest_irq) 4027ff178cdSJimmy Vetayases lowest_irq = apic_io_vectbase[i]; 4037ff178cdSJimmy Vetayases if (apic_io_vectend[i] > highest_irq) 4047ff178cdSJimmy Vetayases highest_irq = apic_io_vectend[i]; 4057ff178cdSJimmy Vetayases } 4067ff178cdSJimmy Vetayases apix_irminfo.apix_ioapic_max_vectors = 4077ff178cdSJimmy Vetayases highest_irq - lowest_irq + 1; 4087ff178cdSJimmy Vetayases /* 4097ff178cdSJimmy Vetayases * Number of available per-CPU vectors excluding 4107ff178cdSJimmy Vetayases * reserved vectors for Dtrace, int80, system-call, 4117ff178cdSJimmy Vetayases * fast-trap, etc. 4127ff178cdSJimmy Vetayases */ 4137ff178cdSJimmy Vetayases apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR - 4147ff178cdSJimmy Vetayases APIX_SW_RESERVED_VECTORS; 4157ff178cdSJimmy Vetayases 4167ff178cdSJimmy Vetayases /* Number of vectors (pre) allocated (SCI and HPET) */ 4177ff178cdSJimmy Vetayases apix_irminfo.apix_vectors_allocated = 0; 4187ff178cdSJimmy Vetayases if (apic_hpet_vect != -1) 4197ff178cdSJimmy Vetayases apix_irminfo.apix_vectors_allocated++; 4207ff178cdSJimmy Vetayases if (apic_sci_vect != -1) 4217ff178cdSJimmy Vetayases apix_irminfo.apix_vectors_allocated++; 4227ff178cdSJimmy Vetayases } 4237ff178cdSJimmy Vetayases } 4247ff178cdSJimmy Vetayases 4257ff178cdSJimmy Vetayases static void 4267ff178cdSJimmy Vetayases apix_init_intr() 4277ff178cdSJimmy Vetayases { 4287ff178cdSJimmy Vetayases processorid_t cpun = psm_get_cpu_id(); 4297ff178cdSJimmy Vetayases uint_t nlvt; 4307ff178cdSJimmy Vetayases uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 4317ff178cdSJimmy Vetayases extern void cmi_cmci_trap(void); 4327ff178cdSJimmy Vetayases 4337ff178cdSJimmy Vetayases apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 4347ff178cdSJimmy Vetayases 4357ff178cdSJimmy Vetayases if (apic_mode == LOCAL_APIC) { 4367ff178cdSJimmy Vetayases /* 4377ff178cdSJimmy Vetayases * We are running APIC in MMIO mode. 4387ff178cdSJimmy Vetayases */ 4397ff178cdSJimmy Vetayases if (apic_flat_model) { 4407ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_FORMAT_REG, 4417ff178cdSJimmy Vetayases APIC_FLAT_MODEL); 4427ff178cdSJimmy Vetayases } else { 4437ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_FORMAT_REG, 4447ff178cdSJimmy Vetayases APIC_CLUSTER_MODEL); 4457ff178cdSJimmy Vetayases } 4467ff178cdSJimmy Vetayases 4477ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_DEST_REG, 4487ff178cdSJimmy Vetayases AV_HIGH_ORDER >> cpun); 4497ff178cdSJimmy Vetayases } 4507ff178cdSJimmy Vetayases 4517ff178cdSJimmy Vetayases if (apic_directed_EOI_supported()) { 4527ff178cdSJimmy Vetayases /* 4537ff178cdSJimmy Vetayases * Setting the 12th bit in the Spurious Interrupt Vector 4547ff178cdSJimmy Vetayases * Register suppresses broadcast EOIs generated by the local 4557ff178cdSJimmy Vetayases * APIC. The suppression of broadcast EOIs happens only when 4567ff178cdSJimmy Vetayases * interrupts are level-triggered. 4577ff178cdSJimmy Vetayases */ 4587ff178cdSJimmy Vetayases svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 4597ff178cdSJimmy Vetayases } 4607ff178cdSJimmy Vetayases 4617ff178cdSJimmy Vetayases /* need to enable APIC before unmasking NMI */ 4627ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 4637ff178cdSJimmy Vetayases 4647ff178cdSJimmy Vetayases /* 4657ff178cdSJimmy Vetayases * Presence of an invalid vector with delivery mode AV_FIXED can 4667ff178cdSJimmy Vetayases * cause an error interrupt, even if the entry is masked...so 4677ff178cdSJimmy Vetayases * write a valid vector to LVT entries along with the mask bit 4687ff178cdSJimmy Vetayases */ 4697ff178cdSJimmy Vetayases 4707ff178cdSJimmy Vetayases /* All APICs have timer and LINT0/1 */ 4717ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 4727ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 4737ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 4747ff178cdSJimmy Vetayases 4757ff178cdSJimmy Vetayases /* 4767ff178cdSJimmy Vetayases * On integrated APICs, the number of LVT entries is 4777ff178cdSJimmy Vetayases * 'Max LVT entry' + 1; on 82489DX's (non-integrated 4787ff178cdSJimmy Vetayases * APICs), nlvt is "3" (LINT0, LINT1, and timer) 4797ff178cdSJimmy Vetayases */ 4807ff178cdSJimmy Vetayases 4817ff178cdSJimmy Vetayases if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 4827ff178cdSJimmy Vetayases nlvt = 3; 4837ff178cdSJimmy Vetayases } else { 4847ff178cdSJimmy Vetayases nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 4857ff178cdSJimmy Vetayases 0xFF) + 1; 4867ff178cdSJimmy Vetayases } 4877ff178cdSJimmy Vetayases 4887ff178cdSJimmy Vetayases if (nlvt >= 5) { 4897ff178cdSJimmy Vetayases /* Enable performance counter overflow interrupt */ 4907ff178cdSJimmy Vetayases 4917417cfdeSKuriakose Kuruvilla if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 4927ff178cdSJimmy Vetayases apic_enable_cpcovf_intr = 0; 4937ff178cdSJimmy Vetayases if (apic_enable_cpcovf_intr) { 4947ff178cdSJimmy Vetayases if (apic_cpcovf_vect == 0) { 4957ff178cdSJimmy Vetayases int ipl = APIC_PCINT_IPL; 4967ff178cdSJimmy Vetayases 4977ff178cdSJimmy Vetayases apic_cpcovf_vect = apix_get_ipivect(ipl, -1); 4987ff178cdSJimmy Vetayases ASSERT(apic_cpcovf_vect); 4997ff178cdSJimmy Vetayases 5007ff178cdSJimmy Vetayases (void) add_avintr(NULL, ipl, 5017ff178cdSJimmy Vetayases (avfunc)kcpc_hw_overflow_intr, 5027ff178cdSJimmy Vetayases "apic pcint", apic_cpcovf_vect, 5037ff178cdSJimmy Vetayases NULL, NULL, NULL, NULL); 5047ff178cdSJimmy Vetayases kcpc_hw_overflow_intr_installed = 1; 5057ff178cdSJimmy Vetayases kcpc_hw_enable_cpc_intr = 5067ff178cdSJimmy Vetayases apic_cpcovf_mask_clear; 5077ff178cdSJimmy Vetayases } 5087ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_PCINT_VECT, 5097ff178cdSJimmy Vetayases apic_cpcovf_vect); 5107ff178cdSJimmy Vetayases } 5117ff178cdSJimmy Vetayases } 5127ff178cdSJimmy Vetayases 5137ff178cdSJimmy Vetayases if (nlvt >= 6) { 5147ff178cdSJimmy Vetayases /* Only mask TM intr if the BIOS apparently doesn't use it */ 5157ff178cdSJimmy Vetayases 5167ff178cdSJimmy Vetayases uint32_t lvtval; 5177ff178cdSJimmy Vetayases 5187ff178cdSJimmy Vetayases lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 5197ff178cdSJimmy Vetayases if (((lvtval & AV_MASK) == AV_MASK) || 5207ff178cdSJimmy Vetayases ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 5217ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_THERM_VECT, 5227ff178cdSJimmy Vetayases AV_MASK|APIC_RESV_IRQ); 5237ff178cdSJimmy Vetayases } 5247ff178cdSJimmy Vetayases } 5257ff178cdSJimmy Vetayases 5267ff178cdSJimmy Vetayases /* Enable error interrupt */ 5277ff178cdSJimmy Vetayases 5287ff178cdSJimmy Vetayases if (nlvt >= 4 && apic_enable_error_intr) { 5297ff178cdSJimmy Vetayases if (apic_errvect == 0) { 5307ff178cdSJimmy Vetayases int ipl = 0xf; /* get highest priority intr */ 5317ff178cdSJimmy Vetayases apic_errvect = apix_get_ipivect(ipl, -1); 5327ff178cdSJimmy Vetayases ASSERT(apic_errvect); 5337ff178cdSJimmy Vetayases /* 5347ff178cdSJimmy Vetayases * Not PSMI compliant, but we are going to merge 5357ff178cdSJimmy Vetayases * with ON anyway 5367ff178cdSJimmy Vetayases */ 5377ff178cdSJimmy Vetayases (void) add_avintr(NULL, ipl, 5387ff178cdSJimmy Vetayases (avfunc)apic_error_intr, "apic error intr", 5397ff178cdSJimmy Vetayases apic_errvect, NULL, NULL, NULL, NULL); 5407ff178cdSJimmy Vetayases } 5417ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 5427ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 5437ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 5447ff178cdSJimmy Vetayases } 5457ff178cdSJimmy Vetayases 5467ff178cdSJimmy Vetayases /* Enable CMCI interrupt */ 5477ff178cdSJimmy Vetayases if (cmi_enable_cmci) { 5487ff178cdSJimmy Vetayases mutex_enter(&cmci_cpu_setup_lock); 5497ff178cdSJimmy Vetayases if (cmci_cpu_setup_registered == 0) { 5507ff178cdSJimmy Vetayases mutex_enter(&cpu_lock); 5517ff178cdSJimmy Vetayases register_cpu_setup_func(cmci_cpu_setup, NULL); 5527ff178cdSJimmy Vetayases mutex_exit(&cpu_lock); 5537ff178cdSJimmy Vetayases cmci_cpu_setup_registered = 1; 5547ff178cdSJimmy Vetayases } 5557ff178cdSJimmy Vetayases mutex_exit(&cmci_cpu_setup_lock); 5567ff178cdSJimmy Vetayases 5577ff178cdSJimmy Vetayases if (apic_cmci_vect == 0) { 5587ff178cdSJimmy Vetayases int ipl = 0x2; 5597ff178cdSJimmy Vetayases apic_cmci_vect = apix_get_ipivect(ipl, -1); 5607ff178cdSJimmy Vetayases ASSERT(apic_cmci_vect); 5617ff178cdSJimmy Vetayases 5627ff178cdSJimmy Vetayases (void) add_avintr(NULL, ipl, 5637ff178cdSJimmy Vetayases (avfunc)cmi_cmci_trap, "apic cmci intr", 5647ff178cdSJimmy Vetayases apic_cmci_vect, NULL, NULL, NULL, NULL); 5657ff178cdSJimmy Vetayases } 5667ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 5677ff178cdSJimmy Vetayases } 5687ff178cdSJimmy Vetayases 5697ff178cdSJimmy Vetayases apic_reg_ops->apic_write_task_reg(0); 5707ff178cdSJimmy Vetayases } 5717ff178cdSJimmy Vetayases 5727ff178cdSJimmy Vetayases static void 5737ff178cdSJimmy Vetayases apix_picinit(void) 5747ff178cdSJimmy Vetayases { 5757ff178cdSJimmy Vetayases int i, j; 5767ff178cdSJimmy Vetayases uint_t isr; 5777ff178cdSJimmy Vetayases 5787ff178cdSJimmy Vetayases APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n")); 5797ff178cdSJimmy Vetayases 5807ff178cdSJimmy Vetayases /* 5817ff178cdSJimmy Vetayases * initialize interrupt remapping before apic 5827ff178cdSJimmy Vetayases * hardware initialization 5837ff178cdSJimmy Vetayases */ 5847ff178cdSJimmy Vetayases apic_intrmap_init(apic_mode); 5857ff178cdSJimmy Vetayases if (apic_vt_ops == psm_vt_ops) 5867ff178cdSJimmy Vetayases apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR; 5877ff178cdSJimmy Vetayases 5887ff178cdSJimmy Vetayases /* 5897ff178cdSJimmy Vetayases * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 5907ff178cdSJimmy Vetayases * bit on without clearing it with EOI. Since softint 5917ff178cdSJimmy Vetayases * uses vector 0x20 to interrupt itself, so softint will 5927ff178cdSJimmy Vetayases * not work on this machine. In order to fix this problem 5937ff178cdSJimmy Vetayases * a check is made to verify all the isr bits are clear. 5947ff178cdSJimmy Vetayases * If not, EOIs are issued to clear the bits. 5957ff178cdSJimmy Vetayases */ 5967ff178cdSJimmy Vetayases for (i = 7; i >= 1; i--) { 5977ff178cdSJimmy Vetayases isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 5987ff178cdSJimmy Vetayases if (isr != 0) 5997ff178cdSJimmy Vetayases for (j = 0; ((j < 32) && (isr != 0)); j++) 6007ff178cdSJimmy Vetayases if (isr & (1 << j)) { 6017ff178cdSJimmy Vetayases apic_reg_ops->apic_write( 6027ff178cdSJimmy Vetayases APIC_EOI_REG, 0); 6037ff178cdSJimmy Vetayases isr &= ~(1 << j); 6047ff178cdSJimmy Vetayases apic_error |= APIC_ERR_BOOT_EOI; 6057ff178cdSJimmy Vetayases } 6067ff178cdSJimmy Vetayases } 6077ff178cdSJimmy Vetayases 6087ff178cdSJimmy Vetayases /* set a flag so we know we have run apic_picinit() */ 6097ff178cdSJimmy Vetayases apic_picinit_called = 1; 6107ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apic_gethrtime_lock); 6117ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apic_ioapic_lock); 6127ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apic_error_lock); 6137ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apic_mode_switch_lock); 6147ff178cdSJimmy Vetayases 6157ff178cdSJimmy Vetayases picsetup(); /* initialise the 8259 */ 6167ff178cdSJimmy Vetayases 6177ff178cdSJimmy Vetayases /* add nmi handler - least priority nmi handler */ 6187ff178cdSJimmy Vetayases LOCK_INIT_CLEAR(&apic_nmi_lock); 6197ff178cdSJimmy Vetayases 6207ff178cdSJimmy Vetayases if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 6217ff178cdSJimmy Vetayases "apix NMI handler", (caddr_t)NULL)) 6227ff178cdSJimmy Vetayases cmn_err(CE_WARN, "apix: Unable to add nmi handler"); 6237ff178cdSJimmy Vetayases 6247ff178cdSJimmy Vetayases apix_init_intr(); 6257ff178cdSJimmy Vetayases 6267ff178cdSJimmy Vetayases /* enable apic mode if imcr present */ 6277ff178cdSJimmy Vetayases if (apic_imcrp) { 6287ff178cdSJimmy Vetayases outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 6297ff178cdSJimmy Vetayases outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 6307ff178cdSJimmy Vetayases } 6317ff178cdSJimmy Vetayases 6327ff178cdSJimmy Vetayases ioapix_init_intr(IOAPIC_MASK); 6337ff178cdSJimmy Vetayases 6347ff178cdSJimmy Vetayases /* setup global IRM pool if applicable */ 6357ff178cdSJimmy Vetayases if (irm_enable) 6367ff178cdSJimmy Vetayases apix_irm_init(); 6377ff178cdSJimmy Vetayases } 6387ff178cdSJimmy Vetayases 6397ff178cdSJimmy Vetayases static __inline__ void 6407ff178cdSJimmy Vetayases apix_send_eoi(void) 6417ff178cdSJimmy Vetayases { 6427ff178cdSJimmy Vetayases if (apic_mode == LOCAL_APIC) 6437ff178cdSJimmy Vetayases LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0); 6447ff178cdSJimmy Vetayases else 6457ff178cdSJimmy Vetayases X2APIC_WRITE(APIC_EOI_REG, 0); 6467ff178cdSJimmy Vetayases } 6477ff178cdSJimmy Vetayases 6487ff178cdSJimmy Vetayases /* 6497ff178cdSJimmy Vetayases * platform_intr_enter 6507ff178cdSJimmy Vetayases * 651636dfb4bSJerry Jelinek * Called at the beginning of the interrupt service routine, but unlike 652636dfb4bSJerry Jelinek * pcplusmp, does not mask interrupts. An EOI is given to the interrupt 653636dfb4bSJerry Jelinek * controller to enable other HW interrupts but interrupts are still 654636dfb4bSJerry Jelinek * masked by the IF flag. 6557ff178cdSJimmy Vetayases * 6567ff178cdSJimmy Vetayases * Return -1 for spurious interrupts 6577ff178cdSJimmy Vetayases * 6587ff178cdSJimmy Vetayases */ 6597ff178cdSJimmy Vetayases static int 6607ff178cdSJimmy Vetayases apix_intr_enter(int ipl, int *vectorp) 6617ff178cdSJimmy Vetayases { 6627ff178cdSJimmy Vetayases struct cpu *cpu = CPU; 6637ff178cdSJimmy Vetayases uint32_t cpuid = CPU->cpu_id; 6647ff178cdSJimmy Vetayases apic_cpus_info_t *cpu_infop; 6657ff178cdSJimmy Vetayases uchar_t vector; 6667ff178cdSJimmy Vetayases apix_vector_t *vecp; 6677ff178cdSJimmy Vetayases int nipl = -1; 6687ff178cdSJimmy Vetayases 6697ff178cdSJimmy Vetayases /* 6707ff178cdSJimmy Vetayases * The real vector delivered is (*vectorp + 0x20), but our caller 6717ff178cdSJimmy Vetayases * subtracts 0x20 from the vector before passing it to us. 6727ff178cdSJimmy Vetayases * (That's why APIC_BASE_VECT is 0x20.) 6737ff178cdSJimmy Vetayases */ 6747ff178cdSJimmy Vetayases vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT; 6757ff178cdSJimmy Vetayases 6767ff178cdSJimmy Vetayases cpu_infop = &apic_cpus[cpuid]; 6777ff178cdSJimmy Vetayases if (vector == APIC_SPUR_INTR) { 6787ff178cdSJimmy Vetayases cpu_infop->aci_spur_cnt++; 6797ff178cdSJimmy Vetayases return (APIC_INT_SPURIOUS); 6807ff178cdSJimmy Vetayases } 6817ff178cdSJimmy Vetayases 6827ff178cdSJimmy Vetayases vecp = xv_vector(cpuid, vector); 6837ff178cdSJimmy Vetayases if (vecp == NULL) { 6847ff178cdSJimmy Vetayases if (APIX_IS_FAKE_INTR(vector)) 6857ff178cdSJimmy Vetayases nipl = apix_rebindinfo.i_pri; 6867ff178cdSJimmy Vetayases apix_send_eoi(); 6877ff178cdSJimmy Vetayases return (nipl); 6887ff178cdSJimmy Vetayases } 6897ff178cdSJimmy Vetayases nipl = vecp->v_pri; 6907ff178cdSJimmy Vetayases 6917ff178cdSJimmy Vetayases /* if interrupted by the clock, increment apic_nsec_since_boot */ 6927ff178cdSJimmy Vetayases if (vector == (apic_clkvect + APIC_BASE_VECT)) { 6937ff178cdSJimmy Vetayases if (!apic_oneshot) { 6947ff178cdSJimmy Vetayases /* NOTE: this is not MT aware */ 6957ff178cdSJimmy Vetayases apic_hrtime_stamp++; 6967ff178cdSJimmy Vetayases apic_nsec_since_boot += apic_nsec_per_intr; 6977ff178cdSJimmy Vetayases apic_hrtime_stamp++; 6987ff178cdSJimmy Vetayases last_count_read = apic_hertz_count; 6997ff178cdSJimmy Vetayases apix_redistribute_compute(); 7007ff178cdSJimmy Vetayases } 7017ff178cdSJimmy Vetayases 7027ff178cdSJimmy Vetayases apix_send_eoi(); 7037ff178cdSJimmy Vetayases 7047ff178cdSJimmy Vetayases return (nipl); 7057ff178cdSJimmy Vetayases } 7067ff178cdSJimmy Vetayases 7077ff178cdSJimmy Vetayases ASSERT(vecp->v_state != APIX_STATE_OBSOLETED); 7087ff178cdSJimmy Vetayases 7097ff178cdSJimmy Vetayases /* pre-EOI handling for level-triggered interrupts */ 7107ff178cdSJimmy Vetayases if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) && 7117ff178cdSJimmy Vetayases (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum]) 7127ff178cdSJimmy Vetayases apix_level_intr_pre_eoi(vecp->v_inum); 7137ff178cdSJimmy Vetayases 7147ff178cdSJimmy Vetayases /* send back EOI */ 7157ff178cdSJimmy Vetayases apix_send_eoi(); 7167ff178cdSJimmy Vetayases 7177ff178cdSJimmy Vetayases cpu_infop->aci_current[nipl] = vector; 7187ff178cdSJimmy Vetayases if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) { 7197ff178cdSJimmy Vetayases cpu_infop->aci_curipl = (uchar_t)nipl; 7207ff178cdSJimmy Vetayases cpu_infop->aci_ISR_in_progress |= 1 << nipl; 7217ff178cdSJimmy Vetayases } 7227ff178cdSJimmy Vetayases 7237ff178cdSJimmy Vetayases #ifdef DEBUG 7247ff178cdSJimmy Vetayases if (vector >= APIX_IPI_MIN) 7257ff178cdSJimmy Vetayases return (nipl); /* skip IPI */ 7267ff178cdSJimmy Vetayases 7277ff178cdSJimmy Vetayases APIC_DEBUG_BUF_PUT(vector); 7287ff178cdSJimmy Vetayases APIC_DEBUG_BUF_PUT(vecp->v_inum); 7297ff178cdSJimmy Vetayases APIC_DEBUG_BUF_PUT(nipl); 7307ff178cdSJimmy Vetayases APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 7317ff178cdSJimmy Vetayases if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 7327ff178cdSJimmy Vetayases drv_usecwait(apic_stretch_interrupts); 7337ff178cdSJimmy Vetayases #endif /* DEBUG */ 7347ff178cdSJimmy Vetayases 7357ff178cdSJimmy Vetayases return (nipl); 7367ff178cdSJimmy Vetayases } 7377ff178cdSJimmy Vetayases 7387ff178cdSJimmy Vetayases /* 7397ff178cdSJimmy Vetayases * Any changes made to this function must also change X2APIC 7407ff178cdSJimmy Vetayases * version of intr_exit. 7417ff178cdSJimmy Vetayases */ 7427ff178cdSJimmy Vetayases static void 7437ff178cdSJimmy Vetayases apix_intr_exit(int prev_ipl, int arg2) 7447ff178cdSJimmy Vetayases { 7457ff178cdSJimmy Vetayases int cpuid = psm_get_cpu_id(); 7467ff178cdSJimmy Vetayases apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid]; 7477ff178cdSJimmy Vetayases apix_impl_t *apixp = apixs[cpuid]; 7487ff178cdSJimmy Vetayases 7497ff178cdSJimmy Vetayases UNREFERENCED_1PARAMETER(arg2); 7507ff178cdSJimmy Vetayases 7517ff178cdSJimmy Vetayases cpu_infop->aci_curipl = (uchar_t)prev_ipl; 7527ff178cdSJimmy Vetayases /* ISR above current pri could not be in progress */ 7537ff178cdSJimmy Vetayases cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; 7547ff178cdSJimmy Vetayases 7557ff178cdSJimmy Vetayases if (apixp->x_obsoletes != NULL) { 7567ff178cdSJimmy Vetayases if (APIX_CPU_LOCK_HELD(cpuid)) 7577ff178cdSJimmy Vetayases return; 7587ff178cdSJimmy Vetayases 7597ff178cdSJimmy Vetayases APIX_ENTER_CPU_LOCK(cpuid); 7607ff178cdSJimmy Vetayases (void) apix_obsolete_vector(apixp->x_obsoletes); 7617ff178cdSJimmy Vetayases APIX_LEAVE_CPU_LOCK(cpuid); 7627ff178cdSJimmy Vetayases } 7637ff178cdSJimmy Vetayases } 7647ff178cdSJimmy Vetayases 7657ff178cdSJimmy Vetayases /* 766636dfb4bSJerry Jelinek * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the 767636dfb4bSJerry Jelinek * given ipl, but apix never uses the TPR and we never mask a subset of the 768636dfb4bSJerry Jelinek * interrupts. They are either all blocked by the IF flag or all can come in. 769636dfb4bSJerry Jelinek * 770636dfb4bSJerry Jelinek * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts 771636dfb4bSJerry Jelinek * can come in if currently enabled by the IF flag. This table shows the state 772636dfb4bSJerry Jelinek * of the IF flag when we leave this function. 773636dfb4bSJerry Jelinek * 774636dfb4bSJerry Jelinek * curr IF | ipl == 15 ipl != 15 775636dfb4bSJerry Jelinek * --------+--------------------------- 776636dfb4bSJerry Jelinek * 0 | 0 0 777636dfb4bSJerry Jelinek * 1 | 0 1 7787ff178cdSJimmy Vetayases */ 7797ff178cdSJimmy Vetayases static void 7807ff178cdSJimmy Vetayases apix_setspl(int ipl) 7817ff178cdSJimmy Vetayases { 7827ff178cdSJimmy Vetayases /* 783636dfb4bSJerry Jelinek * Interrupts at ipl above this cannot be in progress, so the following 784636dfb4bSJerry Jelinek * mask is ok. 7857ff178cdSJimmy Vetayases */ 7867ff178cdSJimmy Vetayases apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 7877ff178cdSJimmy Vetayases 788636dfb4bSJerry Jelinek if (ipl == XC_HI_PIL) 789636dfb4bSJerry Jelinek cli(); 7907ff178cdSJimmy Vetayases } 7917ff178cdSJimmy Vetayases 7927ff178cdSJimmy Vetayases int 7937ff178cdSJimmy Vetayases apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl) 7947ff178cdSJimmy Vetayases { 7957ff178cdSJimmy Vetayases uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec); 7967ff178cdSJimmy Vetayases uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec); 7977ff178cdSJimmy Vetayases apix_vector_t *vecp = xv_vector(cpuid, vector); 7987ff178cdSJimmy Vetayases 7997ff178cdSJimmy Vetayases UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl); 8007ff178cdSJimmy Vetayases ASSERT(vecp != NULL && LOCK_HELD(&apix_lock)); 8017ff178cdSJimmy Vetayases 8027ff178cdSJimmy Vetayases if (vecp->v_type == APIX_TYPE_FIXED) 8037ff178cdSJimmy Vetayases apix_intx_set_shared(vecp->v_inum, 1); 8047ff178cdSJimmy Vetayases 8057ff178cdSJimmy Vetayases /* There are more interrupts, so it's already been enabled */ 8067ff178cdSJimmy Vetayases if (vecp->v_share > 1) 8077ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8087ff178cdSJimmy Vetayases 8097ff178cdSJimmy Vetayases /* return if it is not hardware interrupt */ 8107ff178cdSJimmy Vetayases if (vecp->v_type == APIX_TYPE_IPI) 8117ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8127ff178cdSJimmy Vetayases 8137ff178cdSJimmy Vetayases /* 8147ff178cdSJimmy Vetayases * if apix_picinit() has not been called yet, just return. 8157ff178cdSJimmy Vetayases * At the end of apic_picinit(), we will call setup_io_intr(). 8167ff178cdSJimmy Vetayases */ 8177ff178cdSJimmy Vetayases if (!apic_picinit_called) 8187ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8197ff178cdSJimmy Vetayases 8207ff178cdSJimmy Vetayases (void) apix_setup_io_intr(vecp); 8217ff178cdSJimmy Vetayases 8227ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8237ff178cdSJimmy Vetayases } 8247ff178cdSJimmy Vetayases 8257ff178cdSJimmy Vetayases int 8267ff178cdSJimmy Vetayases apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl) 8277ff178cdSJimmy Vetayases { 8287ff178cdSJimmy Vetayases uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec); 8297ff178cdSJimmy Vetayases uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec); 8307ff178cdSJimmy Vetayases apix_vector_t *vecp = xv_vector(cpuid, vector); 8317ff178cdSJimmy Vetayases 8327ff178cdSJimmy Vetayases UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl); 8337ff178cdSJimmy Vetayases ASSERT(vecp != NULL && LOCK_HELD(&apix_lock)); 8347ff178cdSJimmy Vetayases 8357ff178cdSJimmy Vetayases if (vecp->v_type == APIX_TYPE_FIXED) 8367ff178cdSJimmy Vetayases apix_intx_set_shared(vecp->v_inum, -1); 8377ff178cdSJimmy Vetayases 8387ff178cdSJimmy Vetayases /* There are more interrupts */ 8397ff178cdSJimmy Vetayases if (vecp->v_share > 1) 8407ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8417ff178cdSJimmy Vetayases 8427ff178cdSJimmy Vetayases /* return if it is not hardware interrupt */ 8437ff178cdSJimmy Vetayases if (vecp->v_type == APIX_TYPE_IPI) 8447ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8457ff178cdSJimmy Vetayases 8467ff178cdSJimmy Vetayases if (!apic_picinit_called) { 8477ff178cdSJimmy Vetayases cmn_err(CE_WARN, "apix: delete 0x%x before apic init", 8487ff178cdSJimmy Vetayases virtvec); 8497ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8507ff178cdSJimmy Vetayases } 8517ff178cdSJimmy Vetayases 8527ff178cdSJimmy Vetayases apix_disable_vector(vecp); 8537ff178cdSJimmy Vetayases 8547ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8557ff178cdSJimmy Vetayases } 8567ff178cdSJimmy Vetayases 8577ff178cdSJimmy Vetayases /* 8587ff178cdSJimmy Vetayases * Try and disable all interrupts. We just assign interrupts to other 8597ff178cdSJimmy Vetayases * processors based on policy. If any were bound by user request, we 8607ff178cdSJimmy Vetayases * let them continue and return failure. We do not bother to check 8617ff178cdSJimmy Vetayases * for cache affinity while rebinding. 8627ff178cdSJimmy Vetayases */ 8637ff178cdSJimmy Vetayases static int 8647ff178cdSJimmy Vetayases apix_disable_intr(processorid_t cpun) 8657ff178cdSJimmy Vetayases { 8667ff178cdSJimmy Vetayases apix_impl_t *apixp = apixs[cpun]; 8677ff178cdSJimmy Vetayases apix_vector_t *vecp, *newp; 8687ff178cdSJimmy Vetayases int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type; 8697ff178cdSJimmy Vetayases 8707ff178cdSJimmy Vetayases lock_set(&apix_lock); 8717ff178cdSJimmy Vetayases 8727ff178cdSJimmy Vetayases apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 8737ff178cdSJimmy Vetayases apic_cpus[cpun].aci_curipl = 0; 8747ff178cdSJimmy Vetayases 8757ff178cdSJimmy Vetayases /* if this is for SUSPEND operation, skip rebinding */ 8767ff178cdSJimmy Vetayases if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) { 8777ff178cdSJimmy Vetayases for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { 8787ff178cdSJimmy Vetayases vecp = apixp->x_vectbl[i]; 8797ff178cdSJimmy Vetayases if (!IS_VECT_ENABLED(vecp)) 8807ff178cdSJimmy Vetayases continue; 8817ff178cdSJimmy Vetayases 8827ff178cdSJimmy Vetayases apix_disable_vector(vecp); 8837ff178cdSJimmy Vetayases } 8847ff178cdSJimmy Vetayases lock_clear(&apix_lock); 8857ff178cdSJimmy Vetayases return (PSM_SUCCESS); 8867ff178cdSJimmy Vetayases } 8877ff178cdSJimmy Vetayases 8887ff178cdSJimmy Vetayases for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { 8897ff178cdSJimmy Vetayases vecp = apixp->x_vectbl[i]; 8907ff178cdSJimmy Vetayases if (!IS_VECT_ENABLED(vecp)) 8917ff178cdSJimmy Vetayases continue; 8927ff178cdSJimmy Vetayases 8937ff178cdSJimmy Vetayases if (vecp->v_flags & APIX_VECT_USER_BOUND) { 8947ff178cdSJimmy Vetayases hardbound++; 8957ff178cdSJimmy Vetayases continue; 8967ff178cdSJimmy Vetayases } 8977ff178cdSJimmy Vetayases type = vecp->v_type; 8987ff178cdSJimmy Vetayases 8997ff178cdSJimmy Vetayases /* 9007ff178cdSJimmy Vetayases * If there are bound interrupts on this cpu, then 9017ff178cdSJimmy Vetayases * rebind them to other processors. 9027ff178cdSJimmy Vetayases */ 9037ff178cdSJimmy Vetayases loop = 0; 9047ff178cdSJimmy Vetayases do { 9057ff178cdSJimmy Vetayases bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE); 9067ff178cdSJimmy Vetayases 9077ff178cdSJimmy Vetayases if (type != APIX_TYPE_MSI) 9087ff178cdSJimmy Vetayases newp = apix_set_cpu(vecp, bindcpu, &ret); 9097ff178cdSJimmy Vetayases else 9107ff178cdSJimmy Vetayases newp = apix_grp_set_cpu(vecp, bindcpu, &ret); 9117ff178cdSJimmy Vetayases } while ((newp == NULL) && (loop++ < apic_nproc)); 9127ff178cdSJimmy Vetayases 9137ff178cdSJimmy Vetayases if (loop >= apic_nproc) { 9147ff178cdSJimmy Vetayases errbound++; 9157ff178cdSJimmy Vetayases cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x", 9167ff178cdSJimmy Vetayases vecp->v_cpuid, vecp->v_vector); 9177ff178cdSJimmy Vetayases } 9187ff178cdSJimmy Vetayases } 9197ff178cdSJimmy Vetayases 9207ff178cdSJimmy Vetayases lock_clear(&apix_lock); 9217ff178cdSJimmy Vetayases 9227ff178cdSJimmy Vetayases if (hardbound || errbound) { 9237ff178cdSJimmy Vetayases cmn_err(CE_WARN, "Could not disable interrupts on %d" 9247ff178cdSJimmy Vetayases "due to user bound interrupts or failed operation", 9257ff178cdSJimmy Vetayases cpun); 9267ff178cdSJimmy Vetayases return (PSM_FAILURE); 9277ff178cdSJimmy Vetayases } 9287ff178cdSJimmy Vetayases 9297ff178cdSJimmy Vetayases return (PSM_SUCCESS); 9307ff178cdSJimmy Vetayases } 9317ff178cdSJimmy Vetayases 9327ff178cdSJimmy Vetayases /* 9337ff178cdSJimmy Vetayases * Bind interrupts to specified CPU 9347ff178cdSJimmy Vetayases */ 9357ff178cdSJimmy Vetayases static void 9367ff178cdSJimmy Vetayases apix_enable_intr(processorid_t cpun) 9377ff178cdSJimmy Vetayases { 9387ff178cdSJimmy Vetayases apix_vector_t *vecp; 9397ff178cdSJimmy Vetayases int i, ret; 9407ff178cdSJimmy Vetayases processorid_t n; 9417ff178cdSJimmy Vetayases 9427ff178cdSJimmy Vetayases lock_set(&apix_lock); 9437ff178cdSJimmy Vetayases 9447ff178cdSJimmy Vetayases apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 9457ff178cdSJimmy Vetayases 9467ff178cdSJimmy Vetayases /* interrupt enabling for system resume */ 9477ff178cdSJimmy Vetayases if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) { 9487ff178cdSJimmy Vetayases for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { 9497ff178cdSJimmy Vetayases vecp = xv_vector(cpun, i); 9507ff178cdSJimmy Vetayases if (!IS_VECT_ENABLED(vecp)) 9517ff178cdSJimmy Vetayases continue; 9527ff178cdSJimmy Vetayases 9537ff178cdSJimmy Vetayases apix_enable_vector(vecp); 9547ff178cdSJimmy Vetayases } 9557ff178cdSJimmy Vetayases apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 9567ff178cdSJimmy Vetayases } 9577ff178cdSJimmy Vetayases 9587ff178cdSJimmy Vetayases for (n = 0; n < apic_nproc; n++) { 9597ff178cdSJimmy Vetayases if (!apic_cpu_in_range(n) || n == cpun || 9607ff178cdSJimmy Vetayases (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0) 9617ff178cdSJimmy Vetayases continue; 9627ff178cdSJimmy Vetayases 9637ff178cdSJimmy Vetayases for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) { 9647ff178cdSJimmy Vetayases vecp = xv_vector(n, i); 9657ff178cdSJimmy Vetayases if (!IS_VECT_ENABLED(vecp) || 9667ff178cdSJimmy Vetayases vecp->v_bound_cpuid != cpun) 9677ff178cdSJimmy Vetayases continue; 9687ff178cdSJimmy Vetayases 9697ff178cdSJimmy Vetayases if (vecp->v_type != APIX_TYPE_MSI) 9707ff178cdSJimmy Vetayases (void) apix_set_cpu(vecp, cpun, &ret); 9717ff178cdSJimmy Vetayases else 9727ff178cdSJimmy Vetayases (void) apix_grp_set_cpu(vecp, cpun, &ret); 9737ff178cdSJimmy Vetayases } 9747ff178cdSJimmy Vetayases } 9757ff178cdSJimmy Vetayases 9767ff178cdSJimmy Vetayases lock_clear(&apix_lock); 9777ff178cdSJimmy Vetayases } 9787ff178cdSJimmy Vetayases 9797ff178cdSJimmy Vetayases /* 9807ff178cdSJimmy Vetayases * Allocate vector for IPI 9817ff178cdSJimmy Vetayases * type == -1 indicates it is an internal request. Do not change 9827ff178cdSJimmy Vetayases * resv_vector for these requests. 9837ff178cdSJimmy Vetayases */ 9847ff178cdSJimmy Vetayases static int 9857ff178cdSJimmy Vetayases apix_get_ipivect(int ipl, int type) 9867ff178cdSJimmy Vetayases { 9877ff178cdSJimmy Vetayases uchar_t vector; 9887ff178cdSJimmy Vetayases 9897ff178cdSJimmy Vetayases if ((vector = apix_alloc_ipi(ipl)) > 0) { 9907ff178cdSJimmy Vetayases if (type != -1) 9917ff178cdSJimmy Vetayases apic_resv_vector[ipl] = vector; 9927ff178cdSJimmy Vetayases return (vector); 9937ff178cdSJimmy Vetayases } 9947ff178cdSJimmy Vetayases apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 9957ff178cdSJimmy Vetayases return (-1); /* shouldn't happen */ 9967ff178cdSJimmy Vetayases } 9977ff178cdSJimmy Vetayases 9987ff178cdSJimmy Vetayases static int 9997ff178cdSJimmy Vetayases apix_get_clkvect(int ipl) 10007ff178cdSJimmy Vetayases { 10017ff178cdSJimmy Vetayases int vector; 10027ff178cdSJimmy Vetayases 10037ff178cdSJimmy Vetayases if ((vector = apix_get_ipivect(ipl, -1)) == -1) 10047ff178cdSJimmy Vetayases return (-1); 10057ff178cdSJimmy Vetayases 10067ff178cdSJimmy Vetayases apic_clkvect = vector - APIC_BASE_VECT; 10077ff178cdSJimmy Vetayases APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n", 10087ff178cdSJimmy Vetayases apic_clkvect)); 10097ff178cdSJimmy Vetayases return (vector); 10107ff178cdSJimmy Vetayases } 10117ff178cdSJimmy Vetayases 10127ff178cdSJimmy Vetayases static int 10137ff178cdSJimmy Vetayases apix_post_cpu_start() 10147ff178cdSJimmy Vetayases { 10157ff178cdSJimmy Vetayases int cpun; 10167ff178cdSJimmy Vetayases static int cpus_started = 1; 10177ff178cdSJimmy Vetayases 10187ff178cdSJimmy Vetayases /* We know this CPU + BSP started successfully. */ 10197ff178cdSJimmy Vetayases cpus_started++; 10207ff178cdSJimmy Vetayases 10217ff178cdSJimmy Vetayases /* 10227ff178cdSJimmy Vetayases * On BSP we would have enabled X2APIC, if supported by processor, 10237ff178cdSJimmy Vetayases * in acpi_probe(), but on AP we do it here. 10247ff178cdSJimmy Vetayases * 10257ff178cdSJimmy Vetayases * We enable X2APIC mode only if BSP is running in X2APIC & the 10267ff178cdSJimmy Vetayases * local APIC mode of the current CPU is MMIO (xAPIC). 10277ff178cdSJimmy Vetayases */ 10287ff178cdSJimmy Vetayases if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 10297ff178cdSJimmy Vetayases apic_local_mode() == LOCAL_APIC) { 10307ff178cdSJimmy Vetayases apic_enable_x2apic(); 10317ff178cdSJimmy Vetayases } 10327ff178cdSJimmy Vetayases 10337ff178cdSJimmy Vetayases /* 10347ff178cdSJimmy Vetayases * Switch back to x2apic IPI sending method for performance when target 10357ff178cdSJimmy Vetayases * CPU has entered x2apic mode. 10367ff178cdSJimmy Vetayases */ 10377ff178cdSJimmy Vetayases if (apic_mode == LOCAL_X2APIC) { 10387ff178cdSJimmy Vetayases apic_switch_ipi_callback(B_FALSE); 10397ff178cdSJimmy Vetayases } 10407ff178cdSJimmy Vetayases 10417ff178cdSJimmy Vetayases splx(ipltospl(LOCK_LEVEL)); 10427ff178cdSJimmy Vetayases apix_init_intr(); 10437ff178cdSJimmy Vetayases 10447ff178cdSJimmy Vetayases /* 10457ff178cdSJimmy Vetayases * since some systems don't enable the internal cache on the non-boot 10467ff178cdSJimmy Vetayases * cpus, so we have to enable them here 10477ff178cdSJimmy Vetayases */ 10487ff178cdSJimmy Vetayases setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 10497ff178cdSJimmy Vetayases 10507ff178cdSJimmy Vetayases #ifdef DEBUG 10517ff178cdSJimmy Vetayases APIC_AV_PENDING_SET(); 10527ff178cdSJimmy Vetayases #else 10537ff178cdSJimmy Vetayases if (apic_mode == LOCAL_APIC) 10547ff178cdSJimmy Vetayases APIC_AV_PENDING_SET(); 10557ff178cdSJimmy Vetayases #endif /* DEBUG */ 10567ff178cdSJimmy Vetayases 10577ff178cdSJimmy Vetayases /* 10587ff178cdSJimmy Vetayases * We may be booting, or resuming from suspend; aci_status will 10597ff178cdSJimmy Vetayases * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 10607ff178cdSJimmy Vetayases * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 10617ff178cdSJimmy Vetayases */ 10627ff178cdSJimmy Vetayases cpun = psm_get_cpu_id(); 10637ff178cdSJimmy Vetayases apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 10647ff178cdSJimmy Vetayases 10657ff178cdSJimmy Vetayases apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 10667ff178cdSJimmy Vetayases 10677ff178cdSJimmy Vetayases return (PSM_SUCCESS); 10687ff178cdSJimmy Vetayases } 10697ff178cdSJimmy Vetayases 10707ff178cdSJimmy Vetayases /* 10717ff178cdSJimmy Vetayases * If this module needs a periodic handler for the interrupt distribution, it 10727ff178cdSJimmy Vetayases * can be added here. The argument to the periodic handler is not currently 10737ff178cdSJimmy Vetayases * used, but is reserved for future. 10747ff178cdSJimmy Vetayases */ 10757ff178cdSJimmy Vetayases static void 10767ff178cdSJimmy Vetayases apix_post_cyclic_setup(void *arg) 10777ff178cdSJimmy Vetayases { 10787ff178cdSJimmy Vetayases UNREFERENCED_1PARAMETER(arg); 10797ff178cdSJimmy Vetayases 1080a288e5a9SJoshua M. Clulow cyc_handler_t cyh; 1081a288e5a9SJoshua M. Clulow cyc_time_t cyt; 1082a288e5a9SJoshua M. Clulow 10837ff178cdSJimmy Vetayases /* cpu_lock is held */ 10847ff178cdSJimmy Vetayases /* set up a periodic handler for intr redistribution */ 10857ff178cdSJimmy Vetayases 10867ff178cdSJimmy Vetayases /* 10877ff178cdSJimmy Vetayases * In peridoc mode intr redistribution processing is done in 10887ff178cdSJimmy Vetayases * apic_intr_enter during clk intr processing 10897ff178cdSJimmy Vetayases */ 10907ff178cdSJimmy Vetayases if (!apic_oneshot) 10917ff178cdSJimmy Vetayases return; 10927ff178cdSJimmy Vetayases 10937ff178cdSJimmy Vetayases /* 10947ff178cdSJimmy Vetayases * Register a periodical handler for the redistribution processing. 1095a288e5a9SJoshua M. Clulow * Though we would generally prefer to use the DDI interface for 1096a288e5a9SJoshua M. Clulow * periodic handler invocation, ddi_periodic_add(9F), we are 1097a288e5a9SJoshua M. Clulow * unfortunately already holding cpu_lock, which ddi_periodic_add will 1098a288e5a9SJoshua M. Clulow * attempt to take for us. Thus, we add our own cyclic directly: 10997ff178cdSJimmy Vetayases */ 1100a288e5a9SJoshua M. Clulow cyh.cyh_func = (void (*)(void *))apix_redistribute_compute; 1101a288e5a9SJoshua M. Clulow cyh.cyh_arg = NULL; 1102a288e5a9SJoshua M. Clulow cyh.cyh_level = CY_LOW_LEVEL; 1103a288e5a9SJoshua M. Clulow 1104a288e5a9SJoshua M. Clulow cyt.cyt_when = 0; 1105a288e5a9SJoshua M. Clulow cyt.cyt_interval = apic_redistribute_sample_interval; 1106a288e5a9SJoshua M. Clulow 1107a288e5a9SJoshua M. Clulow apic_cyclic_id = cyclic_add(&cyh, &cyt); 11087ff178cdSJimmy Vetayases } 11097ff178cdSJimmy Vetayases 1110636dfb4bSJerry Jelinek /* 1111636dfb4bSJerry Jelinek * Called the first time we enable x2apic mode on this cpu. 1112636dfb4bSJerry Jelinek * Update some of the function pointers to use x2apic routines. 1113636dfb4bSJerry Jelinek */ 11147ff178cdSJimmy Vetayases void 11157ff178cdSJimmy Vetayases x2apic_update_psm() 11167ff178cdSJimmy Vetayases { 11177ff178cdSJimmy Vetayases struct psm_ops *pops = &apix_ops; 11187ff178cdSJimmy Vetayases 11197ff178cdSJimmy Vetayases ASSERT(pops != NULL); 11207ff178cdSJimmy Vetayases 11217ff178cdSJimmy Vetayases /* 1122636dfb4bSJerry Jelinek * The pcplusmp module's version of x2apic_update_psm makes additional 1123636dfb4bSJerry Jelinek * changes that we do not have to make here. It needs to make those 1124636dfb4bSJerry Jelinek * changes because pcplusmp relies on the TPR register and the means of 1125636dfb4bSJerry Jelinek * addressing that changes when using the local apic versus the x2apic. 1126636dfb4bSJerry Jelinek * It's also worth noting that the apix driver specific function end up 1127636dfb4bSJerry Jelinek * being apix_foo as opposed to apic_foo and x2apic_foo. 11287ff178cdSJimmy Vetayases */ 11297ff178cdSJimmy Vetayases pops->psm_send_ipi = x2apic_send_ipi; 11307ff178cdSJimmy Vetayases 11317ff178cdSJimmy Vetayases send_dirintf = pops->psm_send_ipi; 11327ff178cdSJimmy Vetayases 11337ff178cdSJimmy Vetayases apic_mode = LOCAL_X2APIC; 11347ff178cdSJimmy Vetayases apic_change_ops(); 11357ff178cdSJimmy Vetayases } 11367ff178cdSJimmy Vetayases 11377ff178cdSJimmy Vetayases /* 11387ff178cdSJimmy Vetayases * This function provides external interface to the nexus for all 11397ff178cdSJimmy Vetayases * functionalities related to the new DDI interrupt framework. 11407ff178cdSJimmy Vetayases * 11417ff178cdSJimmy Vetayases * Input: 11427ff178cdSJimmy Vetayases * dip - pointer to the dev_info structure of the requested device 11437ff178cdSJimmy Vetayases * hdlp - pointer to the internal interrupt handle structure for the 11447ff178cdSJimmy Vetayases * requested interrupt 11457ff178cdSJimmy Vetayases * intr_op - opcode for this call 11467ff178cdSJimmy Vetayases * result - pointer to the integer that will hold the result to be 11477ff178cdSJimmy Vetayases * passed back if return value is PSM_SUCCESS 11487ff178cdSJimmy Vetayases * 11497ff178cdSJimmy Vetayases * Output: 11507ff178cdSJimmy Vetayases * return value is either PSM_SUCCESS or PSM_FAILURE 11517ff178cdSJimmy Vetayases */ 11527ff178cdSJimmy Vetayases static int 11537ff178cdSJimmy Vetayases apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 11547ff178cdSJimmy Vetayases psm_intr_op_t intr_op, int *result) 11557ff178cdSJimmy Vetayases { 11567ff178cdSJimmy Vetayases int cap; 11577ff178cdSJimmy Vetayases apix_vector_t *vecp, *newvecp; 11587ff178cdSJimmy Vetayases struct intrspec *ispec, intr_spec; 11597ff178cdSJimmy Vetayases processorid_t target; 11607ff178cdSJimmy Vetayases 11617ff178cdSJimmy Vetayases ispec = &intr_spec; 11627ff178cdSJimmy Vetayases ispec->intrspec_pri = hdlp->ih_pri; 11637ff178cdSJimmy Vetayases ispec->intrspec_vec = hdlp->ih_inum; 11647ff178cdSJimmy Vetayases ispec->intrspec_func = hdlp->ih_cb_func; 11657ff178cdSJimmy Vetayases 11667ff178cdSJimmy Vetayases switch (intr_op) { 11677ff178cdSJimmy Vetayases case PSM_INTR_OP_ALLOC_VECTORS: 11687ff178cdSJimmy Vetayases switch (hdlp->ih_type) { 11697ff178cdSJimmy Vetayases case DDI_INTR_TYPE_MSI: 11707ff178cdSJimmy Vetayases /* allocate MSI vectors */ 11717ff178cdSJimmy Vetayases *result = apix_alloc_msi(dip, hdlp->ih_inum, 11727ff178cdSJimmy Vetayases hdlp->ih_scratch1, 11737ff178cdSJimmy Vetayases (int)(uintptr_t)hdlp->ih_scratch2); 11747ff178cdSJimmy Vetayases break; 11757ff178cdSJimmy Vetayases case DDI_INTR_TYPE_MSIX: 11767ff178cdSJimmy Vetayases /* allocate MSI-X vectors */ 11777ff178cdSJimmy Vetayases *result = apix_alloc_msix(dip, hdlp->ih_inum, 11787ff178cdSJimmy Vetayases hdlp->ih_scratch1, 11797ff178cdSJimmy Vetayases (int)(uintptr_t)hdlp->ih_scratch2); 11807ff178cdSJimmy Vetayases break; 11817ff178cdSJimmy Vetayases case DDI_INTR_TYPE_FIXED: 11827ff178cdSJimmy Vetayases /* allocate or share vector for fixed */ 11837ff178cdSJimmy Vetayases if ((ihdl_plat_t *)hdlp->ih_private == NULL) { 11847ff178cdSJimmy Vetayases return (PSM_FAILURE); 11857ff178cdSJimmy Vetayases } 11867ff178cdSJimmy Vetayases ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp; 11877ff178cdSJimmy Vetayases *result = apix_intx_alloc_vector(dip, hdlp->ih_inum, 11887ff178cdSJimmy Vetayases ispec); 11897ff178cdSJimmy Vetayases break; 11907ff178cdSJimmy Vetayases default: 11917ff178cdSJimmy Vetayases return (PSM_FAILURE); 11927ff178cdSJimmy Vetayases } 11937ff178cdSJimmy Vetayases break; 11947ff178cdSJimmy Vetayases case PSM_INTR_OP_FREE_VECTORS: 11957ff178cdSJimmy Vetayases apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1, 11967ff178cdSJimmy Vetayases hdlp->ih_type); 11977ff178cdSJimmy Vetayases break; 11987ff178cdSJimmy Vetayases case PSM_INTR_OP_XLATE_VECTOR: 11997ff178cdSJimmy Vetayases /* 12007ff178cdSJimmy Vetayases * Vectors are allocated by ALLOC and freed by FREE. 12017ff178cdSJimmy Vetayases * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector). 12027ff178cdSJimmy Vetayases */ 12037ff178cdSJimmy Vetayases *result = APIX_INVALID_VECT; 12047ff178cdSJimmy Vetayases vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); 12057ff178cdSJimmy Vetayases if (vecp != NULL) { 12067ff178cdSJimmy Vetayases *result = APIX_VIRTVECTOR(vecp->v_cpuid, 12077ff178cdSJimmy Vetayases vecp->v_vector); 12087ff178cdSJimmy Vetayases break; 12097ff178cdSJimmy Vetayases } 12107ff178cdSJimmy Vetayases 12117ff178cdSJimmy Vetayases /* 12127ff178cdSJimmy Vetayases * No vector to device mapping exists. If this is FIXED type 12137ff178cdSJimmy Vetayases * then check if this IRQ is already mapped for another device 12147ff178cdSJimmy Vetayases * then return the vector number for it (i.e. shared IRQ case). 12157ff178cdSJimmy Vetayases * Otherwise, return PSM_FAILURE. 12167ff178cdSJimmy Vetayases */ 12177ff178cdSJimmy Vetayases if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) { 12187ff178cdSJimmy Vetayases vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum, 12197ff178cdSJimmy Vetayases ispec); 12207ff178cdSJimmy Vetayases *result = (vecp == NULL) ? APIX_INVALID_VECT : 12217ff178cdSJimmy Vetayases APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector); 12227ff178cdSJimmy Vetayases } 12237ff178cdSJimmy Vetayases if (*result == APIX_INVALID_VECT) 12247ff178cdSJimmy Vetayases return (PSM_FAILURE); 12257ff178cdSJimmy Vetayases break; 12267ff178cdSJimmy Vetayases case PSM_INTR_OP_GET_PENDING: 12277ff178cdSJimmy Vetayases vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); 12287ff178cdSJimmy Vetayases if (vecp == NULL) 12297ff178cdSJimmy Vetayases return (PSM_FAILURE); 12307ff178cdSJimmy Vetayases 12317ff178cdSJimmy Vetayases *result = apix_get_pending(vecp); 12327ff178cdSJimmy Vetayases break; 12337ff178cdSJimmy Vetayases case PSM_INTR_OP_CLEAR_MASK: 12347ff178cdSJimmy Vetayases if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 12357ff178cdSJimmy Vetayases return (PSM_FAILURE); 12367ff178cdSJimmy Vetayases 12377ff178cdSJimmy Vetayases vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); 12387ff178cdSJimmy Vetayases if (vecp == NULL) 12397ff178cdSJimmy Vetayases return (PSM_FAILURE); 12407ff178cdSJimmy Vetayases 12417ff178cdSJimmy Vetayases apix_intx_clear_mask(vecp->v_inum); 12427ff178cdSJimmy Vetayases break; 12437ff178cdSJimmy Vetayases case PSM_INTR_OP_SET_MASK: 12447ff178cdSJimmy Vetayases if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 12457ff178cdSJimmy Vetayases return (PSM_FAILURE); 12467ff178cdSJimmy Vetayases 12477ff178cdSJimmy Vetayases vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); 12487ff178cdSJimmy Vetayases if (vecp == NULL) 12497ff178cdSJimmy Vetayases return (PSM_FAILURE); 12507ff178cdSJimmy Vetayases 12517ff178cdSJimmy Vetayases apix_intx_set_mask(vecp->v_inum); 12527ff178cdSJimmy Vetayases break; 12537ff178cdSJimmy Vetayases case PSM_INTR_OP_GET_SHARED: 12547ff178cdSJimmy Vetayases if (hdlp->ih_type != DDI_INTR_TYPE_FIXED) 12557ff178cdSJimmy Vetayases return (PSM_FAILURE); 12567ff178cdSJimmy Vetayases 12577ff178cdSJimmy Vetayases vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type); 12587ff178cdSJimmy Vetayases if (vecp == NULL) 12597ff178cdSJimmy Vetayases return (PSM_FAILURE); 12607ff178cdSJimmy Vetayases 12617ff178cdSJimmy Vetayases *result = apix_intx_get_shared(vecp->v_inum); 12627ff178cdSJimmy Vetayases break; 12637ff178cdSJimmy Vetayases case PSM_INTR_OP_SET_PRI: 12647ff178cdSJimmy Vetayases /* 12657ff178cdSJimmy Vetayases * Called prior to adding the interrupt handler or when 12667ff178cdSJimmy Vetayases * an interrupt handler is unassigned. 12677ff178cdSJimmy Vetayases */ 12687ff178cdSJimmy Vetayases if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 12697ff178cdSJimmy Vetayases return (PSM_SUCCESS); 12707ff178cdSJimmy Vetayases 12717ff178cdSJimmy Vetayases if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL) 12727ff178cdSJimmy Vetayases return (PSM_FAILURE); 12737ff178cdSJimmy Vetayases 12747ff178cdSJimmy Vetayases break; 12757ff178cdSJimmy Vetayases case PSM_INTR_OP_SET_CPU: 12767ff178cdSJimmy Vetayases case PSM_INTR_OP_GRP_SET_CPU: 12777ff178cdSJimmy Vetayases /* 12787ff178cdSJimmy Vetayases * The interrupt handle given here has been allocated 12797ff178cdSJimmy Vetayases * specifically for this command, and ih_private carries 12807ff178cdSJimmy Vetayases * a CPU value. 12817ff178cdSJimmy Vetayases */ 12827ff178cdSJimmy Vetayases *result = EINVAL; 12837ff178cdSJimmy Vetayases target = (int)(intptr_t)hdlp->ih_private; 12847ff178cdSJimmy Vetayases if (!apic_cpu_in_range(target)) { 12857ff178cdSJimmy Vetayases DDI_INTR_IMPLDBG((CE_WARN, 12867ff178cdSJimmy Vetayases "[grp_]set_cpu: cpu out of range: %d\n", target)); 12877ff178cdSJimmy Vetayases return (PSM_FAILURE); 12887ff178cdSJimmy Vetayases } 12897ff178cdSJimmy Vetayases 12907ff178cdSJimmy Vetayases lock_set(&apix_lock); 12917ff178cdSJimmy Vetayases 12927ff178cdSJimmy Vetayases vecp = apix_get_req_vector(hdlp, hdlp->ih_flags); 12937ff178cdSJimmy Vetayases if (!IS_VECT_ENABLED(vecp)) { 12947ff178cdSJimmy Vetayases DDI_INTR_IMPLDBG((CE_WARN, 12957ff178cdSJimmy Vetayases "[grp]_set_cpu: invalid vector 0x%x\n", 12967ff178cdSJimmy Vetayases hdlp->ih_vector)); 12977ff178cdSJimmy Vetayases lock_clear(&apix_lock); 12987ff178cdSJimmy Vetayases return (PSM_FAILURE); 12997ff178cdSJimmy Vetayases } 13007ff178cdSJimmy Vetayases 13017ff178cdSJimmy Vetayases *result = 0; 13027ff178cdSJimmy Vetayases 13037ff178cdSJimmy Vetayases if (intr_op == PSM_INTR_OP_SET_CPU) 13047ff178cdSJimmy Vetayases newvecp = apix_set_cpu(vecp, target, result); 13057ff178cdSJimmy Vetayases else 13067ff178cdSJimmy Vetayases newvecp = apix_grp_set_cpu(vecp, target, result); 13077ff178cdSJimmy Vetayases 13087ff178cdSJimmy Vetayases lock_clear(&apix_lock); 13097ff178cdSJimmy Vetayases 13107ff178cdSJimmy Vetayases if (newvecp == NULL) { 13117ff178cdSJimmy Vetayases *result = EIO; 13127ff178cdSJimmy Vetayases return (PSM_FAILURE); 13137ff178cdSJimmy Vetayases } 13147ff178cdSJimmy Vetayases newvecp->v_bound_cpuid = target; 13157ff178cdSJimmy Vetayases hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid, 13167ff178cdSJimmy Vetayases newvecp->v_vector); 13177ff178cdSJimmy Vetayases break; 13187ff178cdSJimmy Vetayases 13197ff178cdSJimmy Vetayases case PSM_INTR_OP_GET_INTR: 13207ff178cdSJimmy Vetayases /* 13217ff178cdSJimmy Vetayases * The interrupt handle given here has been allocated 13227ff178cdSJimmy Vetayases * specifically for this command, and ih_private carries 13237ff178cdSJimmy Vetayases * a pointer to a apic_get_intr_t. 13247ff178cdSJimmy Vetayases */ 13257ff178cdSJimmy Vetayases if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS) 13267ff178cdSJimmy Vetayases return (PSM_FAILURE); 13277ff178cdSJimmy Vetayases break; 13287ff178cdSJimmy Vetayases 13297ff178cdSJimmy Vetayases case PSM_INTR_OP_CHECK_MSI: 13307ff178cdSJimmy Vetayases /* 13317ff178cdSJimmy Vetayases * Check MSI/X is supported or not at APIC level and 13327ff178cdSJimmy Vetayases * masked off the MSI/X bits in hdlp->ih_type if not 13337ff178cdSJimmy Vetayases * supported before return. If MSI/X is supported, 13347ff178cdSJimmy Vetayases * leave the ih_type unchanged and return. 13357ff178cdSJimmy Vetayases * 13367ff178cdSJimmy Vetayases * hdlp->ih_type passed in from the nexus has all the 13377ff178cdSJimmy Vetayases * interrupt types supported by the device. 13387ff178cdSJimmy Vetayases */ 13397ff178cdSJimmy Vetayases if (apic_support_msi == 0) { /* uninitialized */ 13407ff178cdSJimmy Vetayases /* 13417ff178cdSJimmy Vetayases * if apic_support_msi is not set, call 13427ff178cdSJimmy Vetayases * apic_check_msi_support() to check whether msi 13437ff178cdSJimmy Vetayases * is supported first 13447ff178cdSJimmy Vetayases */ 13457ff178cdSJimmy Vetayases if (apic_check_msi_support() == PSM_SUCCESS) 13467ff178cdSJimmy Vetayases apic_support_msi = 1; /* supported */ 13477ff178cdSJimmy Vetayases else 13487ff178cdSJimmy Vetayases apic_support_msi = -1; /* not-supported */ 13497ff178cdSJimmy Vetayases } 13507ff178cdSJimmy Vetayases if (apic_support_msi == 1) { 13517ff178cdSJimmy Vetayases if (apic_msix_enable) 13527ff178cdSJimmy Vetayases *result = hdlp->ih_type; 13537ff178cdSJimmy Vetayases else 13547ff178cdSJimmy Vetayases *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX; 13557ff178cdSJimmy Vetayases } else 13567ff178cdSJimmy Vetayases *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI | 13577ff178cdSJimmy Vetayases DDI_INTR_TYPE_MSIX); 13587ff178cdSJimmy Vetayases break; 13597ff178cdSJimmy Vetayases case PSM_INTR_OP_GET_CAP: 13607ff178cdSJimmy Vetayases cap = DDI_INTR_FLAG_PENDING; 13617ff178cdSJimmy Vetayases if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) 13627ff178cdSJimmy Vetayases cap |= DDI_INTR_FLAG_MASKABLE; 13637ff178cdSJimmy Vetayases *result = cap; 13647ff178cdSJimmy Vetayases break; 13657ff178cdSJimmy Vetayases case PSM_INTR_OP_APIC_TYPE: 13667ff178cdSJimmy Vetayases ((apic_get_type_t *)(hdlp->ih_private))->avgi_type = 13677ff178cdSJimmy Vetayases apix_get_apic_type(); 13687ff178cdSJimmy Vetayases ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr = 13697ff178cdSJimmy Vetayases APIX_IPI_MIN; 13707ff178cdSJimmy Vetayases ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu = 13717ff178cdSJimmy Vetayases apic_nproc; 13727ff178cdSJimmy Vetayases hdlp->ih_ver = apic_get_apic_version(); 13737ff178cdSJimmy Vetayases break; 13747ff178cdSJimmy Vetayases case PSM_INTR_OP_SET_CAP: 13757ff178cdSJimmy Vetayases default: 13767ff178cdSJimmy Vetayases return (PSM_FAILURE); 13777ff178cdSJimmy Vetayases } 13787ff178cdSJimmy Vetayases 13797ff178cdSJimmy Vetayases return (PSM_SUCCESS); 13807ff178cdSJimmy Vetayases } 13817ff178cdSJimmy Vetayases 13827ff178cdSJimmy Vetayases static void 13837ff178cdSJimmy Vetayases apix_cleanup_busy(void) 13847ff178cdSJimmy Vetayases { 13857ff178cdSJimmy Vetayases int i, j; 13867ff178cdSJimmy Vetayases apix_vector_t *vecp; 13877ff178cdSJimmy Vetayases 13887ff178cdSJimmy Vetayases for (i = 0; i < apic_nproc; i++) { 13897ff178cdSJimmy Vetayases if (!apic_cpu_in_range(i)) 13907ff178cdSJimmy Vetayases continue; 13917ff178cdSJimmy Vetayases apic_cpus[i].aci_busy = 0; 13927ff178cdSJimmy Vetayases for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) { 13937ff178cdSJimmy Vetayases if ((vecp = xv_vector(i, j)) != NULL) 13947ff178cdSJimmy Vetayases vecp->v_busy = 0; 13957ff178cdSJimmy Vetayases } 13967ff178cdSJimmy Vetayases } 13977ff178cdSJimmy Vetayases } 13987ff178cdSJimmy Vetayases 13997ff178cdSJimmy Vetayases static void 14007ff178cdSJimmy Vetayases apix_redistribute_compute(void) 14017ff178cdSJimmy Vetayases { 14027ff178cdSJimmy Vetayases int i, j, max_busy; 14037ff178cdSJimmy Vetayases 14047ff178cdSJimmy Vetayases if (!apic_enable_dynamic_migration) 14057ff178cdSJimmy Vetayases return; 14067ff178cdSJimmy Vetayases 14077ff178cdSJimmy Vetayases if (++apic_nticks == apic_sample_factor_redistribution) { 14087ff178cdSJimmy Vetayases /* 14097ff178cdSJimmy Vetayases * Time to call apic_intr_redistribute(). 14107ff178cdSJimmy Vetayases * reset apic_nticks. This will cause max_busy 14117ff178cdSJimmy Vetayases * to be calculated below and if it is more than 14127ff178cdSJimmy Vetayases * apic_int_busy, we will do the whole thing 14137ff178cdSJimmy Vetayases */ 14147ff178cdSJimmy Vetayases apic_nticks = 0; 14157ff178cdSJimmy Vetayases } 14167ff178cdSJimmy Vetayases max_busy = 0; 14177ff178cdSJimmy Vetayases for (i = 0; i < apic_nproc; i++) { 14187ff178cdSJimmy Vetayases if (!apic_cpu_in_range(i)) 14197ff178cdSJimmy Vetayases continue; 14207ff178cdSJimmy Vetayases /* 14217ff178cdSJimmy Vetayases * Check if curipl is non zero & if ISR is in 14227ff178cdSJimmy Vetayases * progress 14237ff178cdSJimmy Vetayases */ 14247ff178cdSJimmy Vetayases if (((j = apic_cpus[i].aci_curipl) != 0) && 14257ff178cdSJimmy Vetayases (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 14267ff178cdSJimmy Vetayases 14277ff178cdSJimmy Vetayases int vect; 14287ff178cdSJimmy Vetayases apic_cpus[i].aci_busy++; 14297ff178cdSJimmy Vetayases vect = apic_cpus[i].aci_current[j]; 14307ff178cdSJimmy Vetayases apixs[i]->x_vectbl[vect]->v_busy++; 14317ff178cdSJimmy Vetayases } 14327ff178cdSJimmy Vetayases 14337ff178cdSJimmy Vetayases if (!apic_nticks && 14347ff178cdSJimmy Vetayases (apic_cpus[i].aci_busy > max_busy)) 14357ff178cdSJimmy Vetayases max_busy = apic_cpus[i].aci_busy; 14367ff178cdSJimmy Vetayases } 14377ff178cdSJimmy Vetayases if (!apic_nticks) { 14387ff178cdSJimmy Vetayases if (max_busy > apic_int_busy_mark) { 14397ff178cdSJimmy Vetayases /* 14407ff178cdSJimmy Vetayases * We could make the following check be 14417ff178cdSJimmy Vetayases * skipped > 1 in which case, we get a 14427ff178cdSJimmy Vetayases * redistribution at half the busy mark (due to 14437ff178cdSJimmy Vetayases * double interval). Need to be able to collect 14447ff178cdSJimmy Vetayases * more empirical data to decide if that is a 14457ff178cdSJimmy Vetayases * good strategy. Punt for now. 14467ff178cdSJimmy Vetayases */ 14477ff178cdSJimmy Vetayases apix_cleanup_busy(); 14487ff178cdSJimmy Vetayases apic_skipped_redistribute = 0; 14497ff178cdSJimmy Vetayases } else 14507ff178cdSJimmy Vetayases apic_skipped_redistribute++; 14517ff178cdSJimmy Vetayases } 14527ff178cdSJimmy Vetayases } 14537ff178cdSJimmy Vetayases 14547ff178cdSJimmy Vetayases /* 14557ff178cdSJimmy Vetayases * intr_ops() service routines 14567ff178cdSJimmy Vetayases */ 14577ff178cdSJimmy Vetayases 14587ff178cdSJimmy Vetayases static int 14597ff178cdSJimmy Vetayases apix_get_pending(apix_vector_t *vecp) 14607ff178cdSJimmy Vetayases { 14617ff178cdSJimmy Vetayases int bit, index, irr, pending; 14627ff178cdSJimmy Vetayases 14637ff178cdSJimmy Vetayases /* need to get on the bound cpu */ 14647ff178cdSJimmy Vetayases mutex_enter(&cpu_lock); 14657ff178cdSJimmy Vetayases affinity_set(vecp->v_cpuid); 14667ff178cdSJimmy Vetayases 14677ff178cdSJimmy Vetayases index = vecp->v_vector / 32; 14687ff178cdSJimmy Vetayases bit = vecp->v_vector % 32; 14697ff178cdSJimmy Vetayases irr = apic_reg_ops->apic_read(APIC_IRR_REG + index); 14707ff178cdSJimmy Vetayases 14717ff178cdSJimmy Vetayases affinity_clear(); 14727ff178cdSJimmy Vetayases mutex_exit(&cpu_lock); 14737ff178cdSJimmy Vetayases 14747ff178cdSJimmy Vetayases pending = (irr & (1 << bit)) ? 1 : 0; 14757ff178cdSJimmy Vetayases if (!pending && vecp->v_type == APIX_TYPE_FIXED) 14767ff178cdSJimmy Vetayases pending = apix_intx_get_pending(vecp->v_inum); 14777ff178cdSJimmy Vetayases 14787ff178cdSJimmy Vetayases return (pending); 14797ff178cdSJimmy Vetayases } 14807ff178cdSJimmy Vetayases 14817ff178cdSJimmy Vetayases static apix_vector_t * 14827ff178cdSJimmy Vetayases apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags) 14837ff178cdSJimmy Vetayases { 14847ff178cdSJimmy Vetayases apix_vector_t *vecp; 14857ff178cdSJimmy Vetayases processorid_t cpuid; 14867ff178cdSJimmy Vetayases int32_t virt_vec = 0; 14877ff178cdSJimmy Vetayases 14887ff178cdSJimmy Vetayases switch (flags & PSMGI_INTRBY_FLAGS) { 14897ff178cdSJimmy Vetayases case PSMGI_INTRBY_IRQ: 14907ff178cdSJimmy Vetayases return (apix_intx_get_vector(hdlp->ih_vector)); 14917ff178cdSJimmy Vetayases case PSMGI_INTRBY_VEC: 14927ff178cdSJimmy Vetayases virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec; 14937ff178cdSJimmy Vetayases 14947ff178cdSJimmy Vetayases cpuid = APIX_VIRTVEC_CPU(virt_vec); 14957ff178cdSJimmy Vetayases if (!apic_cpu_in_range(cpuid)) 14967ff178cdSJimmy Vetayases return (NULL); 14977ff178cdSJimmy Vetayases 14987ff178cdSJimmy Vetayases vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec)); 14997ff178cdSJimmy Vetayases break; 15007ff178cdSJimmy Vetayases case PSMGI_INTRBY_DEFAULT: 15017ff178cdSJimmy Vetayases vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum, 15027ff178cdSJimmy Vetayases hdlp->ih_type); 15037ff178cdSJimmy Vetayases break; 15047ff178cdSJimmy Vetayases default: 15057ff178cdSJimmy Vetayases return (NULL); 15067ff178cdSJimmy Vetayases } 15077ff178cdSJimmy Vetayases 15087ff178cdSJimmy Vetayases return (vecp); 15097ff178cdSJimmy Vetayases } 15107ff178cdSJimmy Vetayases 15117ff178cdSJimmy Vetayases static int 15127ff178cdSJimmy Vetayases apix_get_intr_info(ddi_intr_handle_impl_t *hdlp, 15137ff178cdSJimmy Vetayases apic_get_intr_t *intr_params_p) 15147ff178cdSJimmy Vetayases { 15157ff178cdSJimmy Vetayases apix_vector_t *vecp; 15167ff178cdSJimmy Vetayases struct autovec *av_dev; 15177ff178cdSJimmy Vetayases int i; 15187ff178cdSJimmy Vetayases 15197ff178cdSJimmy Vetayases vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags); 15207ff178cdSJimmy Vetayases if (IS_VECT_FREE(vecp)) { 15217ff178cdSJimmy Vetayases intr_params_p->avgi_num_devs = 0; 15227ff178cdSJimmy Vetayases intr_params_p->avgi_cpu_id = 0; 15237ff178cdSJimmy Vetayases intr_params_p->avgi_req_flags = 0; 15247ff178cdSJimmy Vetayases return (PSM_SUCCESS); 15257ff178cdSJimmy Vetayases } 15267ff178cdSJimmy Vetayases 15277ff178cdSJimmy Vetayases if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) { 15287ff178cdSJimmy Vetayases intr_params_p->avgi_cpu_id = vecp->v_cpuid; 15297ff178cdSJimmy Vetayases 15307ff178cdSJimmy Vetayases /* Return user bound info for intrd. */ 15317ff178cdSJimmy Vetayases if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) { 15327ff178cdSJimmy Vetayases intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND; 15337ff178cdSJimmy Vetayases intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND; 15347ff178cdSJimmy Vetayases } 15357ff178cdSJimmy Vetayases } 15367ff178cdSJimmy Vetayases 15377ff178cdSJimmy Vetayases if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR) 15387ff178cdSJimmy Vetayases intr_params_p->avgi_vector = vecp->v_vector; 15397ff178cdSJimmy Vetayases 15407ff178cdSJimmy Vetayases if (intr_params_p->avgi_req_flags & 15417ff178cdSJimmy Vetayases (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS)) 15427ff178cdSJimmy Vetayases /* Get number of devices from apic_irq table shared field. */ 15437ff178cdSJimmy Vetayases intr_params_p->avgi_num_devs = vecp->v_share; 15447ff178cdSJimmy Vetayases 15457ff178cdSJimmy Vetayases if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) { 15467ff178cdSJimmy Vetayases 15477ff178cdSJimmy Vetayases intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS; 15487ff178cdSJimmy Vetayases 15497ff178cdSJimmy Vetayases /* Some devices have NULL dip. Don't count these. */ 15507ff178cdSJimmy Vetayases if (intr_params_p->avgi_num_devs > 0) { 15517ff178cdSJimmy Vetayases for (i = 0, av_dev = vecp->v_autovect; av_dev; 15527ff178cdSJimmy Vetayases av_dev = av_dev->av_link) { 15537ff178cdSJimmy Vetayases if (av_dev->av_vector && av_dev->av_dip) 15547ff178cdSJimmy Vetayases i++; 15557ff178cdSJimmy Vetayases } 15567ff178cdSJimmy Vetayases intr_params_p->avgi_num_devs = 15577ff178cdSJimmy Vetayases (uint8_t)MIN(intr_params_p->avgi_num_devs, i); 15587ff178cdSJimmy Vetayases } 15597ff178cdSJimmy Vetayases 15607ff178cdSJimmy Vetayases /* There are no viable dips to return. */ 15617ff178cdSJimmy Vetayases if (intr_params_p->avgi_num_devs == 0) { 15627ff178cdSJimmy Vetayases intr_params_p->avgi_dip_list = NULL; 15637ff178cdSJimmy Vetayases 15647ff178cdSJimmy Vetayases } else { /* Return list of dips */ 15657ff178cdSJimmy Vetayases 15667ff178cdSJimmy Vetayases /* Allocate space in array for that number of devs. */ 15677ff178cdSJimmy Vetayases intr_params_p->avgi_dip_list = kmem_zalloc( 15687ff178cdSJimmy Vetayases intr_params_p->avgi_num_devs * 15697ff178cdSJimmy Vetayases sizeof (dev_info_t *), 15707ff178cdSJimmy Vetayases KM_NOSLEEP); 15717ff178cdSJimmy Vetayases if (intr_params_p->avgi_dip_list == NULL) { 15727ff178cdSJimmy Vetayases DDI_INTR_IMPLDBG((CE_WARN, 15737ff178cdSJimmy Vetayases "apix_get_vector_intr_info: no memory")); 15747ff178cdSJimmy Vetayases return (PSM_FAILURE); 15757ff178cdSJimmy Vetayases } 15767ff178cdSJimmy Vetayases 15777ff178cdSJimmy Vetayases /* 15787ff178cdSJimmy Vetayases * Loop through the device list of the autovec table 15797ff178cdSJimmy Vetayases * filling in the dip array. 15807ff178cdSJimmy Vetayases * 15817ff178cdSJimmy Vetayases * Note that the autovect table may have some special 15827ff178cdSJimmy Vetayases * entries which contain NULL dips. These will be 15837ff178cdSJimmy Vetayases * ignored. 15847ff178cdSJimmy Vetayases */ 15857ff178cdSJimmy Vetayases for (i = 0, av_dev = vecp->v_autovect; av_dev; 15867ff178cdSJimmy Vetayases av_dev = av_dev->av_link) { 15877ff178cdSJimmy Vetayases if (av_dev->av_vector && av_dev->av_dip) 15887ff178cdSJimmy Vetayases intr_params_p->avgi_dip_list[i++] = 15897ff178cdSJimmy Vetayases av_dev->av_dip; 15907ff178cdSJimmy Vetayases } 15917ff178cdSJimmy Vetayases } 15927ff178cdSJimmy Vetayases } 15937ff178cdSJimmy Vetayases 15947ff178cdSJimmy Vetayases return (PSM_SUCCESS); 15957ff178cdSJimmy Vetayases } 15967ff178cdSJimmy Vetayases 15977ff178cdSJimmy Vetayases static char * 15987ff178cdSJimmy Vetayases apix_get_apic_type(void) 15997ff178cdSJimmy Vetayases { 16007ff178cdSJimmy Vetayases return (apix_psm_info.p_mach_idstring); 16017ff178cdSJimmy Vetayases } 16027ff178cdSJimmy Vetayases 16037ff178cdSJimmy Vetayases apix_vector_t * 16047ff178cdSJimmy Vetayases apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result) 16057ff178cdSJimmy Vetayases { 16067ff178cdSJimmy Vetayases apix_vector_t *newp = NULL; 16077ff178cdSJimmy Vetayases dev_info_t *dip; 16087ff178cdSJimmy Vetayases int inum, cap_ptr; 16097ff178cdSJimmy Vetayases ddi_acc_handle_t handle; 16102edb3dccSJudy Chen ddi_intr_msix_t *msix_p = NULL; 16117ff178cdSJimmy Vetayases ushort_t msix_ctrl; 161230acb30dSHans Rosenfeld uintptr_t off = 0; 161330acb30dSHans Rosenfeld uint32_t mask = 0; 16147ff178cdSJimmy Vetayases 16157ff178cdSJimmy Vetayases ASSERT(LOCK_HELD(&apix_lock)); 16167ff178cdSJimmy Vetayases *result = ENXIO; 16177ff178cdSJimmy Vetayases 16187ff178cdSJimmy Vetayases /* Fail if this is an MSI intr and is part of a group. */ 16197ff178cdSJimmy Vetayases if (vecp->v_type == APIX_TYPE_MSI) { 16207ff178cdSJimmy Vetayases if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1) 16217ff178cdSJimmy Vetayases return (NULL); 16227ff178cdSJimmy Vetayases else 16237ff178cdSJimmy Vetayases return (apix_grp_set_cpu(vecp, new_cpu, result)); 16247ff178cdSJimmy Vetayases } 16257ff178cdSJimmy Vetayases 16267ff178cdSJimmy Vetayases /* 16277ff178cdSJimmy Vetayases * Mask MSI-X. It's unmasked when MSI-X gets enabled. 16287ff178cdSJimmy Vetayases */ 16292edb3dccSJudy Chen if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) { 16307ff178cdSJimmy Vetayases if ((dip = APIX_GET_DIP(vecp)) == NULL) 16317ff178cdSJimmy Vetayases return (NULL); 16327ff178cdSJimmy Vetayases inum = vecp->v_devp->dv_inum; 16337ff178cdSJimmy Vetayases 16347ff178cdSJimmy Vetayases handle = i_ddi_get_pci_config_handle(dip); 16357ff178cdSJimmy Vetayases cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); 16367ff178cdSJimmy Vetayases msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL); 16377ff178cdSJimmy Vetayases if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) { 16387ff178cdSJimmy Vetayases /* 16397ff178cdSJimmy Vetayases * Function is not masked, then mask "inum"th 16407ff178cdSJimmy Vetayases * entry in the MSI-X table 16417ff178cdSJimmy Vetayases */ 16427ff178cdSJimmy Vetayases msix_p = i_ddi_get_msix(dip); 16437ff178cdSJimmy Vetayases off = (uintptr_t)msix_p->msix_tbl_addr + (inum * 16447ff178cdSJimmy Vetayases PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET; 16457ff178cdSJimmy Vetayases mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off); 16467ff178cdSJimmy Vetayases ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, 16477ff178cdSJimmy Vetayases mask | 1); 16487ff178cdSJimmy Vetayases } 16497ff178cdSJimmy Vetayases } 16507ff178cdSJimmy Vetayases 16517ff178cdSJimmy Vetayases *result = 0; 16527ff178cdSJimmy Vetayases if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL) 16537ff178cdSJimmy Vetayases *result = EIO; 16547ff178cdSJimmy Vetayases 16552edb3dccSJudy Chen /* Restore mask bit */ 16562edb3dccSJudy Chen if (msix_p != NULL) 16572edb3dccSJudy Chen ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask); 16582edb3dccSJudy Chen 16597ff178cdSJimmy Vetayases return (newp); 16607ff178cdSJimmy Vetayases } 16617ff178cdSJimmy Vetayases 16627ff178cdSJimmy Vetayases /* 16637ff178cdSJimmy Vetayases * Set cpu for MSIs 16647ff178cdSJimmy Vetayases */ 16657ff178cdSJimmy Vetayases apix_vector_t * 16667ff178cdSJimmy Vetayases apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result) 16677ff178cdSJimmy Vetayases { 16687ff178cdSJimmy Vetayases apix_vector_t *newp, *vp; 16697ff178cdSJimmy Vetayases uint32_t orig_cpu = vecp->v_cpuid; 16707ff178cdSJimmy Vetayases int orig_vect = vecp->v_vector; 167130acb30dSHans Rosenfeld int i, num_vectors, cap_ptr, msi_mask_off = 0; 167230acb30dSHans Rosenfeld uint32_t msi_pvm = 0; 16737ff178cdSJimmy Vetayases ushort_t msi_ctrl; 16747ff178cdSJimmy Vetayases ddi_acc_handle_t handle; 16757ff178cdSJimmy Vetayases dev_info_t *dip; 16767ff178cdSJimmy Vetayases 16777ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x," 16787ff178cdSJimmy Vetayases " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu)); 16797ff178cdSJimmy Vetayases 16807ff178cdSJimmy Vetayases ASSERT(LOCK_HELD(&apix_lock)); 16817ff178cdSJimmy Vetayases 16827ff178cdSJimmy Vetayases *result = ENXIO; 16837ff178cdSJimmy Vetayases 16847ff178cdSJimmy Vetayases if (vecp->v_type != APIX_TYPE_MSI) { 16857ff178cdSJimmy Vetayases DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n")); 16867ff178cdSJimmy Vetayases return (NULL); 16877ff178cdSJimmy Vetayases } 16887ff178cdSJimmy Vetayases 16897ff178cdSJimmy Vetayases if ((dip = APIX_GET_DIP(vecp)) == NULL) 16907ff178cdSJimmy Vetayases return (NULL); 16917ff178cdSJimmy Vetayases 16927ff178cdSJimmy Vetayases num_vectors = i_ddi_intr_get_current_nintrs(dip); 16937ff178cdSJimmy Vetayases if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) { 16947ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_WARN, 16957ff178cdSJimmy Vetayases "set_grp: base vec not part of a grp or not aligned: " 16967ff178cdSJimmy Vetayases "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors)); 16977ff178cdSJimmy Vetayases return (NULL); 16987ff178cdSJimmy Vetayases } 16997ff178cdSJimmy Vetayases 17007ff178cdSJimmy Vetayases if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type)) 17017ff178cdSJimmy Vetayases return (NULL); 17027ff178cdSJimmy Vetayases 17037ff178cdSJimmy Vetayases *result = EIO; 17047ff178cdSJimmy Vetayases for (i = 1; i < num_vectors; i++) { 17057ff178cdSJimmy Vetayases if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL) 17067ff178cdSJimmy Vetayases return (NULL); 17077ff178cdSJimmy Vetayases #ifdef DEBUG 17087ff178cdSJimmy Vetayases /* 17097ff178cdSJimmy Vetayases * Sanity check: CPU and dip is the same for all entries. 17107ff178cdSJimmy Vetayases * May be called when first msi to be enabled, at this time 17117ff178cdSJimmy Vetayases * add_avintr() is not called for other msi 17127ff178cdSJimmy Vetayases */ 17137ff178cdSJimmy Vetayases if ((vp->v_share != 0) && 17147ff178cdSJimmy Vetayases ((APIX_GET_DIP(vp) != dip) || 17157ff178cdSJimmy Vetayases (vp->v_cpuid != vecp->v_cpuid))) { 17167ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_WARN, 17177ff178cdSJimmy Vetayases "set_grp: cpu or dip for vec 0x%x difft than for " 17187ff178cdSJimmy Vetayases "vec 0x%x\n", orig_vect, orig_vect + i)); 17197ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_WARN, 17207ff178cdSJimmy Vetayases " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu, 17217ff178cdSJimmy Vetayases vp->v_cpuid, (void *)dip, 17227ff178cdSJimmy Vetayases (void *)APIX_GET_DIP(vp))); 17237ff178cdSJimmy Vetayases return (NULL); 17247ff178cdSJimmy Vetayases } 17257ff178cdSJimmy Vetayases #endif /* DEBUG */ 17267ff178cdSJimmy Vetayases } 17277ff178cdSJimmy Vetayases 17287ff178cdSJimmy Vetayases cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip); 17297ff178cdSJimmy Vetayases handle = i_ddi_get_pci_config_handle(dip); 17307ff178cdSJimmy Vetayases msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL); 17317ff178cdSJimmy Vetayases 17327ff178cdSJimmy Vetayases /* MSI Per vector masking is supported. */ 17337ff178cdSJimmy Vetayases if (msi_ctrl & PCI_MSI_PVM_MASK) { 17347ff178cdSJimmy Vetayases if (msi_ctrl & PCI_MSI_64BIT_MASK) 17357ff178cdSJimmy Vetayases msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS; 17367ff178cdSJimmy Vetayases else 17377ff178cdSJimmy Vetayases msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK; 17387ff178cdSJimmy Vetayases msi_pvm = pci_config_get32(handle, msi_mask_off); 17397ff178cdSJimmy Vetayases pci_config_put32(handle, msi_mask_off, (uint32_t)-1); 17407ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_CONT, 17417ff178cdSJimmy Vetayases "set_grp: pvm supported. Mask set to 0x%x\n", 17427ff178cdSJimmy Vetayases pci_config_get32(handle, msi_mask_off))); 17437ff178cdSJimmy Vetayases } 17447ff178cdSJimmy Vetayases 17457ff178cdSJimmy Vetayases if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL) 17467ff178cdSJimmy Vetayases *result = 0; 17477ff178cdSJimmy Vetayases 17487ff178cdSJimmy Vetayases /* Reenable vectors if per vector masking is supported. */ 17497ff178cdSJimmy Vetayases if (msi_ctrl & PCI_MSI_PVM_MASK) { 17507ff178cdSJimmy Vetayases pci_config_put32(handle, msi_mask_off, msi_pvm); 17517ff178cdSJimmy Vetayases APIC_VERBOSE(INTR, (CE_CONT, 17527ff178cdSJimmy Vetayases "set_grp: pvm supported. Mask restored to 0x%x\n", 17537ff178cdSJimmy Vetayases pci_config_get32(handle, msi_mask_off))); 17547ff178cdSJimmy Vetayases } 17557ff178cdSJimmy Vetayases 17567ff178cdSJimmy Vetayases return (newp); 17577ff178cdSJimmy Vetayases } 17587ff178cdSJimmy Vetayases 17597ff178cdSJimmy Vetayases void 17607ff178cdSJimmy Vetayases apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector) 17617ff178cdSJimmy Vetayases { 17627ff178cdSJimmy Vetayases apic_irq_t *irqp; 17637ff178cdSJimmy Vetayases 17647ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 17657ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 17667ff178cdSJimmy Vetayases irqp->airq_cpu = cpuid; 17677ff178cdSJimmy Vetayases irqp->airq_vector = vector; 17687ff178cdSJimmy Vetayases apic_record_rdt_entry(irqp, irqno); 17697ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 17707ff178cdSJimmy Vetayases } 17717ff178cdSJimmy Vetayases 17727ff178cdSJimmy Vetayases apix_vector_t * 17737ff178cdSJimmy Vetayases apix_intx_get_vector(int irqno) 17747ff178cdSJimmy Vetayases { 17757ff178cdSJimmy Vetayases apic_irq_t *irqp; 17767ff178cdSJimmy Vetayases uint32_t cpuid; 17777ff178cdSJimmy Vetayases uchar_t vector; 17787ff178cdSJimmy Vetayases 17797ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 17807ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno & 0xff]; 17817ff178cdSJimmy Vetayases if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) { 17827ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 17837ff178cdSJimmy Vetayases return (NULL); 17847ff178cdSJimmy Vetayases } 17857ff178cdSJimmy Vetayases cpuid = irqp->airq_cpu; 17867ff178cdSJimmy Vetayases vector = irqp->airq_vector; 17877ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 17887ff178cdSJimmy Vetayases 17897ff178cdSJimmy Vetayases return (xv_vector(cpuid, vector)); 17907ff178cdSJimmy Vetayases } 17917ff178cdSJimmy Vetayases 17927ff178cdSJimmy Vetayases /* 17937ff178cdSJimmy Vetayases * Must called with interrupts disabled and apic_ioapic_lock held 17947ff178cdSJimmy Vetayases */ 17957ff178cdSJimmy Vetayases void 17967ff178cdSJimmy Vetayases apix_intx_enable(int irqno) 17977ff178cdSJimmy Vetayases { 17987ff178cdSJimmy Vetayases uchar_t ioapicindex, intin; 17997ff178cdSJimmy Vetayases apic_irq_t *irqp = apic_irq_table[irqno]; 18007ff178cdSJimmy Vetayases ioapic_rdt_t irdt; 18017ff178cdSJimmy Vetayases apic_cpus_info_t *cpu_infop; 18027ff178cdSJimmy Vetayases apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector); 18037ff178cdSJimmy Vetayases 18047ff178cdSJimmy Vetayases ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp)); 18057ff178cdSJimmy Vetayases 18067ff178cdSJimmy Vetayases ioapicindex = irqp->airq_ioapicindex; 18077ff178cdSJimmy Vetayases intin = irqp->airq_intin_no; 18087ff178cdSJimmy Vetayases cpu_infop = &apic_cpus[irqp->airq_cpu]; 18097ff178cdSJimmy Vetayases 18107ff178cdSJimmy Vetayases irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry; 18117ff178cdSJimmy Vetayases irdt.ir_hi = cpu_infop->aci_local_id; 18127ff178cdSJimmy Vetayases 18137ff178cdSJimmy Vetayases apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL, 18147ff178cdSJimmy Vetayases vecp->v_type, 1, ioapicindex); 18157ff178cdSJimmy Vetayases apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private, 18167ff178cdSJimmy Vetayases (void *)&irdt, vecp->v_type, 1); 18177ff178cdSJimmy Vetayases apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt); 18187ff178cdSJimmy Vetayases 18197ff178cdSJimmy Vetayases /* write RDT entry high dword - destination */ 18207ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin, 18217ff178cdSJimmy Vetayases irdt.ir_hi); 18227ff178cdSJimmy Vetayases 18237ff178cdSJimmy Vetayases /* Write the vector, trigger, and polarity portion of the RDT */ 18247ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo); 18257ff178cdSJimmy Vetayases 18267ff178cdSJimmy Vetayases vecp->v_state = APIX_STATE_ENABLED; 18277ff178cdSJimmy Vetayases 18287ff178cdSJimmy Vetayases APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x" 18297ff178cdSJimmy Vetayases " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n", 18307ff178cdSJimmy Vetayases ioapicindex, intin, irdt.ir_lo, irdt.ir_hi)); 18317ff178cdSJimmy Vetayases } 18327ff178cdSJimmy Vetayases 18337ff178cdSJimmy Vetayases /* 18347ff178cdSJimmy Vetayases * Must called with interrupts disabled and apic_ioapic_lock held 18357ff178cdSJimmy Vetayases */ 18367ff178cdSJimmy Vetayases void 18377ff178cdSJimmy Vetayases apix_intx_disable(int irqno) 18387ff178cdSJimmy Vetayases { 18397ff178cdSJimmy Vetayases apic_irq_t *irqp = apic_irq_table[irqno]; 18407ff178cdSJimmy Vetayases int ioapicindex, intin; 18417ff178cdSJimmy Vetayases 18427ff178cdSJimmy Vetayases ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp)); 18437ff178cdSJimmy Vetayases /* 18447ff178cdSJimmy Vetayases * The assumption here is that this is safe, even for 18457ff178cdSJimmy Vetayases * systems with IOAPICs that suffer from the hardware 18467ff178cdSJimmy Vetayases * erratum because all devices have been quiesced before 18477ff178cdSJimmy Vetayases * they unregister their interrupt handlers. If that 18487ff178cdSJimmy Vetayases * assumption turns out to be false, this mask operation 18497ff178cdSJimmy Vetayases * can induce the same erratum result we're trying to 18507ff178cdSJimmy Vetayases * avoid. 18517ff178cdSJimmy Vetayases */ 18527ff178cdSJimmy Vetayases ioapicindex = irqp->airq_ioapicindex; 18537ff178cdSJimmy Vetayases intin = irqp->airq_intin_no; 18547ff178cdSJimmy Vetayases ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK); 18557ff178cdSJimmy Vetayases 18567ff178cdSJimmy Vetayases APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x" 18577ff178cdSJimmy Vetayases " intin 0x%x\n", ioapicindex, intin)); 18587ff178cdSJimmy Vetayases } 18597ff178cdSJimmy Vetayases 18607ff178cdSJimmy Vetayases void 18617ff178cdSJimmy Vetayases apix_intx_free(int irqno) 18627ff178cdSJimmy Vetayases { 18637ff178cdSJimmy Vetayases apic_irq_t *irqp; 18647ff178cdSJimmy Vetayases 18657ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 18667ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 18677ff178cdSJimmy Vetayases 18687ff178cdSJimmy Vetayases if (IS_IRQ_FREE(irqp)) { 18697ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 18707ff178cdSJimmy Vetayases return; 18717ff178cdSJimmy Vetayases } 18727ff178cdSJimmy Vetayases 18737ff178cdSJimmy Vetayases irqp->airq_mps_intr_index = FREE_INDEX; 18747ff178cdSJimmy Vetayases irqp->airq_cpu = IRQ_UNINIT; 18757ff178cdSJimmy Vetayases irqp->airq_vector = APIX_INVALID_VECT; 18767ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 18777ff178cdSJimmy Vetayases } 18787ff178cdSJimmy Vetayases 18797ff178cdSJimmy Vetayases #ifdef DEBUG 18807ff178cdSJimmy Vetayases int apix_intr_deliver_timeouts = 0; 18817ff178cdSJimmy Vetayases int apix_intr_rirr_timeouts = 0; 18827ff178cdSJimmy Vetayases int apix_intr_rirr_reset_failure = 0; 18837ff178cdSJimmy Vetayases #endif 18847ff178cdSJimmy Vetayases int apix_max_reps_irr_pending = 10; 18857ff178cdSJimmy Vetayases 18867ff178cdSJimmy Vetayases #define GET_RDT_BITS(ioapic, intin, bits) \ 18877ff178cdSJimmy Vetayases (READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits)) 18887ff178cdSJimmy Vetayases #define APIX_CHECK_IRR_DELAY drv_usectohz(5000) 18897ff178cdSJimmy Vetayases 18907ff178cdSJimmy Vetayases int 18917ff178cdSJimmy Vetayases apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector) 18927ff178cdSJimmy Vetayases { 18937ff178cdSJimmy Vetayases apic_irq_t *irqp = apic_irq_table[irqno]; 18947ff178cdSJimmy Vetayases ulong_t iflag; 18957ff178cdSJimmy Vetayases int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked; 18967ff178cdSJimmy Vetayases 18977ff178cdSJimmy Vetayases ASSERT(irqp != NULL); 18987ff178cdSJimmy Vetayases 18997ff178cdSJimmy Vetayases iflag = intr_clear(); 19007ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 19017ff178cdSJimmy Vetayases 19027ff178cdSJimmy Vetayases ioapic_ix = irqp->airq_ioapicindex; 19037ff178cdSJimmy Vetayases intin_no = irqp->airq_intin_no; 19047ff178cdSJimmy Vetayases level = apic_level_intr[irqno]; 19057ff178cdSJimmy Vetayases 19067ff178cdSJimmy Vetayases /* 19077ff178cdSJimmy Vetayases * Wait for the delivery status bit to be cleared. This should 19087ff178cdSJimmy Vetayases * be a very small amount of time. 19097ff178cdSJimmy Vetayases */ 19107ff178cdSJimmy Vetayases repeats = 0; 19117ff178cdSJimmy Vetayases do { 19127ff178cdSJimmy Vetayases repeats++; 19137ff178cdSJimmy Vetayases 19147ff178cdSJimmy Vetayases for (waited = 0; waited < apic_max_reps_clear_pending; 19157ff178cdSJimmy Vetayases waited++) { 19167ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0) 19177ff178cdSJimmy Vetayases break; 19187ff178cdSJimmy Vetayases } 19197ff178cdSJimmy Vetayases if (!level) 19207ff178cdSJimmy Vetayases break; 19217ff178cdSJimmy Vetayases 19227ff178cdSJimmy Vetayases /* 19237ff178cdSJimmy Vetayases * Mask the RDT entry for level-triggered interrupts. 19247ff178cdSJimmy Vetayases */ 19257ff178cdSJimmy Vetayases irqp->airq_rdt_entry |= AV_MASK; 19267ff178cdSJimmy Vetayases rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 19277ff178cdSJimmy Vetayases intin_no); 19287ff178cdSJimmy Vetayases if ((masked = (rdt_entry & AV_MASK)) == 0) { 19297ff178cdSJimmy Vetayases /* Mask it */ 19307ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no, 19317ff178cdSJimmy Vetayases AV_MASK | rdt_entry); 19327ff178cdSJimmy Vetayases } 19337ff178cdSJimmy Vetayases 19347ff178cdSJimmy Vetayases /* 19357ff178cdSJimmy Vetayases * If there was a race and an interrupt was injected 19367ff178cdSJimmy Vetayases * just before we masked, check for that case here. 19377ff178cdSJimmy Vetayases * Then, unmask the RDT entry and try again. If we're 19387ff178cdSJimmy Vetayases * on our last try, don't unmask (because we want the 19397ff178cdSJimmy Vetayases * RDT entry to remain masked for the rest of the 19407ff178cdSJimmy Vetayases * function). 19417ff178cdSJimmy Vetayases */ 19427ff178cdSJimmy Vetayases rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 19437ff178cdSJimmy Vetayases intin_no); 19447ff178cdSJimmy Vetayases if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) && 19457ff178cdSJimmy Vetayases (repeats < apic_max_reps_clear_pending)) { 19467ff178cdSJimmy Vetayases /* Unmask it */ 19477ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 19487ff178cdSJimmy Vetayases intin_no, rdt_entry & ~AV_MASK); 19497ff178cdSJimmy Vetayases irqp->airq_rdt_entry &= ~AV_MASK; 19507ff178cdSJimmy Vetayases } 19517ff178cdSJimmy Vetayases } while ((rdt_entry & AV_PENDING) && 19527ff178cdSJimmy Vetayases (repeats < apic_max_reps_clear_pending)); 19537ff178cdSJimmy Vetayases 19547ff178cdSJimmy Vetayases #ifdef DEBUG 19557ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0) 19567ff178cdSJimmy Vetayases apix_intr_deliver_timeouts++; 19577ff178cdSJimmy Vetayases #endif 19587ff178cdSJimmy Vetayases 19597ff178cdSJimmy Vetayases if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method)) 19607ff178cdSJimmy Vetayases goto done; 19617ff178cdSJimmy Vetayases 19627ff178cdSJimmy Vetayases /* 19637ff178cdSJimmy Vetayases * wait for remote IRR to be cleared for level-triggered 19647ff178cdSJimmy Vetayases * interrupts 19657ff178cdSJimmy Vetayases */ 19667ff178cdSJimmy Vetayases repeats = 0; 19677ff178cdSJimmy Vetayases do { 19687ff178cdSJimmy Vetayases repeats++; 19697ff178cdSJimmy Vetayases 19707ff178cdSJimmy Vetayases for (waited = 0; waited < apic_max_reps_clear_pending; 19717ff178cdSJimmy Vetayases waited++) { 19727ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) 19737ff178cdSJimmy Vetayases == 0) 19747ff178cdSJimmy Vetayases break; 19757ff178cdSJimmy Vetayases } 19767ff178cdSJimmy Vetayases 19777ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { 19787ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 19797ff178cdSJimmy Vetayases intr_restore(iflag); 19807ff178cdSJimmy Vetayases 19817ff178cdSJimmy Vetayases delay(APIX_CHECK_IRR_DELAY); 19827ff178cdSJimmy Vetayases 19837ff178cdSJimmy Vetayases iflag = intr_clear(); 19847ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 19857ff178cdSJimmy Vetayases } 19867ff178cdSJimmy Vetayases } while (repeats < apix_max_reps_irr_pending); 19877ff178cdSJimmy Vetayases 19887ff178cdSJimmy Vetayases if (repeats >= apix_max_reps_irr_pending) { 19897ff178cdSJimmy Vetayases #ifdef DEBUG 19907ff178cdSJimmy Vetayases apix_intr_rirr_timeouts++; 19917ff178cdSJimmy Vetayases #endif 19927ff178cdSJimmy Vetayases 19937ff178cdSJimmy Vetayases /* 19947ff178cdSJimmy Vetayases * If we waited and the Remote IRR bit is still not cleared, 19957ff178cdSJimmy Vetayases * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS 19967ff178cdSJimmy Vetayases * times for this interrupt, try the last-ditch workaround: 19977ff178cdSJimmy Vetayases */ 19987ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { 19997ff178cdSJimmy Vetayases /* 20007ff178cdSJimmy Vetayases * Trying to clear the bit through normal 20017ff178cdSJimmy Vetayases * channels has failed. So as a last-ditch 20027ff178cdSJimmy Vetayases * effort, try to set the trigger mode to 20037ff178cdSJimmy Vetayases * edge, then to level. This has been 20047ff178cdSJimmy Vetayases * observed to work on many systems. 20057ff178cdSJimmy Vetayases */ 20067ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 20077ff178cdSJimmy Vetayases intin_no, 20087ff178cdSJimmy Vetayases READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 20097ff178cdSJimmy Vetayases intin_no) & ~AV_LEVEL); 20107ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 20117ff178cdSJimmy Vetayases intin_no, 20127ff178cdSJimmy Vetayases READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, 20137ff178cdSJimmy Vetayases intin_no) | AV_LEVEL); 20147ff178cdSJimmy Vetayases } 20157ff178cdSJimmy Vetayases 20167ff178cdSJimmy Vetayases if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) { 20177ff178cdSJimmy Vetayases #ifdef DEBUG 20187ff178cdSJimmy Vetayases apix_intr_rirr_reset_failure++; 20197ff178cdSJimmy Vetayases #endif 20207ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 20217ff178cdSJimmy Vetayases intr_restore(iflag); 20227ff178cdSJimmy Vetayases prom_printf("apix: Remote IRR still " 20237ff178cdSJimmy Vetayases "not clear for IOAPIC %d intin %d.\n" 20247ff178cdSJimmy Vetayases "\tInterrupts to this pin may cease " 20257ff178cdSJimmy Vetayases "functioning.\n", ioapic_ix, intin_no); 20267ff178cdSJimmy Vetayases return (1); /* return failure */ 20277ff178cdSJimmy Vetayases } 20287ff178cdSJimmy Vetayases } 20297ff178cdSJimmy Vetayases 20307ff178cdSJimmy Vetayases done: 20317ff178cdSJimmy Vetayases /* change apic_irq_table */ 20327ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 20337ff178cdSJimmy Vetayases intr_restore(iflag); 20347ff178cdSJimmy Vetayases apix_intx_set_vector(irqno, cpuid, vector); 20357ff178cdSJimmy Vetayases iflag = intr_clear(); 20367ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 20377ff178cdSJimmy Vetayases 20387ff178cdSJimmy Vetayases /* reprogramme IO-APIC RDT entry */ 20397ff178cdSJimmy Vetayases apix_intx_enable(irqno); 20407ff178cdSJimmy Vetayases 20417ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 20427ff178cdSJimmy Vetayases intr_restore(iflag); 20437ff178cdSJimmy Vetayases 20447ff178cdSJimmy Vetayases return (0); 20457ff178cdSJimmy Vetayases } 20467ff178cdSJimmy Vetayases 20477ff178cdSJimmy Vetayases static int 20487ff178cdSJimmy Vetayases apix_intx_get_pending(int irqno) 20497ff178cdSJimmy Vetayases { 20507ff178cdSJimmy Vetayases apic_irq_t *irqp; 20517ff178cdSJimmy Vetayases int intin, ioapicindex, pending; 20527ff178cdSJimmy Vetayases ulong_t iflag; 20537ff178cdSJimmy Vetayases 20547ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 20557ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 20567ff178cdSJimmy Vetayases if (IS_IRQ_FREE(irqp)) { 20577ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 20587ff178cdSJimmy Vetayases return (0); 20597ff178cdSJimmy Vetayases } 20607ff178cdSJimmy Vetayases 20617ff178cdSJimmy Vetayases /* check IO-APIC delivery status */ 20627ff178cdSJimmy Vetayases intin = irqp->airq_intin_no; 20637ff178cdSJimmy Vetayases ioapicindex = irqp->airq_ioapicindex; 20647ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 20657ff178cdSJimmy Vetayases 20667ff178cdSJimmy Vetayases iflag = intr_clear(); 20677ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 20687ff178cdSJimmy Vetayases 20697ff178cdSJimmy Vetayases pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) & 20707ff178cdSJimmy Vetayases AV_PENDING) ? 1 : 0; 20717ff178cdSJimmy Vetayases 20727ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 20737ff178cdSJimmy Vetayases intr_restore(iflag); 20747ff178cdSJimmy Vetayases 20757ff178cdSJimmy Vetayases return (pending); 20767ff178cdSJimmy Vetayases } 20777ff178cdSJimmy Vetayases 2078636dfb4bSJerry Jelinek /* 2079636dfb4bSJerry Jelinek * This function will mask the interrupt on the I/O APIC 2080636dfb4bSJerry Jelinek */ 20817ff178cdSJimmy Vetayases static void 20827ff178cdSJimmy Vetayases apix_intx_set_mask(int irqno) 20837ff178cdSJimmy Vetayases { 20847ff178cdSJimmy Vetayases int intin, ioapixindex, rdt_entry; 20857ff178cdSJimmy Vetayases ulong_t iflag; 20867ff178cdSJimmy Vetayases apic_irq_t *irqp; 20877ff178cdSJimmy Vetayases 20887ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 20897ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 20907ff178cdSJimmy Vetayases 20917ff178cdSJimmy Vetayases ASSERT(irqp->airq_mps_intr_index != FREE_INDEX); 20927ff178cdSJimmy Vetayases 20937ff178cdSJimmy Vetayases intin = irqp->airq_intin_no; 20947ff178cdSJimmy Vetayases ioapixindex = irqp->airq_ioapicindex; 20957ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 20967ff178cdSJimmy Vetayases 20977ff178cdSJimmy Vetayases iflag = intr_clear(); 20987ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 20997ff178cdSJimmy Vetayases 21007ff178cdSJimmy Vetayases rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin); 21017ff178cdSJimmy Vetayases 21027ff178cdSJimmy Vetayases /* clear mask */ 21037ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin, 21047ff178cdSJimmy Vetayases (AV_MASK | rdt_entry)); 21057ff178cdSJimmy Vetayases 21067ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 21077ff178cdSJimmy Vetayases intr_restore(iflag); 21087ff178cdSJimmy Vetayases } 21097ff178cdSJimmy Vetayases 2110636dfb4bSJerry Jelinek /* 2111636dfb4bSJerry Jelinek * This function will clear the mask for the interrupt on the I/O APIC 2112636dfb4bSJerry Jelinek */ 21137ff178cdSJimmy Vetayases static void 21147ff178cdSJimmy Vetayases apix_intx_clear_mask(int irqno) 21157ff178cdSJimmy Vetayases { 21167ff178cdSJimmy Vetayases int intin, ioapixindex, rdt_entry; 21177ff178cdSJimmy Vetayases ulong_t iflag; 21187ff178cdSJimmy Vetayases apic_irq_t *irqp; 21197ff178cdSJimmy Vetayases 21207ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 21217ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 21227ff178cdSJimmy Vetayases 21237ff178cdSJimmy Vetayases ASSERT(irqp->airq_mps_intr_index != FREE_INDEX); 21247ff178cdSJimmy Vetayases 21257ff178cdSJimmy Vetayases intin = irqp->airq_intin_no; 21267ff178cdSJimmy Vetayases ioapixindex = irqp->airq_ioapicindex; 21277ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 21287ff178cdSJimmy Vetayases 21297ff178cdSJimmy Vetayases iflag = intr_clear(); 21307ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 21317ff178cdSJimmy Vetayases 21327ff178cdSJimmy Vetayases rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin); 21337ff178cdSJimmy Vetayases 21347ff178cdSJimmy Vetayases /* clear mask */ 21357ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin, 21367ff178cdSJimmy Vetayases ((~AV_MASK) & rdt_entry)); 21377ff178cdSJimmy Vetayases 21387ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 21397ff178cdSJimmy Vetayases intr_restore(iflag); 21407ff178cdSJimmy Vetayases } 21417ff178cdSJimmy Vetayases 21427ff178cdSJimmy Vetayases /* 21437ff178cdSJimmy Vetayases * For level-triggered interrupt, mask the IRQ line. Mask means 21447ff178cdSJimmy Vetayases * new interrupts will not be delivered. The interrupt already 21457ff178cdSJimmy Vetayases * accepted by a local APIC is not affected 21467ff178cdSJimmy Vetayases */ 21477ff178cdSJimmy Vetayases void 21487ff178cdSJimmy Vetayases apix_level_intr_pre_eoi(int irq) 21497ff178cdSJimmy Vetayases { 21507ff178cdSJimmy Vetayases apic_irq_t *irqp = apic_irq_table[irq]; 21517ff178cdSJimmy Vetayases int apic_ix, intin_ix; 21527ff178cdSJimmy Vetayases 21537ff178cdSJimmy Vetayases if (irqp == NULL) 21547ff178cdSJimmy Vetayases return; 21557ff178cdSJimmy Vetayases 21567ff178cdSJimmy Vetayases ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL); 21577ff178cdSJimmy Vetayases 21587ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 21597ff178cdSJimmy Vetayases 21607ff178cdSJimmy Vetayases intin_ix = irqp->airq_intin_no; 21617ff178cdSJimmy Vetayases apic_ix = irqp->airq_ioapicindex; 21627ff178cdSJimmy Vetayases 21637ff178cdSJimmy Vetayases if (irqp->airq_cpu != CPU->cpu_id) { 21647ff178cdSJimmy Vetayases if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method)) 21657ff178cdSJimmy Vetayases ioapic_write_eoi(apic_ix, irqp->airq_vector); 21667ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 21677ff178cdSJimmy Vetayases return; 21687ff178cdSJimmy Vetayases } 21697ff178cdSJimmy Vetayases 21707ff178cdSJimmy Vetayases if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) { 21717ff178cdSJimmy Vetayases /* 21727ff178cdSJimmy Vetayases * This is a IOxAPIC and there is EOI register: 21737ff178cdSJimmy Vetayases * Change the vector to reserved unused vector, so that 21747ff178cdSJimmy Vetayases * the EOI from Local APIC won't clear the Remote IRR for 21757ff178cdSJimmy Vetayases * this level trigger interrupt. Instead, we'll manually 21767ff178cdSJimmy Vetayases * clear it in apix_post_hardint() after ISR handling. 21777ff178cdSJimmy Vetayases */ 21787ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, 21797ff178cdSJimmy Vetayases (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR); 21807ff178cdSJimmy Vetayases } else { 21817ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, 21827ff178cdSJimmy Vetayases AV_MASK | irqp->airq_rdt_entry); 21837ff178cdSJimmy Vetayases } 21847ff178cdSJimmy Vetayases 21857ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 21867ff178cdSJimmy Vetayases } 21877ff178cdSJimmy Vetayases 21887ff178cdSJimmy Vetayases /* 21897ff178cdSJimmy Vetayases * For level-triggered interrupt, unmask the IRQ line 21907ff178cdSJimmy Vetayases * or restore the original vector number. 21917ff178cdSJimmy Vetayases */ 21927ff178cdSJimmy Vetayases void 21937ff178cdSJimmy Vetayases apix_level_intr_post_dispatch(int irq) 21947ff178cdSJimmy Vetayases { 21957ff178cdSJimmy Vetayases apic_irq_t *irqp = apic_irq_table[irq]; 21967ff178cdSJimmy Vetayases int apic_ix, intin_ix; 21977ff178cdSJimmy Vetayases 21987ff178cdSJimmy Vetayases if (irqp == NULL) 21997ff178cdSJimmy Vetayases return; 22007ff178cdSJimmy Vetayases 22017ff178cdSJimmy Vetayases lock_set(&apic_ioapic_lock); 22027ff178cdSJimmy Vetayases 22037ff178cdSJimmy Vetayases intin_ix = irqp->airq_intin_no; 22047ff178cdSJimmy Vetayases apic_ix = irqp->airq_ioapicindex; 22057ff178cdSJimmy Vetayases 22067ff178cdSJimmy Vetayases if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) { 22077ff178cdSJimmy Vetayases /* 22087ff178cdSJimmy Vetayases * Already sent EOI back to Local APIC. 22097ff178cdSJimmy Vetayases * Send EOI to IO-APIC 22107ff178cdSJimmy Vetayases */ 22117ff178cdSJimmy Vetayases ioapic_write_eoi(apic_ix, irqp->airq_vector); 22127ff178cdSJimmy Vetayases } else { 22137ff178cdSJimmy Vetayases /* clear the mask or restore the vector */ 22147ff178cdSJimmy Vetayases WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix, 22157ff178cdSJimmy Vetayases irqp->airq_rdt_entry); 22167ff178cdSJimmy Vetayases 22177ff178cdSJimmy Vetayases /* send EOI to IOxAPIC */ 22187ff178cdSJimmy Vetayases if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) 22197ff178cdSJimmy Vetayases ioapic_write_eoi(apic_ix, irqp->airq_vector); 22207ff178cdSJimmy Vetayases } 22217ff178cdSJimmy Vetayases 22227ff178cdSJimmy Vetayases lock_clear(&apic_ioapic_lock); 22237ff178cdSJimmy Vetayases } 22247ff178cdSJimmy Vetayases 22257ff178cdSJimmy Vetayases static int 22267ff178cdSJimmy Vetayases apix_intx_get_shared(int irqno) 22277ff178cdSJimmy Vetayases { 22287ff178cdSJimmy Vetayases apic_irq_t *irqp; 22297ff178cdSJimmy Vetayases int share; 22307ff178cdSJimmy Vetayases 22317ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 22327ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 22337ff178cdSJimmy Vetayases if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) { 22347ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 22357ff178cdSJimmy Vetayases return (0); 22367ff178cdSJimmy Vetayases } 22377ff178cdSJimmy Vetayases share = irqp->airq_share; 22387ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 22397ff178cdSJimmy Vetayases 22407ff178cdSJimmy Vetayases return (share); 22417ff178cdSJimmy Vetayases } 22427ff178cdSJimmy Vetayases 22437ff178cdSJimmy Vetayases static void 22447ff178cdSJimmy Vetayases apix_intx_set_shared(int irqno, int delta) 22457ff178cdSJimmy Vetayases { 22467ff178cdSJimmy Vetayases apic_irq_t *irqp; 22477ff178cdSJimmy Vetayases 22487ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 22497ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 22507ff178cdSJimmy Vetayases if (IS_IRQ_FREE(irqp)) { 22517ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 22527ff178cdSJimmy Vetayases return; 22537ff178cdSJimmy Vetayases } 22547ff178cdSJimmy Vetayases irqp->airq_share += delta; 22557ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 22567ff178cdSJimmy Vetayases } 22577ff178cdSJimmy Vetayases 22587ff178cdSJimmy Vetayases /* 22597ff178cdSJimmy Vetayases * Setup IRQ table. Return IRQ no or -1 on failure 22607ff178cdSJimmy Vetayases */ 22617ff178cdSJimmy Vetayases static int 22627ff178cdSJimmy Vetayases apix_intx_setup(dev_info_t *dip, int inum, int irqno, 22637ff178cdSJimmy Vetayases struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp) 22647ff178cdSJimmy Vetayases { 22657ff178cdSJimmy Vetayases int origirq = ispec->intrspec_vec; 22667ff178cdSJimmy Vetayases int newirq; 22677ff178cdSJimmy Vetayases short intr_index; 22687ff178cdSJimmy Vetayases uchar_t ipin, ioapic, ioapicindex; 22697ff178cdSJimmy Vetayases apic_irq_t *irqp; 22707ff178cdSJimmy Vetayases 22717ff178cdSJimmy Vetayases UNREFERENCED_1PARAMETER(inum); 22727ff178cdSJimmy Vetayases 22737ff178cdSJimmy Vetayases if (intrp != NULL) { 22747ff178cdSJimmy Vetayases intr_index = (short)(intrp - apic_io_intrp); 22757ff178cdSJimmy Vetayases ioapic = intrp->intr_destid; 22767ff178cdSJimmy Vetayases ipin = intrp->intr_destintin; 22777ff178cdSJimmy Vetayases 22787ff178cdSJimmy Vetayases /* Find ioapicindex. If destid was ALL, we will exit with 0. */ 22797ff178cdSJimmy Vetayases for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--) 22807ff178cdSJimmy Vetayases if (apic_io_id[ioapicindex] == ioapic) 22817ff178cdSJimmy Vetayases break; 22827ff178cdSJimmy Vetayases ASSERT((ioapic == apic_io_id[ioapicindex]) || 22837ff178cdSJimmy Vetayases (ioapic == INTR_ALL_APIC)); 22847ff178cdSJimmy Vetayases 22857ff178cdSJimmy Vetayases /* check whether this intin# has been used by another irqno */ 22867ff178cdSJimmy Vetayases if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1) 22877ff178cdSJimmy Vetayases return (newirq); 22887ff178cdSJimmy Vetayases 22897ff178cdSJimmy Vetayases } else if (iflagp != NULL) { /* ACPI */ 22907ff178cdSJimmy Vetayases intr_index = ACPI_INDEX; 22917ff178cdSJimmy Vetayases ioapicindex = acpi_find_ioapic(irqno); 22927ff178cdSJimmy Vetayases ASSERT(ioapicindex != 0xFF); 22937ff178cdSJimmy Vetayases ioapic = apic_io_id[ioapicindex]; 22947ff178cdSJimmy Vetayases ipin = irqno - apic_io_vectbase[ioapicindex]; 22957ff178cdSJimmy Vetayases 22967ff178cdSJimmy Vetayases if (apic_irq_table[irqno] && 22977ff178cdSJimmy Vetayases apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) { 22987ff178cdSJimmy Vetayases ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin && 22997ff178cdSJimmy Vetayases apic_irq_table[irqno]->airq_ioapicindex == 23007ff178cdSJimmy Vetayases ioapicindex); 23017ff178cdSJimmy Vetayases return (irqno); 23027ff178cdSJimmy Vetayases } 23037ff178cdSJimmy Vetayases 23047ff178cdSJimmy Vetayases } else { /* default configuration */ 23057ff178cdSJimmy Vetayases intr_index = DEFAULT_INDEX; 23067ff178cdSJimmy Vetayases ioapicindex = 0; 23077ff178cdSJimmy Vetayases ioapic = apic_io_id[ioapicindex]; 23087ff178cdSJimmy Vetayases ipin = (uchar_t)irqno; 23097ff178cdSJimmy Vetayases } 23107ff178cdSJimmy Vetayases 23117ff178cdSJimmy Vetayases /* allocate a new IRQ no */ 23127ff178cdSJimmy Vetayases if ((irqp = apic_irq_table[irqno]) == NULL) { 23137ff178cdSJimmy Vetayases irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP); 23147ff178cdSJimmy Vetayases apic_irq_table[irqno] = irqp; 23157ff178cdSJimmy Vetayases } else { 23167ff178cdSJimmy Vetayases if (irqp->airq_mps_intr_index != FREE_INDEX) { 23177ff178cdSJimmy Vetayases newirq = apic_allocate_irq(apic_first_avail_irq); 23187ff178cdSJimmy Vetayases if (newirq == -1) { 23197ff178cdSJimmy Vetayases return (-1); 23207ff178cdSJimmy Vetayases } 23217ff178cdSJimmy Vetayases irqno = newirq; 23227ff178cdSJimmy Vetayases irqp = apic_irq_table[irqno]; 23237ff178cdSJimmy Vetayases ASSERT(irqp != NULL); 23247ff178cdSJimmy Vetayases } 23257ff178cdSJimmy Vetayases } 23267ff178cdSJimmy Vetayases apic_max_device_irq = max(irqno, apic_max_device_irq); 23277ff178cdSJimmy Vetayases apic_min_device_irq = min(irqno, apic_min_device_irq); 23287ff178cdSJimmy Vetayases 23297ff178cdSJimmy Vetayases irqp->airq_mps_intr_index = intr_index; 23307ff178cdSJimmy Vetayases irqp->airq_ioapicindex = ioapicindex; 23317ff178cdSJimmy Vetayases irqp->airq_intin_no = ipin; 23327ff178cdSJimmy Vetayases irqp->airq_dip = dip; 23337ff178cdSJimmy Vetayases irqp->airq_origirq = (uchar_t)origirq; 23347ff178cdSJimmy Vetayases if (iflagp != NULL) 23357ff178cdSJimmy Vetayases irqp->airq_iflag = *iflagp; 23367ff178cdSJimmy Vetayases irqp->airq_cpu = IRQ_UNINIT; 23377ff178cdSJimmy Vetayases irqp->airq_vector = 0; 23387ff178cdSJimmy Vetayases 23397ff178cdSJimmy Vetayases return (irqno); 23407ff178cdSJimmy Vetayases } 23417ff178cdSJimmy Vetayases 23427ff178cdSJimmy Vetayases /* 23437ff178cdSJimmy Vetayases * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error 23447ff178cdSJimmy Vetayases */ 23457ff178cdSJimmy Vetayases static int 23467ff178cdSJimmy Vetayases apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype, 23477ff178cdSJimmy Vetayases struct intrspec *ispec) 23487ff178cdSJimmy Vetayases { 23497ff178cdSJimmy Vetayases int irqno = ispec->intrspec_vec; 23507ff178cdSJimmy Vetayases int newirq, i; 23517ff178cdSJimmy Vetayases iflag_t intr_flag; 23527ff178cdSJimmy Vetayases ACPI_SUBTABLE_HEADER *hp; 23537ff178cdSJimmy Vetayases ACPI_MADT_INTERRUPT_OVERRIDE *isop; 23547ff178cdSJimmy Vetayases struct apic_io_intr *intrp; 23557ff178cdSJimmy Vetayases 23567ff178cdSJimmy Vetayases if (!apic_enable_acpi || apic_use_acpi_madt_only) { 23577ff178cdSJimmy Vetayases int busid; 23587ff178cdSJimmy Vetayases 23597ff178cdSJimmy Vetayases if (bustype == 0) 23607ff178cdSJimmy Vetayases bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA; 23617ff178cdSJimmy Vetayases 23627ff178cdSJimmy Vetayases /* loop checking BUS_ISA/BUS_EISA */ 23637ff178cdSJimmy Vetayases for (i = 0; i < 2; i++) { 23647ff178cdSJimmy Vetayases if (((busid = apic_find_bus_id(bustype)) != -1) && 23657ff178cdSJimmy Vetayases ((intrp = apic_find_io_intr_w_busid(irqno, busid)) 23667ff178cdSJimmy Vetayases != NULL)) { 23677ff178cdSJimmy Vetayases return (apix_intx_setup(dip, inum, irqno, 23687ff178cdSJimmy Vetayases intrp, ispec, NULL)); 23697ff178cdSJimmy Vetayases } 23707ff178cdSJimmy Vetayases bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA; 23717ff178cdSJimmy Vetayases } 23727ff178cdSJimmy Vetayases 23737ff178cdSJimmy Vetayases /* fall back to default configuration */ 23747ff178cdSJimmy Vetayases return (-1); 23757ff178cdSJimmy Vetayases } 23767ff178cdSJimmy Vetayases 23777ff178cdSJimmy Vetayases /* search iso entries first */ 23787ff178cdSJimmy Vetayases if (acpi_iso_cnt != 0) { 23797ff178cdSJimmy Vetayases hp = (ACPI_SUBTABLE_HEADER *)acpi_isop; 23807ff178cdSJimmy Vetayases i = 0; 23817ff178cdSJimmy Vetayases while (i < acpi_iso_cnt) { 23827ff178cdSJimmy Vetayases if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) { 23837ff178cdSJimmy Vetayases isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp; 23847ff178cdSJimmy Vetayases if (isop->Bus == 0 && 23857ff178cdSJimmy Vetayases isop->SourceIrq == irqno) { 23867ff178cdSJimmy Vetayases newirq = isop->GlobalIrq; 23877ff178cdSJimmy Vetayases intr_flag.intr_po = isop->IntiFlags & 23887ff178cdSJimmy Vetayases ACPI_MADT_POLARITY_MASK; 23897ff178cdSJimmy Vetayases intr_flag.intr_el = (isop->IntiFlags & 23907ff178cdSJimmy Vetayases ACPI_MADT_TRIGGER_MASK) >> 2; 23917ff178cdSJimmy Vetayases intr_flag.bustype = BUS_ISA; 23927ff178cdSJimmy Vetayases 23937ff178cdSJimmy Vetayases return (apix_intx_setup(dip, inum, 23947ff178cdSJimmy Vetayases newirq, NULL, ispec, &intr_flag)); 23957ff178cdSJimmy Vetayases } 23967ff178cdSJimmy Vetayases i++; 23977ff178cdSJimmy Vetayases } 23987ff178cdSJimmy Vetayases hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) + 23997ff178cdSJimmy Vetayases hp->Length); 24007ff178cdSJimmy Vetayases } 24017ff178cdSJimmy Vetayases } 24027ff178cdSJimmy Vetayases intr_flag.intr_po = INTR_PO_ACTIVE_HIGH; 24037ff178cdSJimmy Vetayases intr_flag.intr_el = INTR_EL_EDGE; 24047ff178cdSJimmy Vetayases intr_flag.bustype = BUS_ISA; 24057ff178cdSJimmy Vetayases return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag)); 24067ff178cdSJimmy Vetayases } 24077ff178cdSJimmy Vetayases 24087ff178cdSJimmy Vetayases 24097ff178cdSJimmy Vetayases /* 24107ff178cdSJimmy Vetayases * Setup IRQ table for pci devices. Return IRQ no or -1 on error 24117ff178cdSJimmy Vetayases */ 24127ff178cdSJimmy Vetayases static int 24137ff178cdSJimmy Vetayases apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype, 24147ff178cdSJimmy Vetayases struct intrspec *ispec) 24157ff178cdSJimmy Vetayases { 24167ff178cdSJimmy Vetayases int busid, devid, pci_irq; 24177ff178cdSJimmy Vetayases ddi_acc_handle_t cfg_handle; 24187ff178cdSJimmy Vetayases uchar_t ipin; 24197ff178cdSJimmy Vetayases iflag_t intr_flag; 24207ff178cdSJimmy Vetayases struct apic_io_intr *intrp; 24217ff178cdSJimmy Vetayases 24227ff178cdSJimmy Vetayases if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0) 24237ff178cdSJimmy Vetayases return (-1); 24247ff178cdSJimmy Vetayases 24257ff178cdSJimmy Vetayases if (busid == 0 && apic_pci_bus_total == 1) 24267ff178cdSJimmy Vetayases busid = (int)apic_single_pci_busid; 24277ff178cdSJimmy Vetayases 24287ff178cdSJimmy Vetayases if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS) 24297ff178cdSJimmy Vetayases return (-1); 24307ff178cdSJimmy Vetayases ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA; 24317ff178cdSJimmy Vetayases pci_config_teardown(&cfg_handle); 24327ff178cdSJimmy Vetayases 24337ff178cdSJimmy Vetayases if (apic_enable_acpi && !apic_use_acpi_madt_only) { /* ACPI */ 24347ff178cdSJimmy Vetayases if (apic_acpi_translate_pci_irq(dip, busid, devid, 24357ff178cdSJimmy Vetayases ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS) 24367ff178cdSJimmy Vetayases return (-1); 24377ff178cdSJimmy Vetayases 24387ff178cdSJimmy Vetayases intr_flag.bustype = (uchar_t)bustype; 24397ff178cdSJimmy Vetayases return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec, 24407ff178cdSJimmy Vetayases &intr_flag)); 24417ff178cdSJimmy Vetayases } 24427ff178cdSJimmy Vetayases 24437ff178cdSJimmy Vetayases /* MP configuration table */ 24447ff178cdSJimmy Vetayases pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3); 24457ff178cdSJimmy Vetayases if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) { 24467ff178cdSJimmy Vetayases pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp); 24477ff178cdSJimmy Vetayases if (pci_irq == -1) 24487ff178cdSJimmy Vetayases return (-1); 24497ff178cdSJimmy Vetayases } 24507ff178cdSJimmy Vetayases 24517ff178cdSJimmy Vetayases return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL)); 24527ff178cdSJimmy Vetayases } 24537ff178cdSJimmy Vetayases 24547ff178cdSJimmy Vetayases /* 24557ff178cdSJimmy Vetayases * Translate and return IRQ no 24567ff178cdSJimmy Vetayases */ 24577ff178cdSJimmy Vetayases static int 24587ff178cdSJimmy Vetayases apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec) 24597ff178cdSJimmy Vetayases { 24607ff178cdSJimmy Vetayases int newirq, irqno = ispec->intrspec_vec; 24617ff178cdSJimmy Vetayases int parent_is_pci_or_pciex = 0, child_is_pciex = 0; 24627ff178cdSJimmy Vetayases int bustype = 0, dev_len; 24637ff178cdSJimmy Vetayases char dev_type[16]; 24647ff178cdSJimmy Vetayases 24657ff178cdSJimmy Vetayases if (apic_defconf) { 24667ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 24677ff178cdSJimmy Vetayases goto defconf; 24687ff178cdSJimmy Vetayases } 24697ff178cdSJimmy Vetayases 24707ff178cdSJimmy Vetayases if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) { 24717ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 24727ff178cdSJimmy Vetayases goto nonpci; 24737ff178cdSJimmy Vetayases } 24747ff178cdSJimmy Vetayases 24757ff178cdSJimmy Vetayases /* 24767ff178cdSJimmy Vetayases * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string() 24777ff178cdSJimmy Vetayases * to avoid extra buffer allocation. 24787ff178cdSJimmy Vetayases */ 24797ff178cdSJimmy Vetayases dev_len = sizeof (dev_type); 24807ff178cdSJimmy Vetayases if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip), 24817ff178cdSJimmy Vetayases DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type, 24827ff178cdSJimmy Vetayases &dev_len) == DDI_PROP_SUCCESS) { 24837ff178cdSJimmy Vetayases if ((strcmp(dev_type, "pci") == 0) || 24847ff178cdSJimmy Vetayases (strcmp(dev_type, "pciex") == 0)) 24857ff178cdSJimmy Vetayases parent_is_pci_or_pciex = 1; 24867ff178cdSJimmy Vetayases } 24877ff178cdSJimmy Vetayases 24887ff178cdSJimmy Vetayases if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, 24897ff178cdSJimmy Vetayases DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type, 24907ff178cdSJimmy Vetayases &dev_len) == DDI_PROP_SUCCESS) { 24917ff178cdSJimmy Vetayases if (strstr(dev_type, "pciex")) 24927ff178cdSJimmy Vetayases child_is_pciex = 1; 24937ff178cdSJimmy Vetayases } 24947ff178cdSJimmy Vetayases 24957ff178cdSJimmy Vetayases mutex_enter(&airq_mutex); 24967ff178cdSJimmy Vetayases 24977ff178cdSJimmy Vetayases if (parent_is_pci_or_pciex) { 24987ff178cdSJimmy Vetayases bustype = child_is_pciex ? BUS_PCIE : BUS_PCI; 24997ff178cdSJimmy Vetayases newirq = apix_intx_setup_pci(dip, inum, bustype, ispec); 25007ff178cdSJimmy Vetayases if (newirq != -1) 25017ff178cdSJimmy Vetayases goto done; 25027ff178cdSJimmy Vetayases bustype = 0; 25037ff178cdSJimmy Vetayases } else if (strcmp(dev_type, "isa") == 0) 25047ff178cdSJimmy Vetayases bustype = BUS_ISA; 25057ff178cdSJimmy Vetayases else if (strcmp(dev_type, "eisa") == 0) 25067ff178cdSJimmy Vetayases bustype = BUS_EISA; 25077ff178cdSJimmy Vetayases 25087ff178cdSJimmy Vetayases nonpci: 25097ff178cdSJimmy Vetayases newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec); 25107ff178cdSJimmy Vetayases if (newirq != -1) 25117ff178cdSJimmy Vetayases goto done; 25127ff178cdSJimmy Vetayases 25137ff178cdSJimmy Vetayases defconf: 25147ff178cdSJimmy Vetayases newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL); 25157ff178cdSJimmy Vetayases if (newirq == -1) { 25167ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 25177ff178cdSJimmy Vetayases return (-1); 25187ff178cdSJimmy Vetayases } 25197ff178cdSJimmy Vetayases done: 25207ff178cdSJimmy Vetayases ASSERT(apic_irq_table[newirq]); 25217ff178cdSJimmy Vetayases mutex_exit(&airq_mutex); 25227ff178cdSJimmy Vetayases return (newirq); 25237ff178cdSJimmy Vetayases } 25247ff178cdSJimmy Vetayases 25257ff178cdSJimmy Vetayases static int 25267ff178cdSJimmy Vetayases apix_intx_alloc_vector(dev_info_t *dip, int inum, struct intrspec *ispec) 25277ff178cdSJimmy Vetayases { 25287ff178cdSJimmy Vetayases int irqno; 25297ff178cdSJimmy Vetayases apix_vector_t *vecp; 25307ff178cdSJimmy Vetayases 25317ff178cdSJimmy Vetayases if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1) 25327ff178cdSJimmy Vetayases return (0); 25337ff178cdSJimmy Vetayases 25347ff178cdSJimmy Vetayases if ((vecp = apix_alloc_intx(dip, inum, irqno)) == NULL) 25357ff178cdSJimmy Vetayases return (0); 25367ff178cdSJimmy Vetayases 25377ff178cdSJimmy Vetayases DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s " 25387ff178cdSJimmy Vetayases "irqno=0x%x cpuid=%d vector=0x%x\n", 25397ff178cdSJimmy Vetayases (void *)dip, ddi_driver_name(dip), irqno, 25407ff178cdSJimmy Vetayases vecp->v_cpuid, vecp->v_vector)); 25417ff178cdSJimmy Vetayases 25427ff178cdSJimmy Vetayases return (1); 25437ff178cdSJimmy Vetayases } 25447ff178cdSJimmy Vetayases 25457ff178cdSJimmy Vetayases /* 25467ff178cdSJimmy Vetayases * Return the vector number if the translated IRQ for this device 25477ff178cdSJimmy Vetayases * has a vector mapping setup. If no IRQ setup exists or no vector is 25487ff178cdSJimmy Vetayases * allocated to it then return 0. 25497ff178cdSJimmy Vetayases */ 25507ff178cdSJimmy Vetayases static apix_vector_t * 25517ff178cdSJimmy Vetayases apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec) 25527ff178cdSJimmy Vetayases { 25537ff178cdSJimmy Vetayases int irqno; 25547ff178cdSJimmy Vetayases apix_vector_t *vecp; 25557ff178cdSJimmy Vetayases 25567ff178cdSJimmy Vetayases /* get the IRQ number */ 25577ff178cdSJimmy Vetayases if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1) 25587ff178cdSJimmy Vetayases return (NULL); 25597ff178cdSJimmy Vetayases 25607ff178cdSJimmy Vetayases /* get the vector number if a vector is allocated to this irqno */ 25617ff178cdSJimmy Vetayases vecp = apix_intx_get_vector(irqno); 25627ff178cdSJimmy Vetayases 25637ff178cdSJimmy Vetayases return (vecp); 25647ff178cdSJimmy Vetayases } 25657ff178cdSJimmy Vetayases 2566583cd330SHans Rosenfeld /* 2567583cd330SHans Rosenfeld * Switch between safe and x2APIC IPI sending method. 2568583cd330SHans Rosenfeld * The CPU may power on in xapic mode or x2apic mode. If the CPU needs to send 2569583cd330SHans Rosenfeld * an IPI to other CPUs before entering x2APIC mode, it still needs to use the 2570583cd330SHans Rosenfeld * xAPIC method. Before sending a StartIPI to the target CPU, psm_send_ipi will 2571583cd330SHans Rosenfeld * be changed to apic_common_send_ipi, which detects current local APIC mode and 2572583cd330SHans Rosenfeld * use the right method to send an IPI. If some CPUs fail to start up, 2573583cd330SHans Rosenfeld * apic_poweron_cnt won't return to zero, so apic_common_send_ipi will always be 2574583cd330SHans Rosenfeld * used. psm_send_ipi can't be simply changed back to x2apic_send_ipi if some 2575583cd330SHans Rosenfeld * CPUs failed to start up because those failed CPUs may recover itself later at 2576583cd330SHans Rosenfeld * unpredictable time. 2577583cd330SHans Rosenfeld */ 2578583cd330SHans Rosenfeld void 2579583cd330SHans Rosenfeld apic_switch_ipi_callback(boolean_t enter) 2580583cd330SHans Rosenfeld { 2581583cd330SHans Rosenfeld ulong_t iflag; 2582583cd330SHans Rosenfeld struct psm_ops *pops = psmops; 2583583cd330SHans Rosenfeld 2584583cd330SHans Rosenfeld iflag = intr_clear(); 2585583cd330SHans Rosenfeld lock_set(&apic_mode_switch_lock); 2586583cd330SHans Rosenfeld if (enter) { 2587583cd330SHans Rosenfeld ASSERT(apic_poweron_cnt >= 0); 2588583cd330SHans Rosenfeld if (apic_poweron_cnt == 0) { 2589583cd330SHans Rosenfeld pops->psm_send_ipi = apic_common_send_ipi; 2590583cd330SHans Rosenfeld send_dirintf = pops->psm_send_ipi; 2591583cd330SHans Rosenfeld } 2592583cd330SHans Rosenfeld apic_poweron_cnt++; 2593583cd330SHans Rosenfeld } else { 2594583cd330SHans Rosenfeld ASSERT(apic_poweron_cnt > 0); 2595583cd330SHans Rosenfeld apic_poweron_cnt--; 2596583cd330SHans Rosenfeld if (apic_poweron_cnt == 0) { 2597583cd330SHans Rosenfeld pops->psm_send_ipi = x2apic_send_ipi; 2598583cd330SHans Rosenfeld send_dirintf = pops->psm_send_ipi; 2599583cd330SHans Rosenfeld } 2600583cd330SHans Rosenfeld } 2601583cd330SHans Rosenfeld lock_clear(&apic_mode_switch_lock); 2602583cd330SHans Rosenfeld intr_restore(iflag); 2603583cd330SHans Rosenfeld } 2604583cd330SHans Rosenfeld 26057ff178cdSJimmy Vetayases /* stub function */ 26067ff178cdSJimmy Vetayases int 26077ff178cdSJimmy Vetayases apix_loaded(void) 26087ff178cdSJimmy Vetayases { 26097ff178cdSJimmy Vetayases return (apix_is_enabled); 26107ff178cdSJimmy Vetayases } 2611