1*993e3fafSRobert Mustacchi /* 2*993e3fafSRobert Mustacchi * Copyright (c) 2014 Martin Pieuchot. All rights reserved. 3*993e3fafSRobert Mustacchi * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4*993e3fafSRobert Mustacchi * Copyright 2016 Joyent, Inc. 5*993e3fafSRobert Mustacchi * 6*993e3fafSRobert Mustacchi * Redistribution and use in source and binary forms, with or without 7*993e3fafSRobert Mustacchi * modification, are permitted provided that the following conditions 8*993e3fafSRobert Mustacchi * are met: 9*993e3fafSRobert Mustacchi * 1. Redistributions of source code must retain the above copyright 10*993e3fafSRobert Mustacchi * notice, this list of conditions and the following disclaimer. 11*993e3fafSRobert Mustacchi * 2. Redistributions in binary form must reproduce the above copyright 12*993e3fafSRobert Mustacchi * notice, this list of conditions and the following disclaimer in the 13*993e3fafSRobert Mustacchi * documentation and/or other materials provided with the distribution. 14*993e3fafSRobert Mustacchi * 15*993e3fafSRobert Mustacchi * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16*993e3fafSRobert Mustacchi * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*993e3fafSRobert Mustacchi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*993e3fafSRobert Mustacchi * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19*993e3fafSRobert Mustacchi * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20*993e3fafSRobert Mustacchi * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21*993e3fafSRobert Mustacchi * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22*993e3fafSRobert Mustacchi * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23*993e3fafSRobert Mustacchi * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24*993e3fafSRobert Mustacchi * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25*993e3fafSRobert Mustacchi * SUCH DAMAGE. 26*993e3fafSRobert Mustacchi */ 27*993e3fafSRobert Mustacchi 28*993e3fafSRobert Mustacchi #ifndef _SYS_USB_HCD_XHCI_XHCIREG_H 29*993e3fafSRobert Mustacchi #define _SYS_USB_HCD_XHCI_XHCIREG_H 30*993e3fafSRobert Mustacchi 31*993e3fafSRobert Mustacchi /* 32*993e3fafSRobert Mustacchi * xHCI Register and Field Definitions 33*993e3fafSRobert Mustacchi */ 34*993e3fafSRobert Mustacchi 35*993e3fafSRobert Mustacchi #ifdef __cplusplus 36*993e3fafSRobert Mustacchi extern "C" { 37*993e3fafSRobert Mustacchi #endif 38*993e3fafSRobert Mustacchi 39*993e3fafSRobert Mustacchi /* 40*993e3fafSRobert Mustacchi * xHCI PCI config registers 41*993e3fafSRobert Mustacchi */ 42*993e3fafSRobert Mustacchi #define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */ 43*993e3fafSRobert Mustacchi #define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */ 44*993e3fafSRobert Mustacchi #define PCI_USB_REV_3_0 0x30 /* USB 3.0 */ 45*993e3fafSRobert Mustacchi #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 46*993e3fafSRobert Mustacchi 47*993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ 48*993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ 49*993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ 50*993e3fafSRobert Mustacchi #define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ 51*993e3fafSRobert Mustacchi 52*993e3fafSRobert Mustacchi /* 53*993e3fafSRobert Mustacchi * xHCI capability registers 54*993e3fafSRobert Mustacchi */ 55*993e3fafSRobert Mustacchi #define XHCI_CAPLENGTH 0x00 /* RO capability */ 56*993e3fafSRobert Mustacchi #define XHCI_RESERVED 0x01 /* Reserved */ 57*993e3fafSRobert Mustacchi #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 58*993e3fafSRobert Mustacchi #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 59*993e3fafSRobert Mustacchi #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 60*993e3fafSRobert Mustacchi 61*993e3fafSRobert Mustacchi /* 62*993e3fafSRobert Mustacchi * Structural Parameters 1 - xHCI 1.1 / 5.3.3 63*993e3fafSRobert Mustacchi */ 64*993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS1 0x04 65*993e3fafSRobert Mustacchi #define XHCI_HCS1_DEVSLOT_MAX(x) ((x) & 0xFF) 66*993e3fafSRobert Mustacchi #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF) 67*993e3fafSRobert Mustacchi #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF) 68*993e3fafSRobert Mustacchi 69*993e3fafSRobert Mustacchi /* 70*993e3fafSRobert Mustacchi * Structural Parameters 2 - xHCI 1.1 / 5.3.4 71*993e3fafSRobert Mustacchi */ 72*993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS2 0x08 73*993e3fafSRobert Mustacchi #define XHCI_HCS2_IST(x) ((x) & 0x7) 74*993e3fafSRobert Mustacchi #define XHCI_HCS2_IST_MICRO(x) (!((x) & 0x8)) 75*993e3fafSRobert Mustacchi #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF) 76*993e3fafSRobert Mustacchi #define XHCI_HCS2_SPR(x) (((x) >> 24) & 0x1) 77*993e3fafSRobert Mustacchi #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3e0) | (((x) >> 27) & 0x1f)) 78*993e3fafSRobert Mustacchi 79*993e3fafSRobert Mustacchi /* 80*993e3fafSRobert Mustacchi * Structural Parameters 3 - xHCI 1.1 / 5.3.5 81*993e3fafSRobert Mustacchi */ 82*993e3fafSRobert Mustacchi #define XHCI_HCSPARAMS3 0x0C 83*993e3fafSRobert Mustacchi #define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF) 84*993e3fafSRobert Mustacchi #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF) 85*993e3fafSRobert Mustacchi 86*993e3fafSRobert Mustacchi /* 87*993e3fafSRobert Mustacchi * Capability Parameters 1 - xHCI 1.1 / 5.3.6 88*993e3fafSRobert Mustacchi */ 89*993e3fafSRobert Mustacchi #define XHCI_HCCPARAMS1 0x10 90*993e3fafSRobert Mustacchi #define XHCI_HCC1_FLAGS_MASK(x) ((x) & 0x7FF) 91*993e3fafSRobert Mustacchi #define XHCI_HCC1_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) 92*993e3fafSRobert Mustacchi #define XHCI_HCC1_XECP(x) (((x) >> 16) & 0xFFFF) 93*993e3fafSRobert Mustacchi 94*993e3fafSRobert Mustacchi /* 95*993e3fafSRobert Mustacchi * Capability Parameters 1 - xHCI 1.1 / 5.3.9 96*993e3fafSRobert Mustacchi */ 97*993e3fafSRobert Mustacchi #define XHCI_HCCPARAMS2 0x1C 98*993e3fafSRobert Mustacchi #define XHCI_HCC2_FLAGS_MASK(x) ((x) & 0x3F) 99*993e3fafSRobert Mustacchi 100*993e3fafSRobert Mustacchi #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 101*993e3fafSRobert Mustacchi #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 102*993e3fafSRobert Mustacchi 103*993e3fafSRobert Mustacchi /* 104*993e3fafSRobert Mustacchi * xHCI operational registers. 105*993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH register 106*993e3fafSRobert Mustacchi */ 107*993e3fafSRobert Mustacchi #define XHCI_USBCMD 0x00 /* XHCI command */ 108*993e3fafSRobert Mustacchi #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 109*993e3fafSRobert Mustacchi #define XHCI_CMD_HCRST 0x00000002 /* RW HC Reset */ 110*993e3fafSRobert Mustacchi #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 111*993e3fafSRobert Mustacchi #define XHCI_CMD_HSEE 0x00000008 /* RW System Error Enable */ 112*993e3fafSRobert Mustacchi #define XHCI_CMD_LHCRST 0x00000080 /* RW Light HC Reset */ 113*993e3fafSRobert Mustacchi #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save */ 114*993e3fafSRobert Mustacchi #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore */ 115*993e3fafSRobert Mustacchi #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 116*993e3fafSRobert Mustacchi #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 117*993e3fafSRobert Mustacchi 118*993e3fafSRobert Mustacchi 119*993e3fafSRobert Mustacchi #define XHCI_USBSTS 0x04 /* XHCI status */ 120*993e3fafSRobert Mustacchi #define XHCI_STS_HCH 0x00000001 /* RO - HC Halted */ 121*993e3fafSRobert Mustacchi #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 122*993e3fafSRobert Mustacchi #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 123*993e3fafSRobert Mustacchi #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 124*993e3fafSRobert Mustacchi #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 125*993e3fafSRobert Mustacchi #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 126*993e3fafSRobert Mustacchi #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 127*993e3fafSRobert Mustacchi #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 128*993e3fafSRobert Mustacchi #define XHCI_STS_HCE 0x00001000 /* RO - HC Error */ 129*993e3fafSRobert Mustacchi 130*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 131*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 132*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 133*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 134*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 135*993e3fafSRobert Mustacchi #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 136*993e3fafSRobert Mustacchi 137*993e3fafSRobert Mustacchi #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 138*993e3fafSRobert Mustacchi #define XHCI_DNCTRL_MASK(n) (1U << (n)) 139*993e3fafSRobert Mustacchi 140*993e3fafSRobert Mustacchi #define XHCI_CRCR 0x18 /* XHCI command ring control */ 141*993e3fafSRobert Mustacchi #define XHCI_CRCR_RCS 0x00000001 /* RW - consumer cycle state */ 142*993e3fafSRobert Mustacchi #define XHCI_CRCR_CS 0x00000002 /* RW - command stop */ 143*993e3fafSRobert Mustacchi #define XHCI_CRCR_CA 0x00000004 /* RW - command abort */ 144*993e3fafSRobert Mustacchi #define XHCI_CRCR_CRR 0x00000008 /* RW - command ring running */ 145*993e3fafSRobert Mustacchi #define XHCI_CRCR_MASK 0x0000000F 146*993e3fafSRobert Mustacchi 147*993e3fafSRobert Mustacchi /* 148*993e3fafSRobert Mustacchi * Device context base address pointer register. 149*993e3fafSRobert Mustacchi */ 150*993e3fafSRobert Mustacchi #define XHCI_DCBAAP 0x30 151*993e3fafSRobert Mustacchi 152*993e3fafSRobert Mustacchi #define XHCI_CONFIG 0x38 153*993e3fafSRobert Mustacchi #define XHCI_CONFIG_SLOTS_MASK 0x000000FF 154*993e3fafSRobert Mustacchi 155*993e3fafSRobert Mustacchi /* 156*993e3fafSRobert Mustacchi * xHCI Port Status Registers and bits. See xHCI 1.1 / 5.4.8. 157*993e3fafSRobert Mustacchi */ 158*993e3fafSRobert Mustacchi #define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */ 159*993e3fafSRobert Mustacchi #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 160*993e3fafSRobert Mustacchi #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 161*993e3fafSRobert Mustacchi #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 162*993e3fafSRobert Mustacchi #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 163*993e3fafSRobert Mustacchi #define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */ 164*993e3fafSRobert Mustacchi #define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */ 165*993e3fafSRobert Mustacchi #define XHCI_PS_PP 0x00000200 /* RW - port power */ 166*993e3fafSRobert Mustacchi #define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */ 167*993e3fafSRobert Mustacchi #define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 168*993e3fafSRobert Mustacchi #define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */ 169*993e3fafSRobert Mustacchi #define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */ 170*993e3fafSRobert Mustacchi #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 171*993e3fafSRobert Mustacchi #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 172*993e3fafSRobert Mustacchi #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 173*993e3fafSRobert Mustacchi #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 174*993e3fafSRobert Mustacchi #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 175*993e3fafSRobert Mustacchi #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 176*993e3fafSRobert Mustacchi #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 177*993e3fafSRobert Mustacchi #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 178*993e3fafSRobert Mustacchi #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 179*993e3fafSRobert Mustacchi #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 180*993e3fafSRobert Mustacchi #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */ 181*993e3fafSRobert Mustacchi #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 182*993e3fafSRobert Mustacchi #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 183*993e3fafSRobert Mustacchi #define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */ 184*993e3fafSRobert Mustacchi #define XHCI_PS_INDPORT(x) ((x) & 0xFF) 185*993e3fafSRobert Mustacchi #define XHCI_PS_INDVAL(x) (((x) & 0xFF00) >> 8) 186*993e3fafSRobert Mustacchi 187*993e3fafSRobert Mustacchi /* 188*993e3fafSRobert Mustacchi * xHCI Port Power Management and Control Register. See xHCI 1.1 / 5.4.9. 189*993e3fafSRobert Mustacchi */ 190*993e3fafSRobert Mustacchi #define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) 191*993e3fafSRobert Mustacchi #define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */ 192*993e3fafSRobert Mustacchi #define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */ 193*993e3fafSRobert Mustacchi #define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */ 194*993e3fafSRobert Mustacchi #define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */ 195*993e3fafSRobert Mustacchi #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 196*993e3fafSRobert Mustacchi #define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 197*993e3fafSRobert Mustacchi #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */ 198*993e3fafSRobert Mustacchi /* RW - host initiated resume durations */ 199*993e3fafSRobert Mustacchi #define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) 200*993e3fafSRobert Mustacchi #define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) 201*993e3fafSRobert Mustacchi #define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */ 202*993e3fafSRobert Mustacchi #define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */ 203*993e3fafSRobert Mustacchi #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 204*993e3fafSRobert Mustacchi #define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* RO - port link info */ 205*993e3fafSRobert Mustacchi #define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errs */ 206*993e3fafSRobert Mustacchi #define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */ 207*993e3fafSRobert Mustacchi 208*993e3fafSRobert Mustacchi /* 209*993e3fafSRobert Mustacchi * xHCI runtime registers - xHCI 1.1 / 5.5. 210*993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers. 211*993e3fafSRobert Mustacchi */ 212*993e3fafSRobert Mustacchi #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 213*993e3fafSRobert Mustacchi #define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF) 214*993e3fafSRobert Mustacchi #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt */ 215*993e3fafSRobert Mustacchi /* management */ 216*993e3fafSRobert Mustacchi #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 217*993e3fafSRobert Mustacchi #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 218*993e3fafSRobert Mustacchi 219*993e3fafSRobert Mustacchi /* 220*993e3fafSRobert Mustacchi * XHCI Interrupt moderation 221*993e3fafSRobert Mustacchi */ 222*993e3fafSRobert Mustacchi #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 223*993e3fafSRobert Mustacchi 224*993e3fafSRobert Mustacchi /* 225*993e3fafSRobert Mustacchi * XHCI event ring segment table size 226*993e3fafSRobert Mustacchi */ 227*993e3fafSRobert Mustacchi #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 228*993e3fafSRobert Mustacchi #define XHCI_ERSTS_MASK 0xffff 229*993e3fafSRobert Mustacchi #define XHCI_ERSTS_SET(x) ((x) & XHCI_ERSTS_MASK) 230*993e3fafSRobert Mustacchi 231*993e3fafSRobert Mustacchi /* 232*993e3fafSRobert Mustacchi * XHCI event ring segment table BA 233*993e3fafSRobert Mustacchi */ 234*993e3fafSRobert Mustacchi #define XHCI_ERSTBA(n) (0x0030 + (0x20 * (n))) 235*993e3fafSRobert Mustacchi 236*993e3fafSRobert Mustacchi /* 237*993e3fafSRobert Mustacchi * XHCI event ring dequeue pointer 238*993e3fafSRobert Mustacchi */ 239*993e3fafSRobert Mustacchi #define XHCI_ERDP(n) (0x0038 + (0x20 * (n))) 240*993e3fafSRobert Mustacchi #define XHCI_ERDP_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */ 241*993e3fafSRobert Mustacchi #define XHCI_ERDP_BUSY 0x00000008 /* RW - event handler busy */ 242*993e3fafSRobert Mustacchi 243*993e3fafSRobert Mustacchi /* 244*993e3fafSRobert Mustacchi * XHCI doorbell registers - xHCI 1.1 / 5.6. 245*993e3fafSRobert Mustacchi * Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers 246*993e3fafSRobert Mustacchi */ 247*993e3fafSRobert Mustacchi #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 248*993e3fafSRobert Mustacchi #define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) 249*993e3fafSRobert Mustacchi #define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) 250*993e3fafSRobert Mustacchi #define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) 251*993e3fafSRobert Mustacchi #define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) 252*993e3fafSRobert Mustacchi 253*993e3fafSRobert Mustacchi /* 254*993e3fafSRobert Mustacchi * XHCI capability IDs - xHCI 1.1 / 7 - Table 146 255*993e3fafSRobert Mustacchi */ 256*993e3fafSRobert Mustacchi #define XHCI_ID_XECP_DONE 0x0000 257*993e3fafSRobert Mustacchi #define XHCI_ID_USB_LEGACY 0x0001 258*993e3fafSRobert Mustacchi #define XHCI_ID_PROTOCOLS 0x0002 259*993e3fafSRobert Mustacchi #define XHCI_ID_POWER_MGMT 0x0003 260*993e3fafSRobert Mustacchi #define XHCI_ID_VIRTUALIZATION 0x0004 261*993e3fafSRobert Mustacchi #define XHCI_ID_MSG_IRQ 0x0005 262*993e3fafSRobert Mustacchi #define XHCI_ID_USB_LOCAL_MEM 0x0006 263*993e3fafSRobert Mustacchi #define XHCI_ID_DEBUG 0x000A 264*993e3fafSRobert Mustacchi #define XHCI_ID_EXT_MSG_IRQ 0x0011 265*993e3fafSRobert Mustacchi 266*993e3fafSRobert Mustacchi #define XHCI_XECP_ID(x) ((x) & 0xFF) 267*993e3fafSRobert Mustacchi #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF) 268*993e3fafSRobert Mustacchi 269*993e3fafSRobert Mustacchi /* 270*993e3fafSRobert Mustacchi * xHCI USB Legacy Support Capability - xHCI 1.1 / 7.1. 271*993e3fafSRobert Mustacchi */ 272*993e3fafSRobert Mustacchi #define XHCI_BIOS_OWNED (1 << 16) 273*993e3fafSRobert Mustacchi #define XHCI_OS_OWNED (1 << 24) 274*993e3fafSRobert Mustacchi 275*993e3fafSRobert Mustacchi /* 276*993e3fafSRobert Mustacchi * These definitions manipulate the generation of SMIs. Note that the contents 277*993e3fafSRobert Mustacchi * of reserved registers are required to be preserved. In addition, Several of 278*993e3fafSRobert Mustacchi * the bits require you to write one to clear. 279*993e3fafSRobert Mustacchi */ 280*993e3fafSRobert Mustacchi #define XHCI_XECP_LEGCTLSTS 0x04 281*993e3fafSRobert Mustacchi #define XHCI_XECP_SMI_MASK (0x7 << 1) + (0xff << 5) + (0x7UL << 17) 282*993e3fafSRobert Mustacchi #define XHCI_XECP_CLEAR_SMI (0x7UL << 29) 283*993e3fafSRobert Mustacchi 284*993e3fafSRobert Mustacchi /* 285*993e3fafSRobert Mustacchi * xHCI Supported Protocol Capability. See xHCI 1.1 / 7.2. 286*993e3fafSRobert Mustacchi */ 287*993e3fafSRobert Mustacchi #define XHCI_XECP_PROT_MAJOR(x) ((x >> 24) & 0xff) 288*993e3fafSRobert Mustacchi #define XHCI_XECP_PROT_MINOR(x) ((x >> 16) & 0xff) 289*993e3fafSRobert Mustacchi #define XHCI_XECP_PROT_PCOUNT(x) ((x >> 8) & 0xff) 290*993e3fafSRobert Mustacchi 291*993e3fafSRobert Mustacchi /* 292*993e3fafSRobert Mustacchi * xHCI Slot Context definitions - xHCI 1.1 / 6.2.2. 293*993e3fafSRobert Mustacchi */ 294*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_ROUTE(x) ((x) & 0xfffff) 295*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_ROUTE(x) ((x) & 0xfffff) 296*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_SPEED(x) (((x) >> 20) & 0xf) 297*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_SPEED(x) (((x) & 0xf) << 20) 298*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_MTT(x) (((x) >> 25) & 0x1) 299*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_MTT(x) (((x) & 0x1) << 25) 300*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_HUB(x) (((x) >> 26) & 0x1) 301*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_HUB(x) (((x) & 0x1) << 26) 302*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_DCI(x) (((x) >> 27) & 0x1f) 303*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_DCI(x) (((x) & 0x1f) << 27) 304*993e3fafSRobert Mustacchi #define XHCI_SCTX_DCI_MASK (0x1fUL << 27) 305*993e3fafSRobert Mustacchi 306*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_MAX_EL(x) ((x) & 0xffff) 307*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_MAX_EL(x) ((x) & 0xffff) 308*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_RHPORT(x) (((x) >> 16) & 0xff) 309*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_RHPORT(x) (((x) & 0xff) << 16) 310*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_NPORTS(x) (((x) >> 24) & 0xff) 311*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_NPORTS(x) (((x) & 0xff) << 24) 312*993e3fafSRobert Mustacchi 313*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_HUB_SID(x) ((x) & 0xff) 314*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_HUB_SID(x) ((x) & 0xff) 315*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_PORT_NUM(x) (((x) >> 8) & 0xff) 316*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_PORT_NUM(x) (((x) & 0xff) << 8) 317*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_TT_THINK_TIME(x) (((x) >> 16) & 0x3) 318*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_TT_THINK_TIME(x) (((x) & 0x3) << 16) 319*993e3fafSRobert Mustacchi #define XHCI_SCTX_SET_IRQ_TARGET(x) (((x) & 0x3ff) << 22) 320*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_IRQ_TARGET(x) (((x) >> 22) & 0x3ff) 321*993e3fafSRobert Mustacchi 322*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_DEV_ADDR(x) ((x) & 0xff) 323*993e3fafSRobert Mustacchi #define XHCI_SCTX_GET_SLOT_STATE(x) (((x) >> 27) & 0x1f) 324*993e3fafSRobert Mustacchi 325*993e3fafSRobert Mustacchi #define XHCI_SLOT_DIS_ENAB 0 326*993e3fafSRobert Mustacchi #define XHCI_SLOT_DEFAULT 1 327*993e3fafSRobert Mustacchi #define XHCI_SLOT_ADDRESSED 2 328*993e3fafSRobert Mustacchi #define XHCI_SLOT_CONFIGURED 3 329*993e3fafSRobert Mustacchi 330*993e3fafSRobert Mustacchi /* 331*993e3fafSRobert Mustacchi * xHCI Slot Context definitions - xHCI 1.1 / 6.2.3. 332*993e3fafSRobert Mustacchi */ 333*993e3fafSRobert Mustacchi #define XHCI_EPCTX_STATE(x) ((x) & 0x7) 334*993e3fafSRobert Mustacchi #define XHCI_EP_DISABLED 0x0 335*993e3fafSRobert Mustacchi #define XHCI_EP_RUNNING 0x1 336*993e3fafSRobert Mustacchi #define XHCI_EP_HALTED 0x2 337*993e3fafSRobert Mustacchi #define XHCI_EP_STOPPED 0x3 338*993e3fafSRobert Mustacchi #define XHCI_EP_ERROR 0x4 339*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MULT(x) (((x) & 0x3) << 8) 340*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MULT(x) (((x) >> 8) & 0x3) 341*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAXP_STREAMS(x) (((x) & 0x1F) << 10) 342*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAXP_STREAMS(x) (((x) >> 10) & 0x1F) 343*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_LSA(x) (((x) & 0x1) << 15) 344*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_LSA(x) (((x) >> 15) & 0x1) 345*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_IVAL(x) (((x) & 0xff) << 16) 346*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_IVAL(x) (((x) >> 16) & 0xFF) 347*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAX_ESIT_HI(x) ((((x) >> 24) & 0xFF) << 16) 348*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAX_ESIT_HI(x) ((((x) >> 16) & 0xFF) << 24) 349*993e3fafSRobert Mustacchi 350*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_CERR(x) (((x) >> 1) & 0x3) 351*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_CERR(x) (((x) & 0x3) << 1) 352*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_EPTYPE(x) (((x) & 0x7) << 3) 353*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_EPTYPE(x) (((x) >> 3) & 0x7) 354*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_HID(x) (((x) & 0x1) << 7) 355*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_HID(x) (((x) >> 7) & 0x1) 356*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MAXB(x) (((x) & 0xff) << 8) 357*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAXB(x) (((x) >> 8) & 0xff) 358*993e3fafSRobert Mustacchi #define XHCI_EPCTX_SET_MPS(x) (((x) & 0xffff) << 16) 359*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MPS(x) (((x) >> 16) & 0xffff) 360*993e3fafSRobert Mustacchi #define XHCI_SPEED_FULL 1 361*993e3fafSRobert Mustacchi #define XHCI_SPEED_LOW 2 362*993e3fafSRobert Mustacchi #define XHCI_SPEED_HIGH 3 363*993e3fafSRobert Mustacchi #define XHCI_SPEED_SUPER 4 364*993e3fafSRobert Mustacchi 365*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_ISOCH_OUT (1) 366*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_BULK_OUT (2) 367*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_INTR_OUT (3) 368*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_CTRL (4) 369*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_ISOCH_IN (5) 370*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_BULK_IN (6) 371*993e3fafSRobert Mustacchi #define XHCI_EPCTX_TYPE_INTR_IN (7) 372*993e3fafSRobert Mustacchi 373*993e3fafSRobert Mustacchi #define XHCI_EPCTX_AVG_TRB_LEN(x) ((x) & 0xffff) 374*993e3fafSRobert Mustacchi #define XHCI_EPCTX_MAX_ESIT_PAYLOAD(x) (((x) & 0xffff) << 16) 375*993e3fafSRobert Mustacchi #define XHCI_EPCTX_GET_MAX_ESIT_PAYLOAD(x) (((x) >> 16) & 0xffff) 376*993e3fafSRobert Mustacchi 377*993e3fafSRobert Mustacchi #define XHCI_INCTX_MASK_DCI(n) (0x1 << (n)) 378*993e3fafSRobert Mustacchi 379*993e3fafSRobert Mustacchi /* 380*993e3fafSRobert Mustacchi * Transfer Request Block definitions. 381*993e3fafSRobert Mustacchi */ 382*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_MASK 0xfc00 383*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE(x) (((x) & XHCI_TRB_TYPE_MASK) >> 10) 384*993e3fafSRobert Mustacchi #define XHCI_TRB_PORTID(x) (((x) & (0xffUL << 24)) >> 24) /* Port ID */ 385*993e3fafSRobert Mustacchi #define XHCI_TRB_MAXSIZE (64 * 1024) 386*993e3fafSRobert Mustacchi 387*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_CODE(x) (((x) >> 24) & 0xff) /* Get TRB code */ 388*993e3fafSRobert Mustacchi #define XHCI_TRB_TDREM(x) (((x) & 0x1f) << 17) /* Set TD remaining len. */ 389*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TDREM(x) (((x) >> 17) & 0x1f) /* Get TD remaining len. */ 390*993e3fafSRobert Mustacchi #define XHCI_TRB_REMAIN(x) ((x) & 0xffffff) /* Remaining length */ 391*993e3fafSRobert Mustacchi #define XHCI_TRB_LEN(x) ((x) & 0x1ffff) /* Transfer length */ 392*993e3fafSRobert Mustacchi #define XHCI_TRB_INTR(x) (((x) & 0x3ff) << 22) /* Set MSI-X target */ 393*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_INTR(x) (((x) >> 22) & 0x3ff) /* Get MSI-X target */ 394*993e3fafSRobert Mustacchi 395*993e3fafSRobert Mustacchi /* 396*993e3fafSRobert Mustacchi * TRB flags that are used between different different TRB types. 397*993e3fafSRobert Mustacchi */ 398*993e3fafSRobert Mustacchi #define XHCI_TRB_CYCLE (1 << 0) /* Enqueue point of xfer ring */ 399*993e3fafSRobert Mustacchi #define XHCI_TRB_ENT (1 << 1) /* Evaluate next TRB */ 400*993e3fafSRobert Mustacchi #define XHCI_TRB_LINKSEG XHCI_TRB_ENT /* Link to next segment */ 401*993e3fafSRobert Mustacchi #define XHCI_TRB_ISP (1 << 2) /* Interrupt on short packet */ 402*993e3fafSRobert Mustacchi #define XHCI_TRB_NOSNOOP (1 << 3) /* PCIe no snoop */ 403*993e3fafSRobert Mustacchi #define XHCI_TRB_CHAIN (1 << 4) /* Chained with next TRB */ 404*993e3fafSRobert Mustacchi #define XHCI_TRB_IOC (1 << 5) /* Interrupt On Completion */ 405*993e3fafSRobert Mustacchi #define XHCI_TRB_IDT (1 << 6) /* Immediate Data */ 406*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TBC(x) (((x) >> 7) & 0x3) /* Get/Set Transfer */ 407*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_TBC(x) (((x) & 0x3) << 7) /* Burst Count */ 408*993e3fafSRobert Mustacchi #define XHCI_TRB_BSR (1 << 9) /* Block Set Address */ 409*993e3fafSRobert Mustacchi #define XHCI_TRB_DCEP (1 << 9) /* Deconfigure endpoint */ 410*993e3fafSRobert Mustacchi #define XHCI_TRB_TSP (1 << 9) /* Transfer State Preserve */ 411*993e3fafSRobert Mustacchi #define XHCI_TRB_BEI (1 << 9) /* Block Event Interrupt */ 412*993e3fafSRobert Mustacchi #define XHCI_TRB_DIR_IN (1 << 16) 413*993e3fafSRobert Mustacchi #define XHCI_TRB_TRT_OUT (2 << 16) 414*993e3fafSRobert Mustacchi #define XHCI_TRB_TRT_IN (3 << 16) 415*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_CYCLE(x) ((x) & 0x1) 416*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_ED(x) (((x) >> 2) & 0x1) 417*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_FLAGS(x) ((x) & 0x1ff) 418*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TYPE(x) (((x) >> 10) & 0x3f) 419*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_EP(x) (((x) >> 16) & 0x1f) 420*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_EP(x) (((x) & 0x1f) << 16) 421*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_STYPE(x) (((x) >> 16) & 0x1f) 422*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_STYPE(x) (((x) & 0x1f) << 16) 423*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_SLOT(x) (((x) >> 24) & 0xff) 424*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_SLOT(x) (((x) & 0xff) << 24) 425*993e3fafSRobert Mustacchi 426*993e3fafSRobert Mustacchi /* 427*993e3fafSRobert Mustacchi * Isochronous specific fields. See xHCI 1.1 / 6.4.1.3. 428*993e3fafSRobert Mustacchi */ 429*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_TLBPC(x) (((x) >> 16) & 0xf) 430*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_TLBPC(x) (((x) & 0xf) << 16) 431*993e3fafSRobert Mustacchi #define XHCI_TRB_GET_FRAME(x) (((x) >> 20) & 0x7ff) 432*993e3fafSRobert Mustacchi #define XHCI_TRB_SET_FRAME(x) (((x) & 0x7ff) << 20) 433*993e3fafSRobert Mustacchi #define XHCI_TRB_SIA (1UL << 31) /* Start Isoch ASAP */ 434*993e3fafSRobert Mustacchi 435*993e3fafSRobert Mustacchi /* 436*993e3fafSRobert Mustacchi * TRB Types. See xHCI 1.1 / 6.4.6. 437*993e3fafSRobert Mustacchi */ 438*993e3fafSRobert Mustacchi 439*993e3fafSRobert Mustacchi /* Transfer Ring Types */ 440*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_NORMAL (1 << 10) 441*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_SETUP (2 << 10) 442*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_DATA (3 << 10) 443*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_STATUS (4 << 10) 444*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_ISOCH (5 << 10) 445*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_LINK (6 << 10) 446*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_EVENT (7 << 10) 447*993e3fafSRobert Mustacchi #define XHCI_TRB_TYPE_NOOP (8 << 10) 448*993e3fafSRobert Mustacchi 449*993e3fafSRobert Mustacchi /* Command ring Types */ 450*993e3fafSRobert Mustacchi #define XHCI_CMD_ENABLE_SLOT (9 << 10) 451*993e3fafSRobert Mustacchi #define XHCI_CMD_DISABLE_SLOT (10 << 10) 452*993e3fafSRobert Mustacchi #define XHCI_CMD_ADDRESS_DEVICE (11 << 10) 453*993e3fafSRobert Mustacchi #define XHCI_CMD_CONFIG_EP (12 << 10) 454*993e3fafSRobert Mustacchi #define XHCI_CMD_EVAL_CTX (13 << 10) 455*993e3fafSRobert Mustacchi #define XHCI_CMD_RESET_EP (14 << 10) 456*993e3fafSRobert Mustacchi #define XHCI_CMD_STOP_EP (15 << 10) 457*993e3fafSRobert Mustacchi #define XHCI_CMD_SET_TR_DEQ (16 << 10) 458*993e3fafSRobert Mustacchi #define XHCI_CMD_RESET_DEV (17 << 10) 459*993e3fafSRobert Mustacchi #define XHCI_CMD_FEVENT (18 << 10) 460*993e3fafSRobert Mustacchi #define XHCI_CMD_NEG_BW (19 << 10) 461*993e3fafSRobert Mustacchi #define XHCI_CMD_SET_LT (20 << 10) 462*993e3fafSRobert Mustacchi #define XHCI_CMD_GET_BW (21 << 10) 463*993e3fafSRobert Mustacchi #define XHCI_CMD_FHEADER (22 << 10) 464*993e3fafSRobert Mustacchi #define XHCI_CMD_NOOP (23 << 10) 465*993e3fafSRobert Mustacchi 466*993e3fafSRobert Mustacchi /* Event ring Types */ 467*993e3fafSRobert Mustacchi #define XHCI_EVT_XFER (32 << 10) 468*993e3fafSRobert Mustacchi #define XHCI_EVT_CMD_COMPLETE (33 << 10) 469*993e3fafSRobert Mustacchi #define XHCI_EVT_PORT_CHANGE (34 << 10) 470*993e3fafSRobert Mustacchi #define XHCI_EVT_BW_REQUEST (35 << 10) 471*993e3fafSRobert Mustacchi #define XHCI_EVT_DOORBELL (36 << 10) 472*993e3fafSRobert Mustacchi #define XHCI_EVT_HOST_CTRL (37 << 10) 473*993e3fafSRobert Mustacchi #define XHCI_EVT_DEVICE_NOTIFY (38 << 10) 474*993e3fafSRobert Mustacchi #define XHCI_EVT_MFINDEX_WRAP (39 << 10) 475*993e3fafSRobert Mustacchi 476*993e3fafSRobert Mustacchi #define XHCI_RING_TYPE_SHIFT(x) ((x) << 10) 477*993e3fafSRobert Mustacchi 478*993e3fafSRobert Mustacchi /* 479*993e3fafSRobert Mustacchi * TRB Completion Codes. See xHCI 1.1 / 6.4.5. 480*993e3fafSRobert Mustacchi */ 481*993e3fafSRobert Mustacchi #define XHCI_CODE_INVALID 0 /* Producer didn't update the code. */ 482*993e3fafSRobert Mustacchi #define XHCI_CODE_SUCCESS 1 /* Badaboum, plaf, plouf, yeepee! */ 483*993e3fafSRobert Mustacchi #define XHCI_CODE_DATA_BUF 2 /* Overrun or underrun */ 484*993e3fafSRobert Mustacchi #define XHCI_CODE_BABBLE 3 /* Device is "babbling" */ 485*993e3fafSRobert Mustacchi #define XHCI_CODE_TXERR 4 /* USB Transaction error */ 486*993e3fafSRobert Mustacchi #define XHCI_CODE_TRB 5 /* Invalid TRB */ 487*993e3fafSRobert Mustacchi #define XHCI_CODE_STALL 6 /* Stall condition */ 488*993e3fafSRobert Mustacchi #define XHCI_CODE_RESOURCE 7 /* No resource available for the cmd */ 489*993e3fafSRobert Mustacchi #define XHCI_CODE_BANDWIDTH 8 /* Not enough bandwidth for the cmd */ 490*993e3fafSRobert Mustacchi #define XHCI_CODE_NO_SLOTS 9 /* MaxSlots limit reached */ 491*993e3fafSRobert Mustacchi #define XHCI_CODE_STREAM_TYPE 10 /* Stream Context Type value detected */ 492*993e3fafSRobert Mustacchi #define XHCI_CODE_SLOT_NOT_ON 11 /* Related device slot is disabled */ 493*993e3fafSRobert Mustacchi #define XHCI_CODE_ENDP_NOT_ON 12 /* Related enpoint is disabled */ 494*993e3fafSRobert Mustacchi #define XHCI_CODE_SHORT_XFER 13 /* Short packet */ 495*993e3fafSRobert Mustacchi #define XHCI_CODE_RING_UNDERRUN 14 /* Empty ring when transmitting isoc */ 496*993e3fafSRobert Mustacchi #define XHCI_CODE_RING_OVERRUN 15 /* Empty ring when receiving isoc */ 497*993e3fafSRobert Mustacchi #define XHCI_CODE_VF_RING_FULL 16 /* VF's event ring is full */ 498*993e3fafSRobert Mustacchi #define XHCI_CODE_PARAMETER 17 /* Context parameter is invalid */ 499*993e3fafSRobert Mustacchi #define XHCI_CODE_BW_OVERRUN 18 /* TD exceeds the bandwidth */ 500*993e3fafSRobert Mustacchi #define XHCI_CODE_CONTEXT_STATE 19 /* Transition from illegal ctx state */ 501*993e3fafSRobert Mustacchi #define XHCI_CODE_NO_PING_RESP 20 /* Unable to complete periodic xfer */ 502*993e3fafSRobert Mustacchi #define XHCI_CODE_EV_RING_FULL 21 /* Unable to post an evt to the ring */ 503*993e3fafSRobert Mustacchi #define XHCI_CODE_INCOMPAT_DEV 22 /* Device cannot be accessed */ 504*993e3fafSRobert Mustacchi #define XHCI_CODE_MISSED_SRV 23 /* Unable to service isoc EP in ESIT */ 505*993e3fafSRobert Mustacchi #define XHCI_CODE_CMD_RING_STOP 24 /* Command Stop (CS) requested */ 506*993e3fafSRobert Mustacchi #define XHCI_CODE_CMD_ABORTED 25 /* Command Abort (CA) operation */ 507*993e3fafSRobert Mustacchi #define XHCI_CODE_XFER_STOPPED 26 /* xfer terminated by a stop endpoint */ 508*993e3fafSRobert Mustacchi #define XHCI_CODE_XFER_STOPINV 27 /* TRB transfer length invalid */ 509*993e3fafSRobert Mustacchi #define XHCI_CODE_XFER_STOPSHORT 28 /* Stopped before end of TD */ 510*993e3fafSRobert Mustacchi #define XHCI_CODE_MELAT 29 /* Max Exit Latency too large */ 511*993e3fafSRobert Mustacchi #define XHCI_CODE_RESERVED 30 512*993e3fafSRobert Mustacchi #define XHCI_CODE_ISOC_OVERRUN 31 /* IN data buffer < Max ESIT Payload */ 513*993e3fafSRobert Mustacchi #define XHCI_CODE_EVENT_LOST 32 /* Internal overrun - impl. specific */ 514*993e3fafSRobert Mustacchi #define XHCI_CODE_UNDEFINED 33 /* Fatal error - impl. specific */ 515*993e3fafSRobert Mustacchi #define XHCI_CODE_INVALID_SID 34 /* Invalid stream ID received */ 516*993e3fafSRobert Mustacchi #define XHCI_CODE_SEC_BW 35 /* Cannot alloc secondary BW Domain */ 517*993e3fafSRobert Mustacchi #define XHCI_CODE_SPLITERR 36 /* USB2 split transaction */ 518*993e3fafSRobert Mustacchi 519*993e3fafSRobert Mustacchi #ifdef __cplusplus 520*993e3fafSRobert Mustacchi } 521*993e3fafSRobert Mustacchi #endif 522*993e3fafSRobert Mustacchi 523*993e3fafSRobert Mustacchi #endif /* _SYS_USB_HCD_XHCI_XHCIREG_H */ 524