xref: /illumos-gate/usr/src/uts/common/sys/usb/hcd/xhci/xhci.h (revision ec82ef79)
1993e3fafSRobert Mustacchi /*
2993e3fafSRobert Mustacchi  * This file and its contents are supplied under the terms of the
3993e3fafSRobert Mustacchi  * Common Development and Distribution License ("CDDL"), version 1.0.
4993e3fafSRobert Mustacchi  * You may only use this file in accordance with the terms of version
5993e3fafSRobert Mustacchi  * 1.0 of the CDDL.
6993e3fafSRobert Mustacchi  *
7993e3fafSRobert Mustacchi  * A full copy of the text of the CDDL should have accompanied this
8993e3fafSRobert Mustacchi  * source.  A copy of the CDDL is also available via the Internet at
9993e3fafSRobert Mustacchi  * http://www.illumos.org/license/CDDL.
10993e3fafSRobert Mustacchi  */
11993e3fafSRobert Mustacchi 
12993e3fafSRobert Mustacchi /*
132aba3acdSRobert Mustacchi  * Copyright (c) 2018, Joyent, Inc.
14*ec82ef79SMatthias Scheler  * Copyright (c) 2019 by Western Digital Corporation
15993e3fafSRobert Mustacchi  */
16993e3fafSRobert Mustacchi 
17993e3fafSRobert Mustacchi #ifndef _SYS_USB_XHCI_XHCI_H
18993e3fafSRobert Mustacchi #define	_SYS_USB_XHCI_XHCI_H
19993e3fafSRobert Mustacchi 
20993e3fafSRobert Mustacchi /*
21993e3fafSRobert Mustacchi  * Extensible Host Controller Interface (xHCI) USB Driver
22993e3fafSRobert Mustacchi  */
23993e3fafSRobert Mustacchi 
24993e3fafSRobert Mustacchi #include <sys/conf.h>
25993e3fafSRobert Mustacchi #include <sys/ddi.h>
26993e3fafSRobert Mustacchi #include <sys/sunddi.h>
27993e3fafSRobert Mustacchi #include <sys/taskq_impl.h>
28993e3fafSRobert Mustacchi #include <sys/sysmacros.h>
29993e3fafSRobert Mustacchi #include <sys/usb/hcd/xhci/xhcireg.h>
30993e3fafSRobert Mustacchi 
31993e3fafSRobert Mustacchi #include <sys/usb/usba.h>
32993e3fafSRobert Mustacchi #include <sys/usb/usba/hcdi.h>
33993e3fafSRobert Mustacchi #include <sys/usb/hubd/hub.h>
34993e3fafSRobert Mustacchi #include <sys/usb/usba/hubdi.h>
35993e3fafSRobert Mustacchi #include <sys/usb/hubd/hubdvar.h>
36993e3fafSRobert Mustacchi 
37993e3fafSRobert Mustacchi 
38993e3fafSRobert Mustacchi #ifdef __cplusplus
39993e3fafSRobert Mustacchi extern "C" {
40993e3fafSRobert Mustacchi #endif
41993e3fafSRobert Mustacchi 
42993e3fafSRobert Mustacchi /*
43993e3fafSRobert Mustacchi  * The base segment for DMA attributes was determined to be 4k based on xHCI 1.1
44993e3fafSRobert Mustacchi  * / table 54: Data Structure Max Size, Boundary, and Alignment Requirement
45993e3fafSRobert Mustacchi  * Summary.  This indicates that the required alignment for most things is
46993e3fafSRobert Mustacchi  * PAGESIZE, which in our current implementation is required to be 4K. We
47993e3fafSRobert Mustacchi  * provide the ring segment value below for the things which need 64K alignment
48993e3fafSRobert Mustacchi  *
49993e3fafSRobert Mustacchi  * Similarly, in the same table, the maximum required alignment is 64 bytes,
50993e3fafSRobert Mustacchi  * hence we use that for everything.
51993e3fafSRobert Mustacchi  *
52993e3fafSRobert Mustacchi  * Next is the scatter/gather lengths. For most of the data structures, we only
53993e3fafSRobert Mustacchi  * want to have a single SGL entry, e.g. just a simple flat mapping. For many of
54993e3fafSRobert Mustacchi  * our transfers, we use the same logic to simplify the implementation of the
55993e3fafSRobert Mustacchi  * driver. However, for bulk transfers, which are the largest by far, we want to
56993e3fafSRobert Mustacchi  * be able to leverage SGLs to give us more DMA flexibility.
57993e3fafSRobert Mustacchi  *
58993e3fafSRobert Mustacchi  * We can transfer up to 64K in one transfer request block (TRB) which
59993e3fafSRobert Mustacchi  * corresponds to a single SGL entry. Each ring we create is a single page in
602aba3acdSRobert Mustacchi  * size and will support at most 256 TRBs. To try and give the operating system
612aba3acdSRobert Mustacchi  * flexibility when allocating DMA transfers, we've opted to allow up to 63
622aba3acdSRobert Mustacchi  * SGLs. Because there isn't a good way to support DMA windows with the xHCI
632aba3acdSRobert Mustacchi  * controller design, if this number is too small then DMA allocations and
642aba3acdSRobert Mustacchi  * binding might fail. If the DMA binding fails, the transfer will fail.
652aba3acdSRobert Mustacchi  *
662aba3acdSRobert Mustacchi  * The reason that we use 63 SGLs and not the expected 64 is that we always need
672aba3acdSRobert Mustacchi  * to allocate an additional TRB for the event data. This leaves us with a
682aba3acdSRobert Mustacchi  * nicely divisible number of entries.
692aba3acdSRobert Mustacchi  *
702aba3acdSRobert Mustacchi  * The final piece of this is the maximum sized transfer that the driver
712aba3acdSRobert Mustacchi  * advertises to the broader framework. This is currently sized at 512 KiB. For
722aba3acdSRobert Mustacchi  * reference the ehci driver sized this value at 640 KiB. It's important to
732aba3acdSRobert Mustacchi  * understand that this isn't reflected in the DMA attribute limitation, because
742aba3acdSRobert Mustacchi  * it's not an attribute of the hardware. Experimentally, this has proven to be
752aba3acdSRobert Mustacchi  * sufficient for most of the drivers that we support today. When considering
762aba3acdSRobert Mustacchi  * increasing this number, please note the impact that might have on the
772aba3acdSRobert Mustacchi  * required number of DMA SGL entries required to satisfy the allocation.
782aba3acdSRobert Mustacchi  *
792aba3acdSRobert Mustacchi  * The value of 512 KiB was originally based on the number of SGLs we supported
802aba3acdSRobert Mustacchi  * multiplied by the maximum transfer size. The original number of
812aba3acdSRobert Mustacchi  * XHCI_TRANSFER_DMA_SGL was 8. The 512 KiB value was based upon taking the
822aba3acdSRobert Mustacchi  * number of SGLs and assuming that each TRB used its maximum transfer size of
832aba3acdSRobert Mustacchi  * 64 KiB.
84993e3fafSRobert Mustacchi  */
852aba3acdSRobert Mustacchi #define	XHCI_TRB_MAX_TRANSFER	65536	/* 64 KiB */
86993e3fafSRobert Mustacchi #define	XHCI_DMA_ALIGN		64
87993e3fafSRobert Mustacchi #define	XHCI_DEF_DMA_SGL	1
882aba3acdSRobert Mustacchi #define	XHCI_TRANSFER_DMA_SGL	63
892aba3acdSRobert Mustacchi #define	XHCI_MAX_TRANSFER	524288	/* 512 KiB */
90993e3fafSRobert Mustacchi 
91993e3fafSRobert Mustacchi /*
92993e3fafSRobert Mustacchi  * Properties and values for rerouting ehci ports to xhci.
93993e3fafSRobert Mustacchi  */
94993e3fafSRobert Mustacchi #define	XHCI_PROP_REROUTE_DISABLE	0
95993e3fafSRobert Mustacchi #define	XHCI_PROP_REROUTE_DEFAULT	1
96993e3fafSRobert Mustacchi 
97993e3fafSRobert Mustacchi /*
98993e3fafSRobert Mustacchi  * This number is a bit made up. Truthfully, the API here isn't the most useful
99993e3fafSRobert Mustacchi  * for what we need to define as it should really be based on the endpoint that
100993e3fafSRobert Mustacchi  * we're interested in rather than the device as a whole.
101993e3fafSRobert Mustacchi  *
102993e3fafSRobert Mustacchi  * We're basically being asked how many TRBs we're willing to schedule in one
103993e3fafSRobert Mustacchi  * go. There's no great way to come up with this number, so we basically are
104993e3fafSRobert Mustacchi  * making up something such that we use up a good portion of a ring, but not too
105993e3fafSRobert Mustacchi  * much of it.
106993e3fafSRobert Mustacchi  */
107993e3fafSRobert Mustacchi #define	XHCI_ISOC_MAX_TRB	64
108993e3fafSRobert Mustacchi 
109993e3fafSRobert Mustacchi #ifdef	DEBUG
110993e3fafSRobert Mustacchi #define	XHCI_DMA_SYNC(dma, flag)	VERIFY0(ddi_dma_sync( \
111993e3fafSRobert Mustacchi 					    (dma).xdb_dma_handle, 0, 0, \
112993e3fafSRobert Mustacchi 					    (flag)))
113993e3fafSRobert Mustacchi #else
114993e3fafSRobert Mustacchi #define	XHCI_DMA_SYNC(dma, flag)	((void) ddi_dma_sync( \
115993e3fafSRobert Mustacchi 					    (dma).xdb_dma_handle, 0, 0, \
116993e3fafSRobert Mustacchi 					    (flag)))
117993e3fafSRobert Mustacchi #endif
118993e3fafSRobert Mustacchi 
1192aba3acdSRobert Mustacchi /*
1202aba3acdSRobert Mustacchi  * TRBs need to indicate the number of remaining USB packets in the overall
1212aba3acdSRobert Mustacchi  * transfer. This is a 5-bit value, which means that the maximum value we can
1222aba3acdSRobert Mustacchi  * store in that TRD field is 31.
1232aba3acdSRobert Mustacchi  */
1242aba3acdSRobert Mustacchi #define	XHCI_MAX_TDSIZE		31
1252aba3acdSRobert Mustacchi 
126993e3fafSRobert Mustacchi /*
127993e3fafSRobert Mustacchi  * This defines a time in 2-ms ticks that is required to wait for the controller
128993e3fafSRobert Mustacchi  * to be ready to go. Section 5.4.8 of the XHCI specification in the description
129993e3fafSRobert Mustacchi  * of the PORTSC register indicates that the upper bound is 20 ms. Therefore the
130993e3fafSRobert Mustacchi  * number of ticks is 10.
131993e3fafSRobert Mustacchi  */
132993e3fafSRobert Mustacchi #define	XHCI_POWER_GOOD	10
133993e3fafSRobert Mustacchi 
134993e3fafSRobert Mustacchi /*
135993e3fafSRobert Mustacchi  * Definitions to determine the default number of interrupts. Note that we only
136993e3fafSRobert Mustacchi  * bother with a single interrupt at this time, though we've arranged the driver
137993e3fafSRobert Mustacchi  * to make it possible to request more if, for some unlikely reason, it becomes
138993e3fafSRobert Mustacchi  * necessary.
139993e3fafSRobert Mustacchi  */
140993e3fafSRobert Mustacchi #define	XHCI_NINTR	1
141993e3fafSRobert Mustacchi 
142993e3fafSRobert Mustacchi /*
143993e3fafSRobert Mustacchi  * Default interrupt modulation value. This enables us to have 4000 interrupts /
144993e3fafSRobert Mustacchi  * second. This is supposed to be the default value of the controller. See xHCI
145993e3fafSRobert Mustacchi  * 1.1 / 4.17.2 for more information.
146993e3fafSRobert Mustacchi  */
1472aba3acdSRobert Mustacchi #define	XHCI_IMOD_DEFAULT	0x000003F8U
148993e3fafSRobert Mustacchi 
149993e3fafSRobert Mustacchi /*
150993e3fafSRobert Mustacchi  * Definitions that surround the default values used in various contexts. These
151993e3fafSRobert Mustacchi  * come from various parts of the xHCI specification. In general, see xHCI 1.1 /
152993e3fafSRobert Mustacchi  * 4.8.2. Note that the MPS_MASK is used for ISOCH and INTR endpoints which have
153993e3fafSRobert Mustacchi  * different sizes.
154993e3fafSRobert Mustacchi  *
155993e3fafSRobert Mustacchi  * The burst member is a bit more complicated. By default for USB 2 devices, it
156993e3fafSRobert Mustacchi  * only matters for ISOCH and INTR endpoints and so we use the macros below to
157993e3fafSRobert Mustacchi  * pull it out of the endpoint description's max packet field. For USB 3, it
158993e3fafSRobert Mustacchi  * matters for non-control endpoints. However, it comes out of a companion
159993e3fafSRobert Mustacchi  * description.
160993e3fafSRobert Mustacchi  *
161993e3fafSRobert Mustacchi  * By default the mult member is zero for all cases except for super speed
162993e3fafSRobert Mustacchi  * ISOCH endpoints, where it comes from the companion descriptor.
163993e3fafSRobert Mustacchi  */
164993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_DEF_CERR		3
165993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_ISOCH_CERR		0
166993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_MPS_MASK		0x07ff
167993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_BURST_MASK		0x1800
168993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_BURST_SHIFT	11
169993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_DEF_MULT		0
170993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_DEF_MAX_ESIT	0
171993e3fafSRobert Mustacchi #define	XHCI_CONTEXT_DEF_CTRL_ATL	8
172993e3fafSRobert Mustacchi 
173993e3fafSRobert Mustacchi /*
174993e3fafSRobert Mustacchi  * This number represents the number of transfers that we'll set up for a given
175993e3fafSRobert Mustacchi  * interrupt transfer. Note that the idea here is that we'll want to allocate a
176993e3fafSRobert Mustacchi  * certain number of transfers to basically ensure that we'll always be able to
177993e3fafSRobert Mustacchi  * have a transfer available, even if the system is a bit caught up in trying to
178993e3fafSRobert Mustacchi  * process it and for some reason we can't fire the interrupt. As such, we
179993e3fafSRobert Mustacchi  * basically want to have enough available that at the fastest interval (125 us)
180993e3fafSRobert Mustacchi  * that we have enough. So in this case we choose 8, with the assumption that we
181993e3fafSRobert Mustacchi  * should be able to process at least one in a given millisecond. Note that this
182993e3fafSRobert Mustacchi  * is not based in fact and is really just as much a guess and a hope.
183993e3fafSRobert Mustacchi  *
184993e3fafSRobert Mustacchi  * While we could then use less resources for other interrupt transfers that are
185993e3fafSRobert Mustacchi  * slower, starting with uniform resource usage will make things a bit easier.
186993e3fafSRobert Mustacchi  */
187993e3fafSRobert Mustacchi #define	XHCI_INTR_IN_NTRANSFERS	8
188993e3fafSRobert Mustacchi 
189993e3fafSRobert Mustacchi /*
190993e3fafSRobert Mustacchi  * This number represents the number of xhci_transfer_t structures that we'll
191993e3fafSRobert Mustacchi  * set up for a given isochronous transfer polling request. A given isochronous
192993e3fafSRobert Mustacchi  * transfer may actually have multiple units of time associated with it. As
193993e3fafSRobert Mustacchi  * such, we basically want to treat this like a case of classic double
194993e3fafSRobert Mustacchi  * buffering. We have one ready to go while the other is being filled up. This
195993e3fafSRobert Mustacchi  * will compensate for additional latency in the system. This is smaller than
196993e3fafSRobert Mustacchi  * the Interrupt IN transfer case above as many callers may ask for multiple
197993e3fafSRobert Mustacchi  * intervals in a single request.
198993e3fafSRobert Mustacchi  */
199993e3fafSRobert Mustacchi #define	XHCI_ISOC_IN_NTRANSFERS	2
200993e3fafSRobert Mustacchi 
201993e3fafSRobert Mustacchi #define	XHCI_PERIODIC_IN_NTRANSFERS					\
203993e3fafSRobert Mustacchi 
204993e3fafSRobert Mustacchi /*
205993e3fafSRobert Mustacchi  * Mask for a route string which is a 20-bit value.
206993e3fafSRobert Mustacchi  */
207993e3fafSRobert Mustacchi #define	XHCI_ROUTE_MASK(x)	((x) & 0xfffff)
208993e3fafSRobert Mustacchi 
209993e3fafSRobert Mustacchi /*
210993e3fafSRobert Mustacchi  * This is the default tick that we use for timeouts while endpoints have
211993e3fafSRobert Mustacchi  * outstanding, active, non-periodic transfers. We choose one second as the USBA
212993e3fafSRobert Mustacchi  * specifies timeouts in units of seconds. Note that this is in microseconds, so
213993e3fafSRobert Mustacchi  * it can be fed into drv_usectohz().
214993e3fafSRobert Mustacchi  */
215993e3fafSRobert Mustacchi #define	XHCI_TICK_TIMEOUT_US	(MICROSEC)
216993e3fafSRobert Mustacchi 
217993e3fafSRobert Mustacchi /*
218993e3fafSRobert Mustacchi  * Set of bits that we need one of to indicate that this port has something
219993e3fafSRobert Mustacchi  * interesting on it.
220993e3fafSRobert Mustacchi  */
221993e3fafSRobert Mustacchi #define	XHCI_HUB_INTR_CHANGE_MASK	(XHCI_PS_CSC | XHCI_PS_PEC | \
222993e3fafSRobert Mustacchi     XHCI_PS_WRC | XHCI_PS_OCC | XHCI_PS_PRC | XHCI_PS_PLC | XHCI_PS_CEC)
223993e3fafSRobert Mustacchi 
224993e3fafSRobert Mustacchi /*
225993e3fafSRobert Mustacchi  * These represent known issues with various xHCI controllers.
226993e3fafSRobert Mustacchi  *
2272aba3acdSRobert Mustacchi  *	XHCI_QUIRK_NO_MSI	MSI support on this controller is known to be
2282aba3acdSRobert Mustacchi  *				broken.
229993e3fafSRobert Mustacchi  *
2302aba3acdSRobert Mustacchi  *	XHCI_QUIRK_32_ONLY	Only use 32-bit DMA addreses with this
2312aba3acdSRobert Mustacchi  *				controller.
232993e3fafSRobert Mustacchi  *
2332aba3acdSRobert Mustacchi  *	XHCI_QUIRK_INTC_EHCI	This is an Intel platform which supports
2342aba3acdSRobert Mustacchi  *				rerouting ports between EHCI and xHCI
2352aba3acdSRobert Mustacchi  *				controllers on the platform.
236993e3fafSRobert Mustacchi  */
237993e3fafSRobert Mustacchi typedef enum xhci_quirk {
238993e3fafSRobert Mustacchi 	XHCI_QUIRK_NO_MSI	= 0x01,
239993e3fafSRobert Mustacchi 	XHCI_QUIRK_32_ONLY	= 0x02,
240993e3fafSRobert Mustacchi 	XHCI_QUIRK_INTC_EHCI	= 0x04
241993e3fafSRobert Mustacchi } xhci_quirk_t;
242993e3fafSRobert Mustacchi 
243993e3fafSRobert Mustacchi /*
244993e3fafSRobert Mustacchi  * xHCI capability parameter flags. These are documented in xHCI 1.1 / 5.3.6.
245993e3fafSRobert Mustacchi  */
246993e3fafSRobert Mustacchi typedef enum xhci_cap_flags {
2472aba3acdSRobert Mustacchi 	XCAP_AC64	= 0x001,
248993e3fafSRobert Mustacchi 	XCAP_BNC	= 0x002,
249993e3fafSRobert Mustacchi 	XCAP_CSZ	= 0x004,
250993e3fafSRobert Mustacchi 	XCAP_PPC	= 0x008,
251993e3fafSRobert Mustacchi 	XCAP_PIND	= 0x010,
252993e3fafSRobert Mustacchi 	XCAP_LHRC	= 0x020,
253993e3fafSRobert Mustacchi 	XCAP_LTC	= 0x040,
254993e3fafSRobert Mustacchi 	XCAP_NSS	= 0x080,
255993e3fafSRobert Mustacchi 	XCAP_PAE	= 0x100,
256993e3fafSRobert Mustacchi 	XCAP_SPC	= 0x200,
257993e3fafSRobert Mustacchi 	XCAP_SEC	= 0x400,
258993e3fafSRobert Mustacchi 	XCAP_CFC	= 0x800
259993e3fafSRobert Mustacchi } xchi_cap_flags_t;
260993e3fafSRobert Mustacchi 
261993e3fafSRobert Mustacchi /*
262993e3fafSRobert Mustacchi  * Second set of capabilities, these are documented in xHCI 1.1 / 5.3.9.
263993e3fafSRobert Mustacchi  */
264993e3fafSRobert Mustacchi typedef enum xhci_cap2_flags {
265993e3fafSRobert Mustacchi 	XCAP2_U3C	= 0x01,
266993e3fafSRobert Mustacchi 	XCAP2_CMC	= 0x02,
267993e3fafSRobert Mustacchi 	XCAP2_FMC	= 0x04,
268993e3fafSRobert Mustacchi 	XCAP2_CTC	= 0x08,
269993e3fafSRobert Mustacchi 	XCAP2_LEC	= 0x10,
270993e3fafSRobert Mustacchi 	XCAP2_CIC	= 0x20
271993e3fafSRobert Mustacchi } xhci_cap2_flags_t;
272993e3fafSRobert Mustacchi 
273993e3fafSRobert Mustacchi /*
274993e3fafSRobert Mustacchi  * These represent and store the various capability registers that we'll need to
275993e3fafSRobert Mustacchi  * use. In addition, we stash a few other versioning related bits here. Note
276993e3fafSRobert Mustacchi  * that we cache more information than we might need so that we have it for
277993e3fafSRobert Mustacchi  * debugging purposes.
278993e3fafSRobert Mustacchi  */
279993e3fafSRobert Mustacchi typedef struct xhci_capability {
280993e3fafSRobert Mustacchi 	uint8_t			xcap_usb_vers;
281993e3fafSRobert Mustacchi 	uint16_t		xcap_hci_vers;
282993e3fafSRobert Mustacchi 	uint32_t		xcap_pagesize;
283993e3fafSRobert Mustacchi 	uint8_t			xcap_max_slots;
284993e3fafSRobert Mustacchi 	uint16_t		xcap_max_intrs;
285993e3fafSRobert Mustacchi 	uint8_t			xcap_max_ports;
286993e3fafSRobert Mustacchi 	boolean_t		xcap_ist_micro;
287993e3fafSRobert Mustacchi 	uint8_t			xcap_ist;
288993e3fafSRobert Mustacchi 	uint16_t		xcap_max_esrt;
289993e3fafSRobert Mustacchi 	boolean_t		xcap_scratch_restore;
290993e3fafSRobert Mustacchi 	uint16_t		xcap_max_scratch;
291993e3fafSRobert Mustacchi 	uint8_t			xcap_u1_lat;
292993e3fafSRobert Mustacchi 	uint16_t		xcap_u2_lat;
293993e3fafSRobert Mustacchi 	xchi_cap_flags_t	xcap_flags;
294993e3fafSRobert Mustacchi 	uint8_t			xcap_max_psa;
295993e3fafSRobert Mustacchi 	uint16_t		xcap_xecp_off;
296993e3fafSRobert Mustacchi 	xhci_cap2_flags_t	xcap_flags2;
297993e3fafSRobert Mustacchi 	int			xcap_intr_types;
298993e3fafSRobert Mustacchi } xhci_capability_t;
299993e3fafSRobert Mustacchi 
300993e3fafSRobert Mustacchi /*
301993e3fafSRobert Mustacchi  * This represents a single logical DMA allocation. For the vast majority of
302993e3fafSRobert Mustacchi  * non-transfer cases, it only represents a single DMA buffer and not a
303993e3fafSRobert Mustacchi  * scatter-gather list.
304993e3fafSRobert Mustacchi  */
305993e3fafSRobert Mustacchi typedef struct xhci_dma_buffer {
306993e3fafSRobert Mustacchi 	caddr_t			xdb_va;		/* Buffer VA */
307993e3fafSRobert Mustacchi 	size_t			xdb_len;	/* Buffer logical len */
308993e3fafSRobert Mustacchi 	ddi_acc_handle_t	xdb_acc_handle;	/* Access handle */
309993e3fafSRobert Mustacchi 	ddi_dma_handle_t	xdb_dma_handle;	/* DMA handle */
310993e3fafSRobert Mustacchi 	int			xdb_ncookies;	/* Number of actual cookies */
311993e3fafSRobert Mustacchi 	ddi_dma_cookie_t	xdb_cookies[XHCI_TRANSFER_DMA_SGL];
312993e3fafSRobert Mustacchi } xhci_dma_buffer_t;
313993e3fafSRobert Mustacchi 
314993e3fafSRobert Mustacchi /*
315993e3fafSRobert Mustacchi  * This is a single transfer descriptor. It's packed to match the hardware
316993e3fafSRobert Mustacchi  * layout.
317993e3fafSRobert Mustacchi  */
318993e3fafSRobert Mustacchi #pragma pack(1)
319993e3fafSRobert Mustacchi typedef struct xhci_trb {
320993e3fafSRobert Mustacchi 	uint64_t	trb_addr;
321993e3fafSRobert Mustacchi 	uint32_t	trb_status;
322993e3fafSRobert Mustacchi 	uint32_t	trb_flags;
323993e3fafSRobert Mustacchi } xhci_trb_t;
324993e3fafSRobert Mustacchi #pragma pack()
325993e3fafSRobert Mustacchi 
326993e3fafSRobert Mustacchi /*
327993e3fafSRobert Mustacchi  * This represents a single transfer that we want to allocate and perform.
328993e3fafSRobert Mustacchi  */
329993e3fafSRobert Mustacchi typedef struct xhci_transfer {
330993e3fafSRobert Mustacchi 	list_node_t		xt_link;
331993e3fafSRobert Mustacchi 	hrtime_t		xt_sched_time;
332993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	xt_buffer;
333993e3fafSRobert Mustacchi 	uint_t			xt_ntrbs;
334993e3fafSRobert Mustacchi 	uint_t			xt_short;
335993e3fafSRobert Mustacchi 	uint_t			xt_timeout;
336993e3fafSRobert Mustacchi 	usb_cr_t		xt_cr;
337993e3fafSRobert Mustacchi 	boolean_t		xt_data_tohost;
338993e3fafSRobert Mustacchi 	xhci_trb_t		*xt_trbs;
3392aba3acdSRobert Mustacchi 	uint64_t		*xt_trbs_pa;
340993e3fafSRobert Mustacchi 	usb_isoc_pkt_descr_t	*xt_isoc;
341993e3fafSRobert Mustacchi 	usb_opaque_t		xt_usba_req;
342993e3fafSRobert Mustacchi } xhci_transfer_t;
343993e3fafSRobert Mustacchi 
344993e3fafSRobert Mustacchi /*
345993e3fafSRobert Mustacchi  * This represents a ring in xHCI, upon which event, transfer, and command TRBs
346993e3fafSRobert Mustacchi  * are scheduled.
347993e3fafSRobert Mustacchi  */
348993e3fafSRobert Mustacchi typedef struct xhci_ring {
349993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	xr_dma;
350993e3fafSRobert Mustacchi 	uint_t			xr_ntrb;
351993e3fafSRobert Mustacchi 	xhci_trb_t		*xr_trb;
352993e3fafSRobert Mustacchi 	uint_t			xr_head;
353993e3fafSRobert Mustacchi 	uint_t			xr_tail;
354993e3fafSRobert Mustacchi 	uint8_t			xr_cycle;
355993e3fafSRobert Mustacchi } xhci_ring_t;
356993e3fafSRobert Mustacchi 
357993e3fafSRobert Mustacchi /*
358993e3fafSRobert Mustacchi  * This structure is used to represent the xHCI Device Context Base Address
359993e3fafSRobert Mustacchi  * Array. It's defined in section 6.1 of the specification and is required for
360993e3fafSRobert Mustacchi  * the controller to start.
361993e3fafSRobert Mustacchi  *
362993e3fafSRobert Mustacchi  * The maximum number of slots supported is always 256, therefore we size this
363993e3fafSRobert Mustacchi  * structure at its maximum.
364993e3fafSRobert Mustacchi  */
365993e3fafSRobert Mustacchi #define	XHCI_MAX_SLOTS	256
366993e3fafSRobert Mustacchi #define	XHCI_DCBAA_SCRATCHPAD_INDEX	0
367993e3fafSRobert Mustacchi 
368993e3fafSRobert Mustacchi typedef struct xhci_dcbaa {
369993e3fafSRobert Mustacchi 	uint64_t		*xdc_base_addrs;
370993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	xdc_dma;
371993e3fafSRobert Mustacchi } xhci_dcbaa_t;
372993e3fafSRobert Mustacchi 
373993e3fafSRobert Mustacchi typedef struct xhci_scratchpad {
374993e3fafSRobert Mustacchi 	uint64_t		*xsp_addrs;
375993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	xsp_addr_dma;
376993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	*xsp_scratch_dma;
377993e3fafSRobert Mustacchi } xhci_scratchpad_t;
378993e3fafSRobert Mustacchi 
379993e3fafSRobert Mustacchi /*
380993e3fafSRobert Mustacchi  * Contexts. These structures are inserted into the DCBAA above and are used for
381993e3fafSRobert Mustacchi  * describing the state of the system. Note, that while many of these are
382993e3fafSRobert Mustacchi  * 32-bytes in size, the xHCI specification defines that they'll be extended to
383993e3fafSRobert Mustacchi  * 64-bytes with all the extra bytes as zeros if the CSZ flag is set in the
384993e3fafSRobert Mustacchi  * HCCPARAMS1 register, e.g. we have the flag XCAP_CSZ set.
385993e3fafSRobert Mustacchi  *
386993e3fafSRobert Mustacchi  * The device context covers the slot context and 31 endpoints.
387993e3fafSRobert Mustacchi  */
388993e3fafSRobert Mustacchi #define	XHCI_DEVICE_CONTEXT_32	1024
389993e3fafSRobert Mustacchi #define	XHCI_DEVICE_CONTEXT_64	2048
390993e3fafSRobert Mustacchi #define	XHCI_NUM_ENDPOINTS	31
391993e3fafSRobert Mustacchi #define	XHCI_DEFAULT_ENDPOINT	0
392993e3fafSRobert Mustacchi 
393993e3fafSRobert Mustacchi #pragma pack(1)
394993e3fafSRobert Mustacchi typedef struct xhci_slot_context {
395993e3fafSRobert Mustacchi 	uint32_t	xsc_info;
396993e3fafSRobert Mustacchi 	uint32_t	xsc_info2;
397993e3fafSRobert Mustacchi 	uint32_t	xsc_tt;
398993e3fafSRobert Mustacchi 	uint32_t	xsc_state;
399993e3fafSRobert Mustacchi 	uint32_t	xsc_reserved[4];
400993e3fafSRobert Mustacchi } xhci_slot_context_t;
401993e3fafSRobert Mustacchi 
402993e3fafSRobert Mustacchi typedef struct xhci_endpoint_context {
403993e3fafSRobert Mustacchi 	uint32_t	xec_info;
404993e3fafSRobert Mustacchi 	uint32_t	xec_info2;
405993e3fafSRobert Mustacchi 	uint64_t	xec_dequeue;
406993e3fafSRobert Mustacchi 	uint32_t	xec_txinfo;
407993e3fafSRobert Mustacchi 	uint32_t	xec_reserved[3];
408993e3fafSRobert Mustacchi } xhci_endpoint_context_t;
409993e3fafSRobert Mustacchi 
410993e3fafSRobert Mustacchi typedef struct xhci_input_context {
411993e3fafSRobert Mustacchi 	uint32_t	xic_drop_flags;
412993e3fafSRobert Mustacchi 	uint32_t	xic_add_flags;
413993e3fafSRobert Mustacchi 	uint32_t	xic_reserved[6];
414993e3fafSRobert Mustacchi } xhci_input_context_t;
415993e3fafSRobert Mustacchi #pragma pack()
416993e3fafSRobert Mustacchi 
417993e3fafSRobert Mustacchi /*
418993e3fafSRobert Mustacchi  * Definitions and structures for maintaining the event ring.
419993e3fafSRobert Mustacchi  */
420993e3fafSRobert Mustacchi #define	XHCI_EVENT_NSEGS	1
421993e3fafSRobert Mustacchi 
422993e3fafSRobert Mustacchi #pragma pack(1)
423993e3fafSRobert Mustacchi typedef struct xhci_event_segment {
424993e3fafSRobert Mustacchi 	uint64_t	xes_addr;
425993e3fafSRobert Mustacchi 	uint16_t	xes_size;
426993e3fafSRobert Mustacchi 	uint16_t	xes_rsvd0;
427993e3fafSRobert Mustacchi 	uint32_t	xes_rsvd1;
428993e3fafSRobert Mustacchi } xhci_event_segment_t;
429993e3fafSRobert Mustacchi #pragma pack()
430993e3fafSRobert Mustacchi 
431993e3fafSRobert Mustacchi typedef struct xhci_event_ring {
432993e3fafSRobert Mustacchi 	xhci_event_segment_t	*xev_segs;
433993e3fafSRobert Mustacchi 	xhci_dma_buffer_t	xev_dma;
434993e3fafSRobert Mustacchi 	xhci_ring_t		xev_ring;
435993e3fafSRobert Mustacchi } xhci_event_ring_t;
436993e3fafSRobert Mustacchi 
437993e3fafSRobert Mustacchi typedef enum xhci_command_ring_state {
438993e3fafSRobert Mustacchi 	XHCI_COMMAND_RING_IDLE		= 0x00,
439993e3fafSRobert Mustacchi 	XHCI_COMMAND_RING_RUNNING	= 0x01,
440993e3fafSRobert Mustacchi 	XHCI_COMMAND_RING_ABORTING	= 0x02,
441993e3fafSRobert Mustacchi 	XHCI_COMMAND_RING_ABORT_DONE	= 0x03
442993e3fafSRobert Mustacchi } xhci_command_ring_state_t;
443993e3fafSRobert Mustacchi 
444993e3fafSRobert Mustacchi typedef struct xhci_command_ring {
445993e3fafSRobert Mustacchi 	xhci_ring_t			xcr_ring;
446993e3fafSRobert Mustacchi 	kmutex_t			xcr_lock;
447993e3fafSRobert Mustacchi 	kcondvar_t			xcr_cv;
448993e3fafSRobert Mustacchi 	list_t				xcr_commands;
449993e3fafSRobert Mustacchi 	timeout_id_t			xcr_timeout;
450993e3fafSRobert Mustacchi 	xhci_command_ring_state_t	xcr_state;
451993e3fafSRobert Mustacchi } xhci_command_ring_t;
452993e3fafSRobert Mustacchi 
453993e3fafSRobert Mustacchi /*
454993e3fafSRobert Mustacchi  * Individual command states.
455993e3fafSRobert Mustacchi  *
456993e3fafSRobert Mustacchi  * XHCI_COMMAND_S_INIT		The command has yet to be inserted into the
4572aba3acdSRobert Mustacchi  *				command ring.
458993e3fafSRobert Mustacchi  *
459993e3fafSRobert Mustacchi  * XHCI_COMMAND_S_QUEUED	The command is queued in the command ring.
460993e3fafSRobert Mustacchi  *
461993e3fafSRobert Mustacchi  * XHCI_COMMAND_S_RECEIVED	A command completion for this was received.
462993e3fafSRobert Mustacchi  *
463993e3fafSRobert Mustacchi  * XHCI_COMMAND_S_DONE		The command has been executed. Note that it may