xref: /illumos-gate/usr/src/uts/common/sys/usb/hcd/uhci/uhcid.h (revision d29f5a71)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
502acac7eSsl  * Common Development and Distribution License (the "License").
602acac7eSsl  * You may not use this file except in compliance with the License.
77c478bd9Sstevel@tonic-gate  *
87c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
107c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
117c478bd9Sstevel@tonic-gate  * and limitations under the License.
127c478bd9Sstevel@tonic-gate  *
137c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
147c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
167c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
177c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bd9Sstevel@tonic-gate  *
197c478bd9Sstevel@tonic-gate  * CDDL HEADER END
207c478bd9Sstevel@tonic-gate  */
217c478bd9Sstevel@tonic-gate /*
22fffe0b30Sqz  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
237c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
247c478bd9Sstevel@tonic-gate  */
257c478bd9Sstevel@tonic-gate 
267c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_UHCID_H
277c478bd9Sstevel@tonic-gate #define	_SYS_USB_UHCID_H
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate 
307c478bd9Sstevel@tonic-gate #ifdef __cplusplus
317c478bd9Sstevel@tonic-gate extern "C" {
327c478bd9Sstevel@tonic-gate #endif
337c478bd9Sstevel@tonic-gate 
347c478bd9Sstevel@tonic-gate /*
357c478bd9Sstevel@tonic-gate  * Universal Host Controller Driver (UHCI)
367c478bd9Sstevel@tonic-gate  *
377c478bd9Sstevel@tonic-gate  * The UHCI driver is a driver which interfaces to the Universal
387c478bd9Sstevel@tonic-gate  * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
397c478bd9Sstevel@tonic-gate  * the Host Controller is defined by the Universal Host Controller Interface.
407c478bd9Sstevel@tonic-gate  *
417c478bd9Sstevel@tonic-gate  * This file contains the data structures for the UHCI driver.
427c478bd9Sstevel@tonic-gate  */
437c478bd9Sstevel@tonic-gate #include <sys/types.h>
447c478bd9Sstevel@tonic-gate #include <sys/pci.h>
457c478bd9Sstevel@tonic-gate #include <sys/kstat.h>
467c478bd9Sstevel@tonic-gate 
477c478bd9Sstevel@tonic-gate #include <sys/usb/usba/usbai_version.h>
487c478bd9Sstevel@tonic-gate #include <sys/usb/usba.h>
497c478bd9Sstevel@tonic-gate #include <sys/usb/usba/usba_types.h>
507c478bd9Sstevel@tonic-gate 
517c478bd9Sstevel@tonic-gate #include <sys/usb/usba/genconsole.h>
527c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hcdi.h>
537c478bd9Sstevel@tonic-gate 
547c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hub.h>
557c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hubdi.h>
567c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hubdvar.h>
577c478bd9Sstevel@tonic-gate 
587c478bd9Sstevel@tonic-gate #include <sys/usb/hcd/uhci/uhci.h>
597c478bd9Sstevel@tonic-gate 
607c478bd9Sstevel@tonic-gate /* limit the xfer size for bulk */
617c478bd9Sstevel@tonic-gate #define	UHCI_BULK_MAX_XFER_SIZE	(124*1024) /* Max bulk xfer size */
627c478bd9Sstevel@tonic-gate 
637c478bd9Sstevel@tonic-gate /* Maximum allowable data transfer size per transaction */
6402acac7eSsl #define	UHCI_MAX_TD_XFER_SIZE	0x500 /* Maximum data per transaction */
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate /*
677c478bd9Sstevel@tonic-gate  * Generic UHCI Macro definitions
687c478bd9Sstevel@tonic-gate  */
697c478bd9Sstevel@tonic-gate #define	UHCI_UNDERRUN_OCCURRED	0x1234
707c478bd9Sstevel@tonic-gate #define	UHCI_OVERRUN_OCCURRED	0x5678
717c478bd9Sstevel@tonic-gate #define	UHCI_PROP_MASK		0x01000020
727c478bd9Sstevel@tonic-gate #define	UHCI_RESET_DELAY	15000
737c478bd9Sstevel@tonic-gate #define	UHCI_TIMEWAIT		10000
747c478bd9Sstevel@tonic-gate 
757c478bd9Sstevel@tonic-gate #define	MAX_SOF_WAIT_COUNT	2
767c478bd9Sstevel@tonic-gate #define	MAX_RH_PORTS		2
777c478bd9Sstevel@tonic-gate #define	DISCONNECTED		2
787c478bd9Sstevel@tonic-gate #define	POLLING_FREQ_7MS	7
797c478bd9Sstevel@tonic-gate #define	PCI_CONF_IOBASE		0x20
807c478bd9Sstevel@tonic-gate #define	PCI_CONF_IOBASE_MASK	0xffe0
817c478bd9Sstevel@tonic-gate 
827c478bd9Sstevel@tonic-gate #define	UHCI_ONE_SECOND		drv_usectohz(1000000)
837c478bd9Sstevel@tonic-gate #define	UHCI_ONE_MS		drv_usectohz(1000)
847c478bd9Sstevel@tonic-gate #define	UHCI_32_MS		drv_usectohz(32*1000)
85*4f71203dSzl #define	UHCI_256_MS		drv_usectohz(256*1000)
867c478bd9Sstevel@tonic-gate #define	UHCI_MAX_INSTS		4
877c478bd9Sstevel@tonic-gate 
887c478bd9Sstevel@tonic-gate #define	POLLED_RAW_BUF_SIZE	8
897c478bd9Sstevel@tonic-gate 
907c478bd9Sstevel@tonic-gate /* Default time out values for bulk and ctrl commands */
917c478bd9Sstevel@tonic-gate #define	UHCI_CTRL_TIMEOUT	5
927c478bd9Sstevel@tonic-gate #define	UHCI_BULK_TIMEOUT	60
937c478bd9Sstevel@tonic-gate 
947c478bd9Sstevel@tonic-gate /* UHCI root hub structure */
957c478bd9Sstevel@tonic-gate typedef struct uhci_root_hub_info {
967c478bd9Sstevel@tonic-gate 	uint_t			rh_status;		/* Last RH status */
977c478bd9Sstevel@tonic-gate 	uint_t			rh_num_ports;		/* #ports on the root */
987c478bd9Sstevel@tonic-gate 
997c478bd9Sstevel@tonic-gate 	/* Last status of ports */
1007c478bd9Sstevel@tonic-gate 	uint_t			rh_port_status[MAX_RH_PORTS];
1017c478bd9Sstevel@tonic-gate 	uint_t			rh_port_changes[MAX_RH_PORTS];
1027c478bd9Sstevel@tonic-gate 	uint_t			rh_port_state[MAX_RH_PORTS]; /* See below */
1037c478bd9Sstevel@tonic-gate 
1047c478bd9Sstevel@tonic-gate 	usba_pipe_handle_data_t	*rh_intr_pipe_handle;	/* RH intr pipe hndle */
1057c478bd9Sstevel@tonic-gate 	usb_hub_descr_t		rh_descr;		/* RH descr's copy */
1067c478bd9Sstevel@tonic-gate 	uint_t			rh_pipe_state;		/* RH intr pipe state */
1077c478bd9Sstevel@tonic-gate 
1087c478bd9Sstevel@tonic-gate 	usb_intr_req_t		*rh_curr_intr_reqp;	/* Current intr req */
1097c478bd9Sstevel@tonic-gate 	usb_intr_req_t		*rh_client_intr_req;	/* save IN request */
1107c478bd9Sstevel@tonic-gate } uhci_root_hub_info_t;
1117c478bd9Sstevel@tonic-gate 
1127c478bd9Sstevel@tonic-gate /*
1137c478bd9Sstevel@tonic-gate  * UHCI Host Controller per instance data structure
1147c478bd9Sstevel@tonic-gate  *
1157c478bd9Sstevel@tonic-gate  * The Host Controller Driver (HCD) maintains the state of Host Controller
1167c478bd9Sstevel@tonic-gate  * (HC). There is an uhci_state structure per instance	of the UHCI
1177c478bd9Sstevel@tonic-gate  * host controller.
1187c478bd9Sstevel@tonic-gate  */
1197c478bd9Sstevel@tonic-gate typedef struct uhci_state {
1207c478bd9Sstevel@tonic-gate 	dev_info_t		*uhci_dip;		/* dip of HC */
1217c478bd9Sstevel@tonic-gate 	uint_t			uhci_instance;
1227c478bd9Sstevel@tonic-gate 	usba_hcdi_ops_t		*uhci_hcdi_ops;		/* HCDI structure */
1237c478bd9Sstevel@tonic-gate 
1247c478bd9Sstevel@tonic-gate 	uint_t			uhci_dma_addr_bind_flag;
1257c478bd9Sstevel@tonic-gate 
126fffe0b30Sqz 	/* UHCI Host Controller Software State information */
127fffe0b30Sqz 	uint_t			uhci_hc_soft_state;
1287c478bd9Sstevel@tonic-gate 
1297c478bd9Sstevel@tonic-gate 	hc_regs_t		*uhci_regsp;		/* Host ctlr regs */
1307c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	uhci_regs_handle;	/* Reg handle */
1317c478bd9Sstevel@tonic-gate 
1327c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	uhci_config_handle;	/* Config space hndle */
1337c478bd9Sstevel@tonic-gate 
1347c478bd9Sstevel@tonic-gate 	/* Frame interval reg */
1357c478bd9Sstevel@tonic-gate 	uint_t			uhci_frame_interval;
1367c478bd9Sstevel@tonic-gate 	ddi_dma_attr_t		uhci_dma_attr;		/* DMA attributes */
1377c478bd9Sstevel@tonic-gate 
1387c478bd9Sstevel@tonic-gate 	ddi_intr_handle_t	*uhci_htable;		/* intr handle */
1399c75c6bfSgovinda 	int			uhci_intr_type;		/* intr type used */
1409c75c6bfSgovinda 	int			uhci_intr_cnt;		/* # of intrs inuse */
1419c75c6bfSgovinda 	uint_t			uhci_intr_pri;		/* intr priority */
1429c75c6bfSgovinda 	int			uhci_intr_cap;		/* intr capabilities */
1437c478bd9Sstevel@tonic-gate 	kmutex_t		uhci_int_mutex;		/* Mutex for struct */
1447c478bd9Sstevel@tonic-gate 
1457c478bd9Sstevel@tonic-gate 	frame_lst_table_t	*uhci_frame_lst_tablep;	/* Virtual HCCA ptr */
1467c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_isoc_q_tailp[NUM_FRAME_LST_ENTRIES];
1477c478bd9Sstevel@tonic-gate 
1487c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	uhci_flt_cookie;	/* DMA cookie */
1497c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	uhci_flt_dma_handle;	/* DMA handle */
1507c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	uhci_flt_mem_handle;	/* Memory handle */
1517c478bd9Sstevel@tonic-gate 
1527c478bd9Sstevel@tonic-gate 	/*
1537c478bd9Sstevel@tonic-gate 	 * There are two pools of memory. One pool contains the memory for
1547c478bd9Sstevel@tonic-gate 	 * the transfer descriptors and other pool contains the memory for
1557c478bd9Sstevel@tonic-gate 	 * the Queue Head pointers. The advantage of the pools is that it's
1567c478bd9Sstevel@tonic-gate 	 * easy to go back and forth between the iommu and the cpu addresses.
1577c478bd9Sstevel@tonic-gate 	 *
1587c478bd9Sstevel@tonic-gate 	 * The pools are protected by the int_mutex because the memory
1597c478bd9Sstevel@tonic-gate 	 * in the pools may be accessed by either the host controller or the
1607c478bd9Sstevel@tonic-gate 	 * host controller driver.
1617c478bd9Sstevel@tonic-gate 	 */
1627c478bd9Sstevel@tonic-gate 
1637c478bd9Sstevel@tonic-gate 	/* General transfer descriptor pool */
1647c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_td_pool_addr;	/* Start of the pool */
1657c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	uhci_td_pool_cookie;	/* DMA cookie */
1667c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	uhci_td_pool_dma_handle; /* DMA hndle */
1677c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	uhci_td_pool_mem_handle; /* Mem hndle */
1687c478bd9Sstevel@tonic-gate 
1697c478bd9Sstevel@tonic-gate 	/* Endpoint descriptor pool */
1707c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_qh_pool_addr;	/* Start of the pool */
1717c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t	uhci_qh_pool_cookie;	/* DMA cookie */
1727c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t	uhci_qh_pool_dma_handle; /* DMA handle */
1737c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t	uhci_qh_pool_mem_handle; /* Mem handle */
1747c478bd9Sstevel@tonic-gate 
1757c478bd9Sstevel@tonic-gate 	/* Semaphore to serialize opens and closes */
1767c478bd9Sstevel@tonic-gate 	ksema_t			uhci_ocsem;
1777c478bd9Sstevel@tonic-gate 
1787c478bd9Sstevel@tonic-gate 	/* Timeout id of the root hub status change pipe handler */
1797c478bd9Sstevel@tonic-gate 	timeout_id_t		uhci_timeout_id;
1807c478bd9Sstevel@tonic-gate 
1817c478bd9Sstevel@tonic-gate 	/* Timeout id of the ctrl/bulk/intr xfers timeout */
1827c478bd9Sstevel@tonic-gate 	timeout_id_t		uhci_cmd_timeout_id;
1837c478bd9Sstevel@tonic-gate 
1847c478bd9Sstevel@tonic-gate 	/*
1857c478bd9Sstevel@tonic-gate 	 * Bandwidth fields
1867c478bd9Sstevel@tonic-gate 	 *
1877c478bd9Sstevel@tonic-gate 	 * The uhci_bandwidth array keeps track of the allocated bandwidth
1887c478bd9Sstevel@tonic-gate 	 * for this host controller. The uhci_bandwidth_isoch_sum field
1897c478bd9Sstevel@tonic-gate 	 * represents the sum of the allocated isochronous bandwidth. The
1907c478bd9Sstevel@tonic-gate 	 * total bandwidth allocated for least allocated list out of the 32
1917c478bd9Sstevel@tonic-gate 	 * interrupt lists is represented by the uhci_bandwdith_intr_min
1927c478bd9Sstevel@tonic-gate 	 * field.
1937c478bd9Sstevel@tonic-gate 	 */
1947c478bd9Sstevel@tonic-gate 	uint_t			uhci_bandwidth[NUM_FRAME_LST_ENTRIES];
1957c478bd9Sstevel@tonic-gate 	uint_t			uhci_bandwidth_isoch_sum;
1967c478bd9Sstevel@tonic-gate 	uint_t			uhci_bandwidth_intr_min;
1977c478bd9Sstevel@tonic-gate 
1987c478bd9Sstevel@tonic-gate 	uhci_root_hub_info_t	uhci_root_hub;	/* Root hub info */
1997c478bd9Sstevel@tonic-gate 
2007c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_outst_tds_head;
2017c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_outst_tds_tail;
2027c478bd9Sstevel@tonic-gate 
2037c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_ctrl_xfers_q_head;
2047c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_ctrl_xfers_q_tail;
2057c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_bulk_xfers_q_head;
2067c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_bulk_xfers_q_tail;
2077c478bd9Sstevel@tonic-gate 
2087c478bd9Sstevel@tonic-gate 	kcondvar_t		uhci_cv_SOF;
2097c478bd9Sstevel@tonic-gate 	uchar_t			uhci_cv_signal;
2107c478bd9Sstevel@tonic-gate 
2117c478bd9Sstevel@tonic-gate 	/* Polled I/O support */
2127c478bd9Sstevel@tonic-gate 	frame_lst_table_t	uhci_polled_save_IntTble[1024];
2137c478bd9Sstevel@tonic-gate 	uint_t			uhci_polled_count;
2147c478bd9Sstevel@tonic-gate 	uint32_t		uhci_polled_flag;
2157c478bd9Sstevel@tonic-gate 
2167c478bd9Sstevel@tonic-gate 	/* Software frame number */
2177c478bd9Sstevel@tonic-gate 	usb_frame_number_t	uhci_sw_frnum;
2187c478bd9Sstevel@tonic-gate 
2197c478bd9Sstevel@tonic-gate 	/* Number of pending bulk commands */
2207c478bd9Sstevel@tonic-gate 	uint32_t		uhci_pending_bulk_cmds;
2217c478bd9Sstevel@tonic-gate 
2227c478bd9Sstevel@tonic-gate 	/* logging support */
2237c478bd9Sstevel@tonic-gate 	usb_log_handle_t	uhci_log_hdl;
2247c478bd9Sstevel@tonic-gate 
2257c478bd9Sstevel@tonic-gate 	/*
2267c478bd9Sstevel@tonic-gate 	 * TD's used for the generation of interrupt
2277c478bd9Sstevel@tonic-gate 	 */
2287c478bd9Sstevel@tonic-gate 	queue_head_t		*uhci_isoc_qh;
2297c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_sof_td;
2307c478bd9Sstevel@tonic-gate 	uhci_td_t		*uhci_isoc_td;
2317c478bd9Sstevel@tonic-gate 
2327c478bd9Sstevel@tonic-gate 	/*
2337c478bd9Sstevel@tonic-gate 	 * Keep io base address, for debugging purpose
2347c478bd9Sstevel@tonic-gate 	 */
2357c478bd9Sstevel@tonic-gate 	uint_t			uhci_iobase;
2367c478bd9Sstevel@tonic-gate 
2377c478bd9Sstevel@tonic-gate 	/*
2387c478bd9Sstevel@tonic-gate 	 * kstat structures
2397c478bd9Sstevel@tonic-gate 	 */
2407c478bd9Sstevel@tonic-gate 	kstat_t			*uhci_intrs_stats;
2417c478bd9Sstevel@tonic-gate 	kstat_t			*uhci_total_stats;
2427c478bd9Sstevel@tonic-gate 	kstat_t			*uhci_count_stats[USB_N_COUNT_KSTATS];
2437c478bd9Sstevel@tonic-gate } uhci_state_t;
2447c478bd9Sstevel@tonic-gate 
2457c478bd9Sstevel@tonic-gate 
2467c478bd9Sstevel@tonic-gate /*
2477c478bd9Sstevel@tonic-gate  * uhci_dma_addr_bind_flag values
2487c478bd9Sstevel@tonic-gate  *
2497c478bd9Sstevel@tonic-gate  * This flag indicates if the various DMA addresses allocated by the UHCI
2507c478bd9Sstevel@tonic-gate  * have been bound to their respective handles. This is needed to recover
2517c478bd9Sstevel@tonic-gate  * without errors from uhci_cleanup when it calls ddi_dma_unbind_handle()
2527c478bd9Sstevel@tonic-gate  */
2537c478bd9Sstevel@tonic-gate #define	UHCI_TD_POOL_BOUND	0x01	/* for TD pools */
2547c478bd9Sstevel@tonic-gate #define	UHCI_QH_POOL_BOUND	0x02	/* for QH pools */
2557c478bd9Sstevel@tonic-gate #define	UHCI_FLA_POOL_BOUND	0x04	/* for Host Ctrlr Framelist Area */
2567c478bd9Sstevel@tonic-gate 
2577c478bd9Sstevel@tonic-gate /*
2587c478bd9Sstevel@tonic-gate  * Definitions for uhci_polled_flag
2597c478bd9Sstevel@tonic-gate  * The flag is set to UHCI_POLLED_FLAG_FALSE by default. The flags is
2607c478bd9Sstevel@tonic-gate  * set to UHCI_POLLED_FLAG_TD_COMPL when shifting from normal mode to
2617c478bd9Sstevel@tonic-gate  * polled mode and if the normal TD is completed at that time. And the
2627c478bd9Sstevel@tonic-gate  * flag is set to UHCI_POLLED_FLAG_TRUE while exiting from the polled
2637c478bd9Sstevel@tonic-gate  * mode. In the timeout handler for root hub status change, this flag
2647c478bd9Sstevel@tonic-gate  * is checked. If set to UHCI_POLLED_FLAG_TRUE, the routine
2657c478bd9Sstevel@tonic-gate  * uhci_process_submitted_td_queue() to process the completed TD.
2667c478bd9Sstevel@tonic-gate  */
2677c478bd9Sstevel@tonic-gate #define	UHCI_POLLED_FLAG_FALSE		0
2687c478bd9Sstevel@tonic-gate #define	UHCI_POLLED_FLAG_TRUE		1
2697c478bd9Sstevel@tonic-gate #define	UHCI_POLLED_FLAG_TD_COMPL	2
2707c478bd9Sstevel@tonic-gate 
2717c478bd9Sstevel@tonic-gate /*
2727c478bd9Sstevel@tonic-gate  * Pipe private structure
2737c478bd9Sstevel@tonic-gate  *
2747c478bd9Sstevel@tonic-gate  * There is an instance of this structure per pipe.  This structure holds
2757c478bd9Sstevel@tonic-gate  * HCD specific pipe information.  A pointer to this structure is kept in
2767c478bd9Sstevel@tonic-gate  * the USBA pipe handle (usba_pipe_handle_data_t).
2777c478bd9Sstevel@tonic-gate  */
2787c478bd9Sstevel@tonic-gate typedef struct uhci_pipe_private {
2797c478bd9Sstevel@tonic-gate 	usba_pipe_handle_data_t	*pp_pipe_handle; /* Back ptr to pipe handle */
2807c478bd9Sstevel@tonic-gate 	queue_head_t		*pp_qh;		/* Pipe's ept */
2817c478bd9Sstevel@tonic-gate 	uint_t			pp_state;	/* See below */
2827c478bd9Sstevel@tonic-gate 	usb_pipe_policy_t	pp_policy;	/* Copy of the pipe policy */
2837c478bd9Sstevel@tonic-gate 	uint_t			pp_node;	/* Node in lattice */
2847c478bd9Sstevel@tonic-gate 	uchar_t			pp_data_toggle;	/* save data toggle bit */
2857c478bd9Sstevel@tonic-gate 
2867c478bd9Sstevel@tonic-gate 	/*
2877c478bd9Sstevel@tonic-gate 	 * Each pipe may have multiple transfer wrappers. Each transfer
2887c478bd9Sstevel@tonic-gate 	 * wrapper represents a USB transfer on the bus.  A transfer is
2897c478bd9Sstevel@tonic-gate 	 * made up of one or more transactions.
2907c478bd9Sstevel@tonic-gate 	 */
2917c478bd9Sstevel@tonic-gate 	struct uhci_trans_wrapper *pp_tw_head;	/* Head of the list */
2927c478bd9Sstevel@tonic-gate 	struct uhci_trans_wrapper *pp_tw_tail;	/* Tail of the list */
2937c478bd9Sstevel@tonic-gate 
2947c478bd9Sstevel@tonic-gate 	/*
2957c478bd9Sstevel@tonic-gate 	 * Starting frame number at which next isoc TD will be inserted
2967c478bd9Sstevel@tonic-gate 	 * for this pipe
2977c478bd9Sstevel@tonic-gate 	 */
2987c478bd9Sstevel@tonic-gate 	uint64_t		pp_frame_num;
2997c478bd9Sstevel@tonic-gate 
3007c478bd9Sstevel@tonic-gate 	/*
3017c478bd9Sstevel@tonic-gate 	 * HCD gets Interrupt/Isochronous IN polling request only once and
3027c478bd9Sstevel@tonic-gate 	 * it has to insert next polling requests after completion of first
3037c478bd9Sstevel@tonic-gate 	 * request until either stop polling/pipe close is called. So  HCD
3047c478bd9Sstevel@tonic-gate 	 * has to take copy of the original Interrupt/Isochronous IN request.
3057c478bd9Sstevel@tonic-gate 	 */
3067c478bd9Sstevel@tonic-gate 	usb_opaque_t		pp_client_periodic_in_reqp;
3077c478bd9Sstevel@tonic-gate } uhci_pipe_private_t;
3087c478bd9Sstevel@tonic-gate 
3097c478bd9Sstevel@tonic-gate /* warlock directives, stable data */
3107c478bd9Sstevel@tonic-gate _NOTE(MUTEX_PROTECTS_DATA(uhci_state_t::uhci_int_mutex, uhci_pipe_private_t))
3117c478bd9Sstevel@tonic-gate _NOTE(LOCK_ORDER(uhci_state::uhci_int_mutex \
3127c478bd9Sstevel@tonic-gate 		usba_pipe_handle_data::p_mutex \
3137c478bd9Sstevel@tonic-gate 		usba_device::usb_mutex \
3147c478bd9Sstevel@tonic-gate 		usba_ph_impl::usba_ph_mutex))
3157c478bd9Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("private mutex", kstat_io))
3167c478bd9Sstevel@tonic-gate _NOTE(SCHEME_PROTECTS_DATA("unshared", usb_isoc_pkt_descr))
3177c478bd9Sstevel@tonic-gate 
3187c478bd9Sstevel@tonic-gate /*
3197c478bd9Sstevel@tonic-gate  * Pipe states
3207c478bd9Sstevel@tonic-gate  *
3217c478bd9Sstevel@tonic-gate  * uhci pipe states will be similar to usba. Refer usbai.h.
3227c478bd9Sstevel@tonic-gate  */
3237c478bd9Sstevel@tonic-gate #define	UHCI_PIPE_STATE_IDLE	1	/* Pipe has opened,ready state */
3247c478bd9Sstevel@tonic-gate #define	UHCI_PIPE_STATE_ACTIVE	2	/* Polling the endpoint,busy state */
3257c478bd9Sstevel@tonic-gate 
3267c478bd9Sstevel@tonic-gate /*
3277c478bd9Sstevel@tonic-gate  * to indicate if we are in close/reset so that we can issue callbacks to
3287c478bd9Sstevel@tonic-gate  * IN packets that are pending
3297c478bd9Sstevel@tonic-gate  */
3307c478bd9Sstevel@tonic-gate #define	UHCI_IN_CLOSE	4
3317c478bd9Sstevel@tonic-gate #define	UHCI_IN_RESET	5
3327c478bd9Sstevel@tonic-gate #define	UHCI_IN_ERROR	6
3337c478bd9Sstevel@tonic-gate 
3347c478bd9Sstevel@tonic-gate /* Function prototype */
3357c478bd9Sstevel@tonic-gate typedef void (*uhci_handler_function_t) (uhci_state_t *uhcip, uhci_td_t  *td);
3367c478bd9Sstevel@tonic-gate 
3377c478bd9Sstevel@tonic-gate /*
3387c478bd9Sstevel@tonic-gate  * Transfer wrapper
3397c478bd9Sstevel@tonic-gate  *
3407c478bd9Sstevel@tonic-gate  * The transfer wrapper represents a USB transfer on the bus and there
3417c478bd9Sstevel@tonic-gate  * is one instance per USB transfer.  A transfer is made up of one or
34202acac7eSsl  * more transactions. UHCI uses one TD for one transaction. So one
34302acac7eSsl  * transfer wrapper may have one or more TDs associated.
3447c478bd9Sstevel@tonic-gate  *
3457c478bd9Sstevel@tonic-gate  * Control and bulk pipes will have one transfer wrapper per transfer
3467c478bd9Sstevel@tonic-gate  * and where as Isochronous and Interrupt pipes will only have one
3477c478bd9Sstevel@tonic-gate  * transfer wrapper. The transfers wrapper are continually reused for
3487c478bd9Sstevel@tonic-gate  * the Interrupt and Isochronous pipes as those pipes are polled.
34902acac7eSsl  *
35002acac7eSsl  * Control, bulk and interrupt transfers will have one DMA buffer per
35102acac7eSsl  * transfer. The data to be transferred are contained in the DMA buffer
35202acac7eSsl  * which is virtually contiguous but physically discontiguous. When
35302acac7eSsl  * preparing the TDs for a USB transfer, the DMA cookies contained in
35402acac7eSsl  * the buffer need to be walked through to retrieve the DMA addresses.
35502acac7eSsl  *
35602acac7eSsl  * Isochronous transfers will have multiple DMA buffers per transfer
35702acac7eSsl  * with each isoc packet having a DMA buffer. And the DMA buffers should
35802acac7eSsl  * only contain one cookie each, so no cookie walking is necessary.
3597c478bd9Sstevel@tonic-gate  */
3607c478bd9Sstevel@tonic-gate typedef struct uhci_trans_wrapper {
3617c478bd9Sstevel@tonic-gate 	struct uhci_trans_wrapper	*tw_next;	/* Next wrapper */
3627c478bd9Sstevel@tonic-gate 	uhci_pipe_private_t		*tw_pipe_private;
3637c478bd9Sstevel@tonic-gate 	size_t				tw_length;	/* Txfer length */
3647c478bd9Sstevel@tonic-gate 	uint_t				tw_tmp;		/* Temp variable */
3657c478bd9Sstevel@tonic-gate 	ddi_dma_handle_t		tw_dmahandle;	/* DMA handle */
3667c478bd9Sstevel@tonic-gate 	ddi_acc_handle_t		tw_accesshandle; /* Acc hndle */
3677c478bd9Sstevel@tonic-gate 	char				*tw_buf;	/* Buffer for txfer */
3687c478bd9Sstevel@tonic-gate 	ddi_dma_cookie_t		tw_cookie;	/* DMA cookie */
36902acac7eSsl 	uint_t				tw_ncookies;	/* DMA cookie count */
37002acac7eSsl 	uint_t				tw_cookie_idx;	/* DMA cookie index */
37102acac7eSsl 	size_t				tw_dma_offs;	/* DMA buffer offset */
3727c478bd9Sstevel@tonic-gate 	int				tw_ctrl_state;	/* See below */
3737c478bd9Sstevel@tonic-gate 	uhci_td_t			*tw_hctd_head;	/* Head TD */
3747c478bd9Sstevel@tonic-gate 	uhci_td_t			*tw_hctd_tail;	/* Tail TD */
3757c478bd9Sstevel@tonic-gate 	uint_t				tw_direction;	/* Direction of TD */
3767c478bd9Sstevel@tonic-gate 	usb_flags_t			tw_flags;	/* Flags */
3777c478bd9Sstevel@tonic-gate 
3787c478bd9Sstevel@tonic-gate 	/*
3797c478bd9Sstevel@tonic-gate 	 * This is the function to call when this td is done. This way
3807c478bd9Sstevel@tonic-gate 	 * we don't have to look in the td to figure out what kind it is.
3817c478bd9Sstevel@tonic-gate 	 */
3827c478bd9Sstevel@tonic-gate 	uhci_handler_function_t		tw_handle_td;
3837c478bd9Sstevel@tonic-gate 
3847c478bd9Sstevel@tonic-gate 	/*
3857c478bd9Sstevel@tonic-gate 	 * This is the callback value used when processing a done td.
3867c478bd9Sstevel@tonic-gate 	 */
3877c478bd9Sstevel@tonic-gate 	usb_opaque_t			tw_handle_callback_value;
3887c478bd9Sstevel@tonic-gate 
3897c478bd9Sstevel@tonic-gate 	uint_t				tw_bytes_xfered;
3907c478bd9Sstevel@tonic-gate 	uint_t				tw_bytes_pending;
3917c478bd9Sstevel@tonic-gate 
3927c478bd9Sstevel@tonic-gate 	/* Maximum amount of time for this command */
3937c478bd9Sstevel@tonic-gate 	uint_t				tw_timeout_cnt;
3947c478bd9Sstevel@tonic-gate 
3957c478bd9Sstevel@tonic-gate 	usb_isoc_req_t			*tw_isoc_req;
3967c478bd9Sstevel@tonic-gate 	uhci_bulk_isoc_xfer_t		tw_xfer_info;
39702acac7eSsl 	uhci_isoc_buf_t			*tw_isoc_bufs;	/* Isoc DMA buffers */
39802acac7eSsl 	size_t				tw_isoc_strtlen;
3997c478bd9Sstevel@tonic-gate 
4007c478bd9Sstevel@tonic-gate 	/* This is used to avoid multiple tw deallocation */
4017c478bd9Sstevel@tonic-gate 	uint_t				tw_claim;
4027c478bd9Sstevel@tonic-gate 
4037c478bd9Sstevel@tonic-gate 	/*
4047c478bd9Sstevel@tonic-gate 	 * Pointer to the data in case of send command
4057c478bd9Sstevel@tonic-gate 	 */
4067c478bd9Sstevel@tonic-gate 	mblk_t				*tw_data;
4077c478bd9Sstevel@tonic-gate 
4087c478bd9Sstevel@tonic-gate 	/* save a copy of current request */
4097c478bd9Sstevel@tonic-gate 	usb_opaque_t			tw_curr_xfer_reqp;
4107c478bd9Sstevel@tonic-gate } uhci_trans_wrapper_t;
4117c478bd9Sstevel@tonic-gate 
41202acac7eSsl /* Macros for uhci DMA buffer */
41302acac7eSsl #define	UHCI_DMA_ATTR_ALIGN	0x800
41402acac7eSsl #define	UHCI_DMA_ATTR_SGLLEN	0x7fffffff
41502acac7eSsl #define	UHCI_CTRL_EPT_MAX_SIZE	64
41602acac7eSsl 
41702acac7eSsl /*
41802acac7eSsl  * Macro for allocation of Bulk and Isoc TD pools
41902acac7eSsl  *
42002acac7eSsl  * When a Bulk or Isoc transfer needs to allocate too many TDs,
42102acac7eSsl  * the allocation for one physical contiguous TD pool may fail
42202acac7eSsl  * due to the fragmentation of physical memory. The number of
42302acac7eSsl  * TDs in one pool should be limited so that a TD pool is within
42402acac7eSsl  * page size under this situation.
42502acac7eSsl  */
42602acac7eSsl #if defined(__sparc)
42702acac7eSsl #define	UHCI_MAX_TD_NUM_PER_POOL	88
42802acac7eSsl #else
42902acac7eSsl #define	UHCI_MAX_TD_NUM_PER_POOL	44
43002acac7eSsl #endif
43102acac7eSsl 
4327c478bd9Sstevel@tonic-gate /* set timeout flag so as to decrement timeout_cnt only once */
4337c478bd9Sstevel@tonic-gate #define	TW_TIMEOUT_FLAG		0x1000
4347c478bd9Sstevel@tonic-gate 
4357c478bd9Sstevel@tonic-gate /* Macro for changing the data toggle */
4367c478bd9Sstevel@tonic-gate #define	ADJ_DATA_TOGGLE(pp) \
4377c478bd9Sstevel@tonic-gate 		(pp)->pp_data_toggle = ((pp)->pp_data_toggle == 0) ? 1 : 0;
4387c478bd9Sstevel@tonic-gate 
4397c478bd9Sstevel@tonic-gate /*
4407c478bd9Sstevel@tonic-gate  * Macros for setting/getting information
4417c478bd9Sstevel@tonic-gate  */
4427c478bd9Sstevel@tonic-gate #define	Get_OpReg32(addr)	ddi_get32(uhcip->uhci_regs_handle, \
4437c478bd9Sstevel@tonic-gate 				    (uint32_t *)&uhcip->uhci_regsp->addr)
4447c478bd9Sstevel@tonic-gate #define	Get_OpReg16(addr)	ddi_get16(uhcip->uhci_regs_handle, \
4457c478bd9Sstevel@tonic-gate 				    (uint16_t *)&uhcip->uhci_regsp->addr)
4467c478bd9Sstevel@tonic-gate #define	Get_OpReg8(addr)	ddi_get8(uhcip->uhci_regs_handle, \
4477c478bd9Sstevel@tonic-gate 				    (uchar_t *)&uhcip->uhci_regsp->addr)
4487c478bd9Sstevel@tonic-gate 
4497c478bd9Sstevel@tonic-gate #define	Set_OpReg32(addr, val)	 ddi_put32(uhcip->uhci_regs_handle, \
4507c478bd9Sstevel@tonic-gate 				    ((uint32_t *)&uhcip->uhci_regsp->addr), \
4517c478bd9Sstevel@tonic-gate 				    ((int32_t)(val)))
4527c478bd9Sstevel@tonic-gate #define	Set_OpReg16(addr, val)	 ddi_put16(uhcip->uhci_regs_handle, \
4537c478bd9Sstevel@tonic-gate 				    ((uint16_t *)&uhcip->uhci_regsp->addr), \
4547c478bd9Sstevel@tonic-gate 				    ((int16_t)(val)))
4557c478bd9Sstevel@tonic-gate 
4567c478bd9Sstevel@tonic-gate #define	QH_PADDR(addr) \
4577c478bd9Sstevel@tonic-gate 		((uint32_t)(uhcip->uhci_qh_pool_cookie.dmac_address + \
4587c478bd9Sstevel@tonic-gate 		(uint32_t)((uintptr_t)(addr) - \
4597c478bd9Sstevel@tonic-gate 		(uintptr_t)uhcip->uhci_qh_pool_addr)))
4607c478bd9Sstevel@tonic-gate 
4617c478bd9Sstevel@tonic-gate 
4627c478bd9Sstevel@tonic-gate #define	QH_VADDR(addr) \
4637c478bd9Sstevel@tonic-gate 		((void *)(((uint32_t)(addr) - \
4647c478bd9Sstevel@tonic-gate 		(uint32_t)uhcip->uhci_qh_pool_cookie.dmac_address) + \
4657c478bd9Sstevel@tonic-gate 		(char *)uhcip->uhci_qh_pool_addr))
4667c478bd9Sstevel@tonic-gate 
4677c478bd9Sstevel@tonic-gate #define	TD_PADDR(addr)	\
4687c478bd9Sstevel@tonic-gate 		((uint32_t)uhcip->uhci_td_pool_cookie.dmac_address + \
4697c478bd9Sstevel@tonic-gate 		(uint32_t)((uintptr_t)(addr) - \
4707c478bd9Sstevel@tonic-gate 		(uintptr_t)(uhcip->uhci_td_pool_addr)))
4717c478bd9Sstevel@tonic-gate 
4727c478bd9Sstevel@tonic-gate #define	BULKTD_PADDR(x, addr)\
4737c478bd9Sstevel@tonic-gate 		((uint32_t)((uintptr_t)(addr) - (uintptr_t)x->pool_addr) + \
4747c478bd9Sstevel@tonic-gate 		(uint32_t)(x)->cookie.dmac_address)
4757c478bd9Sstevel@tonic-gate 
4767c478bd9Sstevel@tonic-gate #define	BULKTD_VADDR(x, addr)\
4777c478bd9Sstevel@tonic-gate 		((void *)(((uint32_t)(addr) - \
4787c478bd9Sstevel@tonic-gate 		(uint32_t)(x)->cookie.dmac_address) + \
4797c478bd9Sstevel@tonic-gate 		(char *)(x)->pool_addr))
4807c478bd9Sstevel@tonic-gate 
4817c478bd9Sstevel@tonic-gate #define	ISOCTD_PADDR(x, addr)\
4827c478bd9Sstevel@tonic-gate 		((uint32_t)((uintptr_t)(addr) - (uintptr_t)(x)->pool_addr) + \
4837c478bd9Sstevel@tonic-gate 		(uint32_t)(x)->cookie.dmac_address)
4847c478bd9Sstevel@tonic-gate 
4857c478bd9Sstevel@tonic-gate #define	TD_VADDR(addr) \
4867c478bd9Sstevel@tonic-gate 		((void *)(((uint32_t)(addr) - \
4877c478bd9Sstevel@tonic-gate 		(uint32_t)uhcip->uhci_td_pool_cookie.dmac_address) + \
4887c478bd9Sstevel@tonic-gate 		(char *)uhcip->uhci_td_pool_addr))
4897c478bd9Sstevel@tonic-gate 
4907c478bd9Sstevel@tonic-gate /*
4917c478bd9Sstevel@tonic-gate  * If the terminate bit is cleared, there shouldn't be any
4927c478bd9Sstevel@tonic-gate  * race condition problems. If the host controller reads the
4937c478bd9Sstevel@tonic-gate  * bit before the driver has a chance to set the bit, the bit
4947c478bd9Sstevel@tonic-gate  * will be reread on the next frame.
4957c478bd9Sstevel@tonic-gate  */
4967c478bd9Sstevel@tonic-gate #define	UHCI_SET_TERMINATE_BIT(addr)	\
4977c478bd9Sstevel@tonic-gate 	SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) | HC_END_OF_LIST)
4987c478bd9Sstevel@tonic-gate #define	UHCI_CLEAR_TERMINATE_BIT(addr)	\
4997c478bd9Sstevel@tonic-gate 	SetQH32(uhcip, addr, GetQH32(uhcip, (addr)) & ~HC_END_OF_LIST)
5007c478bd9Sstevel@tonic-gate 
5017c478bd9Sstevel@tonic-gate #define	UHCI_XFER_TYPE(ept)		((ept)->bmAttributes & USB_EP_ATTR_MASK)
5027c478bd9Sstevel@tonic-gate #define	UHCI_XFER_DIR(ept)		((ept)->bEndpointAddress & \
5037c478bd9Sstevel@tonic-gate 						USB_EP_DIR_MASK)
5047c478bd9Sstevel@tonic-gate 
5057c478bd9Sstevel@tonic-gate /*
5067c478bd9Sstevel@tonic-gate  * for HCD based kstats:
5077c478bd9Sstevel@tonic-gate  * uhci_intrs_stats_t structure
5087c478bd9Sstevel@tonic-gate  */
5097c478bd9Sstevel@tonic-gate typedef struct uhci_intrs_stats {
5107c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_hc_halted;
5117c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_hc_process_err;
5127c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_host_sys_err;
5137c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_resume_detected;
5147c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_usb_err_intr;
5157c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_usb_intr;
5167c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_total;
5177c478bd9Sstevel@tonic-gate 	struct kstat_named	uhci_intrs_not_claimed;
5187c478bd9Sstevel@tonic-gate } uhci_intrs_stats_t;
5197c478bd9Sstevel@tonic-gate 
5207c478bd9Sstevel@tonic-gate /*
5217c478bd9Sstevel@tonic-gate  * uhci defines for kstats
5227c478bd9Sstevel@tonic-gate  */
5237c478bd9Sstevel@tonic-gate #define	UHCI_INTRS_STATS(uhci)	((uhci)->uhci_intrs_stats)
5247c478bd9Sstevel@tonic-gate #define	UHCI_INTRS_STATS_DATA(uhci)	\
5257c478bd9Sstevel@tonic-gate 	((uhci_intrs_stats_t *)UHCI_INTRS_STATS((uhci))->ks_data)
5267c478bd9Sstevel@tonic-gate 
5277c478bd9Sstevel@tonic-gate #define	UHCI_TOTAL_STATS(uhci)		((uhci)->uhci_total_stats)
5287c478bd9Sstevel@tonic-gate #define	UHCI_TOTAL_STATS_DATA(uhci)	(KSTAT_IO_PTR((uhci)->uhci_total_stats))
5297c478bd9Sstevel@tonic-gate #define	UHCI_CTRL_STATS(uhci)	\
5307c478bd9Sstevel@tonic-gate 		(KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_CONTROL]))
5317c478bd9Sstevel@tonic-gate #define	UHCI_BULK_STATS(uhci)	\
5327c478bd9Sstevel@tonic-gate 		(KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_BULK]))
5337c478bd9Sstevel@tonic-gate #define	UHCI_INTR_STATS(uhci)	\
5347c478bd9Sstevel@tonic-gate 		(KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_INTR]))
5357c478bd9Sstevel@tonic-gate #define	UHCI_ISOC_STATS(uhci)	\
5367c478bd9Sstevel@tonic-gate 		(KSTAT_IO_PTR((uhci)->uhci_count_stats[USB_EP_ATTR_ISOCH]))
5377c478bd9Sstevel@tonic-gate 
5387c478bd9Sstevel@tonic-gate #define	UHCI_UNIT(dev)	(getminor((dev)) & ~HUBD_IS_ROOT_HUB)
5397c478bd9Sstevel@tonic-gate 
5407c478bd9Sstevel@tonic-gate #define	UHCI_PERIODIC_ENDPOINT(ept) \
5417c478bd9Sstevel@tonic-gate 	(((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) || \
5427c478bd9Sstevel@tonic-gate 	((((ept)->bmAttributes) & USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH))
5437c478bd9Sstevel@tonic-gate 
544fffe0b30Sqz /*
545fffe0b30Sqz  * Host Contoller Software States
546fffe0b30Sqz  *
547fffe0b30Sqz  * UHCI_CTLR_INIT_STATE:
548fffe0b30Sqz  *      The host controller soft state will be set to this during the
549fffe0b30Sqz  *      uhci_attach.
550fffe0b30Sqz  *
551fffe0b30Sqz  * UHCI_CTLR_SUSPEND_STATE:
552fffe0b30Sqz  *      The host controller soft state will be set to this during the
553fffe0b30Sqz  *      uhci_cpr_suspend.
554fffe0b30Sqz  *
555fffe0b30Sqz  * UHCI_CTLR_OPERATIONAL_STATE:
556fffe0b30Sqz  *      The host controller soft state will be set to this after moving
557fffe0b30Sqz  *      host controller to operational state and host controller start
558fffe0b30Sqz  *      generating SOF successfully.
559fffe0b30Sqz  *
560fffe0b30Sqz  * UHCI_CTLR_ERROR_STATE:
561fffe0b30Sqz  *      The host controller soft state will be set to this during the
562fffe0b30Sqz  *      hardware error or no SOF conditions.
563fffe0b30Sqz  *
564fffe0b30Sqz  *      Under non-operational state, only pipe stop polling, pipe reset
565fffe0b30Sqz  *      and pipe close are allowed. But all other entry points like pipe
566fffe0b30Sqz  *      open, get/set pipe policy, cotrol send/receive, bulk send/receive
567fffe0b30Sqz  *      isoch send/receive, start polling etc. will fail.
568fffe0b30Sqz  */
569fffe0b30Sqz #define	UHCI_CTLR_INIT_STATE		0	/* Initilization state */
570fffe0b30Sqz #define	UHCI_CTLR_SUSPEND_STATE		1	/* Suspend state */
571fffe0b30Sqz #define	UHCI_CTLR_OPERATIONAL_STATE	2	/* Operational state */
572fffe0b30Sqz #define	UHCI_CTLR_ERROR_STATE		3	/* Hardware error */
573fffe0b30Sqz 
5747c478bd9Sstevel@tonic-gate /*
5757c478bd9Sstevel@tonic-gate  * Debug printing Masks
5767c478bd9Sstevel@tonic-gate  */
5777c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ATTA		0x00000001	/* Attach time */
5787c478bd9Sstevel@tonic-gate #define	PRINT_MASK_LISTS	0x00000002	/* List management */
5797c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ROOT_HUB	0x00000004	/* Root hub stuff */
5807c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ALLOC	0x00000008	/* Alloc/dealloc descr */
5817c478bd9Sstevel@tonic-gate #define	PRINT_MASK_INTR		0x00000010	/* Interrupt handling */
5827c478bd9Sstevel@tonic-gate #define	PRINT_MASK_BW		0x00000020	/* Bandwidth */
5837c478bd9Sstevel@tonic-gate #define	PRINT_MASK_CBOPS	0x00000040	/* CB-OPS */
5847c478bd9Sstevel@tonic-gate #define	PRINT_MASK_HCDI		0x00000080	/* HCDI entry points */
5857c478bd9Sstevel@tonic-gate #define	PRINT_MASK_DUMPING	0x00000100	/* Dump HCD state info */
5867c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ISOC		0x00000200	/* For ISOC xfers */
5877c478bd9Sstevel@tonic-gate 
5887c478bd9Sstevel@tonic-gate #define	PRINT_MASK_ALL		0xFFFFFFFF
5897c478bd9Sstevel@tonic-gate 
5907c478bd9Sstevel@tonic-gate #ifdef __cplusplus
5917c478bd9Sstevel@tonic-gate }
5927c478bd9Sstevel@tonic-gate #endif
5937c478bd9Sstevel@tonic-gate 
5947c478bd9Sstevel@tonic-gate #endif	/* _SYS_USB_UHCID_H */
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