1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_UHCI_H 28 #define _SYS_USB_UHCI_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/types.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * Universal Host Controller Driver (UHCI) 40 * 41 * The UHCI driver is a driver which interfaces to the Universal 42 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 43 * the Host Controller is defined by the Universal Host Controller 44 * Interface spec. 45 */ 46 47 48 #define LEGACYMODE_REG_OFFSET 0xc0 49 #define LEGACYMODE_REG_INIT_VALUE 0xaf00 50 51 /* 52 * The register set of the UCHI controller 53 * This structure is laid out for proper alignment so no need to pack(1). 54 */ 55 typedef volatile struct hcr_regs { 56 uint16_t USBCMD; 57 uint16_t USBSTS; 58 uint16_t USBINTR; 59 uint16_t FRNUM; 60 uint32_t FRBASEADD; 61 uchar_t SOFMOD; 62 uchar_t rsvd[3]; 63 uint16_t PORTSC[2]; 64 } hc_regs_t; 65 66 /* 67 * #defines for the USB Command Register 68 */ 69 #define USBCMD_REG_MAXPKT_64 0x0080 70 #define USBCMD_REG_CONFIG_FLAG 0x0040 71 #define USBCMD_REG_SW_DEBUG 0x0020 72 #define USBCMD_REG_FGBL_RESUME 0x0010 73 #define USBCMD_REG_ENER_GBL_SUSPEND 0x0008 74 #define USBCMD_REG_GBL_RESET 0x0004 75 #define USBCMD_REG_HC_RESET 0x0002 76 #define USBCMD_REG_HC_RUN 0x0001 77 78 79 /* 80 * #defines for the USB Status Register 81 */ 82 #define USBSTS_REG_HC_HALTED 0x0020 83 #define USBSTS_REG_HC_PROCESS_ERR 0x0010 84 #define USBSTS_REG_HOST_SYS_ERR 0x0008 85 #define USBSTS_REG_RESUME_DETECT 0x0004 86 #define USBSTS_REG_USB_ERR_INTR 0x0002 87 #define USBSTS_REG_USB_INTR 0x0001 88 89 /* 90 * #defines for the USB Root Hub Port Register 91 */ 92 #define HCR_PORT_CCS 0x1 93 #define HCR_PORT_CSC 0x2 94 #define HCR_PORT_ENABLE 0x4 95 #define HCR_PORT_ENDIS_CHG 0x8 96 #define HCR_PORT_LINE_STATSU 0x30 97 #define HCR_PORT_RESUME_DETECT 0x40 98 #define HCR_PORT_LSDA 0x100 99 #define HCR_PORT_RESET 0x200 100 #define HCR_PORT_SUSPEND 0x1000 101 102 /* 103 * #defines for USB Interrupt Enable Register 104 */ 105 #define USBINTR_REG_SPINT_EN 0x0008 106 #define USBINTR_REG_IOC_EN 0x0004 107 #define USBINTR_REG_RESUME_INT_EN 0x0002 108 #define USBINTR_REG_TOCRC_INT_EN 0x0001 109 110 #define ENABLE_ALL_INTRS 0x000F 111 #define DISABLE_ALL_INTRS 0x0000 112 #define UHCI_INTR_MASK 0x3f 113 114 115 #define SetReg32(hndl, addr, val) ddi_put32((hndl), \ 116 &(addr), (val)) 117 #define GetReg32(hndl, addr) ddi_get32((hndl), &(addr)) 118 119 #define SetQH32(ucp, addr, val) \ 120 SetReg32((ucp)->uhci_qh_pool_mem_handle, (addr), (val)) 121 #define GetQH32(ucp, addr) \ 122 GetReg32((ucp)->uhci_qh_pool_mem_handle, (addr)) 123 124 #define SetTD32(ucp, addr, val) \ 125 SetReg32((ucp)->uhci_td_pool_mem_handle, (addr), (val)) 126 #define GetTD32(ucp, addr) \ 127 GetReg32((ucp)->uhci_td_pool_mem_handle, (addr)) 128 129 #define SetFL32(ucp, addr, val) \ 130 SetReg32((ucp)->uhci_flt_mem_handle, (addr), (val)) 131 #define GetFL32(ucp, addr) \ 132 GetReg32((ucp)->uhci_flt_mem_handle, (addr)) 133 134 135 /* 136 * UHCI Queue Head structure, aligned on 16 byte boundary 137 */ 138 typedef struct uhci_qh { 139 /* Hardware controlled bits */ 140 uint32_t link_ptr; /* Next Queue Head / TD */ 141 uint32_t element_ptr; /* Next queue head / TD */ 142 143 /* Software controlled bits */ 144 uint16_t node; /* Node that its attached */ 145 uint16_t qh_flag; /* See below */ 146 147 struct uhci_qh *prev_qh; /* Pointer to Prev queue head */ 148 struct uhci_td *td_tailp; /* Pointer to the last TD of QH */ 149 struct uhci_bulk_isoc_xfer_info *bulk_xfer_info; 150 uint64_t __pad1; /* align to 16 bytes */ 151 } queue_head_t; 152 153 #define NUM_STATIC_NODES 63 154 #define NUM_INTR_QH_LISTS 64 155 #define NUM_FRAME_LST_ENTRIES 1024 156 #define TREE_HEIGHT 5 157 #define VIRTUAL_TREE_HEIGHT 5 158 #define SIZE_OF_FRAME_LST_TABLE 1024 * 4 159 160 #define HC_TD_HEAD 0x0 161 #define HC_QUEUE_HEAD 0x2 162 #define HC_DEPTH_FIRST 0x4 163 #define HC_END_OF_LIST 0x1 164 165 #define QUEUE_HEAD_FLAG_STATIC 0x1 166 #define QUEUE_HEAD_FLAG_FREE 0x2 167 #define QUEUE_HEAD_FLAG_BUSY 0x3 168 169 #define QH_LINK_PTR_MASK 0xFFFFFFF0 170 #define QH_ELEMENT_PTR_MASK 0xFFFFFFF0 171 #define FRAME_LST_PTR_MASK 0xFFFFFFF0 172 173 174 #define GetField(u, td, f, o, l) \ 175 ((GetTD32(u, (td)->f) >> (o)) & ((1U<<l)-1)) 176 177 #define SetField(u, td, f, o, l, v) \ 178 SetTD32(u, (td)->f, \ 179 (GetTD32(u, (td)->f) & ~(((1U<<l)-1) << o)) | \ 180 (((v) & ((1U<<l)-1)) << o)) 181 182 #define GetTD_alen(u, td) GetField((u), (td), dw2, 0, 11) 183 #define GetTD_status(u, td) GetField((u), (td), dw2, 16, 8) 184 #define GetTD_ioc(u, td) GetField((u), (td), dw2, 24, 1) 185 #define GetTD_iso(u, td) GetField((u), (td), dw2, 25, 1) 186 #define GetTD_ls(u, td) GetField((u), (td), dw2, 26, 1) 187 #define GetTD_c_err(u, td) GetField((u), (td), dw2, 27, 2) 188 #define GetTD_spd(u, td) GetField((u), (td), dw2, 29, 1) 189 #define GetTD_PID(u, td) GetField((u), (td), dw3, 0, 8) 190 #define GetTD_devaddr(u, td) GetField((u), (td), dw3, 8, 7) 191 #define GetTD_endpt(u, td) GetField((u), (td), dw3, 15, 4) 192 #define GetTD_dtogg(u, td) GetField((u), (td), dw3, 19, 1) 193 #define GetTD_mlen(u, td) GetField((u), (td), dw3, 21, 11) 194 195 #define SetTD_alen(u, td, v) SetField((u), (td), dw2, 0, 11, (v)) 196 #define SetTD_status(u, td, v) SetField((u), (td), dw2, 16, 8, (v)) 197 #define SetTD_ioc(u, td, v) SetField((u), (td), dw2, 24, 1, (v)) 198 #define SetTD_iso(u, td, v) SetField((u), (td), dw2, 25, 1, (v)) 199 #define SetTD_ls(u, td, v) SetField((u), (td), dw2, 26, 1, (v)) 200 #define SetTD_c_err(u, td, v) SetField((u), (td), dw2, 27, 2, (v)) 201 #define SetTD_spd(u, td, v) SetField((u), (td), dw2, 29, 1, (v)) 202 #define SetTD_PID(u, td, v) SetField((u), (td), dw3, 0, 8, (v)) 203 #define SetTD_devaddr(u, td, v) SetField((u), (td), dw3, 8, 7, (v)) 204 #define SetTD_endpt(u, td, v) SetField((u), (td), dw3, 15, 4, (v)) 205 #define SetTD_dtogg(u, td, v) SetField((u), (td), dw3, 19, 1, (v)) 206 #define SetTD_mlen(u, td, v) SetField((u), (td), dw3, 21, 11, (v)) 207 208 /* 209 * UHCI Transfer Descriptor structure, aligned on 16 byte boundary 210 */ 211 typedef struct uhci_td { 212 213 /* Information required by HC for executing the request */ 214 /* Pointer to the next TD/QH */ 215 uint32_t link_ptr; 216 uint32_t dw2; 217 uint32_t dw3; 218 /* Data buffer address */ 219 uint32_t buffer_address; 220 221 /* Information required by HCD for managing the request */ 222 struct uhci_td *qh_td_prev; 223 struct uhci_td *tw_td_next; 224 struct uhci_td *outst_td_next; 225 struct uhci_td *outst_td_prev; 226 struct uhci_trans_wrapper *tw; 227 struct uhci_td *isoc_next; 228 struct uhci_td *isoc_prev; 229 ushort_t isoc_pkt_index; 230 ushort_t flag; 231 uint_t starting_frame; 232 uint_t _pad[3]; /* 16 byte alignment */ 233 } uhci_td_t; 234 235 #define TD_FLAG_FREE 0x1 236 #define TD_FLAG_BUSY 0x2 237 #define TD_FLAG_DUMMY 0x3 238 239 #define INTERRUPT_ON_COMPLETION 0x1 240 #define END_POINT_ADDRESS_MASK 0xF 241 #define UHCI_MAX_ERR_COUNT 3 242 #define MAX_NUM_BULK_TDS_PER_XFER 128 243 244 /* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */ 245 #define UHCI_TD_ACTIVE 0x80 246 #define UHCI_TD_STALLED 0x40 247 #define UHCI_TD_DATA_BUFFER_ERR 0x20 248 #define UHCI_TD_BABBLE_ERR 0x10 249 #define UHCI_TD_NAK_RECEIVED 0x08 250 #define UHCI_TD_CRC_TIMEOUT 0x04 251 #define UHCI_TD_BITSTUFF_ERR 0x02 252 253 #define TD_INACTIVE 0x7F 254 #define TD_STATUS_MASK 0x76 255 #define ZERO_LENGTH 0x7FF 256 257 #define PID_SETUP 0x2D 258 #define PID_IN 0x69 259 #define PID_OUT 0xe1 260 261 #define SETUP_SIZE 8 262 263 #define SETUP 0x11 264 #define DATA 0x12 265 #define STATUS 0x13 266 267 #define UHCI_INVALID_PTR NULL 268 #define LOW_SPEED_DEVICE 1 269 270 /* 271 * These provide synchronization between TD deletions. 272 */ 273 #define UHCI_NOT_CLAIMED 0x0 274 #define UHCI_INTR_HDLR_CLAIMED 0x1 275 #define UHCI_MODIFY_TD_BITS_CLAIMED 0x2 276 #define UHCI_TIMEOUT_HDLR_CLAIMED 0x3 277 278 279 /* 280 * Structure for Bulk and Isoc transfers 281 */ 282 typedef struct uhci_bulk_isoc_xfer_info { 283 caddr_t pool_addr; 284 ddi_dma_cookie_t cookie; /* DMA cookie */ 285 ddi_dma_handle_t dma_handle; /* DMA handle */ 286 ddi_acc_handle_t mem_handle; /* Memory handle */ 287 ushort_t num_tds; 288 } uhci_bulk_isoc_xfer_t; 289 290 /* 291 * Macros related to ISOC transfers 292 */ 293 #define UHCI_SIZE_OF_HW_FRNUM 11 294 #define UHCI_BIT_10_MASK 0x400 295 #define UHCI_MAX_ISOC_FRAMES 1024 296 #define UHCI_MAX_ISOC_PKTS 256 297 #define UHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 298 299 #define FRNUM_MASK 0x3FF 300 #define SW_FRNUM_MASK 0xFFFFFFFFFFFFF800 301 #define INVALID_FRNUM 0 302 #define FRNUM_OFFSET 5 303 #define MAX_FRAME_NUM 1023 304 305 typedef uint32_t frame_lst_table_t; 306 307 /* 308 * Bandwidth allocation 309 * The following definitions are used during bandwidth 310 * calculations for a given endpoint maximum packet size. 311 */ 312 #define MAX_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 313 #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 314 #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 315 #define SOF 6 /* Length in bytes of SOF */ 316 #define EOF 2 /* Length in bytes of EOF */ 317 318 /* 319 * Minimum polling interval for low speed endpoint 320 * 321 * According USB Specifications, a full-speed endpoint can specify 322 * a desired polling interval 1ms to 255ms and a low speed endpoints 323 * are limited to specifying only 10ms to 255ms. But some old keyboards 324 * and mice uses polling interval of 8ms. For compatibility purpose, 325 * we are using polling interval between 8ms and 255ms for low speed 326 * endpoints. 327 */ 328 #define MIN_LOW_SPEED_POLL_INTERVAL 8 329 330 /* 331 * For non-periodic transfers, reserve at least for one low-speed device 332 * transaction and according to USB Bandwidth Analysis white paper, it 333 * comes around 12% of USB frame time. Then periodic transfers will get 334 * 88% of USB frame time. 335 */ 336 #define MAX_PERIODIC_BANDWIDTH (((MAX_BUS_BANDWIDTH - SOF - EOF)*88)/100) 337 338 /* 339 * The following are the protocol overheads in terms of Bytes for the 340 * different transfer types. All these protocol overhead values are 341 * derived from the 5.9.3 section of USB Specification and with the 342 * help of Bandwidth Analysis white paper which is posted on the USB 343 * developer forum. 344 */ 345 #define FS_NON_ISOC_PROTO_OVERHEAD 14 346 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 347 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 348 #define LOW_SPEED_PROTO_OVERHEAD 97 349 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 350 351 /* 352 * The Host Controller (HC) delays are the USB host controller specific 353 * delays. The value shown below is the host controller delay for the 354 * Sand core USB host controller. 355 */ 356 #define HOST_CONTROLLER_DELAY 18 357 358 /* 359 * The low speed clock below represents that to transmit one low-speed 360 * bit takes eight times more than one full speed bit time. 361 */ 362 #define LOW_SPEED_CLOCK 8 363 364 /* the 16 byte alignment is required for every TD and QH start addr */ 365 #define UHCI_QH_ALIGN_SZ 16 366 #define UHCI_TD_ALIGN_SZ 16 367 368 #ifdef __cplusplus 369 } 370 #endif 371 372 #endif /* _SYS_USB_UHCI_H */ 373