xref: /illumos-gate/usr/src/uts/common/sys/usb/hcd/uhci/uhci.h (revision 02acac7e)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_USB_UHCI_H
27 #define	_SYS_USB_UHCI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/types.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 /*
38  * Universal Host Controller Driver (UHCI)
39  *
40  * The UHCI driver is a driver which interfaces to the Universal
41  * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
42  * the Host Controller is defined by the Universal Host Controller
43  * Interface spec.
44  */
45 
46 
47 #define	LEGACYMODE_REG_OFFSET		0xc0
48 #define	LEGACYMODE_REG_INIT_VALUE	0xaf00
49 
50 /*
51  *   The register set of the UCHI controller
52  *   This structure is laid out for proper alignment so no need to pack(1).
53  */
54 typedef volatile struct hcr_regs {
55 	uint16_t	USBCMD;
56 	uint16_t	USBSTS;
57 	uint16_t	USBINTR;
58 	uint16_t	FRNUM;
59 	uint32_t	FRBASEADD;
60 	uchar_t		SOFMOD;
61 	uchar_t		rsvd[3];
62 	uint16_t	PORTSC[2];
63 } hc_regs_t;
64 
65 /*
66  * #defines for the USB Command Register
67  */
68 #define	USBCMD_REG_MAXPKT_64		0x0080
69 #define	USBCMD_REG_CONFIG_FLAG		0x0040
70 #define	USBCMD_REG_SW_DEBUG		0x0020
71 #define	USBCMD_REG_FGBL_RESUME		0x0010
72 #define	USBCMD_REG_ENER_GBL_SUSPEND	0x0008
73 #define	USBCMD_REG_GBL_RESET		0x0004
74 #define	USBCMD_REG_HC_RESET		0x0002
75 #define	USBCMD_REG_HC_RUN		0x0001
76 
77 
78 /*
79  * #defines for the USB Status Register
80  */
81 #define	USBSTS_REG_HC_HALTED		0x0020
82 #define	USBSTS_REG_HC_PROCESS_ERR	0x0010
83 #define	USBSTS_REG_HOST_SYS_ERR 	0x0008
84 #define	USBSTS_REG_RESUME_DETECT	0x0004
85 #define	USBSTS_REG_USB_ERR_INTR		0x0002
86 #define	USBSTS_REG_USB_INTR		0x0001
87 
88 /*
89  * #defines for the USB Root Hub Port Register
90  */
91 #define	HCR_PORT_CCS			0x1
92 #define	HCR_PORT_CSC			0x2
93 #define	HCR_PORT_ENABLE			0x4
94 #define	HCR_PORT_ENDIS_CHG		0x8
95 #define	HCR_PORT_LINE_STATSU		0x30
96 #define	HCR_PORT_RESUME_DETECT		0x40
97 #define	HCR_PORT_LSDA			0x100
98 #define	HCR_PORT_RESET			0x200
99 #define	HCR_PORT_SUSPEND		0x1000
100 
101 /*
102  * #defines for USB Interrupt Enable Register
103  */
104 #define	USBINTR_REG_SPINT_EN		0x0008
105 #define	USBINTR_REG_IOC_EN		0x0004
106 #define	USBINTR_REG_RESUME_INT_EN	0x0002
107 #define	USBINTR_REG_TOCRC_INT_EN	0x0001
108 
109 #define	ENABLE_ALL_INTRS		0x000F
110 #define	DISABLE_ALL_INTRS		0x0000
111 #define	UHCI_INTR_MASK			0x3f
112 
113 
114 #define	SetReg32(hndl, addr, val)	ddi_put32((hndl), \
115 						&(addr), (val))
116 #define	GetReg32(hndl, addr)		ddi_get32((hndl), &(addr))
117 
118 #define	SetQH32(ucp, addr, val)		\
119 		SetReg32((ucp)->uhci_qh_pool_mem_handle, (addr), (val))
120 #define	GetQH32(ucp, addr)		\
121 		GetReg32((ucp)->uhci_qh_pool_mem_handle, (addr))
122 
123 #define	SetTD32(ucp, addr, val)		\
124 		SetReg32((ucp)->uhci_td_pool_mem_handle, (addr), (val))
125 #define	GetTD32(ucp, addr)		\
126 		GetReg32((ucp)->uhci_td_pool_mem_handle, (addr))
127 
128 #define	SetFL32(ucp, addr, val)		\
129 		SetReg32((ucp)->uhci_flt_mem_handle, (addr), (val))
130 #define	GetFL32(ucp, addr)		\
131 		GetReg32((ucp)->uhci_flt_mem_handle, (addr))
132 
133 
134 /*
135  * UHCI Queue Head structure, aligned on 16 byte boundary
136  */
137 typedef struct uhci_qh {
138 	/* Hardware controlled bits */
139 	uint32_t		link_ptr;	/* Next Queue Head / TD */
140 	uint32_t		element_ptr;	/* Next queue head / TD	*/
141 
142 	/* Software controlled bits */
143 	uint16_t	node;		/* Node	that its attached */
144 	uint16_t	qh_flag;	/* See	below */
145 
146 	struct	uhci_qh	*prev_qh;	/* Pointer to Prev queue head */
147 	struct	uhci_td	*td_tailp;	/* Pointer to the last TD of QH	*/
148 	struct	uhci_bulk_isoc_xfer_info *bulk_xfer_info;
149 	uint64_t	__pad1;		/* align to 16 bytes */
150 } queue_head_t;
151 
152 #define	NUM_STATIC_NODES		63
153 #define	NUM_INTR_QH_LISTS		64
154 #define	NUM_FRAME_LST_ENTRIES		1024
155 #define	TREE_HEIGHT			5
156 #define	VIRTUAL_TREE_HEIGHT		5
157 #define	SIZE_OF_FRAME_LST_TABLE		1024 * 4
158 
159 #define	HC_TD_HEAD			0x0
160 #define	HC_QUEUE_HEAD			0x2
161 #define	HC_DEPTH_FIRST			0x4
162 #define	HC_END_OF_LIST			0x1
163 
164 #define	QUEUE_HEAD_FLAG_STATIC		0x1
165 #define	QUEUE_HEAD_FLAG_FREE		0x2
166 #define	QUEUE_HEAD_FLAG_BUSY		0x3
167 
168 #define	QH_LINK_PTR_MASK		0xFFFFFFF0
169 #define	QH_ELEMENT_PTR_MASK		0xFFFFFFF0
170 #define	FRAME_LST_PTR_MASK		0xFFFFFFF0
171 
172 
173 #define	GetField(u, td, f, o, l) \
174 	((GetTD32(u, (td)->f) >> (o)) & ((1U<<l)-1))
175 
176 #define	SetField(u, td, f, o, l, v) \
177 	SetTD32(u, (td)->f, \
178 	(GetTD32(u, (td)->f) & ~(((1U<<l)-1) << o)) | \
179 	(((v) & ((1U<<l)-1)) << o))
180 
181 #define	GetTD_alen(u, td)	GetField((u), (td), dw2, 0, 11)
182 #define	GetTD_status(u, td)	GetField((u), (td), dw2, 16, 8)
183 #define	GetTD_ioc(u, td)	GetField((u), (td), dw2, 24, 1)
184 #define	GetTD_iso(u, td)	GetField((u), (td), dw2, 25, 1)
185 #define	GetTD_ls(u, td)		GetField((u), (td), dw2, 26, 1)
186 #define	GetTD_c_err(u, td)	GetField((u), (td), dw2, 27, 2)
187 #define	GetTD_spd(u, td)	GetField((u), (td), dw2, 29, 1)
188 #define	GetTD_PID(u, td)	GetField((u), (td), dw3, 0, 8)
189 #define	GetTD_devaddr(u, td)	GetField((u), (td), dw3, 8, 7)
190 #define	GetTD_endpt(u, td)	GetField((u), (td), dw3, 15, 4)
191 #define	GetTD_dtogg(u, td)	GetField((u), (td), dw3, 19, 1)
192 #define	GetTD_mlen(u, td)	GetField((u), (td), dw3, 21, 11)
193 
194 #define	SetTD_alen(u, td, v)	SetField((u), (td), dw2, 0, 11, (v))
195 #define	SetTD_status(u, td, v)	SetField((u), (td), dw2, 16, 8, (v))
196 #define	SetTD_ioc(u, td, v)	SetField((u), (td), dw2, 24, 1, (v))
197 #define	SetTD_iso(u, td, v)	SetField((u), (td), dw2, 25, 1, (v))
198 #define	SetTD_ls(u, td, v)	SetField((u), (td), dw2, 26, 1, (v))
199 #define	SetTD_c_err(u, td, v)	SetField((u), (td), dw2, 27, 2, (v))
200 #define	SetTD_spd(u, td, v)	SetField((u), (td), dw2, 29, 1, (v))
201 #define	SetTD_PID(u, td, v)	SetField((u), (td), dw3, 0, 8, (v))
202 #define	SetTD_devaddr(u, td, v)	SetField((u), (td), dw3, 8, 7, (v))
203 #define	SetTD_endpt(u, td, v)	SetField((u), (td), dw3, 15, 4, (v))
204 #define	SetTD_dtogg(u, td, v)	SetField((u), (td), dw3, 19, 1, (v))
205 #define	SetTD_mlen(u, td, v)	SetField((u), (td), dw3, 21, 11, (v))
206 
207 /*
208  * UHCI Transfer Descriptor structure, aligned on 16 byte boundary
209  */
210 typedef struct uhci_td {
211 
212 	/* Information required by HC for executing the request */
213 					/* Pointer to the next TD/QH */
214 	uint32_t			link_ptr;
215 	uint32_t			dw2;
216 	uint32_t			dw3;
217 					/* Data buffer address */
218 	uint32_t			buffer_address;
219 
220 	/* Information required by HCD for managing the request */
221 	struct	uhci_td			*qh_td_prev;
222 	struct	uhci_td			*tw_td_next;
223 	struct	uhci_td			*outst_td_next;
224 	struct	uhci_td			*outst_td_prev;
225 	struct	uhci_trans_wrapper	*tw;
226 	struct	uhci_td			*isoc_next;
227 	struct	uhci_td			*isoc_prev;
228 	ushort_t			isoc_pkt_index;
229 	ushort_t			flag;
230 	uint_t				starting_frame;
231 	uint_t				_pad[3];	/* 16 byte alignment */
232 } uhci_td_t;
233 
234 #define	TD_FLAG_FREE			0x1
235 #define	TD_FLAG_BUSY			0x2
236 #define	TD_FLAG_DUMMY			0x3
237 
238 #define	INTERRUPT_ON_COMPLETION		0x1
239 #define	END_POINT_ADDRESS_MASK		0xF
240 #define	UHCI_MAX_ERR_COUNT		3
241 #define	MAX_NUM_BULK_TDS_PER_XFER	128
242 
243 /* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */
244 #define	UHCI_TD_ACTIVE			0x80
245 #define	UHCI_TD_STALLED			0x40
246 #define	UHCI_TD_DATA_BUFFER_ERR		0x20
247 #define	UHCI_TD_BABBLE_ERR		0x10
248 #define	UHCI_TD_NAK_RECEIVED		0x08
249 #define	UHCI_TD_CRC_TIMEOUT		0x04
250 #define	UHCI_TD_BITSTUFF_ERR		0x02
251 
252 #define	TD_INACTIVE			0x7F
253 #define	TD_STATUS_MASK			0x76
254 #define	ZERO_LENGTH			0x7FF
255 
256 #define	PID_SETUP			0x2D
257 #define	PID_IN				0x69
258 #define	PID_OUT				0xe1
259 
260 #define	SETUP_SIZE			8
261 
262 #define	SETUP				0x11
263 #define	DATA				0x12
264 #define	STATUS				0x13
265 
266 #define	UHCI_INVALID_PTR		NULL
267 #define	LOW_SPEED_DEVICE		1
268 
269 /*
270  * These provide synchronization between TD deletions.
271  */
272 #define	UHCI_NOT_CLAIMED		0x0
273 #define	UHCI_INTR_HDLR_CLAIMED		0x1
274 #define	UHCI_MODIFY_TD_BITS_CLAIMED	0x2
275 #define	UHCI_TIMEOUT_HDLR_CLAIMED	0x3
276 
277 
278 /*
279  * Structure for Bulk and Isoc TD pools
280  */
281 typedef struct uhci_bulk_isoc_td_pool {
282 	caddr_t				pool_addr;
283 	ddi_dma_cookie_t		cookie;	    /* DMA cookie */
284 	ddi_dma_handle_t		dma_handle; /* DMA handle */
285 	ddi_acc_handle_t		mem_handle; /* Memory handle */
286 	ushort_t			num_tds;
287 } uhci_bulk_isoc_td_pool_t;
288 
289 /*
290  *  Structure for Bulk and Isoc transfers
291  */
292 typedef struct uhci_bulk_isoc_xfer_info {
293 	uhci_bulk_isoc_td_pool_t	*td_pools;
294 	ushort_t			num_pools;
295 	ushort_t			num_tds;
296 } uhci_bulk_isoc_xfer_t;
297 
298 /*
299  * Structure for Isoc DMA buffer
300  *	One Isoc transfer includes multiple Isoc packets.
301  *	One DMA buffer is allocated for one packet each.
302  */
303 typedef struct uhci_isoc_buf {
304 	caddr_t			buf_addr;	/* Starting buffer address */
305 	ddi_dma_cookie_t	cookie;		/* DMA cookie */
306 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
307 	ddi_acc_handle_t	mem_handle;	/* Memory handle */
308 	size_t			length;		/* Buffer length */
309 	ushort_t		index;
310 } uhci_isoc_buf_t;
311 
312 /*
313  * Macros related to ISOC transfers
314  */
315 #define	UHCI_SIZE_OF_HW_FRNUM		11
316 #define	UHCI_BIT_10_MASK		0x400
317 #define	UHCI_MAX_ISOC_FRAMES		1024
318 #define	UHCI_MAX_ISOC_PKTS		256
319 #define	UHCI_DEFAULT_ISOC_RCV_PKTS	1	/* isoc pkts per req */
320 
321 #define	FRNUM_MASK			0x3FF
322 #define	SW_FRNUM_MASK			0xFFFFFFFFFFFFF800
323 #define	INVALID_FRNUM			0
324 #define	FRNUM_OFFSET			5
325 #define	MAX_FRAME_NUM			1023
326 
327 typedef	uint32_t frame_lst_table_t;
328 
329 /*
330  * Bandwidth allocation
331  *	The following definitions are  used during  bandwidth
332  *	calculations for a given endpoint maximum packet size.
333  */
334 #define	MAX_BUS_BANDWIDTH	1500	/* Up to 1500 bytes per frame */
335 #define	MAX_POLL_INTERVAL	255	/* Maximum polling interval */
336 #define	MIN_POLL_INTERVAL	1	/* Minimum polling interval */
337 #define	SOF			6	/* Length in bytes of SOF */
338 #define	EOF			2	/* Length in bytes of EOF */
339 
340 /*
341  * Minimum polling interval for low speed endpoint
342  *
343  * According USB Specifications, a full-speed endpoint can specify
344  * a desired polling interval 1ms to 255ms and a low speed endpoints
345  * are limited to specifying only 10ms to 255ms. But some old keyboards
346  * and mice uses polling interval of 8ms. For compatibility purpose,
347  * we are using polling interval between 8ms and 255ms for low speed
348  * endpoints.
349  */
350 #define	MIN_LOW_SPEED_POLL_INTERVAL	8
351 
352 /*
353  * For non-periodic transfers, reserve at least for one low-speed device
354  * transaction and according to USB Bandwidth Analysis white paper,  it
355  * comes around 12% of USB frame time. Then periodic transfers will get
356  * 88% of USB frame time.
357  */
358 #define	MAX_PERIODIC_BANDWIDTH	(((MAX_BUS_BANDWIDTH - SOF - EOF)*88)/100)
359 
360 /*
361  * The following are the protocol overheads in terms of Bytes for the
362  * different transfer types.  All these protocol overhead  values are
363  * derived from the 5.9.3 section of USB Specification	and  with the
364  * help of Bandwidth Analysis white paper which is posted on the  USB
365  * developer forum.
366  */
367 #define	FS_NON_ISOC_PROTO_OVERHEAD	14
368 #define	FS_ISOC_INPUT_PROTO_OVERHEAD	11
369 #define	FS_ISOC_OUTPUT_PROTO_OVERHEAD	10
370 #define	LOW_SPEED_PROTO_OVERHEAD	97
371 #define	HUB_LOW_SPEED_PROTO_OVERHEAD	01
372 
373 /*
374  * The Host Controller (HC) delays are the USB host controller specific
375  * delays. The value shown below is the host  controller delay for  the
376  * Sand core USB host controller.
377  */
378 #define	HOST_CONTROLLER_DELAY		18
379 
380 /*
381  * The low speed clock below represents that to transmit one low-speed
382  * bit takes eight times more than one full speed bit time.
383  */
384 #define	LOW_SPEED_CLOCK			8
385 
386 /* the 16 byte alignment is required for every TD and QH start addr */
387 #define	UHCI_QH_ALIGN_SZ		16
388 #define	UHCI_TD_ALIGN_SZ		16
389 
390 #ifdef __cplusplus
391 }
392 #endif
393 
394 #endif /* _SYS_USB_UHCI_H */
395