1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_UHCI_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_USB_UHCI_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*7c478bd9Sstevel@tonic-gate 32*7c478bd9Sstevel@tonic-gate #include <sys/types.h> 33*7c478bd9Sstevel@tonic-gate 34*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 35*7c478bd9Sstevel@tonic-gate extern "C" { 36*7c478bd9Sstevel@tonic-gate #endif 37*7c478bd9Sstevel@tonic-gate 38*7c478bd9Sstevel@tonic-gate /* 39*7c478bd9Sstevel@tonic-gate * Universal Host Controller Driver (UHCI) 40*7c478bd9Sstevel@tonic-gate * 41*7c478bd9Sstevel@tonic-gate * The UHCI driver is a driver which interfaces to the Universal 42*7c478bd9Sstevel@tonic-gate * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 43*7c478bd9Sstevel@tonic-gate * the Host Controller is defined by the Universal Host Controller 44*7c478bd9Sstevel@tonic-gate * Interface spec. 45*7c478bd9Sstevel@tonic-gate */ 46*7c478bd9Sstevel@tonic-gate 47*7c478bd9Sstevel@tonic-gate 48*7c478bd9Sstevel@tonic-gate #define LEGACYMODE_REG_OFFSET 0xc0 49*7c478bd9Sstevel@tonic-gate #define LEGACYMODE_REG_INIT_VALUE 0xaf00 50*7c478bd9Sstevel@tonic-gate 51*7c478bd9Sstevel@tonic-gate /* 52*7c478bd9Sstevel@tonic-gate * The register set of the UCHI controller 53*7c478bd9Sstevel@tonic-gate * This structure is laid out for proper alignment so no need to pack(1). 54*7c478bd9Sstevel@tonic-gate */ 55*7c478bd9Sstevel@tonic-gate typedef volatile struct hcr_regs { 56*7c478bd9Sstevel@tonic-gate uint16_t USBCMD; 57*7c478bd9Sstevel@tonic-gate uint16_t USBSTS; 58*7c478bd9Sstevel@tonic-gate uint16_t USBINTR; 59*7c478bd9Sstevel@tonic-gate uint16_t FRNUM; 60*7c478bd9Sstevel@tonic-gate uint32_t FRBASEADD; 61*7c478bd9Sstevel@tonic-gate uchar_t SOFMOD; 62*7c478bd9Sstevel@tonic-gate uchar_t rsvd[3]; 63*7c478bd9Sstevel@tonic-gate uint16_t PORTSC[2]; 64*7c478bd9Sstevel@tonic-gate } hc_regs_t; 65*7c478bd9Sstevel@tonic-gate 66*7c478bd9Sstevel@tonic-gate /* 67*7c478bd9Sstevel@tonic-gate * #defines for the USB Command Register 68*7c478bd9Sstevel@tonic-gate */ 69*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_MAXPKT_64 0x0080 70*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_CONFIG_FLAG 0x0040 71*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_SW_DEBUG 0x0020 72*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_FGBL_RESUME 0x0010 73*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_ENER_GBL_SUSPEND 0x0008 74*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_GBL_RESET 0x0004 75*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_HC_RESET 0x0002 76*7c478bd9Sstevel@tonic-gate #define USBCMD_REG_HC_RUN 0x0001 77*7c478bd9Sstevel@tonic-gate 78*7c478bd9Sstevel@tonic-gate 79*7c478bd9Sstevel@tonic-gate /* 80*7c478bd9Sstevel@tonic-gate * #defines for the USB Status Register 81*7c478bd9Sstevel@tonic-gate */ 82*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_HC_HALTED 0x0020 83*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_HC_PROCESS_ERR 0x0010 84*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_HOST_SYS_ERR 0x0008 85*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_RESUME_DETECT 0x0004 86*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_USB_ERR_INTR 0x0002 87*7c478bd9Sstevel@tonic-gate #define USBSTS_REG_USB_INTR 0x0001 88*7c478bd9Sstevel@tonic-gate 89*7c478bd9Sstevel@tonic-gate /* 90*7c478bd9Sstevel@tonic-gate * #defines for the USB Root Hub Port Register 91*7c478bd9Sstevel@tonic-gate */ 92*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CCS 0x1 93*7c478bd9Sstevel@tonic-gate #define HCR_PORT_CSC 0x2 94*7c478bd9Sstevel@tonic-gate #define HCR_PORT_ENABLE 0x4 95*7c478bd9Sstevel@tonic-gate #define HCR_PORT_ENDIS_CHG 0x8 96*7c478bd9Sstevel@tonic-gate #define HCR_PORT_LINE_STATSU 0x30 97*7c478bd9Sstevel@tonic-gate #define HCR_PORT_RESUME_DETECT 0x40 98*7c478bd9Sstevel@tonic-gate #define HCR_PORT_LSDA 0x100 99*7c478bd9Sstevel@tonic-gate #define HCR_PORT_RESET 0x200 100*7c478bd9Sstevel@tonic-gate #define HCR_PORT_SUSPEND 0x1000 101*7c478bd9Sstevel@tonic-gate 102*7c478bd9Sstevel@tonic-gate /* 103*7c478bd9Sstevel@tonic-gate * #defines for USB Interrupt Enable Register 104*7c478bd9Sstevel@tonic-gate */ 105*7c478bd9Sstevel@tonic-gate #define USBINTR_REG_SPINT_EN 0x0008 106*7c478bd9Sstevel@tonic-gate #define USBINTR_REG_IOC_EN 0x0004 107*7c478bd9Sstevel@tonic-gate #define USBINTR_REG_RESUME_INT_EN 0x0002 108*7c478bd9Sstevel@tonic-gate #define USBINTR_REG_TOCRC_INT_EN 0x0001 109*7c478bd9Sstevel@tonic-gate 110*7c478bd9Sstevel@tonic-gate #define ENABLE_ALL_INTRS 0x000F 111*7c478bd9Sstevel@tonic-gate #define DISABLE_ALL_INTRS 0x0000 112*7c478bd9Sstevel@tonic-gate #define UHCI_INTR_MASK 0x3f 113*7c478bd9Sstevel@tonic-gate 114*7c478bd9Sstevel@tonic-gate 115*7c478bd9Sstevel@tonic-gate #define SetReg32(hndl, addr, val) ddi_put32((hndl), \ 116*7c478bd9Sstevel@tonic-gate &(addr), (val)) 117*7c478bd9Sstevel@tonic-gate #define GetReg32(hndl, addr) ddi_get32((hndl), &(addr)) 118*7c478bd9Sstevel@tonic-gate 119*7c478bd9Sstevel@tonic-gate #define SetQH32(ucp, addr, val) \ 120*7c478bd9Sstevel@tonic-gate SetReg32((ucp)->uhci_qh_pool_mem_handle, (addr), (val)) 121*7c478bd9Sstevel@tonic-gate #define GetQH32(ucp, addr) \ 122*7c478bd9Sstevel@tonic-gate GetReg32((ucp)->uhci_qh_pool_mem_handle, (addr)) 123*7c478bd9Sstevel@tonic-gate 124*7c478bd9Sstevel@tonic-gate #define SetTD32(ucp, addr, val) \ 125*7c478bd9Sstevel@tonic-gate SetReg32((ucp)->uhci_td_pool_mem_handle, (addr), (val)) 126*7c478bd9Sstevel@tonic-gate #define GetTD32(ucp, addr) \ 127*7c478bd9Sstevel@tonic-gate GetReg32((ucp)->uhci_td_pool_mem_handle, (addr)) 128*7c478bd9Sstevel@tonic-gate 129*7c478bd9Sstevel@tonic-gate #define SetFL32(ucp, addr, val) \ 130*7c478bd9Sstevel@tonic-gate SetReg32((ucp)->uhci_flt_mem_handle, (addr), (val)) 131*7c478bd9Sstevel@tonic-gate #define GetFL32(ucp, addr) \ 132*7c478bd9Sstevel@tonic-gate GetReg32((ucp)->uhci_flt_mem_handle, (addr)) 133*7c478bd9Sstevel@tonic-gate 134*7c478bd9Sstevel@tonic-gate 135*7c478bd9Sstevel@tonic-gate /* 136*7c478bd9Sstevel@tonic-gate * UHCI Queue Head structure, aligned on 16 byte boundary 137*7c478bd9Sstevel@tonic-gate */ 138*7c478bd9Sstevel@tonic-gate typedef struct uhci_qh { 139*7c478bd9Sstevel@tonic-gate /* Hardware controlled bits */ 140*7c478bd9Sstevel@tonic-gate uint32_t link_ptr; /* Next Queue Head / TD */ 141*7c478bd9Sstevel@tonic-gate uint32_t element_ptr; /* Next queue head / TD */ 142*7c478bd9Sstevel@tonic-gate 143*7c478bd9Sstevel@tonic-gate /* Software controlled bits */ 144*7c478bd9Sstevel@tonic-gate uint16_t node; /* Node that its attached */ 145*7c478bd9Sstevel@tonic-gate uint16_t qh_flag; /* See below */ 146*7c478bd9Sstevel@tonic-gate 147*7c478bd9Sstevel@tonic-gate struct uhci_qh *prev_qh; /* Pointer to Prev queue head */ 148*7c478bd9Sstevel@tonic-gate struct uhci_td *td_tailp; /* Pointer to the last TD of QH */ 149*7c478bd9Sstevel@tonic-gate struct uhci_bulk_isoc_xfer_info *bulk_xfer_info; 150*7c478bd9Sstevel@tonic-gate uint64_t __pad1; /* align to 16 bytes */ 151*7c478bd9Sstevel@tonic-gate } queue_head_t; 152*7c478bd9Sstevel@tonic-gate 153*7c478bd9Sstevel@tonic-gate #define NUM_STATIC_NODES 63 154*7c478bd9Sstevel@tonic-gate #define NUM_INTR_QH_LISTS 64 155*7c478bd9Sstevel@tonic-gate #define NUM_FRAME_LST_ENTRIES 1024 156*7c478bd9Sstevel@tonic-gate #define TREE_HEIGHT 5 157*7c478bd9Sstevel@tonic-gate #define VIRTUAL_TREE_HEIGHT 5 158*7c478bd9Sstevel@tonic-gate #define SIZE_OF_FRAME_LST_TABLE 1024 * 4 159*7c478bd9Sstevel@tonic-gate 160*7c478bd9Sstevel@tonic-gate #define HC_TD_HEAD 0x0 161*7c478bd9Sstevel@tonic-gate #define HC_QUEUE_HEAD 0x2 162*7c478bd9Sstevel@tonic-gate #define HC_DEPTH_FIRST 0x4 163*7c478bd9Sstevel@tonic-gate #define HC_END_OF_LIST 0x1 164*7c478bd9Sstevel@tonic-gate 165*7c478bd9Sstevel@tonic-gate #define QUEUE_HEAD_FLAG_STATIC 0x1 166*7c478bd9Sstevel@tonic-gate #define QUEUE_HEAD_FLAG_FREE 0x2 167*7c478bd9Sstevel@tonic-gate #define QUEUE_HEAD_FLAG_BUSY 0x3 168*7c478bd9Sstevel@tonic-gate 169*7c478bd9Sstevel@tonic-gate #define QH_LINK_PTR_MASK 0xFFFFFFF0 170*7c478bd9Sstevel@tonic-gate #define QH_ELEMENT_PTR_MASK 0xFFFFFFF0 171*7c478bd9Sstevel@tonic-gate #define FRAME_LST_PTR_MASK 0xFFFFFFF0 172*7c478bd9Sstevel@tonic-gate 173*7c478bd9Sstevel@tonic-gate 174*7c478bd9Sstevel@tonic-gate #define GetField(u, td, f, o, l) \ 175*7c478bd9Sstevel@tonic-gate ((GetTD32(u, (td)->f) >> (o)) & ((1U<<l)-1)) 176*7c478bd9Sstevel@tonic-gate 177*7c478bd9Sstevel@tonic-gate #define SetField(u, td, f, o, l, v) \ 178*7c478bd9Sstevel@tonic-gate SetTD32(u, (td)->f, \ 179*7c478bd9Sstevel@tonic-gate (GetTD32(u, (td)->f) & ~(((1U<<l)-1) << o)) | \ 180*7c478bd9Sstevel@tonic-gate (((v) & ((1U<<l)-1)) << o)) 181*7c478bd9Sstevel@tonic-gate 182*7c478bd9Sstevel@tonic-gate #define GetTD_alen(u, td) GetField((u), (td), dw2, 0, 11) 183*7c478bd9Sstevel@tonic-gate #define GetTD_status(u, td) GetField((u), (td), dw2, 16, 8) 184*7c478bd9Sstevel@tonic-gate #define GetTD_ioc(u, td) GetField((u), (td), dw2, 24, 1) 185*7c478bd9Sstevel@tonic-gate #define GetTD_iso(u, td) GetField((u), (td), dw2, 25, 1) 186*7c478bd9Sstevel@tonic-gate #define GetTD_ls(u, td) GetField((u), (td), dw2, 26, 1) 187*7c478bd9Sstevel@tonic-gate #define GetTD_c_err(u, td) GetField((u), (td), dw2, 27, 2) 188*7c478bd9Sstevel@tonic-gate #define GetTD_spd(u, td) GetField((u), (td), dw2, 29, 1) 189*7c478bd9Sstevel@tonic-gate #define GetTD_PID(u, td) GetField((u), (td), dw3, 0, 8) 190*7c478bd9Sstevel@tonic-gate #define GetTD_devaddr(u, td) GetField((u), (td), dw3, 8, 7) 191*7c478bd9Sstevel@tonic-gate #define GetTD_endpt(u, td) GetField((u), (td), dw3, 15, 4) 192*7c478bd9Sstevel@tonic-gate #define GetTD_dtogg(u, td) GetField((u), (td), dw3, 19, 1) 193*7c478bd9Sstevel@tonic-gate #define GetTD_mlen(u, td) GetField((u), (td), dw3, 21, 11) 194*7c478bd9Sstevel@tonic-gate 195*7c478bd9Sstevel@tonic-gate #define SetTD_alen(u, td, v) SetField((u), (td), dw2, 0, 11, (v)) 196*7c478bd9Sstevel@tonic-gate #define SetTD_status(u, td, v) SetField((u), (td), dw2, 16, 8, (v)) 197*7c478bd9Sstevel@tonic-gate #define SetTD_ioc(u, td, v) SetField((u), (td), dw2, 24, 1, (v)) 198*7c478bd9Sstevel@tonic-gate #define SetTD_iso(u, td, v) SetField((u), (td), dw2, 25, 1, (v)) 199*7c478bd9Sstevel@tonic-gate #define SetTD_ls(u, td, v) SetField((u), (td), dw2, 26, 1, (v)) 200*7c478bd9Sstevel@tonic-gate #define SetTD_c_err(u, td, v) SetField((u), (td), dw2, 27, 2, (v)) 201*7c478bd9Sstevel@tonic-gate #define SetTD_spd(u, td, v) SetField((u), (td), dw2, 29, 1, (v)) 202*7c478bd9Sstevel@tonic-gate #define SetTD_PID(u, td, v) SetField((u), (td), dw3, 0, 8, (v)) 203*7c478bd9Sstevel@tonic-gate #define SetTD_devaddr(u, td, v) SetField((u), (td), dw3, 8, 7, (v)) 204*7c478bd9Sstevel@tonic-gate #define SetTD_endpt(u, td, v) SetField((u), (td), dw3, 15, 4, (v)) 205*7c478bd9Sstevel@tonic-gate #define SetTD_dtogg(u, td, v) SetField((u), (td), dw3, 19, 1, (v)) 206*7c478bd9Sstevel@tonic-gate #define SetTD_mlen(u, td, v) SetField((u), (td), dw3, 21, 11, (v)) 207*7c478bd9Sstevel@tonic-gate 208*7c478bd9Sstevel@tonic-gate /* 209*7c478bd9Sstevel@tonic-gate * UHCI Transfer Descriptor structure, aligned on 16 byte boundary 210*7c478bd9Sstevel@tonic-gate */ 211*7c478bd9Sstevel@tonic-gate typedef struct uhci_td { 212*7c478bd9Sstevel@tonic-gate 213*7c478bd9Sstevel@tonic-gate /* Information required by HC for executing the request */ 214*7c478bd9Sstevel@tonic-gate /* Pointer to the next TD/QH */ 215*7c478bd9Sstevel@tonic-gate uint32_t link_ptr; 216*7c478bd9Sstevel@tonic-gate uint32_t dw2; 217*7c478bd9Sstevel@tonic-gate uint32_t dw3; 218*7c478bd9Sstevel@tonic-gate /* Data buffer address */ 219*7c478bd9Sstevel@tonic-gate uint32_t buffer_address; 220*7c478bd9Sstevel@tonic-gate 221*7c478bd9Sstevel@tonic-gate /* Information required by HCD for managing the request */ 222*7c478bd9Sstevel@tonic-gate struct uhci_td *qh_td_prev; 223*7c478bd9Sstevel@tonic-gate struct uhci_td *tw_td_next; 224*7c478bd9Sstevel@tonic-gate struct uhci_td *outst_td_next; 225*7c478bd9Sstevel@tonic-gate struct uhci_td *outst_td_prev; 226*7c478bd9Sstevel@tonic-gate struct uhci_trans_wrapper *tw; 227*7c478bd9Sstevel@tonic-gate struct uhci_td *isoc_next; 228*7c478bd9Sstevel@tonic-gate struct uhci_td *isoc_prev; 229*7c478bd9Sstevel@tonic-gate ushort_t isoc_pkt_index; 230*7c478bd9Sstevel@tonic-gate ushort_t flag; 231*7c478bd9Sstevel@tonic-gate uint_t starting_frame; 232*7c478bd9Sstevel@tonic-gate uint_t _pad[3]; /* 16 byte alignment */ 233*7c478bd9Sstevel@tonic-gate } uhci_td_t; 234*7c478bd9Sstevel@tonic-gate 235*7c478bd9Sstevel@tonic-gate #define TD_FLAG_FREE 0x1 236*7c478bd9Sstevel@tonic-gate #define TD_FLAG_BUSY 0x2 237*7c478bd9Sstevel@tonic-gate #define TD_FLAG_DUMMY 0x3 238*7c478bd9Sstevel@tonic-gate 239*7c478bd9Sstevel@tonic-gate #define INTERRUPT_ON_COMPLETION 0x1 240*7c478bd9Sstevel@tonic-gate #define END_POINT_ADDRESS_MASK 0xF 241*7c478bd9Sstevel@tonic-gate #define UHCI_MAX_ERR_COUNT 3 242*7c478bd9Sstevel@tonic-gate #define MAX_NUM_BULK_TDS_PER_XFER 128 243*7c478bd9Sstevel@tonic-gate 244*7c478bd9Sstevel@tonic-gate /* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */ 245*7c478bd9Sstevel@tonic-gate #define UHCI_TD_ACTIVE 0x80 246*7c478bd9Sstevel@tonic-gate #define UHCI_TD_STALLED 0x40 247*7c478bd9Sstevel@tonic-gate #define UHCI_TD_DATA_BUFFER_ERR 0x20 248*7c478bd9Sstevel@tonic-gate #define UHCI_TD_BABBLE_ERR 0x10 249*7c478bd9Sstevel@tonic-gate #define UHCI_TD_NAK_RECEIVED 0x08 250*7c478bd9Sstevel@tonic-gate #define UHCI_TD_CRC_TIMEOUT 0x04 251*7c478bd9Sstevel@tonic-gate #define UHCI_TD_BITSTUFF_ERR 0x02 252*7c478bd9Sstevel@tonic-gate 253*7c478bd9Sstevel@tonic-gate #define TD_INACTIVE 0x7F 254*7c478bd9Sstevel@tonic-gate #define TD_STATUS_MASK 0x76 255*7c478bd9Sstevel@tonic-gate #define ZERO_LENGTH 0x7FF 256*7c478bd9Sstevel@tonic-gate 257*7c478bd9Sstevel@tonic-gate #define PID_SETUP 0x2D 258*7c478bd9Sstevel@tonic-gate #define PID_IN 0x69 259*7c478bd9Sstevel@tonic-gate #define PID_OUT 0xe1 260*7c478bd9Sstevel@tonic-gate 261*7c478bd9Sstevel@tonic-gate #define SETUP_SIZE 8 262*7c478bd9Sstevel@tonic-gate 263*7c478bd9Sstevel@tonic-gate #define SETUP 0x11 264*7c478bd9Sstevel@tonic-gate #define DATA 0x12 265*7c478bd9Sstevel@tonic-gate #define STATUS 0x13 266*7c478bd9Sstevel@tonic-gate 267*7c478bd9Sstevel@tonic-gate #define UHCI_INVALID_PTR NULL 268*7c478bd9Sstevel@tonic-gate #define LOW_SPEED_DEVICE 1 269*7c478bd9Sstevel@tonic-gate 270*7c478bd9Sstevel@tonic-gate /* 271*7c478bd9Sstevel@tonic-gate * These provide synchronization between TD deletions. 272*7c478bd9Sstevel@tonic-gate */ 273*7c478bd9Sstevel@tonic-gate #define UHCI_NOT_CLAIMED 0x0 274*7c478bd9Sstevel@tonic-gate #define UHCI_INTR_HDLR_CLAIMED 0x1 275*7c478bd9Sstevel@tonic-gate #define UHCI_MODIFY_TD_BITS_CLAIMED 0x2 276*7c478bd9Sstevel@tonic-gate #define UHCI_TIMEOUT_HDLR_CLAIMED 0x3 277*7c478bd9Sstevel@tonic-gate 278*7c478bd9Sstevel@tonic-gate 279*7c478bd9Sstevel@tonic-gate /* 280*7c478bd9Sstevel@tonic-gate * Structure for Bulk and Isoc transfers 281*7c478bd9Sstevel@tonic-gate */ 282*7c478bd9Sstevel@tonic-gate typedef struct uhci_bulk_isoc_xfer_info { 283*7c478bd9Sstevel@tonic-gate caddr_t pool_addr; 284*7c478bd9Sstevel@tonic-gate ddi_dma_cookie_t cookie; /* DMA cookie */ 285*7c478bd9Sstevel@tonic-gate ddi_dma_handle_t dma_handle; /* DMA handle */ 286*7c478bd9Sstevel@tonic-gate ddi_acc_handle_t mem_handle; /* Memory handle */ 287*7c478bd9Sstevel@tonic-gate ushort_t num_tds; 288*7c478bd9Sstevel@tonic-gate } uhci_bulk_isoc_xfer_t; 289*7c478bd9Sstevel@tonic-gate 290*7c478bd9Sstevel@tonic-gate /* 291*7c478bd9Sstevel@tonic-gate * Macros related to ISOC transfers 292*7c478bd9Sstevel@tonic-gate */ 293*7c478bd9Sstevel@tonic-gate #define UHCI_SIZE_OF_HW_FRNUM 11 294*7c478bd9Sstevel@tonic-gate #define UHCI_BIT_10_MASK 0x400 295*7c478bd9Sstevel@tonic-gate #define UHCI_MAX_ISOC_FRAMES 1024 296*7c478bd9Sstevel@tonic-gate #define UHCI_MAX_ISOC_PKTS 256 297*7c478bd9Sstevel@tonic-gate #define UHCI_DEFAULT_ISOC_RCV_PKTS 1 /* isoc pkts per req */ 298*7c478bd9Sstevel@tonic-gate 299*7c478bd9Sstevel@tonic-gate #define FRNUM_MASK 0x3FF 300*7c478bd9Sstevel@tonic-gate #define SW_FRNUM_MASK 0xFFFFFFFFFFFFF800 301*7c478bd9Sstevel@tonic-gate #define INVALID_FRNUM 0 302*7c478bd9Sstevel@tonic-gate #define FRNUM_OFFSET 5 303*7c478bd9Sstevel@tonic-gate #define MAX_FRAME_NUM 1023 304*7c478bd9Sstevel@tonic-gate 305*7c478bd9Sstevel@tonic-gate typedef uint32_t frame_lst_table_t; 306*7c478bd9Sstevel@tonic-gate 307*7c478bd9Sstevel@tonic-gate /* 308*7c478bd9Sstevel@tonic-gate * Bandwidth allocation 309*7c478bd9Sstevel@tonic-gate * The following definitions are used during bandwidth 310*7c478bd9Sstevel@tonic-gate * calculations for a given endpoint maximum packet size. 311*7c478bd9Sstevel@tonic-gate */ 312*7c478bd9Sstevel@tonic-gate #define MAX_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per frame */ 313*7c478bd9Sstevel@tonic-gate #define MAX_POLL_INTERVAL 255 /* Maximum polling interval */ 314*7c478bd9Sstevel@tonic-gate #define MIN_POLL_INTERVAL 1 /* Minimum polling interval */ 315*7c478bd9Sstevel@tonic-gate #define SOF 6 /* Length in bytes of SOF */ 316*7c478bd9Sstevel@tonic-gate #define EOF 2 /* Length in bytes of EOF */ 317*7c478bd9Sstevel@tonic-gate 318*7c478bd9Sstevel@tonic-gate /* 319*7c478bd9Sstevel@tonic-gate * Minimum polling interval for low speed endpoint 320*7c478bd9Sstevel@tonic-gate * 321*7c478bd9Sstevel@tonic-gate * According USB Specifications, a full-speed endpoint can specify 322*7c478bd9Sstevel@tonic-gate * a desired polling interval 1ms to 255ms and a low speed endpoints 323*7c478bd9Sstevel@tonic-gate * are limited to specifying only 10ms to 255ms. But some old keyboards 324*7c478bd9Sstevel@tonic-gate * and mice uses polling interval of 8ms. For compatibility purpose, 325*7c478bd9Sstevel@tonic-gate * we are using polling interval between 8ms and 255ms for low speed 326*7c478bd9Sstevel@tonic-gate * endpoints. 327*7c478bd9Sstevel@tonic-gate */ 328*7c478bd9Sstevel@tonic-gate #define MIN_LOW_SPEED_POLL_INTERVAL 8 329*7c478bd9Sstevel@tonic-gate 330*7c478bd9Sstevel@tonic-gate /* 331*7c478bd9Sstevel@tonic-gate * For non-periodic transfers, reserve at least for one low-speed device 332*7c478bd9Sstevel@tonic-gate * transaction and according to USB Bandwidth Analysis white paper, it 333*7c478bd9Sstevel@tonic-gate * comes around 12% of USB frame time. Then periodic transfers will get 334*7c478bd9Sstevel@tonic-gate * 88% of USB frame time. 335*7c478bd9Sstevel@tonic-gate */ 336*7c478bd9Sstevel@tonic-gate #define MAX_PERIODIC_BANDWIDTH (((MAX_BUS_BANDWIDTH - SOF - EOF)*88)/100) 337*7c478bd9Sstevel@tonic-gate 338*7c478bd9Sstevel@tonic-gate /* 339*7c478bd9Sstevel@tonic-gate * The following are the protocol overheads in terms of Bytes for the 340*7c478bd9Sstevel@tonic-gate * different transfer types. All these protocol overhead values are 341*7c478bd9Sstevel@tonic-gate * derived from the 5.9.3 section of USB Specification and with the 342*7c478bd9Sstevel@tonic-gate * help of Bandwidth Analysis white paper which is posted on the USB 343*7c478bd9Sstevel@tonic-gate * developer forum. 344*7c478bd9Sstevel@tonic-gate */ 345*7c478bd9Sstevel@tonic-gate #define FS_NON_ISOC_PROTO_OVERHEAD 14 346*7c478bd9Sstevel@tonic-gate #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 347*7c478bd9Sstevel@tonic-gate #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 348*7c478bd9Sstevel@tonic-gate #define LOW_SPEED_PROTO_OVERHEAD 97 349*7c478bd9Sstevel@tonic-gate #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 350*7c478bd9Sstevel@tonic-gate 351*7c478bd9Sstevel@tonic-gate /* 352*7c478bd9Sstevel@tonic-gate * The Host Controller (HC) delays are the USB host controller specific 353*7c478bd9Sstevel@tonic-gate * delays. The value shown below is the host controller delay for the 354*7c478bd9Sstevel@tonic-gate * Sand core USB host controller. 355*7c478bd9Sstevel@tonic-gate */ 356*7c478bd9Sstevel@tonic-gate #define HOST_CONTROLLER_DELAY 18 357*7c478bd9Sstevel@tonic-gate 358*7c478bd9Sstevel@tonic-gate /* 359*7c478bd9Sstevel@tonic-gate * The low speed clock below represents that to transmit one low-speed 360*7c478bd9Sstevel@tonic-gate * bit takes eight times more than one full speed bit time. 361*7c478bd9Sstevel@tonic-gate */ 362*7c478bd9Sstevel@tonic-gate #define LOW_SPEED_CLOCK 8 363*7c478bd9Sstevel@tonic-gate 364*7c478bd9Sstevel@tonic-gate /* the 16 byte alignment is required for every TD and QH start addr */ 365*7c478bd9Sstevel@tonic-gate #define UHCI_QH_ALIGN_SZ 16 366*7c478bd9Sstevel@tonic-gate #define UHCI_TD_ALIGN_SZ 16 367*7c478bd9Sstevel@tonic-gate 368*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 369*7c478bd9Sstevel@tonic-gate } 370*7c478bd9Sstevel@tonic-gate #endif 371*7c478bd9Sstevel@tonic-gate 372*7c478bd9Sstevel@tonic-gate #endif /* _SYS_USB_UHCI_H */ 373