17c478bdstevel@tonic-gate/*
27c478bdstevel@tonic-gate * CDDL HEADER START
37c478bdstevel@tonic-gate *
47c478bdstevel@tonic-gate * The contents of this file are subject to the terms of the
502acac7sl * Common Development and Distribution License (the "License").
602acac7sl * You may not use this file except in compliance with the License.
77c478bdstevel@tonic-gate *
87c478bdstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97c478bdstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
107c478bdstevel@tonic-gate * See the License for the specific language governing permissions
117c478bdstevel@tonic-gate * and limitations under the License.
127c478bdstevel@tonic-gate *
137c478bdstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
147c478bdstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157c478bdstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
167c478bdstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
177c478bdstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
187c478bdstevel@tonic-gate *
197c478bdstevel@tonic-gate * CDDL HEADER END
207c478bdstevel@tonic-gate */
217c478bdstevel@tonic-gate/*
220f1b305Seth Goldberg * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
237c478bdstevel@tonic-gate * Use is subject to license terms.
247c478bdstevel@tonic-gate */
257c478bdstevel@tonic-gate
267c478bdstevel@tonic-gate#ifndef _SYS_USB_UHCI_H
277c478bdstevel@tonic-gate#define	_SYS_USB_UHCI_H
287c478bdstevel@tonic-gate
297c478bdstevel@tonic-gate
307c478bdstevel@tonic-gate#include <sys/types.h>
317c478bdstevel@tonic-gate
327c478bdstevel@tonic-gate#ifdef __cplusplus
337c478bdstevel@tonic-gateextern "C" {
347c478bdstevel@tonic-gate#endif
357c478bdstevel@tonic-gate
367c478bdstevel@tonic-gate/*
377c478bdstevel@tonic-gate * Universal Host Controller Driver (UHCI)
387c478bdstevel@tonic-gate *
397c478bdstevel@tonic-gate * The UHCI driver is a driver which interfaces to the Universal
407c478bdstevel@tonic-gate * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to
417c478bdstevel@tonic-gate * the Host Controller is defined by the Universal Host Controller
427c478bdstevel@tonic-gate * Interface spec.
437c478bdstevel@tonic-gate */
447c478bdstevel@tonic-gate
457c478bdstevel@tonic-gate
467c478bdstevel@tonic-gate#define	LEGACYMODE_REG_OFFSET		0xc0
477c478bdstevel@tonic-gate#define	LEGACYMODE_REG_INIT_VALUE	0xaf00
487c478bdstevel@tonic-gate
497c478bdstevel@tonic-gate/*
507c478bdstevel@tonic-gate *   The register set of the UCHI controller
517c478bdstevel@tonic-gate *   This structure is laid out for proper alignment so no need to pack(1).
527c478bdstevel@tonic-gate */
537c478bdstevel@tonic-gatetypedef volatile struct hcr_regs {
547c478bdstevel@tonic-gate	uint16_t	USBCMD;
557c478bdstevel@tonic-gate	uint16_t	USBSTS;
567c478bdstevel@tonic-gate	uint16_t	USBINTR;
577c478bdstevel@tonic-gate	uint16_t	FRNUM;
587c478bdstevel@tonic-gate	uint32_t	FRBASEADD;
597c478bdstevel@tonic-gate	uchar_t		SOFMOD;
607c478bdstevel@tonic-gate	uchar_t		rsvd[3];
617c478bdstevel@tonic-gate	uint16_t	PORTSC[2];
627c478bdstevel@tonic-gate} hc_regs_t;
637c478bdstevel@tonic-gate
647c478bdstevel@tonic-gate/*
657c478bdstevel@tonic-gate * #defines for the USB Command Register
667c478bdstevel@tonic-gate */
677c478bdstevel@tonic-gate#define	USBCMD_REG_MAXPKT_64		0x0080
687c478bdstevel@tonic-gate#define	USBCMD_REG_CONFIG_FLAG		0x0040
697c478bdstevel@tonic-gate#define	USBCMD_REG_SW_DEBUG		0x0020
707c478bdstevel@tonic-gate#define	USBCMD_REG_FGBL_RESUME		0x0010
710f1b305Seth Goldberg#define	USBCMD_REG_ENTER_GBL_SUSPEND	0x0008
727c478bdstevel@tonic-gate#define	USBCMD_REG_GBL_RESET		0x0004
737c478bdstevel@tonic-gate#define	USBCMD_REG_HC_RESET		0x0002
747c478bdstevel@tonic-gate#define	USBCMD_REG_HC_RUN		0x0001
757c478bdstevel@tonic-gate
767c478bdstevel@tonic-gate
777c478bdstevel@tonic-gate/*
787c478bdstevel@tonic-gate * #defines for the USB Status Register
797c478bdstevel@tonic-gate */
807c478bdstevel@tonic-gate#define	USBSTS_REG_HC_HALTED		0x0020
817c478bdstevel@tonic-gate#define	USBSTS_REG_HC_PROCESS_ERR	0x0010
827c478bdstevel@tonic-gate#define	USBSTS_REG_HOST_SYS_ERR 	0x0008
837c478bdstevel@tonic-gate#define	USBSTS_REG_RESUME_DETECT	0x0004
847c478bdstevel@tonic-gate#define	USBSTS_REG_USB_ERR_INTR		0x0002
857c478bdstevel@tonic-gate#define	USBSTS_REG_USB_INTR		0x0001
867c478bdstevel@tonic-gate
877c478bdstevel@tonic-gate/*
887c478bdstevel@tonic-gate * #defines for the USB Root Hub Port Register
897c478bdstevel@tonic-gate */
907c478bdstevel@tonic-gate#define	HCR_PORT_CCS			0x1
917c478bdstevel@tonic-gate#define	HCR_PORT_CSC			0x2
927c478bdstevel@tonic-gate#define	HCR_PORT_ENABLE			0x4
937c478bdstevel@tonic-gate#define	HCR_PORT_ENDIS_CHG		0x8
947c478bdstevel@tonic-gate#define	HCR_PORT_LINE_STATSU		0x30
957c478bdstevel@tonic-gate#define	HCR_PORT_RESUME_DETECT		0x40
967c478bdstevel@tonic-gate#define	HCR_PORT_LSDA			0x100
977c478bdstevel@tonic-gate#define	HCR_PORT_RESET			0x200
987c478bdstevel@tonic-gate#define	HCR_PORT_SUSPEND		0x1000
997c478bdstevel@tonic-gate
1007c478bdstevel@tonic-gate/*
1017c478bdstevel@tonic-gate * #defines for USB Interrupt Enable Register
1027c478bdstevel@tonic-gate */
1037c478bdstevel@tonic-gate#define	USBINTR_REG_SPINT_EN		0x0008
1047c478bdstevel@tonic-gate#define	USBINTR_REG_IOC_EN		0x0004
1057c478bdstevel@tonic-gate#define	USBINTR_REG_RESUME_INT_EN	0x0002
1067c478bdstevel@tonic-gate#define	USBINTR_REG_TOCRC_INT_EN	0x0001
1077c478bdstevel@tonic-gate
1087c478bdstevel@tonic-gate#define	ENABLE_ALL_INTRS		0x000F
1097c478bdstevel@tonic-gate#define	DISABLE_ALL_INTRS		0x0000
110932cf98sl#define	UHCI_INTR_MASK			0x1f
1117c478bdstevel@tonic-gate
1127c478bdstevel@tonic-gate
1137c478bdstevel@tonic-gate#define	SetReg32(hndl, addr, val)	ddi_put32((hndl), \
1147c478bdstevel@tonic-gate						&(addr), (val))
1157c478bdstevel@tonic-gate#define	GetReg32(hndl, addr)		ddi_get32((hndl), &(addr))
1167c478bdstevel@tonic-gate
1177c478bdstevel@tonic-gate#define	SetQH32(ucp, addr, val)		\
1187c478bdstevel@tonic-gate		SetReg32((ucp)->uhci_qh_pool_mem_handle, (addr), (val))
1197c478bdstevel@tonic-gate#define	GetQH32(ucp, addr)		\
1207c478bdstevel@tonic-gate		GetReg32((ucp)->uhci_qh_pool_mem_handle, (addr))
1217c478bdstevel@tonic-gate
1227c478bdstevel@tonic-gate#define	SetTD32(ucp, addr, val)		\
1237c478bdstevel@tonic-gate		SetReg32((ucp)->uhci_td_pool_mem_handle, (addr), (val))
1247c478bdstevel@tonic-gate#define	GetTD32(ucp, addr)		\
1257c478bdstevel@tonic-gate		GetReg32((ucp)->uhci_td_pool_mem_handle, (addr))
1267c478bdstevel@tonic-gate
1277c478bdstevel@tonic-gate#define	SetFL32(ucp, addr, val)		\
1287c478bdstevel@tonic-gate		SetReg32((ucp)->uhci_flt_mem_handle, (addr), (val))
1297c478bdstevel@tonic-gate#define	GetFL32(ucp, addr)		\
1307c478bdstevel@tonic-gate		GetReg32((ucp)->uhci_flt_mem_handle, (addr))
1317c478bdstevel@tonic-gate
1327c478bdstevel@tonic-gate
1337c478bdstevel@tonic-gate/*
1347c478bdstevel@tonic-gate * UHCI Queue Head structure, aligned on 16 byte boundary
1357c478bdstevel@tonic-gate */
1367c478bdstevel@tonic-gatetypedef struct uhci_qh {
1377c478bdstevel@tonic-gate	/* Hardware controlled bits */
1387c478bdstevel@tonic-gate	uint32_t		link_ptr;	/* Next Queue Head / TD */
1397c478bdstevel@tonic-gate	uint32_t		element_ptr;	/* Next queue head / TD	*/
1407c478bdstevel@tonic-gate
1417c478bdstevel@tonic-gate	/* Software controlled bits */
1427c478bdstevel@tonic-gate	uint16_t	node;		/* Node	that its attached */
1437c478bdstevel@tonic-gate	uint16_t	qh_flag;	/* See	below */
1447c478bdstevel@tonic-gate
1457c478bdstevel@tonic-gate	struct	uhci_qh	*prev_qh;	/* Pointer to Prev queue head */
1467c478bdstevel@tonic-gate	struct	uhci_td	*td_tailp;	/* Pointer to the last TD of QH	*/
1477c478bdstevel@tonic-gate	struct	uhci_bulk_isoc_xfer_info *bulk_xfer_info;
1487c478bdstevel@tonic-gate	uint64_t	__pad1;		/* align to 16 bytes */
1497c478bdstevel@tonic-gate} queue_head_t;
1507c478bdstevel@tonic-gate
1517c478bdstevel@tonic-gate#define	NUM_STATIC_NODES		63
1527c478bdstevel@tonic-gate#define	NUM_INTR_QH_LISTS		64
1537c478bdstevel@tonic-gate#define	NUM_FRAME_LST_ENTRIES		1024
1547c478bdstevel@tonic-gate#define	TREE_HEIGHT			5
1557c478bdstevel@tonic-gate#define	VIRTUAL_TREE_HEIGHT		5
1567c478bdstevel@tonic-gate#define	SIZE_OF_FRAME_LST_TABLE		1024 * 4
1577c478bdstevel@tonic-gate
1587c478bdstevel@tonic-gate#define	HC_TD_HEAD			0x0
1597c478bdstevel@tonic-gate#define	HC_QUEUE_HEAD			0x2
1607c478bdstevel@tonic-gate#define	HC_DEPTH_FIRST			0x4
1617c478bdstevel@tonic-gate#define	HC_END_OF_LIST			0x1
1627c478bdstevel@tonic-gate
1637c478bdstevel@tonic-gate#define	QUEUE_HEAD_FLAG_STATIC		0x1
1647c478bdstevel@tonic-gate#define	QUEUE_HEAD_FLAG_FREE		0x2
1657c478bdstevel@tonic-gate#define	QUEUE_HEAD_FLAG_BUSY		0x3
1667c478bdstevel@tonic-gate
1677c478bdstevel@tonic-gate#define	QH_LINK_PTR_MASK		0xFFFFFFF0
1687c478bdstevel@tonic-gate#define	QH_ELEMENT_PTR_MASK		0xFFFFFFF0
1697c478bdstevel@tonic-gate#define	FRAME_LST_PTR_MASK		0xFFFFFFF0
1707c478bdstevel@tonic-gate
1717c478bdstevel@tonic-gate
1727c478bdstevel@tonic-gate#define	GetField(u, td, f, o, l) \
1737c478bdstevel@tonic-gate	((GetTD32(u, (td)->f) >> (o)) & ((1U<<l)-1))
1747c478bdstevel@tonic-gate
1757c478bdstevel@tonic-gate#define	SetField(u, td, f, o, l, v) \
1767c478bdstevel@tonic-gate	SetTD32(u, (td)->f, \
1777c478bdstevel@tonic-gate	(GetTD32(u, (td)->f) & ~(((1U<<l)-1) << o)) | \
1787c478bdstevel@tonic-gate	(((v) & ((1U<<l)-1)) << o))
1797c478bdstevel@tonic-gate
1807c478bdstevel@tonic-gate#define	GetTD_alen(u, td)	GetField((u), (td), dw2, 0, 11)
1817c478bdstevel@tonic-gate#define	GetTD_status(u, td)	GetField((u), (td), dw2, 16, 8)
1827c478bdstevel@tonic-gate#define	GetTD_ioc(u, td)	GetField((u), (td), dw2, 24, 1)
1837c478bdstevel@tonic-gate#define	GetTD_iso(u, td)	GetField((u), (td), dw2, 25, 1)
1847c478bdstevel@tonic-gate#define	GetTD_ls(u, td)		GetField((u), (td), dw2, 26, 1)
1857c478bdstevel@tonic-gate#define	GetTD_c_err(u, td)	GetField((u), (td), dw2, 27, 2)
1867c478bdstevel@tonic-gate#define	GetTD_spd(u, td)	GetField((u), (td), dw2, 29, 1)
1877c478bdstevel@tonic-gate#define	GetTD_PID(u, td)	GetField((u), (td), dw3, 0, 8)
1887c478bdstevel@tonic-gate#define	GetTD_devaddr(u, td)	GetField((u), (td), dw3, 8, 7)
1897c478bdstevel@tonic-gate#define	GetTD_endpt(u, td)	GetField((u), (td), dw3, 15, 4)
1907c478bdstevel@tonic-gate#define	GetTD_dtogg(u, td)	GetField((u), (td), dw3, 19, 1)
1917c478bdstevel@tonic-gate#define	GetTD_mlen(u, td)	GetField((u), (td), dw3, 21, 11)
1927c478bdstevel@tonic-gate
1937c478bdstevel@tonic-gate#define	SetTD_alen(u, td, v)	SetField((u), (td), dw2, 0, 11, (v))
1947c478bdstevel@tonic-gate#define	SetTD_status(u, td, v)	SetField((u), (td), dw2, 16, 8, (v))
1957c478bdstevel@tonic-gate#define	SetTD_ioc(u, td, v)	SetField((u), (td), dw2, 24, 1, (v))
1967c478bdstevel@tonic-gate#define	SetTD_iso(u, td, v)	SetField((u), (td), dw2, 25, 1, (v))
1977c478bdstevel@tonic-gate#define	SetTD_ls(u, td, v)	SetField((u), (td), dw2, 26, 1, (v))
1987c478bdstevel@tonic-gate#define	SetTD_c_err(u, td, v)	SetField((u), (td), dw2, 27, 2, (v))
1997c478bdstevel@tonic-gate#define	SetTD_spd(u, td, v)	SetField((u), (td), dw2, 29, 1, (v))
2007c478bdstevel@tonic-gate#define	SetTD_PID(u, td, v)	SetField((u), (td), dw3, 0, 8, (v))
2017c478bdstevel@tonic-gate#define	SetTD_devaddr(u, td, v)	SetField((u), (td), dw3, 8, 7, (v))
2027c478bdstevel@tonic-gate#define	SetTD_endpt(u, td, v)	SetField((u), (td), dw3, 15, 4, (v))
2037c478bdstevel@tonic-gate#define	SetTD_dtogg(u, td, v)	SetField((u), (td), dw3, 19, 1, (v))
2047c478bdstevel@tonic-gate#define	SetTD_mlen(u, td, v)	SetField((u), (td), dw3, 21, 11, (v))
2057c478bdstevel@tonic-gate
2067c478bdstevel@tonic-gate/*
2077c478bdstevel@tonic-gate * UHCI Transfer Descriptor structure, aligned on 16 byte boundary
2087c478bdstevel@tonic-gate */
2097c478bdstevel@tonic-gatetypedef struct uhci_td {
2107c478bdstevel@tonic-gate
2117c478bdstevel@tonic-gate	/* Information required by HC for executing the request */
2127c478bdstevel@tonic-gate					/* Pointer to the next TD/QH */
2137c478bdstevel@tonic-gate	uint32_t			link_ptr;
2147c478bdstevel@tonic-gate	uint32_t			dw2;
2157c478bdstevel@tonic-gate	uint32_t			dw3;
21602acac7sl					/* Data buffer address */
2177c478bdstevel@tonic-gate	uint32_t			buffer_address;
2187c478bdstevel@tonic-gate
2197c478bdstevel@tonic-gate	/* Information required by HCD for managing the request */
2207c478bdstevel@tonic-gate	struct	uhci_td			*qh_td_prev;
2217c478bdstevel@tonic-gate	struct	uhci_td			*tw_td_next;
2227c478bdstevel@tonic-gate	struct	uhci_td			*outst_td_next;
2237c478bdstevel@tonic-gate	struct	uhci_td			*outst_td_prev;
2247c478bdstevel@tonic-gate	struct	uhci_trans_wrapper	*tw;
2257c478bdstevel@tonic-gate	struct	uhci_td			*isoc_next;
2267c478bdstevel@tonic-gate	struct	uhci_td			*isoc_prev;
2277c478bdstevel@tonic-gate	ushort_t			isoc_pkt_index;
2287c478bdstevel@tonic-gate	ushort_t			flag;
2297c478bdstevel@tonic-gate	uint_t				starting_frame;
2307c478bdstevel@tonic-gate	uint_t				_pad[3];	/* 16 byte alignment */
2317c478bdstevel@tonic-gate} uhci_td_t;
2327c478bdstevel@tonic-gate
2337c478bdstevel@tonic-gate#define	TD_FLAG_FREE			0x1
2347c478bdstevel@tonic-gate#define	TD_FLAG_BUSY			0x2
2357c478bdstevel@tonic-gate#define	TD_FLAG_DUMMY			0x3
2367c478bdstevel@tonic-gate
2377c478bdstevel@tonic-gate#define	INTERRUPT_ON_COMPLETION		0x1
2387c478bdstevel@tonic-gate#define	END_POINT_ADDRESS_MASK		0xF
2397c478bdstevel@tonic-gate#define	UHCI_MAX_ERR_COUNT		3
2407c478bdstevel@tonic-gate#define	MAX_NUM_BULK_TDS_PER_XFER	128
2417c478bdstevel@tonic-gate
2427c478bdstevel@tonic-gate/* section 3.2.2 of UHCI1.1 spec, bits 23:16 of status field */
2437c478bdstevel@tonic-gate#define	UHCI_TD_ACTIVE			0x80
2447c478bdstevel@tonic-gate#define	UHCI_TD_STALLED			0x40
2457c478bdstevel@tonic-gate#define	UHCI_TD_DATA_BUFFER_ERR		0x20
2467c478bdstevel@tonic-gate#define	UHCI_TD_BABBLE_ERR		0x10
2477c478bdstevel@tonic-gate#define	UHCI_TD_NAK_RECEIVED		0x08
2487c478bdstevel@tonic-gate#define	UHCI_TD_CRC_TIMEOUT		0x04
2497c478bdstevel@tonic-gate#define	UHCI_TD_BITSTUFF_ERR		0x02
2507c478bdstevel@tonic-gate
2517c478bdstevel@tonic-gate#define	TD_INACTIVE			0x7F
2527c478bdstevel@tonic-gate#define	TD_STATUS_MASK			0x76
2537c478bdstevel@tonic-gate#define	ZERO_LENGTH			0x7FF
2547c478bdstevel@tonic-gate
2557c478bdstevel@tonic-gate#define	PID_SETUP			0x2D
2567c478bdstevel@tonic-gate#define	PID_IN				0x69
2577c478bdstevel@tonic-gate#define	PID_OUT				0xe1
2587c478bdstevel@tonic-gate
2597c478bdstevel@tonic-gate#define	SETUP_SIZE			8
2607c478bdstevel@tonic-gate
2617c478bdstevel@tonic-gate#define	SETUP				0x11
2627c478bdstevel@tonic-gate#define	DATA				0x12
2637c478bdstevel@tonic-gate#define	STATUS				0x13
2647c478bdstevel@tonic-gate
2657c478bdstevel@tonic-gate#define	UHCI_INVALID_PTR		NULL
2667c478bdstevel@tonic-gate#define	LOW_SPEED_DEVICE		1
2677c478bdstevel@tonic-gate
2687c478bdstevel@tonic-gate/*
2697c478bdstevel@tonic-gate * These provide synchronization between TD deletions.
2707c478bdstevel@tonic-gate */
2717c478bdstevel@tonic-gate#define	UHCI_NOT_CLAIMED		0x0
2727c478bdstevel@tonic-gate#define	UHCI_INTR_HDLR_CLAIMED		0x1
2737c478bdstevel@tonic-gate#define	UHCI_MODIFY_TD_BITS_CLAIMED	0x2
2747c478bdstevel@tonic-gate#define	UHCI_TIMEOUT_HDLR_CLAIMED	0x3
2757c478bdstevel@tonic-gate
2767c478bdstevel@tonic-gate
2777c478bdstevel@tonic-gate/*
27802acac7sl * Structure for Bulk and Isoc TD pools
27902acac7sl */
28002acac7sltypedef struct uhci_bulk_isoc_td_pool {
28102acac7sl	caddr_t				pool_addr;
28202acac7sl	ddi_dma_cookie_t		cookie;	    /* DMA cookie */
28302acac7sl	ddi_dma_handle_t		dma_handle; /* DMA handle */
28402acac7sl	ddi_acc_handle_t		mem_handle; /* Memory handle */
28502acac7sl	ushort_t			num_tds;
28602acac7sl} uhci_bulk_isoc_td_pool_t;
28702acac7sl
28802acac7sl/*
2897c478bdstevel@tonic-gate *  Structure for Bulk and Isoc transfers
2907c478bdstevel@tonic-gate */
2917c478bdstevel@tonic-gatetypedef struct uhci_bulk_isoc_xfer_info {
29202acac7sl	uhci_bulk_isoc_td_pool_t	*td_pools;
29302acac7sl	ushort_t			num_pools;
29402acac7sl	ushort_t			num_tds;
29502acac7sl} uhci_bulk_isoc_xfer_t;
29602acac7sl
29702acac7sl/*
29802acac7sl * Structure for Isoc DMA buffer
29902acac7sl *	One Isoc transfer includes multiple Isoc packets.
30002acac7sl *	One DMA buffer is allocated for one packet each.
30102acac7sl */
30202acac7sltypedef struct uhci_isoc_buf {
30302acac7sl	caddr_t			buf_addr;	/* Starting buffer address */
3047c478bdstevel@tonic-gate	ddi_dma_cookie_t	cookie;		/* DMA cookie */
3057c478bdstevel@tonic-gate	ddi_dma_handle_t	dma_handle;	/* DMA handle */
3067c478bdstevel@tonic-gate	ddi_acc_handle_t	mem_handle;	/* Memory handle */
30702acac7sl	size_t			length;		/* Buffer length */
30802acac7sl	ushort_t		index;
30902acac7sl} uhci_isoc_buf_t;
3107c478bdstevel@tonic-gate
3117c478bdstevel@tonic-gate/*
3127c478bdstevel@tonic-gate * Macros related to ISOC transfers
3137c478bdstevel@tonic-gate */
3147c478bdstevel@tonic-gate#define	UHCI_SIZE_OF_HW_FRNUM		11
3157c478bdstevel@tonic-gate#define	UHCI_BIT_10_MASK		0x400
3167c478bdstevel@tonic-gate#define	UHCI_MAX_ISOC_FRAMES		1024
3177c478bdstevel@tonic-gate#define	UHCI_MAX_ISOC_PKTS		256
3187c478bdstevel@tonic-gate#define	UHCI_DEFAULT_ISOC_RCV_PKTS	1	/* isoc pkts per req */
3197c478bdstevel@tonic-gate
3207c478bdstevel@tonic-gate#define	FRNUM_MASK			0x3FF
3217c478bdstevel@tonic-gate#define	SW_FRNUM_MASK			0xFFFFFFFFFFFFF800
3227c478bdstevel@tonic-gate#define	INVALID_FRNUM			0
3237c478bdstevel@tonic-gate#define	FRNUM_OFFSET			5
3247c478bdstevel@tonic-gate#define	MAX_FRAME_NUM			1023
3257c478bdstevel@tonic-gate
3267c478bdstevel@tonic-gatetypedef	uint32_t frame_lst_table_t;
3277c478bdstevel@tonic-gate
3287c478bdstevel@tonic-gate/*
3297c478bdstevel@tonic-gate * Bandwidth allocation
3307c478bdstevel@tonic-gate *	The following definitions are  used during  bandwidth
3317c478bdstevel@tonic-gate *	calculations for a given endpoint maximum packet size.
3327c478bdstevel@tonic-gate */
3337c478bdstevel@tonic-gate#define	MAX_BUS_BANDWIDTH	1500	/* Up to 1500 bytes per frame */
3347c478bdstevel@tonic-gate#define	MAX_POLL_INTERVAL	255	/* Maximum polling interval */
3357c478bdstevel@tonic-gate#define	MIN_POLL_INTERVAL	1	/* Minimum polling interval */
3367c478bdstevel@tonic-gate#define	SOF			6	/* Length in bytes of SOF */
3377c478bdstevel@tonic-gate#define	EOF			2	/* Length in bytes of EOF */
3387c478bdstevel@tonic-gate
3397c478bdstevel@tonic-gate/*
3407c478bdstevel@tonic-gate * Minimum polling interval for low speed endpoint
3417c478bdstevel@tonic-gate *
3427c478bdstevel@tonic-gate * According USB Specifications, a full-speed endpoint can specify
3437c478bdstevel@tonic-gate * a desired polling interval 1ms to 255ms and a low speed endpoints
3447c478bdstevel@tonic-gate * are limited to specifying only 10ms to 255ms. But some old keyboards
3457c478bdstevel@tonic-gate * and mice uses polling interval of 8ms. For compatibility purpose,
3467c478bdstevel@tonic-gate * we are using polling interval between 8ms and 255ms for low speed
3477c478bdstevel@tonic-gate * endpoints.
3487c478bdstevel@tonic-gate */
3497c478bdstevel@tonic-gate#define	MIN_LOW_SPEED_POLL_INTERVAL	8
3507c478bdstevel@tonic-gate
3517c478bdstevel@tonic-gate/*
3527c478bdstevel@tonic-gate * For non-periodic transfers, reserve at least for one low-speed device
3537c478bdstevel@tonic-gate * transaction and according to USB Bandwidth Analysis white paper,  it
3547c478bdstevel@tonic-gate * comes around 12% of USB frame time. Then periodic transfers will get
3557c478bdstevel@tonic-gate * 88% of USB frame time.
3567c478bdstevel@tonic-gate */
3577c478bdstevel@tonic-gate#define	MAX_PERIODIC_BANDWIDTH	(((MAX_BUS_BANDWIDTH - SOF - EOF)*88)/100)
3587c478bdstevel@tonic-gate
3597c478bdstevel@tonic-gate/*
3607c478bdstevel@tonic-gate * The following are the protocol overheads in terms of Bytes for the
3617c478bdstevel@tonic-gate * different transfer types.  All these protocol overhead  values are
3627c478bdstevel@tonic-gate * derived from the 5.9.3 section of USB Specification	and  with the
3637c478bdstevel@tonic-gate * help of Bandwidth Analysis white paper which is posted on the  USB
3647c478bdstevel@tonic-gate * developer forum.
3657c478bdstevel@tonic-gate */
3667c478bdstevel@tonic-gate#define	FS_NON_ISOC_PROTO_OVERHEAD	14
3677c478bdstevel@tonic-gate#define	FS_ISOC_INPUT_PROTO_OVERHEAD	11
3687c478bdstevel@tonic-gate#define	FS_ISOC_OUTPUT_PROTO_OVERHEAD	10
3697c478bdstevel@tonic-gate#define	LOW_SPEED_PROTO_OVERHEAD	97
3707c478bdstevel@tonic-gate#define	HUB_LOW_SPEED_PROTO_OVERHEAD	01
3717c478bdstevel@tonic-gate
3727c478bdstevel@tonic-gate/*
3737c478bdstevel@tonic-gate * The Host Controller (HC) delays are the USB host controller specific
3747c478bdstevel@tonic-gate * delays. The value shown below is the host  controller delay for  the
3757c478bdstevel@tonic-gate * Sand core USB host controller.
3767c478bdstevel@tonic-gate */
3777c478bdstevel@tonic-gate#define	HOST_CONTROLLER_DELAY		18
3787c478bdstevel@tonic-gate
3797c478bdstevel@tonic-gate/*
3807c478bdstevel@tonic-gate * The low speed clock below represents that to transmit one low-speed
3817c478bdstevel@tonic-gate * bit takes eight times more than one full speed bit time.
3827c478bdstevel@tonic-gate */
3837c478bdstevel@tonic-gate#define	LOW_SPEED_CLOCK			8
3847c478bdstevel@tonic-gate
3857c478bdstevel@tonic-gate/* the 16 byte alignment is required for every TD and QH start addr */
3867c478bdstevel@tonic-gate#define	UHCI_QH_ALIGN_SZ		16
3877c478bdstevel@tonic-gate#define	UHCI_TD_ALIGN_SZ		16
3887c478bdstevel@tonic-gate
3897c478bdstevel@tonic-gate#ifdef __cplusplus
3907c478bdstevel@tonic-gate}
3917c478bdstevel@tonic-gate#endif
3927c478bdstevel@tonic-gate
3937c478bdstevel@tonic-gate#endif /* _SYS_USB_UHCI_H */
394