17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 502acac7eSsl * Common Development and Distribution License (the "License"). 602acac7eSsl * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*d29f5a71Szhigang lu - Sun Microsystems - Beijing China * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #ifndef _SYS_USB_OHCI_H 277c478bd9Sstevel@tonic-gate #define _SYS_USB_OHCI_H 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #ifdef __cplusplus 317c478bd9Sstevel@tonic-gate extern "C" { 327c478bd9Sstevel@tonic-gate #endif 337c478bd9Sstevel@tonic-gate 347c478bd9Sstevel@tonic-gate /* 357c478bd9Sstevel@tonic-gate * Open Host Controller Driver (OHCI) 367c478bd9Sstevel@tonic-gate * 377c478bd9Sstevel@tonic-gate * The USB Open Host Controller driver is a software driver which interfaces 387c478bd9Sstevel@tonic-gate * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 397c478bd9Sstevel@tonic-gate * The interface to USB Open Host Controller is defined by the OpenHCI Host 407c478bd9Sstevel@tonic-gate * Controller Interface. 417c478bd9Sstevel@tonic-gate * 427c478bd9Sstevel@tonic-gate * This header file describes the registers and data structures shared by the 437c478bd9Sstevel@tonic-gate * USB Open Host Controller and the USB Open Host Controller Driver. 447c478bd9Sstevel@tonic-gate */ 457c478bd9Sstevel@tonic-gate 467c478bd9Sstevel@tonic-gate #include <sys/types.h> 477c478bd9Sstevel@tonic-gate #include <sys/pci.h> 487c478bd9Sstevel@tonic-gate #include <sys/kstat.h> 497c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 507c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 517c478bd9Sstevel@tonic-gate #include <sys/ndi_impldefs.h> 527c478bd9Sstevel@tonic-gate 537c478bd9Sstevel@tonic-gate #include <sys/usb/usba.h> 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hcdi.h> 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hub.h> 587c478bd9Sstevel@tonic-gate #include <sys/usb/usba/hubdi.h> 597c478bd9Sstevel@tonic-gate #include <sys/usb/hubd/hubdvar.h> 607c478bd9Sstevel@tonic-gate 617c478bd9Sstevel@tonic-gate #include <sys/id32.h> 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate #define OHCI_MAX_RH_PORTS 15 /* Maximum root hub ports */ 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate /* 667c478bd9Sstevel@tonic-gate * Each OHCI buffer can hold upto 8k bytes of data. Hence there is a 677c478bd9Sstevel@tonic-gate * restriction of 4k alignment while allocating a dma buffer. 687c478bd9Sstevel@tonic-gate */ 697c478bd9Sstevel@tonic-gate #define OHCI_4K_ALIGN 0x1000 707c478bd9Sstevel@tonic-gate 717c478bd9Sstevel@tonic-gate /* 727c478bd9Sstevel@tonic-gate * USB Host controller DMA scatter gather list defines for 737c478bd9Sstevel@tonic-gate * Sparc and non-sparc architectures. 747c478bd9Sstevel@tonic-gate */ 757c478bd9Sstevel@tonic-gate #if defined(__sparc) 767c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_MAX_XFER 0xffffffffull 777c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_COUNT_MAX 0xffffffffull 787c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_GRANULAR 512 797c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_ALIGNMENT OHCI_4K_ALIGN 807c478bd9Sstevel@tonic-gate #else 817c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_MAX_XFER 0x00ffffffull 827c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_COUNT_MAX 0x00ffffffull 837c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_GRANULAR 1 8402acac7eSsl #define OHCI_DMA_ATTR_ALIGNMENT OHCI_4K_ALIGN 857c478bd9Sstevel@tonic-gate #endif 867c478bd9Sstevel@tonic-gate 8702acac7eSsl #define OHCI_DMA_ATTR_TW_SGLLEN 0x7fffffff /* not limited */ 8802acac7eSsl #define OHCI_DMA_ATTR_TD_SGLLEN 2 /* maximum 8K per TD */ 8902acac7eSsl 907c478bd9Sstevel@tonic-gate /* 917c478bd9Sstevel@tonic-gate * According to the OHCI spec ED and TD need to be 16 byte aligned. 927c478bd9Sstevel@tonic-gate * However, iTD needs to be 32 byte aligned. Since we do not 937c478bd9Sstevel@tonic-gate * distinguish between iTD and TD, make them both 32 byte aligned. 947c478bd9Sstevel@tonic-gate * 957c478bd9Sstevel@tonic-gate * ED = 16 byte aligned 967c478bd9Sstevel@tonic-gate * TD = 32 byte aligned 977c478bd9Sstevel@tonic-gate * HCCA = 256 byte aligned 987c478bd9Sstevel@tonic-gate */ 997c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_ED_ALIGNMENT 0x010 1007c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_TD_ALIGNMENT 0x020 1017c478bd9Sstevel@tonic-gate #define OHCI_DMA_ATTR_HCCA_ALIGNMENT 0x100 1027c478bd9Sstevel@tonic-gate 103f806f48bShs /* 104f806f48bShs * Vendor id and Device id for ULI1575 southbridge. 105f806f48bShs */ 106f806f48bShs #define PCI_ULI1575_VENID 0x10B9 107f806f48bShs #define PCI_ULI1575_DEVID 0x5237 108f806f48bShs 109f806f48bShs /* 110f806f48bShs * Need a workaround for ULI1575 chipset. Following OHCI 111f806f48bShs * Operational Memory Registers are not cleared to their 112f806f48bShs * default value on reset. Explicitly set the registers 113f806f48bShs * to default value after reset. 114f806f48bShs */ 115f806f48bShs #define HCR_CONTROL_DEFAULT 0x0 116f806f48bShs #define HCR_INT_ENABLE_DEFAULT 0x0 117f806f48bShs #define HCR_HCCA_DEFAULT 0x0 118f806f48bShs #define HCR_CONTROL_HEAD_ED_DEFAULT 0x0 119f806f48bShs #define HCR_BULK_HEAD_ED_DEFAULT 0x0 120f806f48bShs #define HCR_FRAME_INTERVAL_DEFAULT 0x2edf 121f806f48bShs #define HCR_PERIODIC_START_DEFAULT 0x0 122f806f48bShs 1237c478bd9Sstevel@tonic-gate /* 1247c478bd9Sstevel@tonic-gate * OpenHCI Operational Registers 1257c478bd9Sstevel@tonic-gate * 1267c478bd9Sstevel@tonic-gate * The Host Controller (HC) contains a set of on-chip operational registers 1277c478bd9Sstevel@tonic-gate * which are mapped into a noncacheable portion of the system addressable 1287c478bd9Sstevel@tonic-gate * space and these registers are also used by the Host Controller Driver 1297c478bd9Sstevel@tonic-gate * (HCD). 1307c478bd9Sstevel@tonic-gate */ 1317c478bd9Sstevel@tonic-gate typedef volatile struct ohci_regs { 1327c478bd9Sstevel@tonic-gate /* Control and status registers */ 1337c478bd9Sstevel@tonic-gate uint32_t hcr_revision; /* Specification version */ 1347c478bd9Sstevel@tonic-gate uint32_t hcr_control; /* Control information */ 1357c478bd9Sstevel@tonic-gate uint32_t hcr_cmd_status; /* Controller status */ 1367c478bd9Sstevel@tonic-gate uint32_t hcr_intr_status; /* Interrupt status register */ 1377c478bd9Sstevel@tonic-gate uint32_t hcr_intr_enable; /* Interrupt enable */ 1387c478bd9Sstevel@tonic-gate uint32_t hcr_intr_disable; /* Interrupt disable */ 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate /* Memory pointer registers */ 1417c478bd9Sstevel@tonic-gate uint32_t hcr_HCCA; /* Pointer to HCCA */ 1427c478bd9Sstevel@tonic-gate uint32_t hcr_periodic_curr; /* Curr. isoch or int endpt */ 1437c478bd9Sstevel@tonic-gate uint32_t hcr_ctrl_head; /* Head of contrl list */ 1447c478bd9Sstevel@tonic-gate uint32_t hcr_ctrl_curr; /* Curr. control endpt */ 1457c478bd9Sstevel@tonic-gate uint32_t hcr_bulk_head; /* Head of the bulk list */ 1467c478bd9Sstevel@tonic-gate uint32_t hcr_bulk_curr; /* Curr. bulk endpt */ 1477c478bd9Sstevel@tonic-gate uint32_t hcr_done_head; /* Head of the done list */ 1487c478bd9Sstevel@tonic-gate 1497c478bd9Sstevel@tonic-gate /* Frame counter registers */ 1507c478bd9Sstevel@tonic-gate uint32_t hcr_frame_interval; /* Frame interval value */ 1517c478bd9Sstevel@tonic-gate uint32_t hcr_frame_remaining; /* Time remaining in frame */ 1527c478bd9Sstevel@tonic-gate uint32_t hcr_frame_number; /* Frame number */ 1537c478bd9Sstevel@tonic-gate uint32_t hcr_periodic_strt; /* Time to start per. list */ 1547c478bd9Sstevel@tonic-gate uint32_t hcr_transfer_ls; /* Low speed threshold */ 1557c478bd9Sstevel@tonic-gate 1567c478bd9Sstevel@tonic-gate /* Root hub registers */ 1577c478bd9Sstevel@tonic-gate uint32_t hcr_rh_descriptorA; /* Root hub register A */ 1587c478bd9Sstevel@tonic-gate uint32_t hcr_rh_descriptorB; /* Root hub register B */ 1597c478bd9Sstevel@tonic-gate uint32_t hcr_rh_status; /* Root hub status */ 1607c478bd9Sstevel@tonic-gate uint32_t hcr_rh_portstatus[OHCI_MAX_RH_PORTS]; /* RH port sts */ 1617c478bd9Sstevel@tonic-gate } ohci_regs_t; 1627c478bd9Sstevel@tonic-gate 1637c478bd9Sstevel@tonic-gate /* hcr_revision bits */ 1647c478bd9Sstevel@tonic-gate #define HCR_REVISION_1_0 0x00000010 /* Revision 1.0 */ 1657c478bd9Sstevel@tonic-gate #define HCR_REVISION_MASK 0x000000FF /* Revision mask */ 1667c478bd9Sstevel@tonic-gate 1677c478bd9Sstevel@tonic-gate /* hcr_control bits */ 1687c478bd9Sstevel@tonic-gate #define HCR_CONTROL_CBSR 0x00000003 /* Control/bulk ratio */ 1697c478bd9Sstevel@tonic-gate #define HCR_CONTROL_PLE 0x00000004 /* Periodic list enable */ 1707c478bd9Sstevel@tonic-gate #define HCR_CONTROL_IE 0x00000008 /* Isochronous enable */ 1717c478bd9Sstevel@tonic-gate #define HCR_CONTROL_CLE 0x00000010 /* Control list enable */ 1727c478bd9Sstevel@tonic-gate #define HCR_CONTROL_BLE 0x00000020 /* Bulk list enable */ 1737c478bd9Sstevel@tonic-gate #define HCR_CONTROL_HCFS 0x000000C0 /* Controller state */ 1747c478bd9Sstevel@tonic-gate #define HCR_CONTROL_IR 0x00000100 /* Interrupt routing */ 1757c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RWC 0x00000200 /* Remote wakeup connected */ 1767c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RWE 0x00000400 /* Remote wakeup enabled */ 1777c478bd9Sstevel@tonic-gate 1787c478bd9Sstevel@tonic-gate /* Values for the Host Controller Functional State bits (HCR_CONTROL_HCFS) */ 1797c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RESET 0x00000000 /* USB Reset */ 1807c478bd9Sstevel@tonic-gate #define HCR_CONTROL_RESUME 0x00000040 /* USB Resume */ 1817c478bd9Sstevel@tonic-gate #define HCR_CONTROL_OPERAT 0x00000080 /* USB Operational */ 1827c478bd9Sstevel@tonic-gate #define HCR_CONTROL_SUSPD 0x000000C0 /* USB Suspend */ 1837c478bd9Sstevel@tonic-gate 1847c478bd9Sstevel@tonic-gate /* hcr_cmd_status bits */ 1857c478bd9Sstevel@tonic-gate #define HCR_STATUS_RESET 0x00000001 /* Host controller reset */ 1867c478bd9Sstevel@tonic-gate #define HCR_STATUS_CLF 0x00000002 /* Control list filled */ 1877c478bd9Sstevel@tonic-gate #define HCR_STATUS_BLF 0x00000004 /* Bulk list filled */ 1887c478bd9Sstevel@tonic-gate #define HCR_STATUS_OCR 0x00000008 /* Ownership change */ 1897c478bd9Sstevel@tonic-gate #define HCR_STATUS_SOC 0x00030000 /* Error frame count */ 1907c478bd9Sstevel@tonic-gate 1917c478bd9Sstevel@tonic-gate /* hcr_intr_status bits and hcr_intr_mask bits */ 1927c478bd9Sstevel@tonic-gate #define HCR_INTR_SO 0x00000001 /* Schedule overrun */ 1937c478bd9Sstevel@tonic-gate #define HCR_INTR_WDH 0x00000002 /* Writeback done head */ 1947c478bd9Sstevel@tonic-gate #define HCR_INTR_SOF 0x00000004 /* Start of frame */ 1957c478bd9Sstevel@tonic-gate #define HCR_INTR_RD 0x00000008 /* Resume detected */ 1967c478bd9Sstevel@tonic-gate #define HCR_INTR_UE 0x00000010 /* Unrecoverable error */ 1977c478bd9Sstevel@tonic-gate #define HCR_INTR_FNO 0x00000020 /* Frame no. overflow */ 1987c478bd9Sstevel@tonic-gate #define HCR_INTR_RHSC 0x00000040 /* Root hub status change */ 1997c478bd9Sstevel@tonic-gate #define HCR_INTR_OC 0x40000000 /* Change in ownership */ 2007c478bd9Sstevel@tonic-gate #define HCR_INTR_MIE 0x80000000 /* Master interrupt enable */ 2017c478bd9Sstevel@tonic-gate 2027c478bd9Sstevel@tonic-gate /* hcr_frame_interval bits */ 2037c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FI 0x00003FFF /* Frame interval */ 2047c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FSMPS 0x7FFF0000 /* Biggest packet */ 2057c478bd9Sstevel@tonic-gate #define HCR_FRME_FSMPS_SHFT 16 /* FSMPS */ 2067c478bd9Sstevel@tonic-gate #define HCR_FRME_INT_FIT 0x80000000 /* Frame interval toggle */ 2077c478bd9Sstevel@tonic-gate #define MAX_OVERHEAD 210 /* Max. bit overhead */ 2087c478bd9Sstevel@tonic-gate 2097c478bd9Sstevel@tonic-gate /* hcr_frame_remaining bits */ 2107c478bd9Sstevel@tonic-gate #define HCR_FRME_REM_FR 0x00003FFF /* Frame remaining */ 2117c478bd9Sstevel@tonic-gate #define HCR_FRME_REM_FRT 0x80000000 /* Frame remaining toggle */ 2127c478bd9Sstevel@tonic-gate 2137c478bd9Sstevel@tonic-gate /* hcr_transfer_ls */ 2147c478bd9Sstevel@tonic-gate #define HCR_TRANS_LST 0x000007FF /* Low Speed threshold */ 2157c478bd9Sstevel@tonic-gate 2167c478bd9Sstevel@tonic-gate /* hcr_rh_descriptorA bits */ 2177c478bd9Sstevel@tonic-gate #define HCR_RHA_NDP 0x000000FF /* No. of ports */ 2187c478bd9Sstevel@tonic-gate #define HCR_RHA_PSM 0x00000100 /* Power switch mode */ 2197c478bd9Sstevel@tonic-gate #define HCR_RHA_NPS 0x00000200 /* No power switching */ 2207c478bd9Sstevel@tonic-gate #define HCR_RHA_DT 0x00000400 /* Device type */ 2217c478bd9Sstevel@tonic-gate #define HCR_RHA_OCPM 0x00000800 /* Over-current protection */ 2227c478bd9Sstevel@tonic-gate #define HCR_RHA_NOCP 0x00001000 /* No over-current protection */ 2237c478bd9Sstevel@tonic-gate #define HCR_RHA_PTPGT 0xFF000000 /* Power on to power good */ 2247c478bd9Sstevel@tonic-gate #define HCR_RHA_PTPGT_SHIFT 24 /* Shift bits for ptpgt */ 2257c478bd9Sstevel@tonic-gate 2267c478bd9Sstevel@tonic-gate /* hcr_rh_descriptorB bits */ 2277c478bd9Sstevel@tonic-gate #define HCR_RHB_DR 0x0000FFFF /* Device removable */ 2287c478bd9Sstevel@tonic-gate #define HCR_RHB_PPCM 0xFFFF0000 /* PortPowerControlMask */ 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate /* hcr_rh_status bits */ 2317c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_LPS 0x00000001 /* Local power status */ 2327c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_OCI 0x00000002 /* Over current indicator */ 2337c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_DRWE 0x00008000 /* Device remote wakeup */ 2347c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_LPSC 0x00010000 /* Local power status change */ 2357c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_OCIC 0x00020000 /* Over current indicator */ 2367c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_CRWE 0x80000000 /* Clear remote wakeup enable */ 2377c478bd9Sstevel@tonic-gate #define HCR_RH_STATUS_MASK 0x10038003 /* Status mask */ 238fef1e07eSsl #define HCR_RH_CHNG_MASK 0x00030000 /* Mask for change bits */ 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate /* hcr_rh_portstatus bits */ 2417c478bd9Sstevel@tonic-gate #define HCR_PORT_CCS 0x00000001 /* Current connect status */ 2427c478bd9Sstevel@tonic-gate #define HCR_PORT_PES 0x00000002 /* Port enable */ 2437c478bd9Sstevel@tonic-gate #define HCR_PORT_PSS 0x00000004 /* Port suspend status */ 2447c478bd9Sstevel@tonic-gate #define HCR_PORT_POCI 0x00000008 /* Port over crrnt indicator */ 2457c478bd9Sstevel@tonic-gate #define HCR_PORT_PRS 0x00000010 /* Port reset status */ 2467c478bd9Sstevel@tonic-gate #define HCR_PORT_PPS 0x00000100 /* Port power status */ 2477c478bd9Sstevel@tonic-gate #define HCR_PORT_CPP 0x00000200 /* Clear port power */ 2487c478bd9Sstevel@tonic-gate #define HCR_PORT_LSDA 0x00000200 /* Low speed device */ 2497c478bd9Sstevel@tonic-gate #define HCR_PORT_CSC 0x00010000 /* Connect status change */ 2507c478bd9Sstevel@tonic-gate #define HCR_PORT_PESC 0x00020000 /* Port enable status change */ 2517c478bd9Sstevel@tonic-gate #define HCR_PORT_PSSC 0x00040000 /* Port suspend status change */ 2527c478bd9Sstevel@tonic-gate #define HCR_PORT_OCIC 0x00080000 /* Port over current change */ 2537c478bd9Sstevel@tonic-gate #define HCR_PORT_PRSC 0x00100000 /* Port reset status chnge */ 2547c478bd9Sstevel@tonic-gate #define HCR_PORT_MASK 0x001F031F /* Reserved written as 0 */ 2557c478bd9Sstevel@tonic-gate #define HCR_PORT_CHNG_MASK 0x001F0000 /* Mask for change bits */ 2567c478bd9Sstevel@tonic-gate 2577c478bd9Sstevel@tonic-gate #define DONE_QUEUE_INTR_COUNTER 0x7 /* Done queue intr counter */ 2587c478bd9Sstevel@tonic-gate 2597c478bd9Sstevel@tonic-gate /* 2607c478bd9Sstevel@tonic-gate * Host Controller Communications Area 2617c478bd9Sstevel@tonic-gate * 2627c478bd9Sstevel@tonic-gate * The Host Controller Communications Area (HCCA) is a 256-byte structre 2637c478bd9Sstevel@tonic-gate * of system memory that is established by the Host Controller Driver (HCD) 2647c478bd9Sstevel@tonic-gate * and this structre is used for communication between HCD and HC. The HCD 2657c478bd9Sstevel@tonic-gate * maintains a pointer to this structure in the Host Controller (HC). This 2667c478bd9Sstevel@tonic-gate * structure must be aligned to a 256-byte boundary. 2677c478bd9Sstevel@tonic-gate */ 2687c478bd9Sstevel@tonic-gate 2697c478bd9Sstevel@tonic-gate #define NUM_INTR_ED_LISTS 32 /* Number of interrupt lists */ 2707c478bd9Sstevel@tonic-gate #define NUM_STATIC_NODES 31 /* Number of static endpoints */ 2717c478bd9Sstevel@tonic-gate 2727c478bd9Sstevel@tonic-gate typedef volatile struct ohci_hcca { 2737c478bd9Sstevel@tonic-gate uint32_t HccaIntTble[NUM_INTR_ED_LISTS]; /* 32 intr lists */ 2747c478bd9Sstevel@tonic-gate /* Ptrs to ohci_ed */ 2757c478bd9Sstevel@tonic-gate uint16_t HccaFrameNo; /* Current frame number */ 2767c478bd9Sstevel@tonic-gate uint16_t HccaPad; /* 0 when HC updates FrameNo */ 2777c478bd9Sstevel@tonic-gate uint32_t HccaDoneHead; /* Head ptr */ 2787c478bd9Sstevel@tonic-gate uint8_t HccaReserved[120]; /* Reserved area */ 2797c478bd9Sstevel@tonic-gate } ohci_hcca_t; 2807c478bd9Sstevel@tonic-gate 2817c478bd9Sstevel@tonic-gate #define HCCA_DONE_HEAD_MASK 0xFFFFFFF0 /* Hcca done head mask */ 2827c478bd9Sstevel@tonic-gate #define HCCA_DONE_HEAD_LSB 0x00000001 /* Lsb of the Done Head */ 2837c478bd9Sstevel@tonic-gate 2847c478bd9Sstevel@tonic-gate 2857c478bd9Sstevel@tonic-gate /* 2867c478bd9Sstevel@tonic-gate * Host Controller Endpoint Descriptor 2877c478bd9Sstevel@tonic-gate * 2887c478bd9Sstevel@tonic-gate * An Endpoint Descriptor (ED) is a memory structure that describes the 2897c478bd9Sstevel@tonic-gate * information necessary for the Host Controller (HC) to communicate with 2907c478bd9Sstevel@tonic-gate * a device endpoint. An ED includes a Transfer Descriptor (TD) pointer. 2917c478bd9Sstevel@tonic-gate * This structure must be aligned to a 16 byte boundary. 2927c478bd9Sstevel@tonic-gate */ 2937c478bd9Sstevel@tonic-gate typedef volatile struct ohci_ed { 2947c478bd9Sstevel@tonic-gate uint32_t hced_ctrl; /* See below */ 2957c478bd9Sstevel@tonic-gate uint32_t hced_tailp; /* (ohci_td *) End of trans. list */ 2967c478bd9Sstevel@tonic-gate uint32_t hced_headp; /* (ohci_td *) Next trans. */ 2977c478bd9Sstevel@tonic-gate uint32_t hced_next; /* (ohci_ed *) Next endpoint */ 2987c478bd9Sstevel@tonic-gate uint32_t hced_prev; /* (ohci_ed *)Virt addr. of prev ept */ 2997c478bd9Sstevel@tonic-gate uint32_t hced_node; /* The node that its attached */ 3007c478bd9Sstevel@tonic-gate uint32_t hced_reclaim_next; /* (ohci_ed *) Reclaim list */ 3017c478bd9Sstevel@tonic-gate uint32_t hced_reclaim_frame; /* Reclaim usb frame number */ 3027c478bd9Sstevel@tonic-gate uint32_t hced_state; /* Endpoint state */ 3037c478bd9Sstevel@tonic-gate uint8_t hce_pad[12]; /* Required padding */ 3047c478bd9Sstevel@tonic-gate } ohci_ed_t; 3057c478bd9Sstevel@tonic-gate 3067c478bd9Sstevel@tonic-gate /* 3077c478bd9Sstevel@tonic-gate * hc_endpoint_descriptor control bits 3087c478bd9Sstevel@tonic-gate */ 3097c478bd9Sstevel@tonic-gate #define HC_EPT_FUNC 0x0000007F /* Address of function */ 3107c478bd9Sstevel@tonic-gate #define HC_EPT_EP 0x00000780 /* Address of endpoint */ 3117c478bd9Sstevel@tonic-gate #define HC_EPT_DataFlow 0x00001800 /* Direction of data flow */ 3127c478bd9Sstevel@tonic-gate #define HC_EPT_DF_IN 0x00001000 /* Data flow in */ 3137c478bd9Sstevel@tonic-gate #define HC_EPT_DF_OUT 0x00000800 /* Data flow out */ 3147c478bd9Sstevel@tonic-gate #define HC_EPT_Speed 0x00002000 /* Speed of the endpoint */ 3157c478bd9Sstevel@tonic-gate #define HC_EPT_sKip 0x00004000 /* Skip bit */ 3167c478bd9Sstevel@tonic-gate #define HC_EPT_Format 0x00008000 /* Type of transfer */ 3177c478bd9Sstevel@tonic-gate #define HC_EPT_MPS 0x0EFF0000 /* Max packet size */ 3187c478bd9Sstevel@tonic-gate #define HC_EPT_8_MPS 0x00080000 /* 8 byte max packet size */ 3197c478bd9Sstevel@tonic-gate #define HC_EPT_64_MPS 0x00400000 /* 64 byte max packet size */ 3207c478bd9Sstevel@tonic-gate #define HC_EPT_Halt 0x00000001 /* Halted */ 3217c478bd9Sstevel@tonic-gate #define HC_EPT_Carry 0x00000002 /* Toggle carry */ 3227c478bd9Sstevel@tonic-gate 3237c478bd9Sstevel@tonic-gate #define HC_EPT_EP_SHFT 7 /* Bits to shift addr */ 3247c478bd9Sstevel@tonic-gate #define HC_EPT_MAXPKTSZ 16 /* Bits to shift maxpktsize */ 3257c478bd9Sstevel@tonic-gate 3267c478bd9Sstevel@tonic-gate #define HC_EPT_TD_TAIL 0xFFFFFFF0 /* TD tail mask */ 3277c478bd9Sstevel@tonic-gate #define HC_EPT_TD_HEAD 0xFFFFFFF0 /* TD head mask */ 3287c478bd9Sstevel@tonic-gate #define HC_EPT_NEXT 0xFFFFFFF0 /* Next endpoint mask */ 3297c478bd9Sstevel@tonic-gate 3307c478bd9Sstevel@tonic-gate /* 3317c478bd9Sstevel@tonic-gate * hced_state 3327c478bd9Sstevel@tonic-gate * 3337c478bd9Sstevel@tonic-gate * ED states 3347c478bd9Sstevel@tonic-gate */ 3357c478bd9Sstevel@tonic-gate #define HC_EPT_FREE 1 /* Free ED */ 3367c478bd9Sstevel@tonic-gate #define HC_EPT_STATIC 2 /* Static ED */ 3377c478bd9Sstevel@tonic-gate #define HC_EPT_ACTIVE 3 /* Active ED */ 3387c478bd9Sstevel@tonic-gate 3397c478bd9Sstevel@tonic-gate 3407c478bd9Sstevel@tonic-gate /* 3417c478bd9Sstevel@tonic-gate * Host Controller Transfer Descriptor 3427c478bd9Sstevel@tonic-gate * 3437c478bd9Sstevel@tonic-gate * A Transfer Descriptor (TD) is a memory structure that describes the 3447c478bd9Sstevel@tonic-gate * information necessary for the Host Controller (HC) to transfer a block 3457c478bd9Sstevel@tonic-gate * of data to or from a device endpoint. These TD's will be attached to 3467c478bd9Sstevel@tonic-gate * a Endpoint Descriptor (ED). This structure includes the fields for both 3477c478bd9Sstevel@tonic-gate * General and Isochronous Transfer Descriptors. The General TDs must be 3487c478bd9Sstevel@tonic-gate * aligned to 16 byte, where as Isochronous TDs must be aligned to 32 byte. 3497c478bd9Sstevel@tonic-gate */ 3507c478bd9Sstevel@tonic-gate typedef volatile struct ohci_td { 3517c478bd9Sstevel@tonic-gate uint32_t hctd_ctrl; /* See below */ 3527c478bd9Sstevel@tonic-gate uint32_t hctd_cbp; /* Next buffer addr */ 3537c478bd9Sstevel@tonic-gate uint32_t hctd_next_td; /* Next TD */ 3547c478bd9Sstevel@tonic-gate uint32_t hctd_buf_end; /* End of buffer */ 3557c478bd9Sstevel@tonic-gate uint32_t hctd_offsets[4]; /* Offsets into buf */ 3567c478bd9Sstevel@tonic-gate /* Used only for isoch */ 3577c478bd9Sstevel@tonic-gate uint32_t hctd_trans_wrapper; /* Transfer wrapper */ 3587c478bd9Sstevel@tonic-gate uint32_t hctd_state; /* TD state */ 3597c478bd9Sstevel@tonic-gate uint32_t hctd_tw_next_td; /* Next TD on TW */ 3607c478bd9Sstevel@tonic-gate uint32_t hctd_ctrl_phase; /* Control Xfer Phase info */ 36102acac7eSsl uint32_t hctd_xfer_offs; /* Starting buffer offset */ 36202acac7eSsl uint32_t hctd_xfer_len; /* Transfer length */ 36302acac7eSsl uint8_t hctd_pad[8]; /* Required padding */ 3647c478bd9Sstevel@tonic-gate } ohci_td_t; 3657c478bd9Sstevel@tonic-gate 3667c478bd9Sstevel@tonic-gate /* 3677c478bd9Sstevel@tonic-gate * Common hc_td control bits both for the General and Isochronous Transfer 3687c478bd9Sstevel@tonic-gate * Descriptors. 3697c478bd9Sstevel@tonic-gate */ 3707c478bd9Sstevel@tonic-gate #define HC_TD_DI 0x00E00000 /* Delay interrupt */ 3717c478bd9Sstevel@tonic-gate #define HC_TD_0I 0x00000000 /* 0 frame for interrupt */ 3727c478bd9Sstevel@tonic-gate #define HC_TD_1I 0x00200000 /* 1 frame for interrupt */ 3737c478bd9Sstevel@tonic-gate #define HC_TD_2I 0x00400000 /* 2 frame for interrupt */ 3747c478bd9Sstevel@tonic-gate #define HC_TD_3I 0x00600000 /* 3 frame for interrupt */ 3757c478bd9Sstevel@tonic-gate #define HC_TD_4I 0x00800000 /* 4 frame's for interrupt */ 3767c478bd9Sstevel@tonic-gate #define HC_TD_5I 0x00A00000 /* 5 frame for interrupt */ 3777c478bd9Sstevel@tonic-gate #define HC_TD_6I 0x00C00000 /* 6 frame for interrupt */ 3787c478bd9Sstevel@tonic-gate #define HC_TD_7I 0x00E00000 /* 7 frame for interrupt */ 3797c478bd9Sstevel@tonic-gate #define HC_TD_CC 0xF0000000 /* Condition code */ 3807c478bd9Sstevel@tonic-gate 3817c478bd9Sstevel@tonic-gate #define HC_TD_R 0x00040000 /* Buffer rounding */ 3827c478bd9Sstevel@tonic-gate #define HC_TD_PID 0x00180000 /* Pid for the token */ 3837c478bd9Sstevel@tonic-gate #define HC_TD_SETUP 0x00000000 /* Setup direction */ 3847c478bd9Sstevel@tonic-gate #define HC_TD_IN 0x00100000 /* In direction */ 3857c478bd9Sstevel@tonic-gate #define HC_TD_OUT 0x00080000 /* Out direction */ 3867c478bd9Sstevel@tonic-gate #define HC_TD_DT 0x03000000 /* Data Toggle */ 3877c478bd9Sstevel@tonic-gate #define HC_TD_MS_DT 0x02000000 /* Master data toggle */ 3887c478bd9Sstevel@tonic-gate #define HC_TD_DT_0 0x00000000 /* Toggle from TD 0 */ 3897c478bd9Sstevel@tonic-gate #define HC_TD_DT_1 0x01000000 /* Toggle from TD 1 */ 3907c478bd9Sstevel@tonic-gate #define HC_TD_EC 0x0C000000 /* Error Count */ 3917c478bd9Sstevel@tonic-gate 3927c478bd9Sstevel@tonic-gate /* 3937c478bd9Sstevel@tonic-gate * hc_td control bits specific to Isochronous Transfer Descriptors. 3947c478bd9Sstevel@tonic-gate */ 3957c478bd9Sstevel@tonic-gate #define HC_ITD_SF 0x0000FFFF /* Starting Frame number */ 3967c478bd9Sstevel@tonic-gate #define HC_ITD_FC 0x07000000 /* Frame count */ 3977c478bd9Sstevel@tonic-gate 3987c478bd9Sstevel@tonic-gate #define HC_ITD_FC_SHIFT 24 /* Frame count shift */ 3997c478bd9Sstevel@tonic-gate #define HC_ITD_PAGE_MASK 0xFFFFF000 4007c478bd9Sstevel@tonic-gate #define HC_ITD_ODD_OFFSET 0xFFFF0000 /* Odd offset */ 4017c478bd9Sstevel@tonic-gate #define HC_ITD_EVEN_OFFSET 0x0000FFFF /* Even offset */ 4027c478bd9Sstevel@tonic-gate #define HC_ITD_OFFSET_SHIFT 16 403b3001defSlg #define HC_ITD_OFFSET_CC 0x0000E000 /* CC of offset or PSW N */ 4047c478bd9Sstevel@tonic-gate #define HC_ITD_OFFSET_ADDR 0x00000FFF /* Offset N */ 4057c478bd9Sstevel@tonic-gate #define HC_ITD_4KBOUNDARY_CROSS 0x00001000 /* Set bit 12 for 4k crossing */ 4067c478bd9Sstevel@tonic-gate 4077c478bd9Sstevel@tonic-gate /* 4087c478bd9Sstevel@tonic-gate * Condition codes both to General and Isochronous Transfer Descriptors. 4097c478bd9Sstevel@tonic-gate * Even these condition codes are valid for offsets of the isochronous 4107c478bd9Sstevel@tonic-gate * transfer descriptos. 4117c478bd9Sstevel@tonic-gate */ 4127c478bd9Sstevel@tonic-gate #define HC_TD_CC_NO_E 0x00000000 /* No error */ 4137c478bd9Sstevel@tonic-gate #define HC_TD_CC_CRC 0x10000000 /* CRC error */ 4147c478bd9Sstevel@tonic-gate #define HC_TD_CC_BS 0x20000000 /* Bit stuffing */ 4157c478bd9Sstevel@tonic-gate #define HC_TD_CC_DTM 0x30000000 /* Data Toggle Mismatch */ 4167c478bd9Sstevel@tonic-gate #define HC_TD_CC_STALL 0x40000000 /* Stall */ 4177c478bd9Sstevel@tonic-gate #define HC_TD_CC_DNR 0x50000000 /* Device not responding */ 4187c478bd9Sstevel@tonic-gate #define HC_TD_CC_PCF 0x60000000 /* PID check failure */ 4197c478bd9Sstevel@tonic-gate #define HC_TD_CC_UPID 0x70000000 /* Unexpected PID */ 4207c478bd9Sstevel@tonic-gate #define HC_TD_CC_DO 0x80000000 /* Data overrrun */ 4217c478bd9Sstevel@tonic-gate #define HC_TD_CC_DU 0x90000000 /* Data underrun */ 4227c478bd9Sstevel@tonic-gate #define HC_TD_CC_BO 0xC0000000 /* Buffer overrun */ 4237c478bd9Sstevel@tonic-gate #define HC_TD_CC_BU 0xD0000000 /* Buffer underrun */ 4247c478bd9Sstevel@tonic-gate #define HC_TD_CC_NA 0xF0000000 /* Not accessed */ 4257c478bd9Sstevel@tonic-gate 4267c478bd9Sstevel@tonic-gate #define HC_TD_NEXT 0xFFFFFFF0 /* Next TD */ 4277c478bd9Sstevel@tonic-gate 4287c478bd9Sstevel@tonic-gate /* 4297c478bd9Sstevel@tonic-gate * Condition codes specific to Isochronous Transfer Descriptors. 4307c478bd9Sstevel@tonic-gate */ 4317c478bd9Sstevel@tonic-gate #define HC_ITD_CC_SHIFT 16 /* ITD CC shift */ 4327c478bd9Sstevel@tonic-gate 4337c478bd9Sstevel@tonic-gate /* 4347c478bd9Sstevel@tonic-gate * hctd_state 4357c478bd9Sstevel@tonic-gate * 4367c478bd9Sstevel@tonic-gate * TD States 4377c478bd9Sstevel@tonic-gate */ 4387c478bd9Sstevel@tonic-gate #define HC_TD_FREE 1 /* Free TD */ 4397c478bd9Sstevel@tonic-gate #define HC_TD_DUMMY 2 /* Dummy TD */ 4407c478bd9Sstevel@tonic-gate #define HC_TD_ACTIVE 3 /* Active TD */ 4417c478bd9Sstevel@tonic-gate #define HC_TD_TIMEOUT 4 /* Timeouted TD */ 4427c478bd9Sstevel@tonic-gate #define HC_TD_RECLAIM 5 /* Reclaimed TD */ 4437c478bd9Sstevel@tonic-gate 4447c478bd9Sstevel@tonic-gate /* 4457c478bd9Sstevel@tonic-gate * hctd_ctrl_phase 4467c478bd9Sstevel@tonic-gate * 4477c478bd9Sstevel@tonic-gate * Control Transfer Phase information 4487c478bd9Sstevel@tonic-gate */ 4497c478bd9Sstevel@tonic-gate #define OHCI_CTRL_SETUP_PHASE 1 /* Setup phase */ 4507c478bd9Sstevel@tonic-gate #define OHCI_CTRL_DATA_PHASE 2 /* Data phase */ 4517c478bd9Sstevel@tonic-gate #define OHCI_CTRL_STATUS_PHASE 3 /* Status phase */ 4527c478bd9Sstevel@tonic-gate 45302acac7eSsl /* 45402acac7eSsl * Structure for Isoc DMA buffer 45502acac7eSsl * One Isoc transfer includes multiple Isoc packets and need to be 45602acac7eSsl * transfered in multiple TDs. 45702acac7eSsl * One DMA buffer is allocated for one Isoc TD which may hold up 45802acac7eSsl * to eight Isoc packets. 45902acac7eSsl */ 46002acac7eSsl typedef struct ohci_isoc_buf { 46102acac7eSsl caddr_t buf_addr; /* Starting buffer address */ 46202acac7eSsl ddi_dma_cookie_t cookie; /* DMA cookie */ 46302acac7eSsl ddi_dma_handle_t dma_handle; /* DMA handle */ 46402acac7eSsl ddi_acc_handle_t mem_handle; /* Memory handle */ 46502acac7eSsl size_t length; /* Buffer length */ 46602acac7eSsl uint_t ncookies; /* DMA cookie count */ 46702acac7eSsl uint_t index; /* Index of the TD */ 46802acac7eSsl } ohci_isoc_buf_t; 4697c478bd9Sstevel@tonic-gate 4707c478bd9Sstevel@tonic-gate #ifdef __cplusplus 4717c478bd9Sstevel@tonic-gate } 4727c478bd9Sstevel@tonic-gate #endif 4737c478bd9Sstevel@tonic-gate 4747c478bd9Sstevel@tonic-gate #endif /* _SYS_USB_OHCI_H */ 475