1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_USB_OHCI_H
28 #define	_SYS_USB_OHCI_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 /*
37  * Open Host Controller Driver (OHCI)
38  *
39  * The USB Open Host Controller driver is a software driver which interfaces
40  * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller.
41  * The interface to USB Open Host Controller is defined by the OpenHCI  Host
42  * Controller Interface.
43  *
44  * This header file describes the registers and data structures shared by the
45  * USB Open Host Controller and the USB Open Host Controller Driver.
46  */
47 
48 #include <sys/types.h>
49 #include <sys/pci.h>
50 #include <sys/kstat.h>
51 #include <sys/sunddi.h>
52 #include <sys/sunndi.h>
53 #include <sys/ndi_impldefs.h>
54 
55 #include <sys/usb/usba.h>
56 
57 #include <sys/usb/usba/hcdi.h>
58 
59 #include <sys/usb/hubd/hub.h>
60 #include <sys/usb/usba/hubdi.h>
61 #include <sys/usb/hubd/hubdvar.h>
62 
63 #include <sys/id32.h>
64 
65 #define	OHCI_MAX_RH_PORTS		15	/* Maximum root hub ports */
66 
67 /*
68  * Each OHCI buffer can hold upto 8k bytes of data. Hence there is a
69  * restriction of 4k alignment while allocating a dma buffer.
70  */
71 #define	OHCI_4K_ALIGN			0x1000
72 
73 /*
74  * USB Host controller DMA scatter gather list defines for
75  * Sparc and non-sparc architectures.
76  */
77 #if defined(__sparc)
78 #define	OHCI_DMA_ATTR_MAX_XFER		0xffffffffull
79 #define	OHCI_DMA_ATTR_COUNT_MAX		0xffffffffull
80 #define	OHCI_DMA_ATTR_GRANULAR		512
81 #define	OHCI_DMA_ATTR_ALIGNMENT		OHCI_4K_ALIGN
82 #else
83 #define	OHCI_DMA_ATTR_MAX_XFER		0x00ffffffull
84 #define	OHCI_DMA_ATTR_COUNT_MAX		0x00ffffffull
85 #define	OHCI_DMA_ATTR_GRANULAR		1
86 #define	OHCI_DMA_ATTR_ALIGNMENT		1
87 #endif
88 
89 /*
90  * According to the OHCI spec ED and TD need to be 16 byte aligned.
91  * However, iTD needs to be 32 byte aligned.  Since we do not
92  * distinguish between iTD and TD, make them both 32 byte aligned.
93  *
94  * ED   =  16 byte aligned
95  * TD   =  32 byte aligned
96  * HCCA = 256 byte aligned
97  */
98 #define	OHCI_DMA_ATTR_ED_ALIGNMENT	0x010
99 #define	OHCI_DMA_ATTR_TD_ALIGNMENT	0x020
100 #define	OHCI_DMA_ATTR_HCCA_ALIGNMENT	0x100
101 
102 /*
103  * OpenHCI Operational Registers
104  *
105  * The Host Controller (HC) contains a set of on-chip operational registers
106  * which are mapped into a noncacheable portion of the system addressable
107  * space and these registers are also used by the Host Controller Driver
108  * (HCD).
109  */
110 typedef volatile struct ohci_regs {
111 	/* Control and status registers */
112 	uint32_t 	hcr_revision;		/* Specification version */
113 	uint32_t	hcr_control;		/* Control information */
114 	uint32_t	hcr_cmd_status;		/* Controller status */
115 	uint32_t	hcr_intr_status;	/* Interrupt status register */
116 	uint32_t 	hcr_intr_enable;	/* Interrupt enable */
117 	uint32_t	hcr_intr_disable;	/* Interrupt disable */
118 
119 	/* Memory pointer registers */
120 	uint32_t	hcr_HCCA;		/* Pointer to HCCA */
121 	uint32_t	hcr_periodic_curr;	/* Curr. isoch or int endpt */
122 	uint32_t	hcr_ctrl_head;		/* Head of contrl list */
123 	uint32_t	hcr_ctrl_curr;		/* Curr. control endpt */
124 	uint32_t	hcr_bulk_head;		/* Head of the bulk list */
125 	uint32_t	hcr_bulk_curr;		/* Curr. bulk endpt */
126 	uint32_t	hcr_done_head;		/* Head of the done list */
127 
128 	/* Frame counter registers */
129 	uint32_t	hcr_frame_interval;	/* Frame interval value */
130 	uint32_t 	hcr_frame_remaining;    /* Time remaining in frame */
131 	uint32_t	hcr_frame_number;	/* Frame number */
132 	uint32_t	hcr_periodic_strt;	/* Time to start per. list */
133 	uint32_t	hcr_transfer_ls;	/* Low speed threshold */
134 
135 	/* Root hub registers */
136 	uint32_t	hcr_rh_descriptorA;	/* Root hub register A */
137 	uint32_t	hcr_rh_descriptorB;	/* Root hub register B */
138 	uint32_t	hcr_rh_status;		/* Root hub status */
139 	uint32_t 	hcr_rh_portstatus[OHCI_MAX_RH_PORTS]; /* RH port sts */
140 } ohci_regs_t;
141 
142 /* hcr_revision bits */
143 #define	HCR_REVISION_1_0	0x00000010	/* Revision 1.0 */
144 #define	HCR_REVISION_MASK	0x000000FF	/* Revision mask */
145 
146 /* hcr_control bits */
147 #define	HCR_CONTROL_CBSR	0x00000003	/* Control/bulk ratio */
148 #define	HCR_CONTROL_PLE		0x00000004	/* Periodic list enable */
149 #define	HCR_CONTROL_IE		0x00000008	/* Isochronous enable */
150 #define	HCR_CONTROL_CLE		0x00000010	/* Control list enable */
151 #define	HCR_CONTROL_BLE		0x00000020	/* Bulk list enable */
152 #define	HCR_CONTROL_HCFS	0x000000C0	/* Controller state */
153 #define	HCR_CONTROL_IR		0x00000100	/* Interrupt routing */
154 #define	HCR_CONTROL_RWC		0x00000200	/* Remote wakeup connected */
155 #define	HCR_CONTROL_RWE		0x00000400	/* Remote wakeup enabled */
156 
157 /* Values for the Host Controller Functional State bits (HCR_CONTROL_HCFS) */
158 #define	HCR_CONTROL_RESET	0x00000000	/* USB Reset */
159 #define	HCR_CONTROL_RESUME	0x00000040	/* USB Resume */
160 #define	HCR_CONTROL_OPERAT	0x00000080	/* USB Operational */
161 #define	HCR_CONTROL_SUSPD	0x000000C0	/* USB Suspend */
162 
163 /* hcr_cmd_status bits */
164 #define	HCR_STATUS_RESET	0x00000001	/* Host controller reset */
165 #define	HCR_STATUS_CLF		0x00000002	/* Control list filled */
166 #define	HCR_STATUS_BLF		0x00000004	/* Bulk list filled */
167 #define	HCR_STATUS_OCR		0x00000008	/* Ownership change */
168 #define	HCR_STATUS_SOC		0x00030000	/* Error frame count */
169 
170 /* hcr_intr_status bits and hcr_intr_mask bits */
171 #define	HCR_INTR_SO		0x00000001	/* Schedule overrun */
172 #define	HCR_INTR_WDH		0x00000002	/* Writeback done head */
173 #define	HCR_INTR_SOF		0x00000004	/* Start of frame */
174 #define	HCR_INTR_RD		0x00000008	/* Resume detected */
175 #define	HCR_INTR_UE		0x00000010	/* Unrecoverable error */
176 #define	HCR_INTR_FNO		0x00000020	/* Frame no. overflow */
177 #define	HCR_INTR_RHSC		0x00000040	/* Root hub status change */
178 #define	HCR_INTR_OC		0x40000000	/* Change in ownership */
179 #define	HCR_INTR_MIE		0x80000000	/* Master interrupt enable */
180 
181 /* hcr_frame_interval bits */
182 #define	HCR_FRME_INT_FI		0x00003FFF	/* Frame interval */
183 #define	HCR_FRME_INT_FSMPS	0x7FFF0000	/* Biggest packet */
184 #define	HCR_FRME_FSMPS_SHFT	16		/* FSMPS */
185 #define	HCR_FRME_INT_FIT	0x80000000	/* Frame interval toggle */
186 #define	MAX_OVERHEAD		210		/* Max. bit overhead */
187 
188 /* hcr_frame_remaining bits */
189 #define	HCR_FRME_REM_FR		0x00003FFF	/* Frame remaining */
190 #define	HCR_FRME_REM_FRT	0x80000000	/* Frame remaining toggle */
191 
192 /* hcr_transfer_ls */
193 #define	HCR_TRANS_LST		0x000007FF	/* Low Speed threshold */
194 
195 /* hcr_rh_descriptorA bits */
196 #define	HCR_RHA_NDP		0x000000FF	/* No. of ports */
197 #define	HCR_RHA_PSM		0x00000100	/* Power switch mode */
198 #define	HCR_RHA_NPS		0x00000200	/* No power switching */
199 #define	HCR_RHA_DT		0x00000400	/* Device type */
200 #define	HCR_RHA_OCPM		0x00000800	/* Over-current protection */
201 #define	HCR_RHA_NOCP		0x00001000	/* No over-current protection */
202 #define	HCR_RHA_PTPGT		0xFF000000	/* Power on to power good */
203 #define	HCR_RHA_PTPGT_SHIFT	24		/* Shift bits for ptpgt */
204 
205 /* hcr_rh_descriptorB bits */
206 #define	HCR_RHB_DR		0x0000FFFF	/* Device removable */
207 #define	HCR_RHB_PPCM		0xFFFF0000	/* PortPowerControlMask */
208 
209 /* hcr_rh_status bits */
210 #define	HCR_RH_STATUS_LPS	0x00000001	/* Local power status */
211 #define	HCR_RH_STATUS_OCI	0x00000002	/* Over current indicator */
212 #define	HCR_RH_STATUS_DRWE	0x00008000	/* Device remote wakeup */
213 #define	HCR_RH_STATUS_LPSC	0x00010000	/* Local power status change */
214 #define	HCR_RH_STATUS_OCIC	0x00020000	/* Over current indicator */
215 #define	HCR_RH_STATUS_CRWE	0x80000000	/* Clear remote wakeup enable */
216 #define	HCR_RH_STATUS_MASK	0x10038003	/* Status mask */
217 
218 /* hcr_rh_portstatus bits */
219 #define	HCR_PORT_CCS		0x00000001	/* Current connect status */
220 #define	HCR_PORT_PES		0x00000002	/* Port enable */
221 #define	HCR_PORT_PSS		0x00000004	/* Port suspend status */
222 #define	HCR_PORT_POCI		0x00000008	/* Port over crrnt indicator */
223 #define	HCR_PORT_PRS		0x00000010	/* Port reset status */
224 #define	HCR_PORT_PPS		0x00000100	/* Port power status */
225 #define	HCR_PORT_CPP		0x00000200	/* Clear port power */
226 #define	HCR_PORT_LSDA		0x00000200	/* Low speed device */
227 #define	HCR_PORT_CSC		0x00010000	/* Connect status change */
228 #define	HCR_PORT_PESC		0x00020000	/* Port enable status change */
229 #define	HCR_PORT_PSSC		0x00040000	/* Port suspend status change */
230 #define	HCR_PORT_OCIC		0x00080000	/* Port over current change */
231 #define	HCR_PORT_PRSC		0x00100000	/* Port reset status chnge */
232 #define	HCR_PORT_MASK		0x001F031F	/* Reserved written as 0 */
233 #define	HCR_PORT_CHNG_MASK	0x001F0000	/* Mask for change bits */
234 
235 #define	DONE_QUEUE_INTR_COUNTER	0x7		/* Done queue intr counter */
236 
237 /*
238  * Host Controller Communications Area
239  *
240  * The Host Controller Communications Area (HCCA) is a 256-byte structre
241  * of system memory that is established by the Host Controller Driver (HCD)
242  * and this structre is used for communication between HCD and HC. The HCD
243  * maintains a pointer to this structure in the Host Controller (HC). This
244  * structure must be aligned to a 256-byte boundary.
245  */
246 
247 #define	NUM_INTR_ED_LISTS	32	/* Number of interrupt lists */
248 #define	NUM_STATIC_NODES	31	/* Number of static endpoints */
249 
250 typedef volatile struct ohci_hcca {
251 	uint32_t	HccaIntTble[NUM_INTR_ED_LISTS]; /* 32 intr lists */
252 							/* Ptrs to ohci_ed */
253 	uint16_t	HccaFrameNo;		/* Current frame number */
254 	uint16_t 	HccaPad;		/* 0 when HC updates FrameNo */
255 	uint32_t	HccaDoneHead;		/* Head ptr */
256 	uint8_t		HccaReserved[120];	/* Reserved area */
257 } ohci_hcca_t;
258 
259 #define	HCCA_DONE_HEAD_MASK	0xFFFFFFF0	/* Hcca done head mask */
260 #define	HCCA_DONE_HEAD_LSB	0x00000001	/* Lsb of the Done Head */
261 
262 
263 /*
264  * Host Controller Endpoint Descriptor
265  *
266  * An Endpoint Descriptor (ED) is a memory structure that describes the
267  * information necessary for the Host Controller (HC) to communicate with
268  * a device endpoint.  An ED includes a Transfer Descriptor (TD) pointer.
269  * This structure must be aligned to a 16 byte boundary.
270  */
271 typedef volatile struct ohci_ed {
272 	uint32_t	hced_ctrl;	/* See below */
273 	uint32_t	hced_tailp;	/* (ohci_td *) End of trans. list */
274 	uint32_t	hced_headp;	/* (ohci_td *) Next trans. */
275 	uint32_t	hced_next;	/* (ohci_ed *) Next endpoint */
276 	uint32_t	hced_prev;	/* (ohci_ed *)Virt addr. of prev ept */
277 	uint32_t	hced_node;	/* The node that its attached */
278 	uint32_t	hced_reclaim_next; /* (ohci_ed *) Reclaim list */
279 	uint32_t	hced_reclaim_frame; /* Reclaim usb frame number */
280 	uint32_t	hced_state;	/* Endpoint state */
281 	uint8_t		hce_pad[12];	/* Required padding */
282 } ohci_ed_t;
283 
284 /*
285  * hc_endpoint_descriptor control bits
286  */
287 #define	HC_EPT_FUNC	0x0000007F		/* Address of function */
288 #define	HC_EPT_EP	0x00000780		/* Address of endpoint */
289 #define	HC_EPT_DataFlow 0x00001800		/* Direction of data flow */
290 #define	HC_EPT_DF_IN    0x00001000		/* Data flow in */
291 #define	HC_EPT_DF_OUT	0x00000800		/* Data flow out */
292 #define	HC_EPT_Speed   	0x00002000		/* Speed of the endpoint */
293 #define	HC_EPT_sKip	0x00004000		/* Skip bit */
294 #define	HC_EPT_Format   0x00008000		/* Type of transfer */
295 #define	HC_EPT_MPS	0x0EFF0000		/* Max packet size */
296 #define	HC_EPT_8_MPS	0x00080000		/* 8 byte max packet size */
297 #define	HC_EPT_64_MPS	0x00400000		/* 64 byte max packet size */
298 #define	HC_EPT_Halt	0x00000001		/* Halted */
299 #define	HC_EPT_Carry	0x00000002		/* Toggle carry */
300 
301 #define	HC_EPT_EP_SHFT	7			/* Bits to shift addr */
302 #define	HC_EPT_MAXPKTSZ	16			/* Bits to shift maxpktsize */
303 
304 #define	HC_EPT_TD_TAIL	0xFFFFFFF0		/* TD tail mask */
305 #define	HC_EPT_TD_HEAD	0xFFFFFFF0		/* TD head mask */
306 #define	HC_EPT_NEXT	0xFFFFFFF0		/* Next endpoint mask */
307 
308 /*
309  * hced_state
310  *
311  * ED states
312  */
313 #define	HC_EPT_FREE	1			/* Free ED */
314 #define	HC_EPT_STATIC	2			/* Static ED */
315 #define	HC_EPT_ACTIVE	3			/* Active ED */
316 
317 
318 /*
319  * Host Controller Transfer Descriptor
320  *
321  * A Transfer Descriptor (TD) is a memory structure that describes the
322  * information necessary for the Host Controller (HC) to transfer a block
323  * of data to or from a device endpoint. These TD's will be attached to
324  * a Endpoint Descriptor (ED). This structure includes the fields for both
325  * General and Isochronous Transfer Descriptors. The General TDs must be
326  * aligned to 16 byte, where as Isochronous TDs must be aligned to 32 byte.
327  */
328 typedef	volatile struct ohci_td {
329 	uint32_t	hctd_ctrl;		/* See below */
330 	uint32_t	hctd_cbp;		/* Next buffer addr */
331 	uint32_t	hctd_next_td;		/* Next TD */
332 	uint32_t	hctd_buf_end;		/* End of buffer */
333 	uint32_t	hctd_offsets[4];	/* Offsets into buf */
334 						/* Used only for isoch */
335 	uint32_t	hctd_trans_wrapper;	/* Transfer wrapper */
336 	uint32_t	hctd_state;		/* TD state */
337 	uint32_t	hctd_tw_next_td;	/* Next TD on TW */
338 	uint32_t	hctd_ctrl_phase;	/* Control Xfer Phase info */
339 	uint8_t		hctd_pad[16];		/* Required padding */
340 } ohci_td_t;
341 
342 /*
343  * Common hc_td control bits both for the General and Isochronous Transfer
344  * Descriptors.
345  */
346 #define	HC_TD_DI	0x00E00000		/* Delay interrupt */
347 #define	HC_TD_0I	0x00000000		/* 0 frame for interrupt */
348 #define	HC_TD_1I	0x00200000		/* 1 frame for interrupt */
349 #define	HC_TD_2I	0x00400000		/* 2 frame for interrupt */
350 #define	HC_TD_3I	0x00600000		/* 3 frame for interrupt */
351 #define	HC_TD_4I	0x00800000		/* 4 frame's for interrupt */
352 #define	HC_TD_5I	0x00A00000		/* 5 frame for interrupt */
353 #define	HC_TD_6I	0x00C00000		/* 6 frame for interrupt */
354 #define	HC_TD_7I	0x00E00000		/* 7 frame for interrupt */
355 #define	HC_TD_CC	0xF0000000		/* Condition code */
356 
357 #define	HC_TD_R		0x00040000		/* Buffer rounding */
358 #define	HC_TD_PID	0x00180000		/* Pid for the token */
359 #define	HC_TD_SETUP	0x00000000		/* Setup direction */
360 #define	HC_TD_IN	0x00100000		/* In direction */
361 #define	HC_TD_OUT	0x00080000		/* Out direction */
362 #define	HC_TD_DT	0x03000000		/* Data Toggle */
363 #define	HC_TD_MS_DT	0x02000000		/* Master data toggle */
364 #define	HC_TD_DT_0	0x00000000		/* Toggle from TD 0 */
365 #define	HC_TD_DT_1	0x01000000		/* Toggle from TD 1 */
366 #define	HC_TD_EC	0x0C000000		/* Error Count */
367 
368 /*
369  * hc_td control bits specific to Isochronous Transfer Descriptors.
370  */
371 #define	HC_ITD_SF		0x0000FFFF	/* Starting Frame number */
372 #define	HC_ITD_FC		0x07000000	/* Frame count */
373 
374 #define	HC_ITD_FC_SHIFT		24		/* Frame count shift */
375 #define	HC_ITD_PAGE_MASK	0xFFFFF000
376 #define	HC_ITD_ODD_OFFSET	0xFFFF0000	/* Odd offset */
377 #define	HC_ITD_EVEN_OFFSET	0x0000FFFF	/* Even offset */
378 #define	HC_ITD_OFFSET_SHIFT	16
379 #define	HC_ITD_OFFSET_CC	0x0000F000	/* CC of offset or PSW N */
380 #define	HC_ITD_OFFSET_ADDR	0x00000FFF	/* Offset N */
381 #define	HC_ITD_4KBOUNDARY_CROSS	0x00001000	/* Set bit 12 for 4k crossing */
382 
383 /*
384  * Condition codes both to General and Isochronous Transfer Descriptors.
385  * Even these condition codes are valid for  offsets of the isochronous
386  * transfer descriptos.
387  */
388 #define	HC_TD_CC_NO_E	0x00000000		/* No error */
389 #define	HC_TD_CC_CRC	0x10000000		/* CRC error */
390 #define	HC_TD_CC_BS	0x20000000		/* Bit stuffing */
391 #define	HC_TD_CC_DTM	0x30000000		/* Data Toggle Mismatch */
392 #define	HC_TD_CC_STALL	0x40000000		/* Stall */
393 #define	HC_TD_CC_DNR	0x50000000		/* Device not responding */
394 #define	HC_TD_CC_PCF	0x60000000		/* PID check failure */
395 #define	HC_TD_CC_UPID	0x70000000		/* Unexpected PID */
396 #define	HC_TD_CC_DO	0x80000000		/* Data overrrun */
397 #define	HC_TD_CC_DU	0x90000000		/* Data underrun */
398 #define	HC_TD_CC_BO	0xC0000000		/* Buffer overrun */
399 #define	HC_TD_CC_BU	0xD0000000		/* Buffer underrun */
400 #define	HC_TD_CC_NA	0xF0000000		/* Not accessed */
401 
402 #define	HC_TD_NEXT	0xFFFFFFF0		/* Next TD */
403 
404 /*
405  * Condition codes specific to Isochronous Transfer Descriptors.
406  */
407 #define	HC_ITD_CC_SHIFT	16			/* ITD CC shift */
408 
409 /*
410  * hctd_state
411  *
412  * TD States
413  */
414 #define	HC_TD_FREE	1			/* Free TD */
415 #define	HC_TD_DUMMY	2			/* Dummy TD */
416 #define	HC_TD_ACTIVE	3			/* Active TD */
417 #define	HC_TD_TIMEOUT	4			/* Timeouted TD */
418 #define	HC_TD_RECLAIM	5			/* Reclaimed TD */
419 
420 /*
421  * hctd_ctrl_phase
422  *
423  * Control Transfer Phase information
424  */
425 #define	OHCI_CTRL_SETUP_PHASE		1	/* Setup phase */
426 #define	OHCI_CTRL_DATA_PHASE		2	/* Data phase */
427 #define	OHCI_CTRL_STATUS_PHASE		3	/* Status phase */
428 
429 
430 #ifdef __cplusplus
431 }
432 #endif
433 
434 #endif	/* _SYS_USB_OHCI_H */
435