1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_USB_OHCI_H
27 #define	_SYS_USB_OHCI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * Open Host Controller Driver (OHCI)
37  *
38  * The USB Open Host Controller driver is a software driver which interfaces
39  * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller.
40  * The interface to USB Open Host Controller is defined by the OpenHCI  Host
41  * Controller Interface.
42  *
43  * This header file describes the registers and data structures shared by the
44  * USB Open Host Controller and the USB Open Host Controller Driver.
45  */
46 
47 #include <sys/types.h>
48 #include <sys/pci.h>
49 #include <sys/kstat.h>
50 #include <sys/sunddi.h>
51 #include <sys/sunndi.h>
52 #include <sys/ndi_impldefs.h>
53 
54 #include <sys/usb/usba.h>
55 
56 #include <sys/usb/usba/hcdi.h>
57 
58 #include <sys/usb/hubd/hub.h>
59 #include <sys/usb/usba/hubdi.h>
60 #include <sys/usb/hubd/hubdvar.h>
61 
62 #include <sys/id32.h>
63 
64 #define	OHCI_MAX_RH_PORTS		15	/* Maximum root hub ports */
65 
66 /*
67  * Each OHCI buffer can hold upto 8k bytes of data. Hence there is a
68  * restriction of 4k alignment while allocating a dma buffer.
69  */
70 #define	OHCI_4K_ALIGN			0x1000
71 
72 /*
73  * USB Host controller DMA scatter gather list defines for
74  * Sparc and non-sparc architectures.
75  */
76 #if defined(__sparc)
77 #define	OHCI_DMA_ATTR_MAX_XFER		0xffffffffull
78 #define	OHCI_DMA_ATTR_COUNT_MAX		0xffffffffull
79 #define	OHCI_DMA_ATTR_GRANULAR		512
80 #define	OHCI_DMA_ATTR_ALIGNMENT		OHCI_4K_ALIGN
81 #else
82 #define	OHCI_DMA_ATTR_MAX_XFER		0x00ffffffull
83 #define	OHCI_DMA_ATTR_COUNT_MAX		0x00ffffffull
84 #define	OHCI_DMA_ATTR_GRANULAR		1
85 #define	OHCI_DMA_ATTR_ALIGNMENT		OHCI_4K_ALIGN
86 #endif
87 
88 #define	OHCI_DMA_ATTR_TW_SGLLEN		0x7fffffff	/* not limited */
89 #define	OHCI_DMA_ATTR_TD_SGLLEN		2	/* maximum 8K per TD */
90 
91 /*
92  * According to the OHCI spec ED and TD need to be 16 byte aligned.
93  * However, iTD needs to be 32 byte aligned.  Since we do not
94  * distinguish between iTD and TD, make them both 32 byte aligned.
95  *
96  * ED   =  16 byte aligned
97  * TD   =  32 byte aligned
98  * HCCA = 256 byte aligned
99  */
100 #define	OHCI_DMA_ATTR_ED_ALIGNMENT	0x010
101 #define	OHCI_DMA_ATTR_TD_ALIGNMENT	0x020
102 #define	OHCI_DMA_ATTR_HCCA_ALIGNMENT	0x100
103 
104 /*
105  * Vendor id and Device id for ULI1575 southbridge.
106  */
107 #define	PCI_ULI1575_VENID	0x10B9
108 #define	PCI_ULI1575_DEVID	0x5237
109 
110 /*
111  * Need a workaround for ULI1575 chipset. Following OHCI
112  * Operational Memory Registers are not cleared to their
113  * default value on reset. Explicitly set the registers
114  * to default value after reset.
115  */
116 #define	HCR_CONTROL_DEFAULT		0x0
117 #define	HCR_INT_ENABLE_DEFAULT		0x0
118 #define	HCR_HCCA_DEFAULT		0x0
119 #define	HCR_CONTROL_HEAD_ED_DEFAULT	0x0
120 #define	HCR_BULK_HEAD_ED_DEFAULT	0x0
121 #define	HCR_FRAME_INTERVAL_DEFAULT	0x2edf
122 #define	HCR_PERIODIC_START_DEFAULT	0x0
123 
124 /*
125  * OpenHCI Operational Registers
126  *
127  * The Host Controller (HC) contains a set of on-chip operational registers
128  * which are mapped into a noncacheable portion of the system addressable
129  * space and these registers are also used by the Host Controller Driver
130  * (HCD).
131  */
132 typedef volatile struct ohci_regs {
133 	/* Control and status registers */
134 	uint32_t 	hcr_revision;		/* Specification version */
135 	uint32_t	hcr_control;		/* Control information */
136 	uint32_t	hcr_cmd_status;		/* Controller status */
137 	uint32_t	hcr_intr_status;	/* Interrupt status register */
138 	uint32_t 	hcr_intr_enable;	/* Interrupt enable */
139 	uint32_t	hcr_intr_disable;	/* Interrupt disable */
140 
141 	/* Memory pointer registers */
142 	uint32_t	hcr_HCCA;		/* Pointer to HCCA */
143 	uint32_t	hcr_periodic_curr;	/* Curr. isoch or int endpt */
144 	uint32_t	hcr_ctrl_head;		/* Head of contrl list */
145 	uint32_t	hcr_ctrl_curr;		/* Curr. control endpt */
146 	uint32_t	hcr_bulk_head;		/* Head of the bulk list */
147 	uint32_t	hcr_bulk_curr;		/* Curr. bulk endpt */
148 	uint32_t	hcr_done_head;		/* Head of the done list */
149 
150 	/* Frame counter registers */
151 	uint32_t	hcr_frame_interval;	/* Frame interval value */
152 	uint32_t 	hcr_frame_remaining;    /* Time remaining in frame */
153 	uint32_t	hcr_frame_number;	/* Frame number */
154 	uint32_t	hcr_periodic_strt;	/* Time to start per. list */
155 	uint32_t	hcr_transfer_ls;	/* Low speed threshold */
156 
157 	/* Root hub registers */
158 	uint32_t	hcr_rh_descriptorA;	/* Root hub register A */
159 	uint32_t	hcr_rh_descriptorB;	/* Root hub register B */
160 	uint32_t	hcr_rh_status;		/* Root hub status */
161 	uint32_t 	hcr_rh_portstatus[OHCI_MAX_RH_PORTS]; /* RH port sts */
162 } ohci_regs_t;
163 
164 /* hcr_revision bits */
165 #define	HCR_REVISION_1_0	0x00000010	/* Revision 1.0 */
166 #define	HCR_REVISION_MASK	0x000000FF	/* Revision mask */
167 
168 /* hcr_control bits */
169 #define	HCR_CONTROL_CBSR	0x00000003	/* Control/bulk ratio */
170 #define	HCR_CONTROL_PLE		0x00000004	/* Periodic list enable */
171 #define	HCR_CONTROL_IE		0x00000008	/* Isochronous enable */
172 #define	HCR_CONTROL_CLE		0x00000010	/* Control list enable */
173 #define	HCR_CONTROL_BLE		0x00000020	/* Bulk list enable */
174 #define	HCR_CONTROL_HCFS	0x000000C0	/* Controller state */
175 #define	HCR_CONTROL_IR		0x00000100	/* Interrupt routing */
176 #define	HCR_CONTROL_RWC		0x00000200	/* Remote wakeup connected */
177 #define	HCR_CONTROL_RWE		0x00000400	/* Remote wakeup enabled */
178 
179 /* Values for the Host Controller Functional State bits (HCR_CONTROL_HCFS) */
180 #define	HCR_CONTROL_RESET	0x00000000	/* USB Reset */
181 #define	HCR_CONTROL_RESUME	0x00000040	/* USB Resume */
182 #define	HCR_CONTROL_OPERAT	0x00000080	/* USB Operational */
183 #define	HCR_CONTROL_SUSPD	0x000000C0	/* USB Suspend */
184 
185 /* hcr_cmd_status bits */
186 #define	HCR_STATUS_RESET	0x00000001	/* Host controller reset */
187 #define	HCR_STATUS_CLF		0x00000002	/* Control list filled */
188 #define	HCR_STATUS_BLF		0x00000004	/* Bulk list filled */
189 #define	HCR_STATUS_OCR		0x00000008	/* Ownership change */
190 #define	HCR_STATUS_SOC		0x00030000	/* Error frame count */
191 
192 /* hcr_intr_status bits and hcr_intr_mask bits */
193 #define	HCR_INTR_SO		0x00000001	/* Schedule overrun */
194 #define	HCR_INTR_WDH		0x00000002	/* Writeback done head */
195 #define	HCR_INTR_SOF		0x00000004	/* Start of frame */
196 #define	HCR_INTR_RD		0x00000008	/* Resume detected */
197 #define	HCR_INTR_UE		0x00000010	/* Unrecoverable error */
198 #define	HCR_INTR_FNO		0x00000020	/* Frame no. overflow */
199 #define	HCR_INTR_RHSC		0x00000040	/* Root hub status change */
200 #define	HCR_INTR_OC		0x40000000	/* Change in ownership */
201 #define	HCR_INTR_MIE		0x80000000	/* Master interrupt enable */
202 
203 /* hcr_frame_interval bits */
204 #define	HCR_FRME_INT_FI		0x00003FFF	/* Frame interval */
205 #define	HCR_FRME_INT_FSMPS	0x7FFF0000	/* Biggest packet */
206 #define	HCR_FRME_FSMPS_SHFT	16		/* FSMPS */
207 #define	HCR_FRME_INT_FIT	0x80000000	/* Frame interval toggle */
208 #define	MAX_OVERHEAD		210		/* Max. bit overhead */
209 
210 /* hcr_frame_remaining bits */
211 #define	HCR_FRME_REM_FR		0x00003FFF	/* Frame remaining */
212 #define	HCR_FRME_REM_FRT	0x80000000	/* Frame remaining toggle */
213 
214 /* hcr_transfer_ls */
215 #define	HCR_TRANS_LST		0x000007FF	/* Low Speed threshold */
216 
217 /* hcr_rh_descriptorA bits */
218 #define	HCR_RHA_NDP		0x000000FF	/* No. of ports */
219 #define	HCR_RHA_PSM		0x00000100	/* Power switch mode */
220 #define	HCR_RHA_NPS		0x00000200	/* No power switching */
221 #define	HCR_RHA_DT		0x00000400	/* Device type */
222 #define	HCR_RHA_OCPM		0x00000800	/* Over-current protection */
223 #define	HCR_RHA_NOCP		0x00001000	/* No over-current protection */
224 #define	HCR_RHA_PTPGT		0xFF000000	/* Power on to power good */
225 #define	HCR_RHA_PTPGT_SHIFT	24		/* Shift bits for ptpgt */
226 
227 /* hcr_rh_descriptorB bits */
228 #define	HCR_RHB_DR		0x0000FFFF	/* Device removable */
229 #define	HCR_RHB_PPCM		0xFFFF0000	/* PortPowerControlMask */
230 
231 /* hcr_rh_status bits */
232 #define	HCR_RH_STATUS_LPS	0x00000001	/* Local power status */
233 #define	HCR_RH_STATUS_OCI	0x00000002	/* Over current indicator */
234 #define	HCR_RH_STATUS_DRWE	0x00008000	/* Device remote wakeup */
235 #define	HCR_RH_STATUS_LPSC	0x00010000	/* Local power status change */
236 #define	HCR_RH_STATUS_OCIC	0x00020000	/* Over current indicator */
237 #define	HCR_RH_STATUS_CRWE	0x80000000	/* Clear remote wakeup enable */
238 #define	HCR_RH_STATUS_MASK	0x10038003	/* Status mask */
239 
240 /* hcr_rh_portstatus bits */
241 #define	HCR_PORT_CCS		0x00000001	/* Current connect status */
242 #define	HCR_PORT_PES		0x00000002	/* Port enable */
243 #define	HCR_PORT_PSS		0x00000004	/* Port suspend status */
244 #define	HCR_PORT_POCI		0x00000008	/* Port over crrnt indicator */
245 #define	HCR_PORT_PRS		0x00000010	/* Port reset status */
246 #define	HCR_PORT_PPS		0x00000100	/* Port power status */
247 #define	HCR_PORT_CPP		0x00000200	/* Clear port power */
248 #define	HCR_PORT_LSDA		0x00000200	/* Low speed device */
249 #define	HCR_PORT_CSC		0x00010000	/* Connect status change */
250 #define	HCR_PORT_PESC		0x00020000	/* Port enable status change */
251 #define	HCR_PORT_PSSC		0x00040000	/* Port suspend status change */
252 #define	HCR_PORT_OCIC		0x00080000	/* Port over current change */
253 #define	HCR_PORT_PRSC		0x00100000	/* Port reset status chnge */
254 #define	HCR_PORT_MASK		0x001F031F	/* Reserved written as 0 */
255 #define	HCR_PORT_CHNG_MASK	0x001F0000	/* Mask for change bits */
256 
257 #define	DONE_QUEUE_INTR_COUNTER	0x7		/* Done queue intr counter */
258 
259 /*
260  * Host Controller Communications Area
261  *
262  * The Host Controller Communications Area (HCCA) is a 256-byte structre
263  * of system memory that is established by the Host Controller Driver (HCD)
264  * and this structre is used for communication between HCD and HC. The HCD
265  * maintains a pointer to this structure in the Host Controller (HC). This
266  * structure must be aligned to a 256-byte boundary.
267  */
268 
269 #define	NUM_INTR_ED_LISTS	32	/* Number of interrupt lists */
270 #define	NUM_STATIC_NODES	31	/* Number of static endpoints */
271 
272 typedef volatile struct ohci_hcca {
273 	uint32_t	HccaIntTble[NUM_INTR_ED_LISTS]; /* 32 intr lists */
274 							/* Ptrs to ohci_ed */
275 	uint16_t	HccaFrameNo;		/* Current frame number */
276 	uint16_t 	HccaPad;		/* 0 when HC updates FrameNo */
277 	uint32_t	HccaDoneHead;		/* Head ptr */
278 	uint8_t		HccaReserved[120];	/* Reserved area */
279 } ohci_hcca_t;
280 
281 #define	HCCA_DONE_HEAD_MASK	0xFFFFFFF0	/* Hcca done head mask */
282 #define	HCCA_DONE_HEAD_LSB	0x00000001	/* Lsb of the Done Head */
283 
284 
285 /*
286  * Host Controller Endpoint Descriptor
287  *
288  * An Endpoint Descriptor (ED) is a memory structure that describes the
289  * information necessary for the Host Controller (HC) to communicate with
290  * a device endpoint.  An ED includes a Transfer Descriptor (TD) pointer.
291  * This structure must be aligned to a 16 byte boundary.
292  */
293 typedef volatile struct ohci_ed {
294 	uint32_t	hced_ctrl;	/* See below */
295 	uint32_t	hced_tailp;	/* (ohci_td *) End of trans. list */
296 	uint32_t	hced_headp;	/* (ohci_td *) Next trans. */
297 	uint32_t	hced_next;	/* (ohci_ed *) Next endpoint */
298 	uint32_t	hced_prev;	/* (ohci_ed *)Virt addr. of prev ept */
299 	uint32_t	hced_node;	/* The node that its attached */
300 	uint32_t	hced_reclaim_next; /* (ohci_ed *) Reclaim list */
301 	uint32_t	hced_reclaim_frame; /* Reclaim usb frame number */
302 	uint32_t	hced_state;	/* Endpoint state */
303 	uint8_t		hce_pad[12];	/* Required padding */
304 } ohci_ed_t;
305 
306 /*
307  * hc_endpoint_descriptor control bits
308  */
309 #define	HC_EPT_FUNC	0x0000007F		/* Address of function */
310 #define	HC_EPT_EP	0x00000780		/* Address of endpoint */
311 #define	HC_EPT_DataFlow 0x00001800		/* Direction of data flow */
312 #define	HC_EPT_DF_IN    0x00001000		/* Data flow in */
313 #define	HC_EPT_DF_OUT	0x00000800		/* Data flow out */
314 #define	HC_EPT_Speed   	0x00002000		/* Speed of the endpoint */
315 #define	HC_EPT_sKip	0x00004000		/* Skip bit */
316 #define	HC_EPT_Format   0x00008000		/* Type of transfer */
317 #define	HC_EPT_MPS	0x0EFF0000		/* Max packet size */
318 #define	HC_EPT_8_MPS	0x00080000		/* 8 byte max packet size */
319 #define	HC_EPT_64_MPS	0x00400000		/* 64 byte max packet size */
320 #define	HC_EPT_Halt	0x00000001		/* Halted */
321 #define	HC_EPT_Carry	0x00000002		/* Toggle carry */
322 
323 #define	HC_EPT_EP_SHFT	7			/* Bits to shift addr */
324 #define	HC_EPT_MAXPKTSZ	16			/* Bits to shift maxpktsize */
325 
326 #define	HC_EPT_TD_TAIL	0xFFFFFFF0		/* TD tail mask */
327 #define	HC_EPT_TD_HEAD	0xFFFFFFF0		/* TD head mask */
328 #define	HC_EPT_NEXT	0xFFFFFFF0		/* Next endpoint mask */
329 
330 /*
331  * hced_state
332  *
333  * ED states
334  */
335 #define	HC_EPT_FREE	1			/* Free ED */
336 #define	HC_EPT_STATIC	2			/* Static ED */
337 #define	HC_EPT_ACTIVE	3			/* Active ED */
338 
339 
340 /*
341  * Host Controller Transfer Descriptor
342  *
343  * A Transfer Descriptor (TD) is a memory structure that describes the
344  * information necessary for the Host Controller (HC) to transfer a block
345  * of data to or from a device endpoint. These TD's will be attached to
346  * a Endpoint Descriptor (ED). This structure includes the fields for both
347  * General and Isochronous Transfer Descriptors. The General TDs must be
348  * aligned to 16 byte, where as Isochronous TDs must be aligned to 32 byte.
349  */
350 typedef	volatile struct ohci_td {
351 	uint32_t	hctd_ctrl;		/* See below */
352 	uint32_t	hctd_cbp;		/* Next buffer addr */
353 	uint32_t	hctd_next_td;		/* Next TD */
354 	uint32_t	hctd_buf_end;		/* End of buffer */
355 	uint32_t	hctd_offsets[4];	/* Offsets into buf */
356 						/* Used only for isoch */
357 	uint32_t	hctd_trans_wrapper;	/* Transfer wrapper */
358 	uint32_t	hctd_state;		/* TD state */
359 	uint32_t	hctd_tw_next_td;	/* Next TD on TW */
360 	uint32_t	hctd_ctrl_phase;	/* Control Xfer Phase info */
361 	uint32_t	hctd_xfer_offs;		/* Starting buffer offset */
362 	uint32_t	hctd_xfer_len;		/* Transfer length */
363 	uint8_t		hctd_pad[8];		/* Required padding */
364 } ohci_td_t;
365 
366 /*
367  * Common hc_td control bits both for the General and Isochronous Transfer
368  * Descriptors.
369  */
370 #define	HC_TD_DI	0x00E00000		/* Delay interrupt */
371 #define	HC_TD_0I	0x00000000		/* 0 frame for interrupt */
372 #define	HC_TD_1I	0x00200000		/* 1 frame for interrupt */
373 #define	HC_TD_2I	0x00400000		/* 2 frame for interrupt */
374 #define	HC_TD_3I	0x00600000		/* 3 frame for interrupt */
375 #define	HC_TD_4I	0x00800000		/* 4 frame's for interrupt */
376 #define	HC_TD_5I	0x00A00000		/* 5 frame for interrupt */
377 #define	HC_TD_6I	0x00C00000		/* 6 frame for interrupt */
378 #define	HC_TD_7I	0x00E00000		/* 7 frame for interrupt */
379 #define	HC_TD_CC	0xF0000000		/* Condition code */
380 
381 #define	HC_TD_R		0x00040000		/* Buffer rounding */
382 #define	HC_TD_PID	0x00180000		/* Pid for the token */
383 #define	HC_TD_SETUP	0x00000000		/* Setup direction */
384 #define	HC_TD_IN	0x00100000		/* In direction */
385 #define	HC_TD_OUT	0x00080000		/* Out direction */
386 #define	HC_TD_DT	0x03000000		/* Data Toggle */
387 #define	HC_TD_MS_DT	0x02000000		/* Master data toggle */
388 #define	HC_TD_DT_0	0x00000000		/* Toggle from TD 0 */
389 #define	HC_TD_DT_1	0x01000000		/* Toggle from TD 1 */
390 #define	HC_TD_EC	0x0C000000		/* Error Count */
391 
392 /*
393  * hc_td control bits specific to Isochronous Transfer Descriptors.
394  */
395 #define	HC_ITD_SF		0x0000FFFF	/* Starting Frame number */
396 #define	HC_ITD_FC		0x07000000	/* Frame count */
397 
398 #define	HC_ITD_FC_SHIFT		24		/* Frame count shift */
399 #define	HC_ITD_PAGE_MASK	0xFFFFF000
400 #define	HC_ITD_ODD_OFFSET	0xFFFF0000	/* Odd offset */
401 #define	HC_ITD_EVEN_OFFSET	0x0000FFFF	/* Even offset */
402 #define	HC_ITD_OFFSET_SHIFT	16
403 #define	HC_ITD_OFFSET_CC	0x0000F000	/* CC of offset or PSW N */
404 #define	HC_ITD_OFFSET_ADDR	0x00000FFF	/* Offset N */
405 #define	HC_ITD_4KBOUNDARY_CROSS	0x00001000	/* Set bit 12 for 4k crossing */
406 
407 /*
408  * Condition codes both to General and Isochronous Transfer Descriptors.
409  * Even these condition codes are valid for  offsets of the isochronous
410  * transfer descriptos.
411  */
412 #define	HC_TD_CC_NO_E	0x00000000		/* No error */
413 #define	HC_TD_CC_CRC	0x10000000		/* CRC error */
414 #define	HC_TD_CC_BS	0x20000000		/* Bit stuffing */
415 #define	HC_TD_CC_DTM	0x30000000		/* Data Toggle Mismatch */
416 #define	HC_TD_CC_STALL	0x40000000		/* Stall */
417 #define	HC_TD_CC_DNR	0x50000000		/* Device not responding */
418 #define	HC_TD_CC_PCF	0x60000000		/* PID check failure */
419 #define	HC_TD_CC_UPID	0x70000000		/* Unexpected PID */
420 #define	HC_TD_CC_DO	0x80000000		/* Data overrrun */
421 #define	HC_TD_CC_DU	0x90000000		/* Data underrun */
422 #define	HC_TD_CC_BO	0xC0000000		/* Buffer overrun */
423 #define	HC_TD_CC_BU	0xD0000000		/* Buffer underrun */
424 #define	HC_TD_CC_NA	0xF0000000		/* Not accessed */
425 
426 #define	HC_TD_NEXT	0xFFFFFFF0		/* Next TD */
427 
428 /*
429  * Condition codes specific to Isochronous Transfer Descriptors.
430  */
431 #define	HC_ITD_CC_SHIFT	16			/* ITD CC shift */
432 
433 /*
434  * hctd_state
435  *
436  * TD States
437  */
438 #define	HC_TD_FREE	1			/* Free TD */
439 #define	HC_TD_DUMMY	2			/* Dummy TD */
440 #define	HC_TD_ACTIVE	3			/* Active TD */
441 #define	HC_TD_TIMEOUT	4			/* Timeouted TD */
442 #define	HC_TD_RECLAIM	5			/* Reclaimed TD */
443 
444 /*
445  * hctd_ctrl_phase
446  *
447  * Control Transfer Phase information
448  */
449 #define	OHCI_CTRL_SETUP_PHASE		1	/* Setup phase */
450 #define	OHCI_CTRL_DATA_PHASE		2	/* Data phase */
451 #define	OHCI_CTRL_STATUS_PHASE		3	/* Status phase */
452 
453 /*
454  * Structure for Isoc DMA buffer
455  *	One Isoc transfer includes multiple Isoc packets and need to be
456  *	transfered in multiple TDs.
457  *	One DMA buffer is allocated for one Isoc TD which may hold up
458  *	to eight Isoc packets.
459  */
460 typedef struct ohci_isoc_buf {
461 	caddr_t			buf_addr;	/* Starting buffer address */
462 	ddi_dma_cookie_t	cookie;		/* DMA cookie */
463 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
464 	ddi_acc_handle_t	mem_handle;	/* Memory handle */
465 	size_t			length;		/* Buffer length */
466 	uint_t			ncookies;	/* DMA cookie count */
467 	uint_t			index;		/* Index of the TD */
468 } ohci_isoc_buf_t;
469 
470 #ifdef __cplusplus
471 }
472 #endif
473 
474 #endif	/* _SYS_USB_OHCI_H */
475