1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_EHCID_H 28 #define _SYS_USB_EHCID_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Enchanced Host Controller Driver (EHCI) 38 * 39 * The EHCI driver is a software driver which interfaces to the Universal 40 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 41 * the Host Controller is defined by the EHCI Host Controller Interface. 42 * 43 * This header file describes the data structures and function prototypes 44 * required for the EHCI Driver to maintain state of Host Controller (HC), 45 * to perform different USB transfers and for the bandwidth allocations. 46 */ 47 48 #include <sys/usb/hcd/ehci/ehci.h> 49 #include <sys/usb/hcd/ehci/ehci_hub.h> 50 51 52 /* 53 * EHCI Bandwidth Maintainence Structure. 54 * 55 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci 56 * host controller. There are 32 bandwidth lists corresponding to 32 ms 57 * periodic frame lists. Each bandwidth list inturn will contain eight 58 * micro frame bandwidth lists. 59 */ 60 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */ 61 62 typedef struct ehci_frame_bandwidth { 63 uint_t ehci_allocated_frame_bandwidth; 64 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES]; 65 } ehci_frame_bandwidth_t; 66 67 68 /* 69 * EHCI Host Controller state structure 70 * 71 * The Host Controller Driver (HCD) maintains the state of Host Controller 72 * (HC). There is an ehci_state structure per instance of the EHCI 73 * host controller. 74 */ 75 typedef struct ehci_state { 76 dev_info_t *ehci_dip; /* Dip of HC */ 77 uint_t ehci_instance; 78 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */ 79 uint_t ehci_flags; /* Used for cleanup */ 80 uint16_t ehci_vendor_id; /* chip vendor */ 81 uint16_t ehci_device_id; /* chip device */ 82 uint8_t ehci_rev_id; /* chip revison */ 83 84 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */ 85 ehci_caps_t *ehci_capsp; /* Capability Regs */ 86 ehci_regs_t *ehci_regsp; /* Operational Regs */ 87 88 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */ 89 uint_t ehci_frame_interval; /* Frme inter reg */ 90 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */ 91 92 ddi_intr_handle_t *ehci_htable; /* intr handle */ 93 int ehci_intr_type; /* intr type used */ 94 int ehci_intr_cnt; /* # of intrs inuse */ 95 uint_t ehci_intr_pri; /* intr priority */ 96 int ehci_intr_cap; /* intr capabilities */ 97 boolean_t ehci_msi_enabled; /* default to true */ 98 kmutex_t ehci_int_mutex; /* Global EHCI mutex */ 99 100 /* Periodic Frame List area */ 101 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep; 102 /* Virtual Periodic Frame List ptr */ 103 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */ 104 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */ 105 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */ 106 107 /* 108 * There are two pools of memory. One pool contains the memory for 109 * the transfer descriptors and other pool contains the memory for 110 * the endpoint descriptors. The advantage of the pools is that it's 111 * easy to go back and forth between the iommu and the cpu addresses. 112 * 113 * The pools are protected by the ehci_int_mutex because the memory 114 * in the pools may be accessed by either the host controller or the 115 * host controller driver. 116 */ 117 118 /* Endpoint descriptor pool */ 119 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */ 120 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */ 121 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */ 122 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */ 123 uint_t ehci_dma_addr_bind_flag; /* DMA flag */ 124 125 /* General transfer descriptor pool */ 126 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */ 127 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */ 128 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */ 129 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */ 130 131 /* Isochronous transfer descriptor pool */ 132 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */ 133 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */ 134 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */ 135 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */ 136 137 /* Condition variable for advance on Asynchronous Schedule */ 138 kcondvar_t ehci_async_schedule_advance_cv; 139 140 /* Head of Asynchronous Schedule List */ 141 ehci_qh_t *ehci_head_of_async_sched_list; 142 143 /* 144 * List of QTD inserted either into Asynchronous or Periodic 145 * Schedule lists. 146 */ 147 ehci_qtd_t *ehci_active_qtd_list; 148 /* 149 * List of ITD active itd list. 150 */ 151 ehci_itd_t *ehci_active_itd_list; 152 153 /* 154 * Bandwidth fields 155 * 156 * The ehci_bandwidth array keeps track of allocated bandwidth for 157 * ehci host controller. There are 32 bandwidth lists corresponding 158 * to 32 ms periodic frame lists. Each bandwidth list in turn will 159 * contain eight micro frame bandwidth lists. 160 * 161 * ehci_min_frame_bandwidth field indicates least allocated milli 162 * second bandwidth list. 163 */ 164 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS]; 165 166 /* No. of open pipes, async qh, and periodic qh */ 167 uint_t ehci_open_pipe_count; 168 uint_t ehci_open_async_count; 169 uint_t ehci_open_periodic_count; 170 171 /* 172 * Endpoint Reclamation List 173 * 174 * The interrupt list processing cannot be stopped when a periodic 175 * endpoint is removed from the list. The endpoints are detached 176 * from the interrupt lattice tree and put on to the reclaimation 177 * list. On next SOF interrupt all those endpoints, which are on 178 * the reclaimation list will be deallocated. 179 */ 180 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */ 181 182 ehci_root_hub_t ehci_root_hub; /* Root hub info */ 183 184 /* Frame number overflow information */ 185 usb_frame_number_t ehci_fno; 186 187 /* For host controller error counter */ 188 uint_t ehci_hc_error; 189 190 /* 191 * ehci_missed_intr_sts is used to save the normal mode interrupt 192 * status information if an interrupt is pending for normal mode 193 * when polled code is entered. 194 */ 195 uint_t ehci_missed_intr_sts; 196 197 /* 198 * Saved copy of the ehci registers of the normal mode & change 199 * required ehci registers values for the polled mode operation. 200 * Before returning from the polled mode to normal mode replace 201 * the required current registers with this saved ehci registers 202 * copy. 203 */ 204 ehci_regs_t ehci_polled_save_regs; 205 206 /* 207 * Saved copy of the interrupt table used in normal ehci mode and 208 * replace this table by another interrupt table that used in the 209 * POLLED mode. 210 */ 211 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS]; 212 213 /* ehci polled mode enter counter */ 214 uint_t ehci_polled_enter_count; 215 216 /* 217 * counter for polled mode and used in suspend mode to see if 218 * there is a keyboard connected. 219 */ 220 uint_t ehci_polled_kbd_count; 221 222 /* counter for polled read and use it to clean the interrupt status */ 223 uint_t ehci_polled_read_count; 224 225 /* EHCI Host Controller Software State information */ 226 uint_t ehci_hc_soft_state; 227 228 /* Log handle for debug, console, log messages */ 229 usb_log_handle_t ehci_log_hdl; 230 231 /* Kstat structures */ 232 kstat_t *ehci_intrs_stats; 233 kstat_t *ehci_total_stats; 234 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS]; 235 } ehci_state_t; 236 237 typedef struct ehci_intrs_stats { 238 struct kstat_named ehci_sts_async_sched_status; 239 struct kstat_named ehci_sts_periodic_sched_status; 240 struct kstat_named ehci_sts_empty_async_schedule; 241 struct kstat_named ehci_sts_host_ctrl_halted; 242 struct kstat_named ehci_sts_async_advance_intr; 243 struct kstat_named ehci_sts_host_system_error_intr; 244 struct kstat_named ehci_sts_frm_list_rollover_intr; 245 struct kstat_named ehci_sts_rh_port_change_intr; 246 struct kstat_named ehci_sts_usb_error_intr; 247 struct kstat_named ehci_sts_usb_intr; 248 struct kstat_named ehci_sts_not_claimed; 249 struct kstat_named ehci_sts_total; 250 } ehci_intrs_stats_t; 251 252 /* 253 * ehci kstat defines 254 */ 255 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats) 256 #define EHCI_INTRS_STATS_DATA(ehci) \ 257 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data) 258 259 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats) 260 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats)) 261 #define EHCI_CTRL_STATS(ehci) \ 262 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL])) 263 #define EHCI_BULK_STATS(ehci) \ 264 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK])) 265 #define EHCI_INTR_STATS(ehci) \ 266 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR])) 267 #define EHCI_ISOC_STATS(ehci) \ 268 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH])) 269 270 /* warlock directives, stable data */ 271 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t)) 272 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri)) 273 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip)) 274 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp)) 275 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance)) 276 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id)) 277 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id)) 278 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id)) 279 280 /* this may not be stable data in the future */ 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr)) 282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle)) 283 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie)) 284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr)) 285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle)) 286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie)) 287 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr)) 288 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle)) 289 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie)) 290 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag)) 291 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl)) 292 293 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \ 294 usba_pipe_handle_data::p_mutex \ 295 usba_device::usb_mutex \ 296 usba_ph_impl::usba_ph_mutex)) 297 298 /* 299 * Host Contoller Software States 300 * 301 * EHCI_CTLR_INIT_STATE: 302 * The host controller soft state will be set to this during the 303 * ehci_attach. 304 * 305 * EHCI_CTLR_SUSPEND_STATE: 306 * The host controller soft state will be set to this during the 307 * ehci_cpr_suspend. 308 * 309 * EHCI_CTLR_OPERATIONAL_STATE: 310 * The host controller soft state will be set to this after moving 311 * host controller to operational state and host controller start 312 * generating SOF successfully. 313 * 314 * EHCI_CTLR_ERROR_STATE: 315 * The host controller soft state will be set to this during the 316 * no SOF or UE error conditions. 317 * 318 * Under this state or condition, only pipe stop polling, pipe reset 319 * and pipe close are allowed. But all other entry points like pipe 320 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 321 * isoch send/receive, start polling etc. will fail. 322 * 323 * State Diagram for the host controller software state 324 * 325 * 326 * ehci_attach->[INIT_STATE] 327 * | 328 * | -------->----[ERROR_STATE]--<-----------<--- 329 * | | Failure (UE/no SOF condition) | 330 * | ^ ^ 331 * V | Success | 332 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling 333 * ^ | 334 * | | 335 * | V 336 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend 337 */ 338 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */ 339 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 340 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 341 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 342 343 /* 344 * Periodic and non-periodic macros 345 */ 346 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 347 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 348 ((endpoint->bmAttributes &\ 349 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 350 351 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 352 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 353 ((endpoint->bmAttributes &\ 354 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 355 356 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 357 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 358 359 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 360 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR)) 361 362 363 /* 364 * EHCI QH and QTD Pool sizes. 365 */ 366 #define EHCI_QH_POOL_SIZE 100 367 #define EHCI_QTD_POOL_SIZE 200 368 #define EHCI_ITD_POOL_SIZE 200 369 370 /* 371 * ehci_dma_addr_bind_flag values 372 * 373 * This flag indicates if the various DMA addresses allocated by the EHCI 374 * have been bound to their respective handles. This is needed to recover 375 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle() 376 */ 377 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */ 378 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */ 379 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */ 380 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */ 381 382 /* 383 * Maximum SOF wait count 384 */ 385 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 386 387 /* 388 * One uFrame 125 micro seconds 389 * One Frame 1 milli second or 8 uFrames 390 */ 391 #define EHCI_uFRAMES_PER_USB_FRAME 8 392 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3 393 394 395 /* 396 * Pipe private structure 397 * 398 * There is an instance of this structure per pipe. This structure holds 399 * HCD specific pipe information. A pointer to this structure is kept in 400 * the USBA pipe handle (usba_pipe_handle_data_t). 401 */ 402 typedef struct ehci_pipe_private { 403 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 404 ehci_qh_t *pp_qh; /* Pipe's qh */ 405 406 /* State of the pipe */ 407 uint_t pp_state; /* See below */ 408 409 /* Local copy of the pipe policy */ 410 usb_pipe_policy_t pp_policy; 411 412 /* For Periodic Pipes Only */ 413 uint_t pp_pnode; /* periodic node */ 414 uchar_t pp_smask; /* Start split mask */ 415 uchar_t pp_cmask; /* Comp split mask */ 416 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 417 uint_t pp_max_periodic_req_cnt; /* Max req count */ 418 419 /* For Isochronous pipes only */ 420 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 421 422 /* 423 * Each pipe may have multiple transfer wrappers. Each transfer 424 * wrapper represents a USB transfer on the bus. A transfer is 425 * made up of one or more transactions. 426 */ 427 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */ 428 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 429 430 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */ 431 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */ 432 433 /* 434 * Pipe's transfer timeout handling & this transfer timeout handling 435 * will be per pipe. 436 */ 437 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */ 438 timeout_id_t pp_timer_id; /* Timer id */ 439 440 /* Done td count */ 441 uint_t pp_count_done_qtds; /* Done td count */ 442 443 /* Errors */ 444 usb_cr_t pp_error; /* Pipe error */ 445 446 /* Condition variable for transfers completion event */ 447 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 448 449 /* Pipe flag */ 450 uint_t pp_flag; /* For polled mode */ 451 452 /* Halting States */ 453 uint_t pp_halt_state; /* Is it halting */ 454 455 /* Condition variable for halt completion event */ 456 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */ 457 458 /* 459 * HCD gets Interrupt/Isochronous IN polling request only once and 460 * it has to insert next polling requests after completion of first 461 * request until either stop polling/pipe close is called. So HCD 462 * has to take copy of the original Interrupt/Isochronous IN request. 463 */ 464 usb_opaque_t pp_client_periodic_in_reqp; 465 } ehci_pipe_private_t; 466 467 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t)) 468 469 /* 470 * Pipe states 471 * 472 * ehci pipe states will be similar to usba. Refer usbai.h. 473 */ 474 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 475 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 476 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 477 478 /* Additional ehci pipe states for the ehci_pipe_cleanup */ 479 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 480 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 481 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 482 483 /* 484 * Pipe flag 485 * 486 * For polled mode flag. 487 */ 488 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */ 489 490 /* Pipe specific flags */ 491 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 492 493 /* 494 * Halting States 495 * prevent halting from interleaving. 496 */ 497 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */ 498 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */ 499 500 /* 501 * Request values for Clear_TT_Buffer 502 */ 503 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \ 504 USB_DEV_REQ_RCPT_OTHER) 505 #define EHCI_CLEAR_TT_BUFFER_BREQ 8 506 507 /* 508 * USB frame offset 509 * 510 * Add appropriate frame offset to the current usb frame number and use it 511 * as a starting frame number for a given usb isochronous request. 512 */ 513 #define EHCI_FRAME_OFFSET 2 /* Frame offset */ 514 515 /* 516 * Different interrupt polling intervals supported for high speed 517 * devices and its range must be from 1 to 16 units. This value is 518 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval 519 * of 4 means a period of 8us (2 ^ (4-1)). 520 * 521 * The following values are defined after above convertion in terms 522 * 125us units. 523 */ 524 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */ 525 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */ 526 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */ 527 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */ 528 529 /* 530 * The following indecies are are used to calculate Start and complete 531 * masks as per the polling interval. 532 */ 533 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */ 534 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */ 535 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */ 536 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */ 537 538 /* 539 * Different interrupt polling intervals supported for low/full/high 540 * speed devices. For high speed devices, the following values are 541 * applicable after convertion. 542 */ 543 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */ 544 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */ 545 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */ 546 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */ 547 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */ 548 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */ 549 550 /* 551 * Number of interrupt transfer requests that should be maintained on 552 * the interrupt endpoint corresponding to different polling intervals 553 * supported. 554 */ 555 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */ 556 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */ 557 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 558 559 /* Function prototype */ 560 typedef void (*ehci_handler_function_t)( 561 ehci_state_t *ehcip, 562 ehci_pipe_private_t *pp, 563 struct ehci_trans_wrapper *tw, 564 ehci_qtd_t *qtd, 565 void *ehci_handle_callback_value); 566 567 568 /* 569 * Transfer wrapper 570 * 571 * The transfer wrapper represents a USB transfer on the bus and there 572 * is one instance per USB transfer. A transfer is made up of one or 573 * more transactions. 574 * 575 * Control and bulk pipes will have one transfer wrapper per transfer 576 * and where as Isochronous and Interrupt pipes will only have one 577 * transfer wrapper. The transfers wrapper are continually reused for 578 * the Interrupt and Isochronous pipes as those pipes are polled. 579 */ 580 typedef struct ehci_trans_wrapper { 581 struct ehci_trans_wrapper *tw_next; /* Next wrapper */ 582 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */ 583 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 584 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 585 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 586 uint32_t tw_id; /* 32bit ID */ 587 size_t tw_length; /* Txfer length */ 588 char *tw_buf; /* Buffer for Xfer */ 589 usb_flags_t tw_flags; /* Flags */ 590 uint_t tw_num_qtds; /* Number of QTDs */ 591 ehci_qtd_t *tw_qtd_head; /* Head QTD */ 592 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */ 593 uint_t tw_direction; /* Direction of QTD */ 594 595 /* Current transfer request pointer */ 596 usb_opaque_t tw_curr_xfer_reqp; 597 598 /* Transfer timeout information */ 599 int tw_timeout; /* Timeout value */ 600 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 601 602 /* 603 * This is the function to call when this td is done. This way 604 * we don't have to look in the td to figure out what kind it is. 605 */ 606 ehci_handler_function_t tw_handle_qtd; 607 608 /* 609 * This is the callback value used when processing a done td. 610 */ 611 usb_opaque_t tw_handle_callback_value; 612 613 /* We preallocate all the td's for each tw and place them here */ 614 ehci_qtd_t *tw_qtd_free_list; 615 ehci_qtd_t *tw_alt_qtd; 616 } ehci_trans_wrapper_t; 617 618 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper)) 619 620 /* 621 * Isochronous Transfer Wrapper 622 * 623 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed 624 * isochronous transfers. A transfer wrapper consists of one or more 625 * transactionsl, but there is one one instance per USB transfer request. 626 * 627 * The isochrnous transfer wrapper are continiously reused because these 628 * pipes are polled. 629 */ 630 typedef struct ehci_isoc_xwrapper { 631 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */ 632 ehci_pipe_private_t *itw_pipe_private; 633 634 /* DMA and memory pointers */ 635 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */ 636 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */ 637 ddi_dma_cookie_t itw_cookie; /* DMA cookie */ 638 639 /* Transfer information */ 640 char *itw_buf; /* Buffer for Xfer */ 641 size_t itw_length; /* Txfer length */ 642 usb_flags_t itw_flags; /* Flags */ 643 usb_port_status_t itw_port_status; /* Port Speed */ 644 uint_t itw_direction; /* Direction of ITD */ 645 646 /* ITD information */ 647 uint_t itw_num_itds; /* Number of ITDs */ 648 ehci_itd_t *itw_itd_head; /* Head ITD */ 649 ehci_itd_t *itw_itd_tail; /* Tail ITD */ 650 usb_isoc_req_t *itw_curr_xfer_reqp; 651 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp; 652 653 /* We preallocate all the td's for each tw and place them here */ 654 ehci_itd_t *itw_itd_free_list; 655 656 /* Device and hub information needed by every iTD */ 657 uint_t itw_hub_addr; 658 uint_t itw_hub_port; 659 uint_t itw_endpoint_num; 660 uint_t itw_device_addr; 661 662 /* 663 * Callback handling function and arguement. Called when an iTD is 664 * is done. 665 */ 666 usb_opaque_t itw_handle_callback_value; 667 668 /* 32bit ID */ 669 uint32_t itw_id; 670 } ehci_isoc_xwrapper_t; 671 672 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t)) 673 674 /* 675 * Time waits for the different EHCI specific operations. 676 * These timeout values are specified in terms of microseconds. 677 */ 678 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 679 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */ 680 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */ 681 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */ 682 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */ 683 684 /* These timeout values are specified in seconds */ 685 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 686 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 687 688 /* EHCI flags for general use */ 689 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 690 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 691 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 692 693 /* 694 * Maximum allowable data transfer size per transaction as supported 695 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96) 696 * 697 * Also within QTD, there will be five buffer pointers abd each buffer 698 * pointer can transfer upto 4k bytes of data. 699 */ 700 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */ 701 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */ 702 703 /* 704 * The maximum allowable bulk data transfer size. It can be different 705 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will 706 * take care of breaking a bulk data request into multiples of ehci 707 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this 708 * value is set to 640k bytes. 709 */ 710 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */ 711 712 /* 713 * Timeout flags 714 * 715 * These flags will be used to stop the timer before timeout handler 716 * gets executed. 717 */ 718 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */ 719 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 720 721 722 /* 723 * High speed bandwidth allocation 724 * 725 * The following definitions are used during bandwidth calculations 726 * for a given high speed endpoint or high speed split transactions. 727 */ 728 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */ 729 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */ 730 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */ 731 #define HS_SOF 12 /* Length in bytes of High speed SOF */ 732 #define HS_EOF 70 /* Length in bytes of High speed EOF */ 733 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 734 735 /* 736 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved 737 * for the non-periodic high-speed transfers. Where as peridoic high-speed 738 * transfers will get 80% of the bus time. In one micro-frame or 125us, we 739 * can transfer 7500 bytes or 60,000 bits. 740 */ 741 #define HS_NON_PERIODIC_BANDWIDTH 1500 742 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \ 743 HS_EOF - HS_NON_PERIODIC_BANDWIDTH) 744 745 /* 746 * High speed periodic frame bandwidth will be eight times the micro frame 747 * high speed periodic bandwidth. 748 */ 749 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES 750 751 /* 752 * The following are the protocol overheads in terms of Bytes for the 753 * different transfer types. All these protocol overhead values are 754 * derived from the 5.11.3 section of USB 2.0 Specification. 755 */ 756 #define HS_NON_ISOC_PROTO_OVERHEAD 55 757 #define HS_ISOC_PROTO_OVERHEAD 38 758 759 /* 760 * The following are THE protocol overheads in terms of Bytes for the 761 * start and complete split transactions tokens overheads. All these 762 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3 763 * of USB2.0 Specification. 764 */ 765 #define START_SPLIT_OVERHEAD 04 766 #define COMPLETE_SPLIT_OVERHEAD 04 767 768 /* 769 * The Host Controller (HC) delays are the USB host controller specific 770 * delays. The value shown below is the host controller delay for the 771 * given EHCI host controller. 772 */ 773 #define EHCI_HOST_CONTROLLER_DELAY 18 774 775 /* 776 * Low/Full speed bandwidth allocation 777 * 778 * The following definitions are used during bandwidth calculations for 779 * a given high speed hub or a transaction translator (TT) and for a 780 * given low/full speed device connected to high speed hub or TT using 781 * split transactions 782 */ 783 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */ 784 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */ 785 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */ 786 #define FS_SOF 6 /* Length in bytes of Full speed SOF */ 787 #define FS_EOF 4 /* Length in bytes of Full speed EOF */ 788 789 /* 790 * Minimum polling interval for low speed endpoint 791 * 792 * According USB 2.0 Specification, a full-speed endpoint can specify 793 * a desired polling interval 1ms to 255ms and a low speed endpoints 794 * are limited to specifying only 10ms to 255ms. But some old keyboards 795 * and mice uses polling interval of 8ms. For compatibility purpose, 796 * we are using polling interval between 8ms and 255ms for low speed 797 * endpoints. The ehci driver will use 8ms polling interval if a low 798 * speed device reports a polling interval that is less than 8ms. 799 */ 800 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */ 801 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */ 802 803 /* 804 * For non-periodic transfers, reserve atleast for one low-speed device 805 * transaction. According to USB Bandwidth Analysis white paper and also 806 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 807 * transaction takes 0x628h full speed bits (197 bytes), which comes to 808 * around 13% of USB frame time. 809 * 810 * The periodic transfers will get around 87% of USB frame time. 811 */ 812 #define FS_NON_PERIODIC_BANDWIDTH 197 813 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \ 814 FS_EOF - FS_NON_PERIODIC_BANDWIDTH) 815 816 /* 817 * The following are the protocol overheads in terms of Bytes for the 818 * different transfer types. All these protocol overhead values are 819 * derived from the 5.11.3 section of USB Specification and with the 820 * help of Bandwidth Analysis white paper which is posted on the USB 821 * developer forum. 822 */ 823 #define FS_NON_ISOC_PROTO_OVERHEAD 14 824 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 825 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 826 #define LOW_SPEED_PROTO_OVERHEAD 97 827 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 828 829 /* The maximum amount of isoch data that can be transferred in one uFrame */ 830 #define MAX_UFRAME_SITD_XFER 188 831 832 /* 833 * The low speed clock below represents that to transmit one low-speed 834 * bit takes eight times more than one full speed bit time. 835 */ 836 #define LOW_SPEED_CLOCK 8 837 838 /* 839 * The Transaction Translator (TT) delay is the additional time needed 840 * to execute low/full speed transaction from high speed split transaction 841 * for the low/full device connected to the high speed extrenal hub. 842 */ 843 #define TT_DELAY 18 844 845 846 /* 847 * Macros for setting/getting information 848 */ 849 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \ 850 (uint32_t *)&addr) 851 852 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \ 853 ((uint32_t *)&addr), \ 854 ((int32_t)(val))) 855 856 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \ 857 (uint32_t *)&addr) 858 859 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \ 860 ((uint32_t *)&addr), \ 861 ((int32_t)(val))) 862 863 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \ 864 (uint32_t *)&addr) 865 866 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \ 867 ((uint32_t *)&addr), \ 868 ((int32_t)(val))) 869 870 #define Get_ITD_BODY(ptr, addr) ddi_get32( \ 871 ehcip->ehci_itd_pool_mem_handle, \ 872 (uint32_t *)&ptr->itd_body[addr]) 873 874 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \ 875 ehcip->ehci_itd_pool_mem_handle, \ 876 ((uint32_t *)&ptr->itd_body[addr]),\ 877 ((int32_t)(val))) 878 879 #define Get_ITD_FRAME(addr) ddi_get64( \ 880 ehcip->ehci_itd_pool_mem_handle, \ 881 (uint64_t *)&addr) 882 883 #define Set_ITD_FRAME(addr, val) ddi_put64( \ 884 ehcip->ehci_itd_pool_mem_handle, \ 885 ((uint64_t *)&addr), \ 886 (val)) 887 888 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \ 889 (uint32_t *)&addr) 890 891 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \ 892 ((uint32_t *)&addr), \ 893 ((int32_t)(uintptr_t)(val))) 894 895 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \ 896 (uint8_t *)&ehcip->ehci_capsp->addr) 897 898 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \ 899 (uint16_t *)&ehcip->ehci_capsp->addr) 900 901 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \ 902 (uint32_t *)&ehcip->ehci_capsp->addr) 903 904 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \ 905 (uint32_t *)&ehcip->ehci_regsp->addr) 906 907 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \ 908 ((uint32_t *)&ehcip->ehci_regsp->addr), \ 909 ((int32_t)(val))) 910 911 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \ 912 ehcip->ehci_qh_pool_dma_handle, \ 913 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \ 914 DDI_DMA_SYNC_FORCPU); \ 915 (void) ddi_dma_sync( \ 916 ehcip->ehci_qtd_pool_dma_handle, \ 917 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \ 918 DDI_DMA_SYNC_FORCPU); 919 920 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \ 921 ehcip->ehci_itd_pool_dma_handle, \ 922 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \ 923 DDI_DMA_SYNC_FORCPU); 924 925 #define Sync_IO_Buffer(dma_handle, length) \ 926 (void) ddi_dma_sync(dma_handle, \ 927 0, length, DDI_DMA_SYNC_FORCPU); 928 929 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 930 (void) ddi_dma_sync(dma_handle, \ 931 0, length, DDI_DMA_SYNC_FORDEV); 932 933 /* 934 * Macros to speed handling of 32bit IDs 935 */ 936 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 937 #define EHCI_LOOKUP_ID(x) id32_lookup((x)) 938 #define EHCI_FREE_ID(x) id32_free((x)) 939 940 941 /* 942 * Miscellaneous definitions. 943 */ 944 945 /* Data toggle bits */ 946 #define DATA0 0 947 #define DATA1 1 948 949 /* Halt bit actions */ 950 #define CLEAR_HALT 0 951 #define SET_HALT 1 952 953 typedef uint_t halt_bit_t; 954 955 /* 956 * Setup Packet 957 */ 958 typedef struct setup_pkt { 959 uchar_t bmRequestType; 960 uchar_t bRequest; 961 ushort_t wValue; 962 ushort_t wIndex; 963 ushort_t wLength; 964 }setup_pkt_t; 965 966 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 967 968 #define REQUEST_TYPE_OFFSET 0 969 #define REQUEST_OFFSET 1 970 #define VALUE_OFFSET 2 971 #define INDEX_OFFSET 4 972 #define LENGTH_OFFSET 6 973 974 #define TYPE_DEV_TO_HOST 0x80000000 975 #define DEVICE 0x00000001 976 #define CONFIGURATION 0x00000002 977 978 /* 979 * The following are used in attach to indicate 980 * what has been succesfully allocated, so detach 981 * can remove them. 982 */ 983 #define EHCI_ATTACH 0x01 /* ehci driver initilization */ 984 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */ 985 #define EHCI_INTR 0x04 /* Interrupt handler registered */ 986 #define EHCI_USBAREG 0x08 /* USBA registered */ 987 #define EHCI_RHREG 0x10 /* Root hub driver loaded */ 988 989 /* 990 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase 991 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to 992 * make sure that EHCI is receiving interrupts. 993 */ 994 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */ 995 996 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 997 998 /* 999 * Debug printing 1000 * Masks 1001 */ 1002 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 1003 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 1004 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 1005 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 1006 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 1007 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 1008 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 1009 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 1010 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */ 1011 #define PRINT_MASK_ALL 0xFFFFFFFF 1012 1013 /* 1014 * workaround for ALI chips 1015 */ 1016 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */ 1017 1018 /* 1019 * NEC on COMBO and Uli M1575 can support PM 1020 */ 1021 #define PCI_VENDOR_NEC_COMBO 0x1033 1022 #define PCI_DEVICE_NEC_COMBO 0xe0 1023 #define PCI_VENDOR_ULi_M1575 0x10b9 1024 #define PCI_DEVICE_ULi_M1575 0x5239 1025 1026 /* 1027 * VIA chips have some problems, the workaround can ensure those chips 1028 * work reliably. Revisions >= 0x80 are part of a southbridge and appear 1029 * to be reliable. 1030 */ 1031 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */ 1032 #define PCI_VIA_REVISION_6212 0x80 /* VIA 6212 revision ID */ 1033 1034 #define EHCI_VIA_LOST_INTERRUPTS 0x01 1035 #define EHCI_VIA_ASYNC_SCHEDULE 0x02 1036 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04 1037 1038 #define EHCI_VIA_WORKAROUNDS \ 1039 (EHCI_VIA_LOST_INTERRUPTS | \ 1040 EHCI_VIA_ASYNC_SCHEDULE | \ 1041 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE) 1042 1043 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */ 1044 1045 1046 /* 1047 * EHCI HCDI entry points 1048 * 1049 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 1050 * between the Universal Serial Bus Driver (USBA) and the Host Controller 1051 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 1052 */ 1053 int ehci_hcdi_pipe_open( 1054 usba_pipe_handle_data_t *ph, 1055 usb_flags_t usb_flags); 1056 int ehci_hcdi_pipe_close( 1057 usba_pipe_handle_data_t *ph, 1058 usb_flags_t usb_flags); 1059 int ehci_hcdi_pipe_reset( 1060 usba_pipe_handle_data_t *ph, 1061 usb_flags_t usb_flags); 1062 int ehci_hcdi_pipe_ctrl_xfer( 1063 usba_pipe_handle_data_t *ph, 1064 usb_ctrl_req_t *ctrl_reqp, 1065 usb_flags_t usb_flags); 1066 int ehci_hcdi_bulk_transfer_size( 1067 usba_device_t *usba_device, 1068 size_t *size); 1069 int ehci_hcdi_pipe_bulk_xfer( 1070 usba_pipe_handle_data_t *ph, 1071 usb_bulk_req_t *bulk_reqp, 1072 usb_flags_t usb_flags); 1073 int ehci_hcdi_pipe_intr_xfer( 1074 usba_pipe_handle_data_t *ph, 1075 usb_intr_req_t *intr_req, 1076 usb_flags_t usb_flags); 1077 int ehci_hcdi_pipe_stop_intr_polling( 1078 usba_pipe_handle_data_t *ph, 1079 usb_flags_t usb_flags); 1080 usb_frame_number_t ehci_hcdi_get_current_frame_number( 1081 usba_device_t *usba_device); 1082 uint_t ehci_hcdi_get_max_isoc_pkts( 1083 usba_device_t *usba_device); 1084 int ehci_hcdi_pipe_isoc_xfer( 1085 usba_pipe_handle_data_t *ph, 1086 usb_isoc_req_t *isoc_reqp, 1087 usb_flags_t usb_flags); 1088 int ehci_hcdi_pipe_stop_isoc_polling( 1089 usba_pipe_handle_data_t *ph, 1090 usb_flags_t usb_flags); 1091 1092 /* 1093 * EHCI Polled entry points function prototypes. 1094 */ 1095 int ehci_hcdi_polled_input_init( 1096 usba_pipe_handle_data_t *ph, 1097 uchar_t **polled_buf, 1098 usb_console_info_impl_t *info); 1099 int ehci_hcdi_polled_input_enter( 1100 usb_console_info_impl_t *info); 1101 int ehci_hcdi_polled_read( 1102 usb_console_info_impl_t *info, 1103 uint_t *num_characters); 1104 int ehci_hcdi_polled_input_exit( 1105 usb_console_info_impl_t *info); 1106 int ehci_hcdi_polled_input_fini( 1107 usb_console_info_impl_t *info); 1108 1109 /* 1110 * EHCI Root Hub entry points function prototypes. 1111 */ 1112 int ehci_init_root_hub( 1113 ehci_state_t *ehcip); 1114 int ehci_load_root_hub_driver( 1115 ehci_state_t *ehcip); 1116 int ehci_unload_root_hub_driver( 1117 ehci_state_t *ehcip); 1118 int ehci_handle_root_hub_pipe_open( 1119 usba_pipe_handle_data_t *ph, 1120 usb_flags_t flags); 1121 int ehci_handle_root_hub_pipe_close( 1122 usba_pipe_handle_data_t *ph); 1123 int ehci_handle_root_hub_pipe_reset( 1124 usba_pipe_handle_data_t *ph, 1125 usb_flags_t flags); 1126 int ehci_handle_root_hub_request( 1127 ehci_state_t *ehcip, 1128 usba_pipe_handle_data_t *ph, 1129 usb_ctrl_req_t *ctrl_reqp); 1130 int ehci_handle_root_hub_pipe_start_intr_polling( 1131 usba_pipe_handle_data_t *ph, 1132 usb_intr_req_t *intr_reqp, 1133 usb_flags_t flags); 1134 void ehci_handle_root_hub_pipe_stop_intr_polling( 1135 usba_pipe_handle_data_t *ph, 1136 usb_flags_t flags); 1137 1138 /* 1139 * EHCI Interrupt Handler entry point. 1140 */ 1141 uint_t ehci_intr(caddr_t arg1, 1142 caddr_t arg2); 1143 1144 #ifdef __cplusplus 1145 } 1146 #endif 1147 1148 #endif /* _SYS_USB_EHCID_H */ 1149