1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_USB_EHCID_H 28 #define _SYS_USB_EHCID_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Enchanced Host Controller Driver (EHCI) 38 * 39 * The EHCI driver is a software driver which interfaces to the Universal 40 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 41 * the Host Controller is defined by the EHCI Host Controller Interface. 42 * 43 * This header file describes the data structures and function prototypes 44 * required for the EHCI Driver to maintain state of Host Controller (HC), 45 * to perform different USB transfers and for the bandwidth allocations. 46 */ 47 48 #include <sys/usb/hcd/ehci/ehci.h> 49 #include <sys/usb/hcd/ehci/ehci_hub.h> 50 51 52 /* 53 * EHCI Bandwidth Maintainence Structure. 54 * 55 * The ehci_bandwidth array keeps track of allocated bandwidth for ehci 56 * host controller. There are 32 bandwidth lists corresponding to 32 ms 57 * periodic frame lists. Each bandwidth list inturn will contain eight 58 * micro frame bandwidth lists. 59 */ 60 #define EHCI_MAX_UFRAMES 8 /* Max uframes 125us per frame */ 61 62 typedef struct ehci_frame_bandwidth { 63 uint_t ehci_allocated_frame_bandwidth; 64 uint_t ehci_micro_frame_bandwidth[EHCI_MAX_UFRAMES]; 65 } ehci_frame_bandwidth_t; 66 67 68 /* 69 * EHCI Host Controller state structure 70 * 71 * The Host Controller Driver (HCD) maintains the state of Host Controller 72 * (HC). There is an ehci_state structure per instance of the EHCI 73 * host controller. 74 */ 75 typedef struct ehci_state { 76 dev_info_t *ehci_dip; /* Dip of HC */ 77 uint_t ehci_instance; 78 usba_hcdi_ops_t *ehci_hcdi_ops; /* HCDI structure */ 79 uint_t ehci_flags; /* Used for cleanup */ 80 uint16_t ehci_vendor_id; /* chip vendor */ 81 uint16_t ehci_device_id; /* chip device */ 82 uint8_t ehci_rev_id; /* chip revison */ 83 84 ddi_acc_handle_t ehci_caps_handle; /* Caps Reg Handle */ 85 ehci_caps_t *ehci_capsp; /* Capability Regs */ 86 ehci_regs_t *ehci_regsp; /* Operational Regs */ 87 88 ddi_acc_handle_t ehci_config_handle; /* Config space hndle */ 89 uint_t ehci_frame_interval; /* Frme inter reg */ 90 ddi_dma_attr_t ehci_dma_attr; /* DMA attributes */ 91 92 ddi_intr_handle_t *ehci_htable; /* intr handle */ 93 uint_t ehci_intr_pri; /* intr priority */ 94 kmutex_t ehci_int_mutex; /* Global EHCI mutex */ 95 96 /* Periodic Frame List area */ 97 ehci_periodic_frame_list_t *ehci_periodic_frame_list_tablep; 98 /* Virtual Periodic Frame List ptr */ 99 ddi_dma_cookie_t ehci_pflt_cookie; /* DMA cookie */ 100 ddi_dma_handle_t ehci_pflt_dma_handle; /* DMA handle */ 101 ddi_acc_handle_t ehci_pflt_mem_handle; /* Memory handle */ 102 103 /* 104 * There are two pools of memory. One pool contains the memory for 105 * the transfer descriptors and other pool contains the memory for 106 * the endpoint descriptors. The advantage of the pools is that it's 107 * easy to go back and forth between the iommu and the cpu addresses. 108 * 109 * The pools are protected by the ehci_int_mutex because the memory 110 * in the pools may be accessed by either the host controller or the 111 * host controller driver. 112 */ 113 114 /* Endpoint descriptor pool */ 115 ehci_qh_t *ehci_qh_pool_addr; /* Start of the pool */ 116 ddi_dma_cookie_t ehci_qh_pool_cookie; /* DMA cookie */ 117 ddi_dma_handle_t ehci_qh_pool_dma_handle; /* DMA handle */ 118 ddi_acc_handle_t ehci_qh_pool_mem_handle; /* Mem handle */ 119 uint_t ehci_dma_addr_bind_flag; /* DMA flag */ 120 121 /* General transfer descriptor pool */ 122 ehci_qtd_t *ehci_qtd_pool_addr; /* Start of the pool */ 123 ddi_dma_cookie_t ehci_qtd_pool_cookie; /* DMA cookie */ 124 ddi_dma_handle_t ehci_qtd_pool_dma_handle; /* DMA hndle */ 125 ddi_acc_handle_t ehci_qtd_pool_mem_handle; /* Mem hndle */ 126 127 /* Isochronous transfer descriptor pool */ 128 ehci_itd_t *ehci_itd_pool_addr; /* Start of the pool */ 129 ddi_dma_cookie_t ehci_itd_pool_cookie; /* DMA cookie */ 130 ddi_dma_handle_t ehci_itd_pool_dma_handle; /* DMA hndle */ 131 ddi_acc_handle_t ehci_itd_pool_mem_handle; /* Mem hndle */ 132 133 /* Condition variable for advance on Asynchronous Schedule */ 134 kcondvar_t ehci_async_schedule_advance_cv; 135 136 /* Head of Asynchronous Schedule List */ 137 ehci_qh_t *ehci_head_of_async_sched_list; 138 139 /* 140 * List of QTD inserted either into Asynchronous or Periodic 141 * Schedule lists. 142 */ 143 ehci_qtd_t *ehci_active_qtd_list; 144 /* 145 * List of ITD active itd list. 146 */ 147 ehci_itd_t *ehci_active_itd_list; 148 149 /* 150 * Bandwidth fields 151 * 152 * The ehci_bandwidth array keeps track of allocated bandwidth for 153 * ehci host controller. There are 32 bandwidth lists corresponding 154 * to 32 ms periodic frame lists. Each bandwidth list in turn will 155 * contain eight micro frame bandwidth lists. 156 * 157 * ehci_min_frame_bandwidth field indicates least allocated milli 158 * second bandwidth list. 159 */ 160 ehci_frame_bandwidth_t ehci_frame_bandwidth[EHCI_NUM_INTR_QH_LISTS]; 161 162 /* No. of open pipes, async qh, and periodic qh */ 163 uint_t ehci_open_pipe_count; 164 uint_t ehci_open_async_count; 165 uint_t ehci_open_periodic_count; 166 167 /* 168 * Endpoint Reclamation List 169 * 170 * The interrupt list processing cannot be stopped when a periodic 171 * endpoint is removed from the list. The endpoints are detached 172 * from the interrupt lattice tree and put on to the reclaimation 173 * list. On next SOF interrupt all those endpoints, which are on 174 * the reclaimation list will be deallocated. 175 */ 176 ehci_qh_t *ehci_reclaim_list; /* Reclaimation list */ 177 178 ehci_root_hub_t ehci_root_hub; /* Root hub info */ 179 180 /* Frame number overflow information */ 181 usb_frame_number_t ehci_fno; 182 183 /* For host controller error counter */ 184 uint_t ehci_hc_error; 185 186 /* 187 * ehci_missed_intr_sts is used to save the normal mode interrupt 188 * status information if an interrupt is pending for normal mode 189 * when polled code is entered. 190 */ 191 uint_t ehci_missed_intr_sts; 192 193 /* 194 * Saved copy of the ehci registers of the normal mode & change 195 * required ehci registers values for the polled mode operation. 196 * Before returning from the polled mode to normal mode replace 197 * the required current registers with this saved ehci registers 198 * copy. 199 */ 200 ehci_regs_t ehci_polled_save_regs; 201 202 /* 203 * Saved copy of the interrupt table used in normal ehci mode and 204 * replace this table by another interrupt table that used in the 205 * POLLED mode. 206 */ 207 ehci_qh_t *ehci_polled_frame_list_table[EHCI_NUM_PERIODIC_FRAME_LISTS]; 208 209 /* ehci polled mode enter counter */ 210 uint_t ehci_polled_enter_count; 211 212 /* 213 * counter for polled mode and used in suspend mode to see if 214 * there is a keyboard connected. 215 */ 216 uint_t ehci_polled_kbd_count; 217 218 /* counter for polled read and use it to clean the interrupt status */ 219 uint_t ehci_polled_read_count; 220 221 /* EHCI Host Controller Software State information */ 222 uint_t ehci_hc_soft_state; 223 224 /* Log handle for debug, console, log messages */ 225 usb_log_handle_t ehci_log_hdl; 226 227 /* Kstat structures */ 228 kstat_t *ehci_intrs_stats; 229 kstat_t *ehci_total_stats; 230 kstat_t *ehci_count_stats[USB_N_COUNT_KSTATS]; 231 } ehci_state_t; 232 233 typedef struct ehci_intrs_stats { 234 struct kstat_named ehci_sts_async_sched_status; 235 struct kstat_named ehci_sts_periodic_sched_status; 236 struct kstat_named ehci_sts_empty_async_schedule; 237 struct kstat_named ehci_sts_host_ctrl_halted; 238 struct kstat_named ehci_sts_async_advance_intr; 239 struct kstat_named ehci_sts_host_system_error_intr; 240 struct kstat_named ehci_sts_frm_list_rollover_intr; 241 struct kstat_named ehci_sts_rh_port_change_intr; 242 struct kstat_named ehci_sts_usb_error_intr; 243 struct kstat_named ehci_sts_usb_intr; 244 struct kstat_named ehci_sts_not_claimed; 245 struct kstat_named ehci_sts_total; 246 } ehci_intrs_stats_t; 247 248 /* 249 * ehci kstat defines 250 */ 251 #define EHCI_INTRS_STATS(ehci) ((ehci)->ehci_intrs_stats) 252 #define EHCI_INTRS_STATS_DATA(ehci) \ 253 ((ehci_intrs_stats_t *)EHCI_INTRS_STATS((ehci))->ks_data) 254 255 #define EHCI_TOTAL_STATS(ehci) ((ehci)->ehci_total_stats) 256 #define EHCI_TOTAL_STATS_DATA(ehci) (KSTAT_IO_PTR((ehci)->ehci_total_stats)) 257 #define EHCI_CTRL_STATS(ehci) \ 258 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_CONTROL])) 259 #define EHCI_BULK_STATS(ehci) \ 260 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_BULK])) 261 #define EHCI_INTR_STATS(ehci) \ 262 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_INTR])) 263 #define EHCI_ISOC_STATS(ehci) \ 264 (KSTAT_IO_PTR((ehci)->ehci_count_stats[USB_EP_ATTR_ISOCH])) 265 266 /* warlock directives, stable data */ 267 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_state_t)) 268 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_intr_pri)) 269 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dip)) 270 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_regsp)) 271 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_instance)) 272 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_vendor_id)) 273 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_device_id)) 274 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_rev_id)) 275 276 /* this may not be stable data in the future */ 277 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_addr)) 278 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_mem_handle)) 279 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qtd_pool_cookie)) 280 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_addr)) 281 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_mem_handle)) 282 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_qh_pool_cookie)) 283 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_addr)) 284 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_mem_handle)) 285 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_itd_pool_cookie)) 286 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_dma_addr_bind_flag)) 287 _NOTE(DATA_READABLE_WITHOUT_LOCK(ehci_state_t::ehci_log_hdl)) 288 289 _NOTE(LOCK_ORDER(ehci_state::ehci_int_mutex \ 290 usba_pipe_handle_data::p_mutex \ 291 usba_device::usb_mutex \ 292 usba_ph_impl::usba_ph_mutex)) 293 294 /* 295 * Host Contoller Software States 296 * 297 * EHCI_CTLR_INIT_STATE: 298 * The host controller soft state will be set to this during the 299 * ehci_attach. 300 * 301 * EHCI_CTLR_SUSPEND_STATE: 302 * The host controller soft state will be set to this during the 303 * ehci_cpr_suspend. 304 * 305 * EHCI_CTLR_OPERATIONAL_STATE: 306 * The host controller soft state will be set to this after moving 307 * host controller to operational state and host controller start 308 * generating SOF successfully. 309 * 310 * EHCI_CTLR_ERROR_STATE: 311 * The host controller soft state will be set to this during the 312 * no SOF or UE error conditions. 313 * 314 * Under this state or condition, only pipe stop polling, pipe reset 315 * and pipe close are allowed. But all other entry points like pipe 316 * open, get/set pipe policy, cotrol send/receive, bulk send/receive 317 * isoch send/receive, start polling etc. will fail. 318 * 319 * State Diagram for the host controller software state 320 * 321 * 322 * ehci_attach->[INIT_STATE] 323 * | 324 * | -------->----[ERROR_STATE]--<-----------<--- 325 * | | Failure (UE/no SOF condition) | 326 * | ^ ^ 327 * V | Success | 328 * ehci_init_ctlr--->--------[OPERATIONAL_STATE]------>-ehci_send/recv/polling 329 * ^ | 330 * | | 331 * | V 332 * -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend 333 */ 334 #define EHCI_CTLR_INIT_STATE 0 /* Initilization state */ 335 #define EHCI_CTLR_SUSPEND_STATE 1 /* Suspend state */ 336 #define EHCI_CTLR_OPERATIONAL_STATE 2 /* Operational state */ 337 #define EHCI_CTLR_ERROR_STATE 3 /* Ue error or no sof state */ 338 339 /* 340 * Periodic and non-periodic macros 341 */ 342 #define EHCI_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 343 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\ 344 ((endpoint->bmAttributes &\ 345 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 346 347 #define EHCI_NON_PERIODIC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 348 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\ 349 ((endpoint->bmAttributes &\ 350 USB_EP_ATTR_MASK) == USB_EP_ATTR_BULK)) 351 352 #define EHCI_ISOC_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 353 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) 354 355 #define EHCI_INTR_ENDPOINT(endpoint) (((endpoint->bmAttributes &\ 356 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR)) 357 358 359 /* 360 * EHCI QH and QTD Pool sizes. 361 */ 362 #define EHCI_QH_POOL_SIZE 100 363 #define EHCI_QTD_POOL_SIZE 200 364 #define EHCI_ITD_POOL_SIZE 200 365 366 /* 367 * ehci_dma_addr_bind_flag values 368 * 369 * This flag indicates if the various DMA addresses allocated by the EHCI 370 * have been bound to their respective handles. This is needed to recover 371 * without errors from ehci_cleanup when it calls ddi_dma_unbind_handle() 372 */ 373 #define EHCI_QTD_POOL_BOUND 0x01 /* For QTD pools */ 374 #define EHCI_QH_POOL_BOUND 0x02 /* For QH pools */ 375 #define EHCI_PFLT_DMA_BOUND 0x04 /* For Periodic Frame List area */ 376 #define EHCI_ITD_POOL_BOUND 0x08 /* For QTD pools */ 377 378 /* 379 * Maximum SOF wait count 380 */ 381 #define MAX_SOF_WAIT_COUNT 2 /* Wait for maximum SOF frames */ 382 383 /* 384 * One uFrame 125 micro seconds 385 * One Frame 1 milli second or 8 uFrames 386 */ 387 #define EHCI_uFRAMES_PER_USB_FRAME 8 388 #define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3 389 390 391 /* 392 * Pipe private structure 393 * 394 * There is an instance of this structure per pipe. This structure holds 395 * HCD specific pipe information. A pointer to this structure is kept in 396 * the USBA pipe handle (usba_pipe_handle_data_t). 397 */ 398 typedef struct ehci_pipe_private { 399 usba_pipe_handle_data_t *pp_pipe_handle; /* Back ptr to handle */ 400 ehci_qh_t *pp_qh; /* Pipe's qh */ 401 402 /* State of the pipe */ 403 uint_t pp_state; /* See below */ 404 405 /* Local copy of the pipe policy */ 406 usb_pipe_policy_t pp_policy; 407 408 /* For Periodic Pipes Only */ 409 uint_t pp_pnode; /* periodic node */ 410 uchar_t pp_smask; /* Start split mask */ 411 uchar_t pp_cmask; /* Comp split mask */ 412 uint_t pp_cur_periodic_req_cnt; /* Curr req count */ 413 uint_t pp_max_periodic_req_cnt; /* Max req count */ 414 415 /* For Isochronous pipes only */ 416 usb_frame_number_t pp_next_frame_number; /* Next frame no */ 417 418 /* 419 * Each pipe may have multiple transfer wrappers. Each transfer 420 * wrapper represents a USB transfer on the bus. A transfer is 421 * made up of one or more transactions. 422 */ 423 struct ehci_trans_wrapper *pp_tw_head; /* Head of the list */ 424 struct ehci_trans_wrapper *pp_tw_tail; /* Tail of the list */ 425 426 struct ehci_isoc_xwrapper *pp_itw_head; /* Head of the list */ 427 struct ehci_isoc_xwrapper *pp_itw_tail; /* Tail of the list */ 428 429 /* 430 * Pipe's transfer timeout handling & this transfer timeout handling 431 * will be per pipe. 432 */ 433 struct ehci_trans_wrapper *pp_timeout_list; /* Timeout list */ 434 timeout_id_t pp_timer_id; /* Timer id */ 435 436 /* Done td count */ 437 uint_t pp_count_done_qtds; /* Done td count */ 438 439 /* Errors */ 440 usb_cr_t pp_error; /* Pipe error */ 441 442 /* Condition variable for transfers completion event */ 443 kcondvar_t pp_xfer_cmpl_cv; /* Xfer completion */ 444 445 /* Pipe flag */ 446 uint_t pp_flag; /* For polled mode */ 447 448 /* Halting States */ 449 uint_t pp_halt_state; /* Is it halting */ 450 451 /* Condition variable for halt completion event */ 452 kcondvar_t pp_halt_cmpl_cv; /* Xfer completion */ 453 454 /* 455 * HCD gets Interrupt/Isochronous IN polling request only once and 456 * it has to insert next polling requests after completion of first 457 * request until either stop polling/pipe close is called. So HCD 458 * has to take copy of the original Interrupt/Isochronous IN request. 459 */ 460 usb_opaque_t pp_client_periodic_in_reqp; 461 } ehci_pipe_private_t; 462 463 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_pipe_private_t)) 464 465 /* 466 * Pipe states 467 * 468 * ehci pipe states will be similar to usba. Refer usbai.h. 469 */ 470 #define EHCI_PIPE_STATE_IDLE 1 /* Pipe is in ready state */ 471 #define EHCI_PIPE_STATE_ACTIVE 2 /* Pipe is in busy state */ 472 #define EHCI_PIPE_STATE_ERROR 3 /* Pipe is in error state */ 473 474 /* Additional ehci pipe states for the ehci_pipe_cleanup */ 475 #define EHCI_PIPE_STATE_CLOSE 4 /* Pipe close */ 476 #define EHCI_PIPE_STATE_RESET 5 /* Pipe reset */ 477 #define EHCI_PIPE_STATE_STOP_POLLING 6 /* Pipe stop polling */ 478 479 /* 480 * Pipe flag 481 * 482 * For polled mode flag. 483 */ 484 #define EHCI_POLLED_MODE_FLAG 1 /* Polled mode flag */ 485 486 /* Pipe specific flags */ 487 #define EHCI_ISOC_XFER_CONTINUE 1 /* For isoc transfers */ 488 489 /* 490 * Halting States 491 * prevent halting from interleaving. 492 */ 493 #define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */ 494 #define EHCI_HALT_STATE_HALTING 1 /* Currently Halting */ 495 496 /* 497 * Request values for Clear_TT_Buffer 498 */ 499 #define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \ 500 USB_DEV_REQ_RCPT_OTHER) 501 #define EHCI_CLEAR_TT_BUFFER_BREQ 8 502 503 /* 504 * USB frame offset 505 * 506 * Add appropriate frame offset to the current usb frame number and use it 507 * as a starting frame number for a given usb isochronous request. 508 */ 509 #define EHCI_FRAME_OFFSET 2 /* Frame offset */ 510 511 /* 512 * Different interrupt polling intervals supported for high speed 513 * devices and its range must be from 1 to 16 units. This value is 514 * used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval 515 * of 4 means a period of 8us (2 ^ (4-1)). 516 * 517 * The following values are defined after above convertion in terms 518 * 125us units. 519 */ 520 #define EHCI_INTR_1US_POLL 1 /* 1us poll interval */ 521 #define EHCI_INTR_2US_POLL 2 /* 2us poll interval */ 522 #define EHCI_INTR_4US_POLL 4 /* 4us poll interval */ 523 #define EHCI_INTR_XUS_POLL 8 /* 8us and above */ 524 525 /* 526 * The following indecies are are used to calculate Start and complete 527 * masks as per the polling interval. 528 */ 529 #define EHCI_1US_MASK_INDEX 14 /* 1us mask index */ 530 #define EHCI_2US_MASK_INDEX 12 /* 2us mask index */ 531 #define EHCI_4US_MASK_INDEX 8 /* 4us mask index */ 532 #define EHCI_XUS_MASK_INDEX 0 /* 8us and above */ 533 534 /* 535 * Different interrupt polling intervals supported for low/full/high 536 * speed devices. For high speed devices, the following values are 537 * applicable after convertion. 538 */ 539 #define EHCI_INTR_1MS_POLL 1 /* 1ms poll interval */ 540 #define EHCI_INTR_2MS_POLL 2 /* 2ms poll interval */ 541 #define EHCI_INTR_4MS_POLL 4 /* 4ms poll interval */ 542 #define EHCI_INTR_8MS_POLL 8 /* 8ms poll interval */ 543 #define EHCI_INTR_16MS_POLL 16 /* 16ms poll interval */ 544 #define EHCI_INTR_32MS_POLL 32 /* 32ms poll interval */ 545 546 /* 547 * Number of interrupt transfer requests that should be maintained on 548 * the interrupt endpoint corresponding to different polling intervals 549 * supported. 550 */ 551 #define EHCI_INTR_1MS_REQS 4 /* 1ms polling interval */ 552 #define EHCI_INTR_2MS_REQS 2 /* 2ms polling interval */ 553 #define EHCI_INTR_XMS_REQS 1 /* Between 4ms and 32ms */ 554 555 /* Function prototype */ 556 typedef void (*ehci_handler_function_t)( 557 ehci_state_t *ehcip, 558 ehci_pipe_private_t *pp, 559 struct ehci_trans_wrapper *tw, 560 ehci_qtd_t *qtd, 561 void *ehci_handle_callback_value); 562 563 564 /* 565 * Transfer wrapper 566 * 567 * The transfer wrapper represents a USB transfer on the bus and there 568 * is one instance per USB transfer. A transfer is made up of one or 569 * more transactions. 570 * 571 * Control and bulk pipes will have one transfer wrapper per transfer 572 * and where as Isochronous and Interrupt pipes will only have one 573 * transfer wrapper. The transfers wrapper are continually reused for 574 * the Interrupt and Isochronous pipes as those pipes are polled. 575 */ 576 typedef struct ehci_trans_wrapper { 577 struct ehci_trans_wrapper *tw_next; /* Next wrapper */ 578 ehci_pipe_private_t *tw_pipe_private; /* Back ptr */ 579 ddi_dma_handle_t tw_dmahandle; /* DMA handle */ 580 ddi_acc_handle_t tw_accesshandle; /* Acc hndle */ 581 ddi_dma_cookie_t tw_cookie; /* DMA cookie */ 582 uint32_t tw_id; /* 32bit ID */ 583 size_t tw_length; /* Txfer length */ 584 char *tw_buf; /* Buffer for Xfer */ 585 usb_flags_t tw_flags; /* Flags */ 586 uint_t tw_num_qtds; /* Number of QTDs */ 587 ehci_qtd_t *tw_qtd_head; /* Head QTD */ 588 ehci_qtd_t *tw_qtd_tail; /* Tail QTD */ 589 uint_t tw_direction; /* Direction of QTD */ 590 591 /* Current transfer request pointer */ 592 usb_opaque_t tw_curr_xfer_reqp; 593 594 /* Transfer timeout information */ 595 int tw_timeout; /* Timeout value */ 596 struct ehci_trans_wrapper *tw_timeout_next; /* Xfer Timeout Q */ 597 598 /* 599 * This is the function to call when this td is done. This way 600 * we don't have to look in the td to figure out what kind it is. 601 */ 602 ehci_handler_function_t tw_handle_qtd; 603 604 /* 605 * This is the callback value used when processing a done td. 606 */ 607 usb_opaque_t tw_handle_callback_value; 608 609 /* We preallocate all the td's for each tw and place them here */ 610 ehci_qtd_t *tw_qtd_free_list; 611 ehci_qtd_t *tw_alt_qtd; 612 } ehci_trans_wrapper_t; 613 614 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_trans_wrapper)) 615 616 /* 617 * Isochronous Transfer Wrapper 618 * 619 * This transfer wrapper is built specifically for the LOW/FULL/HIGH speed 620 * isochronous transfers. A transfer wrapper consists of one or more 621 * transactionsl, but there is one one instance per USB transfer request. 622 * 623 * The isochrnous transfer wrapper are continiously reused because these 624 * pipes are polled. 625 */ 626 typedef struct ehci_isoc_xwrapper { 627 struct ehci_isoc_xwrapper *itw_next; /* Next wrapper in pp */ 628 ehci_pipe_private_t *itw_pipe_private; 629 630 /* DMA and memory pointers */ 631 ddi_dma_handle_t itw_dmahandle; /* DMA handle ETT */ 632 ddi_acc_handle_t itw_accesshandle; /* Acc hndle */ 633 ddi_dma_cookie_t itw_cookie; /* DMA cookie */ 634 635 /* Transfer information */ 636 char *itw_buf; /* Buffer for Xfer */ 637 size_t itw_length; /* Txfer length */ 638 usb_flags_t itw_flags; /* Flags */ 639 usb_port_status_t itw_port_status; /* Port Speed */ 640 uint_t itw_direction; /* Direction of ITD */ 641 642 /* ITD information */ 643 uint_t itw_num_itds; /* Number of ITDs */ 644 ehci_itd_t *itw_itd_head; /* Head ITD */ 645 ehci_itd_t *itw_itd_tail; /* Tail ITD */ 646 usb_isoc_req_t *itw_curr_xfer_reqp; 647 usb_isoc_pkt_descr_t *itw_curr_isoc_pktp; 648 649 /* We preallocate all the td's for each tw and place them here */ 650 ehci_itd_t *itw_itd_free_list; 651 652 /* Device and hub information needed by every iTD */ 653 uint_t itw_hub_addr; 654 uint_t itw_hub_port; 655 uint_t itw_endpoint_num; 656 uint_t itw_device_addr; 657 658 /* 659 * Callback handling function and arguement. Called when an iTD is 660 * is done. 661 */ 662 usb_opaque_t itw_handle_callback_value; 663 664 /* 32bit ID */ 665 uint32_t itw_id; 666 } ehci_isoc_xwrapper_t; 667 668 _NOTE(MUTEX_PROTECTS_DATA(ehci_state_t::ehci_int_mutex, ehci_isoc_xwrapper_t)) 669 670 /* 671 * Time waits for the different EHCI specific operations. 672 * These timeout values are specified in terms of microseconds. 673 */ 674 #define EHCI_RESET_TIMEWAIT 10000 /* HC reset waiting time */ 675 #define EHCI_TIMEWAIT 10000 /* HC any other waiting time */ 676 #define EHCI_SOF_TIMEWAIT 20000 /* SOF Wait time */ 677 #define EHCI_TAKEOVER_DELAY 10000 /* HC take over waiting time */ 678 #define EHCI_TAKEOVER_WAIT_COUNT 25 /* HC take over waiting count */ 679 680 /* These timeout values are specified in seconds */ 681 #define EHCI_DEFAULT_XFER_TIMEOUT 5 /* Default transfer timeout */ 682 #define EHCI_XFER_CMPL_TIMEWAIT 3 /* Xfers completion timewait */ 683 684 /* EHCI flags for general use */ 685 #define EHCI_FLAGS_NOSLEEP 0x000 /* Don't wait for SOF */ 686 #define EHCI_FLAGS_SLEEP 0x100 /* Wait for SOF */ 687 #define EHCI_FLAGS_DMA_SYNC 0x200 /* Call ddi_dma_sync */ 688 689 /* 690 * Maximum allowable data transfer size per transaction as supported 691 * by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96) 692 * 693 * Also within QTD, there will be five buffer pointers abd each buffer 694 * pointer can transfer upto 4k bytes of data. 695 */ 696 #define EHCI_MAX_QTD_XFER_SIZE 0x5000 /* Maxmum data per transaction */ 697 #define EHCI_MAX_QTD_BUF_SIZE 0x1000 /* Maxmum data per buffer */ 698 699 /* 700 * The maximum allowable bulk data transfer size. It can be different 701 * from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will 702 * take care of breaking a bulk data request into multiples of ehci 703 * EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this 704 * value is set to 640k bytes. 705 */ 706 #define EHCI_MAX_BULK_XFER_SIZE 0xA0000 /* Maximum bulk transfer size */ 707 708 /* 709 * Timeout flags 710 * 711 * These flags will be used to stop the timer before timeout handler 712 * gets executed. 713 */ 714 #define EHCI_REMOVE_XFER_IFLAST 1 /* Stop the timer if it is last QTD */ 715 #define EHCI_REMOVE_XFER_ALWAYS 2 /* Stop the timer without condition */ 716 717 718 /* 719 * High speed bandwidth allocation 720 * 721 * The following definitions are used during bandwidth calculations 722 * for a given high speed endpoint or high speed split transactions. 723 */ 724 #define HS_BUS_BANDWIDTH 7500 /* Up to 7500 bytes per 125us */ 725 #define HS_MAX_POLL_INTERVAL 16 /* Max high speed polling interval */ 726 #define HS_MIN_POLL_INTERVAL 1 /* Min high speed polling interval */ 727 #define HS_SOF 12 /* Length in bytes of High speed SOF */ 728 #define HS_EOF 70 /* Length in bytes of High speed EOF */ 729 #define TREE_HEIGHT 5 /* Log base 2 of 32 */ 730 731 /* 732 * As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved 733 * for the non-periodic high-speed transfers. Where as peridoic high-speed 734 * transfers will get 80% of the bus time. In one micro-frame or 125us, we 735 * can transfer 7500 bytes or 60,000 bits. 736 */ 737 #define HS_NON_PERIODIC_BANDWIDTH 1500 738 #define HS_PERIODIC_BANDWIDTH (HS_BUS_BANDWIDTH - HS_SOF - \ 739 HS_EOF - HS_NON_PERIODIC_BANDWIDTH) 740 741 /* 742 * High speed periodic frame bandwidth will be eight times the micro frame 743 * high speed periodic bandwidth. 744 */ 745 #define HS_PERIODIC_FRAME_BANDWIDTH HS_PERIODIC_BANDWIDTH * EHCI_MAX_UFRAMES 746 747 /* 748 * The following are the protocol overheads in terms of Bytes for the 749 * different transfer types. All these protocol overhead values are 750 * derived from the 5.11.3 section of USB 2.0 Specification. 751 */ 752 #define HS_NON_ISOC_PROTO_OVERHEAD 55 753 #define HS_ISOC_PROTO_OVERHEAD 38 754 755 /* 756 * The following are THE protocol overheads in terms of Bytes for the 757 * start and complete split transactions tokens overheads. All these 758 * protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3 759 * of USB2.0 Specification. 760 */ 761 #define START_SPLIT_OVERHEAD 04 762 #define COMPLETE_SPLIT_OVERHEAD 04 763 764 /* 765 * The Host Controller (HC) delays are the USB host controller specific 766 * delays. The value shown below is the host controller delay for the 767 * given EHCI host controller. 768 */ 769 #define EHCI_HOST_CONTROLLER_DELAY 18 770 771 /* 772 * Low/Full speed bandwidth allocation 773 * 774 * The following definitions are used during bandwidth calculations for 775 * a given high speed hub or a transaction translator (TT) and for a 776 * given low/full speed device connected to high speed hub or TT using 777 * split transactions 778 */ 779 #define FS_BUS_BANDWIDTH 1500 /* Up to 1500 bytes per 1ms */ 780 #define FS_MAX_POLL_INTERVAL 255 /* Max full speed poll interval */ 781 #define FS_MIN_POLL_INTERVAL 1 /* Min full speed polling interval */ 782 #define FS_SOF 6 /* Length in bytes of Full speed SOF */ 783 #define FS_EOF 4 /* Length in bytes of Full speed EOF */ 784 785 /* 786 * Minimum polling interval for low speed endpoint 787 * 788 * According USB 2.0 Specification, a full-speed endpoint can specify 789 * a desired polling interval 1ms to 255ms and a low speed endpoints 790 * are limited to specifying only 10ms to 255ms. But some old keyboards 791 * and mice uses polling interval of 8ms. For compatibility purpose, 792 * we are using polling interval between 8ms and 255ms for low speed 793 * endpoints. The ehci driver will use 8ms polling interval if a low 794 * speed device reports a polling interval that is less than 8ms. 795 */ 796 #define LS_MAX_POLL_INTERVAL 255 /* Max low speed poll interval */ 797 #define LS_MIN_POLL_INTERVAL 8 /* Min low speed polling interval */ 798 799 /* 800 * For non-periodic transfers, reserve atleast for one low-speed device 801 * transaction. According to USB Bandwidth Analysis white paper and also 802 * as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed 803 * transaction takes 0x628h full speed bits (197 bytes), which comes to 804 * around 13% of USB frame time. 805 * 806 * The periodic transfers will get around 87% of USB frame time. 807 */ 808 #define FS_NON_PERIODIC_BANDWIDTH 197 809 #define FS_PERIODIC_BANDWIDTH (FS_BUS_BANDWIDTH - FS_SOF - \ 810 FS_EOF - FS_NON_PERIODIC_BANDWIDTH) 811 812 /* 813 * The following are the protocol overheads in terms of Bytes for the 814 * different transfer types. All these protocol overhead values are 815 * derived from the 5.11.3 section of USB Specification and with the 816 * help of Bandwidth Analysis white paper which is posted on the USB 817 * developer forum. 818 */ 819 #define FS_NON_ISOC_PROTO_OVERHEAD 14 820 #define FS_ISOC_INPUT_PROTO_OVERHEAD 11 821 #define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10 822 #define LOW_SPEED_PROTO_OVERHEAD 97 823 #define HUB_LOW_SPEED_PROTO_OVERHEAD 01 824 825 /* The maximum amount of isoch data that can be transferred in one uFrame */ 826 #define MAX_UFRAME_SITD_XFER 188 827 828 /* 829 * The low speed clock below represents that to transmit one low-speed 830 * bit takes eight times more than one full speed bit time. 831 */ 832 #define LOW_SPEED_CLOCK 8 833 834 /* 835 * The Transaction Translator (TT) delay is the additional time needed 836 * to execute low/full speed transaction from high speed split transaction 837 * for the low/full device connected to the high speed extrenal hub. 838 */ 839 #define TT_DELAY 18 840 841 842 /* 843 * Macros for setting/getting information 844 */ 845 #define Get_QH(addr) ddi_get32(ehcip->ehci_qh_pool_mem_handle, \ 846 (uint32_t *)&addr) 847 848 #define Set_QH(addr, val) ddi_put32(ehcip->ehci_qh_pool_mem_handle, \ 849 ((uint32_t *)&addr), \ 850 ((int32_t)(val))) 851 852 #define Get_QTD(addr) ddi_get32(ehcip->ehci_qtd_pool_mem_handle, \ 853 (uint32_t *)&addr) 854 855 #define Set_QTD(addr, val) ddi_put32(ehcip->ehci_qtd_pool_mem_handle, \ 856 ((uint32_t *)&addr), \ 857 ((int32_t)(val))) 858 859 #define Get_ITD(addr) ddi_get32(ehcip->ehci_itd_pool_mem_handle, \ 860 (uint32_t *)&addr) 861 862 #define Set_ITD(addr, val) ddi_put32(ehcip->ehci_itd_pool_mem_handle, \ 863 ((uint32_t *)&addr), \ 864 ((int32_t)(val))) 865 866 #define Get_ITD_BODY(ptr, addr) ddi_get32( \ 867 ehcip->ehci_itd_pool_mem_handle, \ 868 (uint32_t *)&ptr->itd_body[addr]) 869 870 #define Set_ITD_BODY(ptr, addr, val) ddi_put32( \ 871 ehcip->ehci_itd_pool_mem_handle, \ 872 ((uint32_t *)&ptr->itd_body[addr]),\ 873 ((int32_t)(val))) 874 875 #define Get_ITD_FRAME(addr) ddi_get64( \ 876 ehcip->ehci_itd_pool_mem_handle, \ 877 (uint64_t *)&addr) 878 879 #define Set_ITD_FRAME(addr, val) ddi_put64( \ 880 ehcip->ehci_itd_pool_mem_handle, \ 881 ((uint64_t *)&addr), \ 882 (val)) 883 884 #define Get_PFLT(addr) ddi_get32(ehcip->ehci_pflt_mem_handle, \ 885 (uint32_t *)&addr) 886 887 #define Set_PFLT(addr, val) ddi_put32(ehcip->ehci_pflt_mem_handle, \ 888 ((uint32_t *)&addr), \ 889 ((int32_t)(uintptr_t)(val))) 890 891 #define Get_8Cap(addr) ddi_get8(ehcip->ehci_caps_handle, \ 892 (uint8_t *)&ehcip->ehci_capsp->addr) 893 894 #define Get_16Cap(addr) ddi_get16(ehcip->ehci_caps_handle, \ 895 (uint16_t *)&ehcip->ehci_capsp->addr) 896 897 #define Get_Cap(addr) ddi_get32(ehcip->ehci_caps_handle, \ 898 (uint32_t *)&ehcip->ehci_capsp->addr) 899 900 #define Get_OpReg(addr) ddi_get32(ehcip->ehci_caps_handle, \ 901 (uint32_t *)&ehcip->ehci_regsp->addr) 902 903 #define Set_OpReg(addr, val) ddi_put32(ehcip->ehci_caps_handle, \ 904 ((uint32_t *)&ehcip->ehci_regsp->addr), \ 905 ((int32_t)(val))) 906 907 #define Sync_QH_QTD_Pool(ehcip) (void) ddi_dma_sync( \ 908 ehcip->ehci_qh_pool_dma_handle, \ 909 0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \ 910 DDI_DMA_SYNC_FORCPU); \ 911 (void) ddi_dma_sync( \ 912 ehcip->ehci_qtd_pool_dma_handle, \ 913 0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \ 914 DDI_DMA_SYNC_FORCPU); 915 916 #define Sync_ITD_Pool(ehcip) (void) ddi_dma_sync( \ 917 ehcip->ehci_itd_pool_dma_handle, \ 918 0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \ 919 DDI_DMA_SYNC_FORCPU); 920 921 #define Sync_IO_Buffer(dma_handle, length) \ 922 (void) ddi_dma_sync(dma_handle, \ 923 0, length, DDI_DMA_SYNC_FORCPU); 924 925 #define Sync_IO_Buffer_for_device(dma_handle, length) \ 926 (void) ddi_dma_sync(dma_handle, \ 927 0, length, DDI_DMA_SYNC_FORDEV); 928 929 /* 930 * Macros to speed handling of 32bit IDs 931 */ 932 #define EHCI_GET_ID(x) id32_alloc((void *)(x), KM_SLEEP) 933 #define EHCI_LOOKUP_ID(x) id32_lookup((x)) 934 #define EHCI_FREE_ID(x) id32_free((x)) 935 936 937 /* 938 * Miscellaneous definitions. 939 */ 940 941 /* Data toggle bits */ 942 #define DATA0 0 943 #define DATA1 1 944 945 /* Halt bit actions */ 946 #define CLEAR_HALT 0 947 #define SET_HALT 1 948 949 typedef uint_t halt_bit_t; 950 951 /* 952 * Setup Packet 953 */ 954 typedef struct setup_pkt { 955 uchar_t bmRequestType; 956 uchar_t bRequest; 957 ushort_t wValue; 958 ushort_t wIndex; 959 ushort_t wLength; 960 }setup_pkt_t; 961 962 #define SETUP_SIZE 8 /* Setup packet is always 8 bytes */ 963 964 #define REQUEST_TYPE_OFFSET 0 965 #define REQUEST_OFFSET 1 966 #define VALUE_OFFSET 2 967 #define INDEX_OFFSET 4 968 #define LENGTH_OFFSET 6 969 970 #define TYPE_DEV_TO_HOST 0x80000000 971 #define DEVICE 0x00000001 972 #define CONFIGURATION 0x00000002 973 974 /* 975 * The following are used in attach to indicate 976 * what has been succesfully allocated, so detach 977 * can remove them. 978 */ 979 #define EHCI_ATTACH 0x01 /* ehci driver initilization */ 980 #define EHCI_ZALLOC 0x02 /* Memory for ehci state structure */ 981 #define EHCI_INTR 0x04 /* Interrupt handler registered */ 982 #define EHCI_USBAREG 0x08 /* USBA registered */ 983 #define EHCI_RHREG 0x10 /* Root hub driver loaded */ 984 985 /* 986 * This variable is used in the EHCI_FLAGS to tell the ISR to broadcase 987 * the ehci_async_schedule_advance_cv when an intr occurs. It is used to 988 * make sure that EHCI is receiving interrupts. 989 */ 990 #define EHCI_CV_INTR 0x20 /* Ask INTR to broadcast cv */ 991 992 #define EHCI_UNIT(dev) (getminor((dev)) & ~HUBD_IS_ROOT_HUB) 993 994 /* 995 * Debug printing 996 * Masks 997 */ 998 #define PRINT_MASK_ATTA 0x00000001 /* Attach time */ 999 #define PRINT_MASK_LISTS 0x00000002 /* List management */ 1000 #define PRINT_MASK_ROOT_HUB 0x00000004 /* Root hub stuff */ 1001 #define PRINT_MASK_ALLOC 0x00000008 /* Alloc/dealloc descr */ 1002 #define PRINT_MASK_INTR 0x00000010 /* Interrupt handling */ 1003 #define PRINT_MASK_BW 0x00000020 /* Bandwidth */ 1004 #define PRINT_MASK_CBOPS 0x00000040 /* CB-OPS */ 1005 #define PRINT_MASK_HCDI 0x00000080 /* HCDI entry points */ 1006 #define PRINT_MASK_DUMPING 0x00000100 /* Dump ehci info */ 1007 #define PRINT_MASK_ALL 0xFFFFFFFF 1008 1009 1010 /* 1011 * workaround for ALI chips 1012 */ 1013 #define PCI_VENDOR_ALI 0x10b9 /* PCI Vendor-id Acer */ 1014 #define PCI_VENDOR_VIA 0x1106 /* PCI Vendor-id VIA */ 1015 1016 #define EHCI_VIA_LOST_INTERRUPTS 0x01 1017 #define EHCI_VIA_ASYNC_SCHEDULE 0x02 1018 #define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04 1019 1020 #define EHCI_VIA_WORKAROUNDS \ 1021 (EHCI_VIA_LOST_INTERRUPTS | \ 1022 EHCI_VIA_ASYNC_SCHEDULE | \ 1023 EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE) 1024 1025 #define EHCI_VIA_MAX_BULK_XFER_SIZE 0x8000 /* Maximum bulk transfer size */ 1026 1027 1028 /* 1029 * EHCI HCDI entry points 1030 * 1031 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 1032 * between the Universal Serial Bus Driver (USBA) and the Host Controller 1033 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 1034 */ 1035 int ehci_hcdi_pipe_open( 1036 usba_pipe_handle_data_t *ph, 1037 usb_flags_t usb_flags); 1038 int ehci_hcdi_pipe_close( 1039 usba_pipe_handle_data_t *ph, 1040 usb_flags_t usb_flags); 1041 int ehci_hcdi_pipe_reset( 1042 usba_pipe_handle_data_t *ph, 1043 usb_flags_t usb_flags); 1044 int ehci_hcdi_pipe_ctrl_xfer( 1045 usba_pipe_handle_data_t *ph, 1046 usb_ctrl_req_t *ctrl_reqp, 1047 usb_flags_t usb_flags); 1048 int ehci_hcdi_bulk_transfer_size( 1049 usba_device_t *usba_device, 1050 size_t *size); 1051 int ehci_hcdi_pipe_bulk_xfer( 1052 usba_pipe_handle_data_t *ph, 1053 usb_bulk_req_t *bulk_reqp, 1054 usb_flags_t usb_flags); 1055 int ehci_hcdi_pipe_intr_xfer( 1056 usba_pipe_handle_data_t *ph, 1057 usb_intr_req_t *intr_req, 1058 usb_flags_t usb_flags); 1059 int ehci_hcdi_pipe_stop_intr_polling( 1060 usba_pipe_handle_data_t *ph, 1061 usb_flags_t usb_flags); 1062 usb_frame_number_t ehci_hcdi_get_current_frame_number( 1063 usba_device_t *usba_device); 1064 uint_t ehci_hcdi_get_max_isoc_pkts( 1065 usba_device_t *usba_device); 1066 int ehci_hcdi_pipe_isoc_xfer( 1067 usba_pipe_handle_data_t *ph, 1068 usb_isoc_req_t *isoc_reqp, 1069 usb_flags_t usb_flags); 1070 int ehci_hcdi_pipe_stop_isoc_polling( 1071 usba_pipe_handle_data_t *ph, 1072 usb_flags_t usb_flags); 1073 1074 /* 1075 * EHCI Polled entry points function prototypes. 1076 */ 1077 int ehci_hcdi_polled_input_init( 1078 usba_pipe_handle_data_t *ph, 1079 uchar_t **polled_buf, 1080 usb_console_info_impl_t *info); 1081 int ehci_hcdi_polled_input_enter( 1082 usb_console_info_impl_t *info); 1083 int ehci_hcdi_polled_read( 1084 usb_console_info_impl_t *info, 1085 uint_t *num_characters); 1086 int ehci_hcdi_polled_input_exit( 1087 usb_console_info_impl_t *info); 1088 int ehci_hcdi_polled_input_fini( 1089 usb_console_info_impl_t *info); 1090 1091 /* 1092 * EHCI Root Hub entry points function prototypes. 1093 */ 1094 int ehci_init_root_hub( 1095 ehci_state_t *ehcip); 1096 int ehci_load_root_hub_driver( 1097 ehci_state_t *ehcip); 1098 int ehci_unload_root_hub_driver( 1099 ehci_state_t *ehcip); 1100 int ehci_handle_root_hub_pipe_open( 1101 usba_pipe_handle_data_t *ph, 1102 usb_flags_t flags); 1103 int ehci_handle_root_hub_pipe_close( 1104 usba_pipe_handle_data_t *ph); 1105 int ehci_handle_root_hub_pipe_reset( 1106 usba_pipe_handle_data_t *ph, 1107 usb_flags_t flags); 1108 int ehci_handle_root_hub_request( 1109 ehci_state_t *ehcip, 1110 usba_pipe_handle_data_t *ph, 1111 usb_ctrl_req_t *ctrl_reqp); 1112 int ehci_handle_root_hub_pipe_start_intr_polling( 1113 usba_pipe_handle_data_t *ph, 1114 usb_intr_req_t *intr_reqp, 1115 usb_flags_t flags); 1116 void ehci_handle_root_hub_pipe_stop_intr_polling( 1117 usba_pipe_handle_data_t *ph, 1118 usb_flags_t flags); 1119 1120 /* 1121 * EHCI Interrupt Handler entry point. 1122 */ 1123 uint_t ehci_intr(caddr_t arg); 1124 1125 #ifdef __cplusplus 1126 } 1127 #endif 1128 1129 #endif /* _SYS_USB_EHCID_H */ 1130